JP2844085B2 - Circuit board and method of mounting semiconductor element - Google Patents
Circuit board and method of mounting semiconductor elementInfo
- Publication number
- JP2844085B2 JP2844085B2 JP18807089A JP18807089A JP2844085B2 JP 2844085 B2 JP2844085 B2 JP 2844085B2 JP 18807089 A JP18807089 A JP 18807089A JP 18807089 A JP18807089 A JP 18807089A JP 2844085 B2 JP2844085 B2 JP 2844085B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- sealing frame
- circuit board
- reinforcing plate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Credit Cards Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えばICカードのような携帯型電子機器に
用いられる極めて厚みの薄い回路基板に搭載される半導
体素子を外圧から保護するための回路基板の構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to protecting a semiconductor element mounted on an extremely thin circuit board used for a portable electronic device such as an IC card from an external pressure. The present invention relates to a circuit board structure.
回路基板に搭載する半導体素子を外圧から保護するた
め、前記半導体素子を密封してなる回路基板において、
前記半導体素子の搭載領域近傍にスリットを設けること
によりなされる。この構造によれば、回路基板に外部か
ら力が作用したとき、前記スリット部に応力が集中する
ので半導体素子に作用する力が減少され、該素子のワ
レ，クラック等の発生を防止できるものである。In order to protect the semiconductor element mounted on the circuit board from external pressure, in a circuit board obtained by sealing the semiconductor element,
This is achieved by providing a slit near the mounting area of the semiconductor element. According to this structure, when a force is applied to the circuit board from the outside, stress concentrates on the slit portion, so that the force acting on the semiconductor element is reduced, and cracks and cracks of the element can be prevented. is there.
ICカードのような薄型の携帯型電子機器に使用される
回路基板は、第２図（ａ）〜（ｃ）に示すようにその薄
型の要求から搭載する素子を、いわゆるチップオンボー
ドで実装する方法が採用されている。また、このような
薄型の携帯型電子機器では、携帯に際してたえず外部か
ら力を受ける機会にさらされており、外圧により半導体
素子４と封止剤16よりなるパッケージ本体が湾曲する現
象が起きるので、内蔵された半導体素子４をこの外圧か
ら保持するため、回路基板12に補強板13を積層し剛性を
高める構造としていた。ここで、補強板13という表現を
用いているが、機能的には前記半導体素子４を封止剤16
で密封するための例えば封止枠15を設けた構造をとる場
合もあるし、回路パターン19が形成された基板12を兼ね
て回路パターン19と半導体素子４とをワイヤー17で結線
し、積層される場合もある。2. Description of the Related Art As shown in FIGS. 2A to 2C, a circuit board used for a thin portable electronic device such as an IC card mounts an element to be mounted on a so-called chip-on-board because of the demand for the thinness. The method has been adopted. Further, in such a thin portable electronic device, the portable electronic device is constantly exposed to an external force when it is carried, and the external pressure causes the package body including the semiconductor element 4 and the sealing agent 16 to bend. In order to hold the built-in semiconductor element 4 from this external pressure, a reinforcing plate 13 is laminated on the circuit board 12 to increase the rigidity. Here, the expression “reinforcement plate 13” is used, but functionally, the semiconductor element 4 is sealed with a sealant 16.
In some cases, for example, a structure in which a sealing frame 15 is provided for sealing is used, and the circuit pattern 19 and the semiconductor element 4 are also connected to each other by wires 17 to serve as the substrate 12 on which the circuit pattern 19 is formed, and are laminated. In some cases.
前記のように、補強板13を積層し剛性を高くしても応
力を受けたときに半導体素子４を含むパッケージが湾曲
する現象は避けられず、搭載された半導体素子４には依
然としてワレ，クラック等が発生していた。この理由を
第２図に従って説明する。第２図（ａ）は封止枠15を設
けた補強板13を基板12と積層した従来の回路基板11の部
分平面図であり、第２図（ｂ）は同図（ａ）のＡ−Ａ断
面図、第２図（ｃ）は同図（ｂ）において回路基板11の
下部から上方に向かって力Ｆが作用し、回路基板11が湾
曲した状態を示している。同図において、力Ｆにより、
回路基板11が湾曲したとき、基板12に搭載された半導体
素子４を厚み方向に折り曲げようとする力が作用するが
加わる力Ｆが基板12に搭載された半導体素子４の剛性を
超えたとき、半導体素子４にはクラック８やワレが発生
することとなる。このように、従来の回路基板11の構造
においては、作用する力Ｆが半導体素子４の剛性を超え
たとき、該素子はワレやクラックを生じてしまうという
問題点があった。As described above, even when the rigidity is increased by stacking the reinforcing plates 13, the phenomenon that the package including the semiconductor element 4 bends when subjected to stress is unavoidable, and the mounted semiconductor element 4 still has cracks and cracks. Etc. had occurred. The reason will be described with reference to FIG. FIG. 2 (a) is a partial plan view of a conventional circuit board 11 in which a reinforcing plate 13 provided with a sealing frame 15 is laminated on a substrate 12, and FIG. FIG. 2 (c) is a cross-sectional view of FIG. 2 (c), showing a state in which a force F acts upward from the lower part of the circuit board 11 in FIG. In FIG.
When the circuit board 11 is curved, a force acting to bend the semiconductor element 4 mounted on the substrate 12 in the thickness direction acts, but when the applied force F exceeds the rigidity of the semiconductor element 4 mounted on the substrate 12, Cracks 8 and cracks occur in the semiconductor element 4. As described above, in the structure of the conventional circuit board 11, when the applied force F exceeds the rigidity of the semiconductor element 4, there is a problem that the element generates cracks and cracks.
このような問題点を解決するために、本発明は補強板
の封止枠の周囲にスリットを設けておき、スリットを設
けた補強板を基板に積層することにより、半導体にクラ
ック，ワレを発生しないようにしたものである。In order to solve such a problem, according to the present invention, cracks and cracks are generated in a semiconductor by providing a slit around a sealing frame of a reinforcing plate and laminating the reinforcing plate provided with the slit on a substrate. It is something that was not done.
回路基板に外力Ｆが作用すると回路基板は湾曲を呈す
るが、補強板に設けられたスリット18により、この部分
のみ他より剛性が低くなるため応力が集中する。従って
回路基板11の湾曲形状はスリット部近傍は変形量が大き
いが、半導体素子４が搭載された領域部は変形量が少な
い。即ち、半導体素子４に加わる力は非常に少ないもの
となるため、該素子のワレ，クラック等の発生を防止す
ることができるものである。When an external force F acts on the circuit board, the circuit board is curved. However, due to the slits 18 provided in the reinforcing plate, only this portion has lower rigidity than the other portions, so that stress is concentrated. Therefore, the curved shape of the circuit board 11 has a large deformation amount near the slit portion, but a small deformation amount in the region where the semiconductor element 4 is mounted. That is, since the force applied to the semiconductor element 4 is very small, it is possible to prevent cracks and the like from occurring in the element.
つまり、回路基板を湾曲させる力が作用しても補強板
に設けられたスリット部に応力が集中するため、半導体
素子に作用する応力は分散される。よって、該素子は外
圧から保護される。That is, even if a force for bending the circuit board acts, the stress concentrates on the slit portion provided in the reinforcing plate, so that the stress acting on the semiconductor element is dispersed. Thus, the element is protected from external pressure.
本発明の一実施例を第１図（ａ）、第１図（ｂ）に従
って説明する。材料厚み0.1mm、銅箔厚み18μｍの両面
銅張積層板に所定の回路導体パターン19を形成した基板
12に、半導体素子４（サイズ5.4mm×5.4mm）を載置し、
前記半導体素子４の電極と基板12の導体パターン19をワ
イヤーボンディング法によりワイヤー17で接続した。一
方、基板12と同等の形状に外形加工し、封止枠15として
8.4mm×8.4mmのサイズにマド抜き加工し、更に、前記封
止枠15の周囲にスリット18を封止枠15の各辺に沿って４
ケ所設けた補強板13を用意し、前記基板12に接着材を介
して積層した。更に、封止枠15内に樹脂を充填し硬化さ
せたのち本発明による回路基板11を得た。なお、前記ス
リット18の幅は1mmとした。また、補強板13の厚さはパ
ッケージの総厚の規制から、0.3mmとした。補強板13の
材質はガラスエポキシ樹脂を使用したが、その他、トリ
アジン変性樹脂、紙フェノール、紙エポキシその他の複
合材料、あるいはステンレス等の金属材料などでもよ
い。なお本発明ではスリットとしているが、スリットに
限るものではなく、要は搭載した素子に加わる応力を分
散し、素子を保護できる構造を提供できるものであれば
よい。また、スリットは部材を貫通して形成しても非貫
通で形成してもどちらでもよいのは勿論のことである。
第３図（ａ），（ｂ），（ｃ）に本発明の他の実施例の
数例を示す。One embodiment of the present invention will be described with reference to FIGS. 1 (a) and 1 (b). A substrate in which a predetermined circuit conductor pattern 19 is formed on a double-sided copper-clad laminate having a material thickness of 0.1 mm and a copper foil thickness of 18 μm
A semiconductor element 4 (size 5.4 mm x 5.4 mm) is placed on 12,
The electrodes of the semiconductor element 4 were connected to the conductor patterns 19 of the substrate 12 by wires 17 by a wire bonding method. On the other hand, the outer shape is processed to the same shape as the substrate 12, and the sealing frame 15 is formed.
A 8.4 mm x 8.4 mm size is punched out, and a slit 18 is formed around the sealing frame 15 along each side of the sealing frame 15.
A reinforcing plate 13 provided at two places was prepared, and was laminated on the substrate 12 via an adhesive. Further, after filling and curing the resin in the sealing frame 15, the circuit board 11 according to the present invention was obtained. The width of the slit 18 was 1 mm. Further, the thickness of the reinforcing plate 13 was set to 0.3 mm from the regulation of the total thickness of the package. Although glass epoxy resin was used as the material of the reinforcing plate 13, a triazine-modified resin, paper phenol, paper epoxy or another composite material, or a metal material such as stainless steel may be used. In the present invention, the slit is used. However, the present invention is not limited to the slit. In short, any slit may be used as long as it can disperse the stress applied to the mounted element and provide a structure capable of protecting the element. Further, it goes without saying that the slit may be formed so as to penetrate the member or may be formed without penetrating the member.
3 (a), 3 (b) and 3 (c) show several examples of other embodiments of the present invention.
第３図（ａ）は半導体４を封止してある封止枠15の周
辺に複数の穴21を設けたものであり、第３図（ｂ）はス
リット18を封止枠15の辺に沿ってＬ字状に設けたもので
あり、第３図（ｃ）はスリット18を封止枠15の辺に対し
て90°ずらしてＬ字状に設けたものである。FIG. 3A shows a case in which a plurality of holes 21 are provided around a sealing frame 15 in which the semiconductor 4 is sealed, and FIG. 3 (c), the slit 18 is provided in an L-shape with the slit 18 being shifted by 90 ° with respect to the side of the sealing frame 15. FIG.
以上述べたとおり、基板に積層する補強板にスリット
を設ける構造としているが、補強板に限るものではな
く、密封実装した半導体素子の搭載領域の近傍であれ
ば、回路基板を構成する部材のいずれに設けられていて
もよく、スリットが設けられる構成部材を特定するもの
ではない。又、表裏に関係なく、スリットを設ける事は
可能である。As described above, the slits are provided in the reinforcing plate laminated on the substrate. However, the present invention is not limited to the reinforcing plate, and any member constituting the circuit board may be provided as long as it is in the vicinity of the mounting region of the hermetically mounted semiconductor element. May not be provided, and does not specify the constituent member provided with the slit. In addition, it is possible to provide a slit regardless of the front and back.
その実施例を第４図（ａ）〜（ｃ）に示す。第４図
（ａ）は補強板がないものの例で、基板12にワイヤ17で
結線した半導体４が載置されている。半導体４は封止剤
16にて封止されている。スリット18は、半導体４を封止
している封止剤16の周辺に設けてある。第４図（ｂ）は
半導体４を基板12にバンプ36にて結線される。第４図
（ｂ）の実施例は基板12上の封止剤16の周囲に凹部20を
設け、スリットの代用をしているものである。第４図
（ｃ）の実施例は基板12の裏側に凹部20を設けたもので
ある。The embodiment is shown in FIGS. 4 (a) to 4 (c). FIG. 4 (a) shows an example without a reinforcing plate, in which a semiconductor 4 connected by wires 17 is mounted on a substrate 12. FIG. Semiconductor 4 is a sealant
Sealed at 16. The slit 18 is provided around the sealant 16 that seals the semiconductor 4. FIG. 4B shows the semiconductor 4 connected to the substrate 12 by bumps 36. In the embodiment shown in FIG. 4B, a recess 20 is provided around the sealant 16 on the substrate 12 to substitute for a slit. In the embodiment shown in FIG. 4C, a concave portion 20 is provided on the back side of the substrate 12.
更に、本実施例では基板に補強板を積層した構造とし
て示しているが、半導体素子を密封実装した単層の回路
基板であってもよく、この場合は前記半導体素子の搭載
領域近傍の前記回路基板にスリットを設けるものであ
る。Furthermore, although the present embodiment shows a structure in which a reinforcing plate is laminated on a substrate, a single-layer circuit board in which a semiconductor element is hermetically mounted may be used. In this case, the circuit near the mounting area of the semiconductor element may be used. A slit is provided on the substrate.
本発明により、回路基板に搭載された半導体素子が外
圧から保護されるため、ICカードのような薄型の携帯型
電子機器の信頼性向上に大きな効果がある。According to the present invention, since a semiconductor element mounted on a circuit board is protected from external pressure, there is a great effect on improving the reliability of a thin portable electronic device such as an IC card.
第１図（ａ）は本発明による一実施例を示す回路基板の
部分平面図、第１図（ｂ）は同図（ａ）のＢ−Ｂ断面
図、第１図（ｃ）は同図（ｂ）の回路基板の湾曲状態
図、第２図（ａ）は従来の回路基板の部分平面図、第２
図（ｂ）は同図（ａ）のＡ−Ａ断面図、第２図（ｃ）は
同図（ｂ）の回路基板の湾曲状態図、第３図（ａ）乃至
（ｃ）は本発明によるスリット形状の他の実施例を示す
部分平面図、第４図（ａ）乃至（ｃ）は本発明による回
路基板の構造の他の実施例を示す断面図である。 ４……半導体素子 ８……クラック 11……回路基板 12……基板 13……補強板 15……封止枠 16……封止剤 17……ワイヤー 18……スリット 19……導体パターン 20……凹部 21……穴 36……バンプ1 (a) is a partial plan view of a circuit board showing an embodiment according to the present invention, FIG. 1 (b) is a sectional view taken along the line BB of FIG. 1 (a), and FIG. 1 (c) is the same figure. FIG. 2 (b) is a diagram showing a curved state of the circuit board, FIG. 2 (a) is a partial plan view of a conventional circuit board, and FIG.
FIG. 2B is a cross-sectional view taken along the line AA of FIG. 2A, FIG. 2C is a diagram showing the state of curvature of the circuit board of FIG. 2B, and FIGS. 4 (a) to 4 (c) are cross-sectional views showing another embodiment of the structure of the circuit board according to the present invention. 4 Semiconductor element 8 Crack 11 Circuit board 12 Substrate 13 Reinforcement plate 15 Sealing frame 16 Sealant 17 Wire 18 Slit 19 Conductor pattern 20 ... recess 21 ... hole 36 ... bump
Claims (6)
子の上面の端子とワイヤーを介して電気的に導通を取る
導体パターンと、 前記半導体素子の外周部に離間して、前記導体パターン
上に封止剤の流出を防止する複数の封止枠を有し、 前記封止枠の前記半導体素子と向かい合う側と反対側に
離間した前記導体パターン上に補強板を有し、 前記半導体素子の上面と前記封止枠の前記半導体素子と
向かい合う側の側面に前記半導体素子と前記ワイヤーを
封止する封止剤を有する回路基板。A conductive pattern having a semiconductor element on a substrate and electrically connected to a terminal on an upper surface of the semiconductor element via a wire, separated from the semiconductor on a surface of the substrate; A plurality of sealing frames for preventing a sealant from flowing out on the conductor pattern, the conductor pattern being separated on a side opposite to a side of the sealing frame facing the semiconductor element. A circuit board having a reinforcing plate thereon, and a sealant for sealing the semiconductor element and the wire on a side of the upper surface of the semiconductor element and a side of the sealing frame facing the semiconductor element.
に、凹部を有する請求項１記載の回路基板。2. The circuit board according to claim 1, wherein a recess is provided between the sealing frame and the reinforcing plate of the board.
に、複数の穴を有する請求項１記載の回路基板。3. The circuit board according to claim 1, wherein a plurality of holes are provided between the sealing frame and the reinforcing plate of the board.
に向かい合うＬ字型の第１の封止枠と、前記前記半導体
素子を中心として前記第１の封止枠に対称となる第２の
Ｌ字型の封止枠からなる請求項１記載の回路基板。4. An L-shaped first sealing frame in which the sealing frame faces one side surface of the semiconductor element, and an L-shaped first sealing frame which is symmetric with respect to the first sealing frame about the semiconductor element. 2. The circuit board according to claim 1, comprising two L-shaped sealing frames.
間した導体パターンを設け、 前記導体パターン上の前記半導体素子に向かい合う側に
封止枠を設け、 前記半導体素子の上面の端子と前記導体パターンをワイ
ヤーで電気的に接続し、 前記封止枠と前記半導体素子を封止し、 前記導体パターン上に前記封止枠と離間して補強板を設
け、前記導体パターン上の前記封止枠と前記補強板間に
基板変形時の応力を緩和するスリットを設ける半導体素
子の実装方法。5. A semiconductor element and a conductor pattern separated from the semiconductor element are provided on a substrate, a sealing frame is provided on a side of the conductor pattern facing the semiconductor element, and a terminal on an upper surface of the semiconductor element and the conductor are provided. The pattern is electrically connected with a wire, the sealing frame and the semiconductor element are sealed, a reinforcing plate is provided on the conductor pattern so as to be spaced apart from the sealing frame, and the sealing frame on the conductor pattern is provided. A method for mounting a semiconductor element, wherein a slit for relaxing stress during substrate deformation is provided between the reinforcing plate and the reinforcing plate.
間した導体パターンを設け、 前記導体パターン上の前記半導体素子に向かい合う側に
封止枠を設け、 前記半導体素子の上面の端子と前記導体パターンをワイ
ヤーで電気的に接続し、 前記封止枠と前記半導体素子を封止し、 前記導体パターン上に前記封止枠と離間して補強板を設
け、前記導体パターン上の前記封止枠と前記補強板間に
基板変形時の応力を緩和するスリットを設ける回路基板
の製造方法。6. A semiconductor element and a conductor pattern separated from the semiconductor element are provided on a substrate, a sealing frame is provided on a side of the conductor pattern facing the semiconductor element, and a terminal on an upper surface of the semiconductor element and the conductor are provided. The pattern is electrically connected with a wire, the sealing frame and the semiconductor element are sealed, a reinforcing plate is provided on the conductor pattern so as to be spaced apart from the sealing frame, and the sealing frame on the conductor pattern is provided. A method for manufacturing a circuit board, wherein a slit is provided between the reinforcing plate and the substrate to relieve stress when the substrate is deformed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18807089A JP2844085B2 (en) | 1989-07-20 | 1989-07-20 | Circuit board and method of mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18807089A JP2844085B2 (en) | 1989-07-20 | 1989-07-20 | Circuit board and method of mounting semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0352255A JPH0352255A (en) | 1991-03-06 |
| JP2844085B2 true JP2844085B2 (en) | 1999-01-06 |
Family
ID=16217184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18807089A Expired - Fee Related JP2844085B2 (en) | 1989-07-20 | 1989-07-20 | Circuit board and method of mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2844085B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019113683A1 (en) * | 2017-12-15 | 2019-06-20 | 2449049 Ontario Inc. | Printed circuit board with stress relief zones for component and solder joint |
| KR20210042316A (en) * | 2018-08-10 | 2021-04-19 | 니타 가부시키가이샤 | IC tag |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0540993U (en) * | 1991-10-23 | 1993-06-01 | 能美防災株式会社 | Fire alarm printed circuit board |
| JP4580509B2 (en) * | 2000-06-14 | 2010-11-17 | 大日本印刷株式会社 | IC carrier with plate-like frame fixed to card mounting board |
| JP2003044816A (en) * | 2001-07-31 | 2003-02-14 | Toppan Forms Co Ltd | IC card |
| CN100558565C (en) | 2002-04-30 | 2009-11-11 | 美克司公司 | binder |
| JP2005346559A (en) * | 2004-06-04 | 2005-12-15 | Nittoku Eng Co Ltd | IC module and manufacturing method thereof |
| JP4779826B2 (en) * | 2006-06-29 | 2011-09-28 | パナソニック株式会社 | Flexible printed circuit board |
| JP5184115B2 (en) * | 2008-01-31 | 2013-04-17 | 日東電工株式会社 | Wiring circuit board and manufacturing method thereof |
| JP2009182228A (en) | 2008-01-31 | 2009-08-13 | Nitto Denko Corp | Wiring circuit board and manufacturing method thereof |
| JP5129783B2 (en) * | 2009-06-02 | 2013-01-30 | 日本特殊陶業株式会社 | Wiring board with reinforcing material and method for manufacturing the same |
| JP2011152502A (en) * | 2010-01-26 | 2011-08-11 | Panasonic Electric Works Co Ltd | Electrostatic atomizer |
| JP5556550B2 (en) * | 2010-09-30 | 2014-07-23 | 凸版印刷株式会社 | High strength IC card |
| JP5575730B2 (en) * | 2011-11-15 | 2014-08-20 | 日本電信電話株式会社 | Multilayer wiring board for semiconductor devices |
| JP6497942B2 (en) * | 2015-01-13 | 2019-04-10 | 日立オートモティブシステムズ株式会社 | Electronic control unit |
| JP2017063077A (en) * | 2015-09-24 | 2017-03-30 | 本田技研工業株式会社 | Circuit board on which multipolar connector is mounted |
| EP3252679B1 (en) | 2016-06-02 | 2021-09-08 | Fujitsu Limited | Rfid tag |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5113612B2 (en) * | 1972-02-21 | 1976-05-01 | ||
| JPS5794954U (en) * | 1980-12-01 | 1982-06-11 |
-
1989
- 1989-07-20 JP JP18807089A patent/JP2844085B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019113683A1 (en) * | 2017-12-15 | 2019-06-20 | 2449049 Ontario Inc. | Printed circuit board with stress relief zones for component and solder joint |
| US10880995B2 (en) | 2017-12-15 | 2020-12-29 | 2449049 Ontario Inc. | Printed circuit board with stress relief zones for component and solder joint protection |
| KR20210042316A (en) * | 2018-08-10 | 2021-04-19 | 니타 가부시키가이샤 | IC tag |
| KR102757130B1 (en) * | 2018-08-10 | 2025-01-21 | 니타 가부시키가이샤 | IC tag |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0352255A (en) | 1991-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2844085B2 (en) | Circuit board and method of mounting semiconductor element | |
| US6633078B2 (en) | Semiconductor device, method for manufacturing an electronic equipment, electronic equipment and portable information terminal | |
| JP3838331B2 (en) | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus | |
| JP3033227B2 (en) | Semiconductor device | |
| US20040256150A1 (en) | Nonconducting substrate, forming a strip or a panel, on which a multiplicity of carrier elements are formed | |
| JPH07115151A (en) | Semiconductor device and manufacturing method thereof | |
| US20020030255A1 (en) | Non-contact type IC card | |
| US20210203302A1 (en) | Multilayer body and method of manufacturing the same | |
| JPH08148635A (en) | Semiconductor device | |
| JP2005026678A (en) | Semiconductor device | |
| JPH03220736A (en) | Mounting method for semiconductor element | |
| JPH03125440A (en) | Electronic parts | |
| JP3548023B2 (en) | Semiconductor device | |
| CN115866874A (en) | Flexible printed circuit board, COF module, and electronic device including the same | |
| AU2006215267A1 (en) | Method and arrangement for contact-connecting semiconductor chips on a metallic substrate | |
| JP3303825B2 (en) | Method for manufacturing semiconductor device | |
| JP3063713B2 (en) | Semiconductor device | |
| JP3216636B2 (en) | Semiconductor device | |
| JP7552191B2 (en) | Mounting structure and method for manufacturing the same | |
| JP2734665B2 (en) | Semiconductor device | |
| JP2661101B2 (en) | IC card | |
| JPH0524553Y2 (en) | ||
| JPH0753989Y2 (en) | IC card module | |
| JPH0721820B2 (en) | IC card | |
| JP2000339427A (en) | IC card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |