JP2723562B2 - Offset correction circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a tofset correction circuit, and more particularly to an offset correction circuit using a differential amplifier.

[Conventional technology]

Conventionally, such an offset correction circuit has been realized using a differential amplifier for correcting an offset voltage of an A / D converter, a D / A converter, a communication LSI, or the like.

FIG. 5 is an offset correction circuit diagram showing an example of such a prior art.

As shown in FIG. 5, the offset correction circuit includes a differential amplifier 1 including a differential amplifier circuit 11 and an NMOS-FET 23 in an output stage, a non-inverting input terminal (+) of the differential amplifier circuit 11 and an inverting input terminal. A correction capacitance circuit 3 composed of correction capacitance elements 12 and 13 connected to the terminal (−), respectively; a reference voltage source (V _REF ) 4, an analog input signal source (A _IN ) 5 and a control signal source ( φ ₁₂ ) 9 and the output side is connected to the differential amplifier 1 and the correction capacitance circuit 3, and the CMOS-FET 14
And a control circuit 2 ′ for offset voltage correction composed of inverters 19 to 21, and a PMOS-FE connected to the power supply terminal 8 is connected to the output transistor 23 of the differential amplifier 1.
T22 and the grounded resistance element 24 are connected, and an output _VOUT is taken out from a connection point between the resistance element 24 and the NMOS-FET 23.

6 (a) and 6 (b) are time series connection circuit diagrams of the correction capacitance circuit shown in FIG. 5, respectively. FIG. 7 shows the relationship between the control signal and the output voltage shown in FIG. 5 in time series. It is a timing chart.

As shown in FIGS. 6 (a) and 7, this correction circuit is controlled by a control signal 9 (φ ₁₂ ), and the control periods T _12-1 and T _12-2 by this control signal are offset voltage. During the sampling period, the capacitor 12 is short-circuited, the reference voltage source V _REF is applied to the non-inverting input terminal (+) of the differential amplifier circuit 11, and at the same time, the output terminal V _OUT becomes the inverting input terminal (-).
Is the period connected to That is, the circuit connection of FIG. 6 (a) represents the connection state of such T _12-1, T _12-2 period.

Here, assuming that both ends of the capacitive element 12 and one side of the capacitive element 13 are biased to the potential V _REF of the reference voltage source 4 and the offset voltage of the differential amplifier circuit 11 is V _OFF1 , the capacitive element 1
The other end of the 3 is biased to V _REF + V _OFF1. That is, the capacitor 13 is charged with _VOFF1 .

Next, as shown in FIGS. 6 (b) and 7, control periods T _02-1 , T _02-2 and T _02-3 without control signal (φ ₁₂ ) 9 are offset voltage hold periods. , The analog input signal (A _IN ) 5 is applied to the non-inverting input terminal (+) of the differential amplifier circuit 11 via the capacitive element 12, and the output voltage V _OUT is
This is a period applied to the inverting input terminal (−) through the line 13. That is, FIG. 6 (b) shows such T _{02-1 to} T _02-3
Indicates the connection state during the period.

Here, one side of the capacitive element 12 is biased by the analog input signal A _IN , but the electric charge accumulated in the capacitive element 12 during the above-described offset voltage sampling period was 0, so the other side of the capacitive element 13 and the differential non-inverting input terminal of the amplifier circuit 11 (+) follows the analog input signal a _iN of the same level of the voltage. On the other hand, one side of the output V _OUT and the capacitor 13 of the differential amplifier 1, becomes A _IN + V _OFF1 the moment when the control period T ₁₂ was switched to the T ₀₂ period, therefore the capacitor 13
Since the charge corresponding to V _OFF1 is accumulated, the other end of the capacitor 13 and the inverting input terminal (−) of the differential amplifier circuit 11 are connected to A _IN
+ 2V _OFF1 . However, in FIG. 6 (b), since a circuit configuration of a differential amplifier hazy negative feedback, finally in a section of the left T ₀₂ charges the V _OFF1 minutes is accumulated in the capacitor 13 In this case, the V _OUT terminal is set to A _IN and the inverted input terminal (−) of the differential amplifier circuit 11 is set to A _IN + V _OFF1 .

As described above, the temporal change of the output voltage of the offset correction circuit is as shown in the voltage waveform _VOUT1 shown in FIG.
Therefore, in the circuit for converting voltage and current shown in FIG. 5, by using a correction circuit including a capacitance element,
Accurate voltage-current conversion can be performed.

FIG. 8 is a block diagram of an A / D converter using the conventional offset correction circuit shown in FIG.

As shown in FIG. 8, this A / D converter has an analog signal 3
The offset correction circuit 35 'described above is input to the input section for inputting 1.
The comparator 33 uses a control signal 37 (the above-mentioned φ ₁₂ ) from a control signal generation circuit 36 to generate a reference voltage.
The output voltage to be compared with 34 is corrected. Note that reference numeral 30 denotes a reference voltage source, and reference numeral 32 denotes a D / A conversion circuit.

[Problems to be solved by the invention]

The above-described conventional offset correction circuit as shown in FIG. 5 performs the correction voltage sampling periods T _12-1 and T _12-2 in the following manner. When the relationship holds, T ₁₂ can not be accurately sampling the offset voltage of the differential amplifier circuit 11 in a section, a timing chart in the output voltage V _OUT2 shown in FIG. 7
V _E1 and V _E2 . Since this error is held as it is in the offset holding period _T02 , when this correction circuit is used in the analog input section of the A / D converter described with reference to FIG. 8, the conversion error is amplified and becomes large. There is a problem.

The problem of the output voltage error is greatly affected by the slew rate, drive current, and offset correction capacitance value of the differential amplifier circuit 11, and particularly when such a circuit is realized on an LSI, the variation in products becomes large and stable characteristics are obtained. It has the disadvantage that it cannot be obtained.

An object of the present invention is to provide an offset correction circuit capable of outputting an offset correction voltage without being affected by the slew rate, output current, offset correction capacitance value, or input voltage value of such a differential amplifier (differential amplifier circuit). Is to provide.

[Means for solving the problem]

An offset correction circuit according to the present invention is a correction capacitor having a differential amplifier connected to an output stage, and first and second capacitance elements respectively connected to a non-inverting input terminal and an inverting input terminal of the differential amplifier. A circuit, an input side is connected to an analog signal input source and a reference voltage source and a control signal source, and an output side is connected to the differential amplifier and the correction capacitance circuit,
In an offset correction circuit having a MOS transistor and a control circuit formed by an inverter, the control circuit forms a plurality of transfer gates by the MOS transistor, and provides two types of control signal sources to provide the plurality of control signal sources. By opening and closing the transfer gate, the control circuit sets three time-series control periods for the input of the differential amplifier, and a first control signal source controls the differential amplifier in the first control period. The reference voltage source is connected to the non-inverting input terminal, the inverting input terminal, and the correction output terminal to short-circuit the first and second capacitance elements, and in the second control period, the second control signal source The first capacitive element connected to the non-inverting input terminal of the differential amplifier is short-circuited to supply a reference voltage, and the inverting input terminal of the differential amplifier is connected to the first capacitive element. The correction output terminal is short-circuited, and in the third control period, the first and second control signal sources are shut off and the analog signal input source is connected to the non-inversion input terminal of the differential amplifier. The first capacitor is connected to the first capacitor and the correction output terminal is connected to the second capacitor connected to the inverting input terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an offset correction circuit diagram showing one embodiment of the present invention.

As shown in FIG. 1, in this embodiment, a differential amplifier 1, a reference voltage source (V _REF ) 4, an analog input signal source (A _IN ) 5, and two control signal sources (φ ₁₁ , φ ₂₁ ) 6 are provided. , 7 and a capacitance element 12,13, and these capacitance elements 12,
13 is a differential amplifier circuit 11 constituting the differential amplifier 1
And a correction capacitor circuit 3 connected to the non-inverting input terminal (+) and the inverting input terminal (−) of the differential amplifier 1.
Three are set by transfer gates 14-18, 25, 28 comprising S-FETs and inverters 19-21, 26, 27.

Next, regarding the operation of this offset correction circuit,
This will be described with reference to FIGS. 2 (a) to 2 (c) and FIG.

2 (a) to 2 (c) are time series connection circuit diagrams of the correction capacitance circuit shown in FIG. 1, respectively. FIG. 3 is a time series showing the relationship between the control signal and the output voltage shown in FIG. It is a timing diagram shown.

As shown in FIG. 1 to FIG. 3, the offset correction circuit has been controlled by two control signals phi ₁₁ and phi _21, a transfer gate 25 and 28 are formed by CMOS-FET in Figure 1 FIG. 2A shows a circuit configuration in a state where is turned on (period T ₂₁ ). Similarly, the circuit configuration shown in FIG. 2 (b) represents a connection state when the control period T _11, the circuit configuration shown in FIG. 2 (c) represents the connection state when the control period T _01. That is, the capacitive element 1
2 and both input and output terminals of the differential amplifier circuit 11 and both ends of the capacitor 13 are biased to the V _REF potential of the reference voltage source 4. In this case, time T _A on both sides of the input terminals and the capacitive element 13 of the differential amplifier circuit 11 is biased to the reference voltage V _REF can be expressed by the following equation.

Incidentally, C _A: capacitance value I _REF capacity 13: Time biased from the drive current The equation of the reference voltage V _REF to the reference voltage V _REF T _A is I
_{When REF} ≫C _A × V _REF , if I _REF is constant, it hardly fluctuates. That is, If Naritate is related, it can be pulled at both ends of the capacitor 13 to V _REF potential in time T _11.

Normally, since it is V _REF >> V _OFF2, CMOS in the next period of T ₁₁
-Turn off the transfer gates 17, 25, 28 consisting of FETs,
By turning on the transfer gates ₁₅ , ₁₆ , and ₁₈ , the potential of V _OUT is instantaneously raised to V _REF + V _OFF2 . That is, the output terminal potential of the differential amplifier circuit 11 within a period of T ₁₁ V _OUT to reliably without receiving other effects, such as V _REF potential or A _IN potential if the drive current of the reference potential V _REF is sufficiently large V _REF + V _{Pulled up} to _OFF2 .

As a result, the period of the next T _01, the output potential V _OUT is without being affected by the offset voltage of the differential amplifier 1 with respect to the potential A _IN of the analog input signal, the analog input potential
It is kept at the potential of A _IN .

FIG. 4 is a block diagram of an A / D converter using the above-described offset correction circuit of the present invention.

As shown in FIG. 4, such a correction circuit 35 since when used in the analog input section of the A / D converter, the potential of T reliably analog input signal ₀₁ period (A _IN) 31 is obtained,
Reference voltage source 30, D / A conversion circuit 32 in this period T _01, a comparator 33, a reference voltage source 34, by performing the A / D converted by the control signal generating circuit 36 and the two control signals 37 and 38 thereof, the precision Good conversion results are obtained.

〔The invention's effect〕

As described above, the offset correction circuit according to the present invention includes the differential amplifier, the correction capacitance circuit, and the control circuit, and performs offset correction of the differential amplifier using two types of control signals. By connecting the non-inverting input terminal and the inverting input terminal of the differential amplifier before the sampling period, the slew rate, output current, offset correction capacitance value and input voltage value of the differential amplifier are not affected. There is an effect that offset correction can be realized, and in particular, there is an effect that an offset correction circuit suitable for monolithicization can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an offset correction circuit diagram showing one embodiment of the present invention, and FIGS. 2 (a) to (c) are time-series connection circuit diagrams of the correction capacitance circuit shown in FIG. FIG. 3 is a timing chart showing the relationship between the control signal and the output voltage shown in FIG. 1 in chronological order, and FIG.
FIG. 5 is a block diagram of a converter, FIG. 5 is an offset correction circuit diagram showing an example of a conventional device, and FIGS.
FIG. 7 is a time series connection circuit diagram of the correction capacitance circuit shown in FIG. 7, FIG. 7 is a timing diagram showing the relationship between the control signal and the output voltage shown in FIG. 5 in time series, and FIG. FIG. 3 is a block diagram of an A / D converter using a circuit. DESCRIPTION OF SYMBOLS 1 ... Differential amplifier, 2 ... Control circuit, 3 ... Correction capacitance circuit, 4
… Reference voltage source (V _REF ), 5… Analog input signal source (A _IN ), 6,7… Control signal (φ ₁₁ , Q ₂₁ ), 8… Power supply terminal, 11… Differential amplifier circuit, 12,13… Capacitance element, 14-18,2
5, 28 transfer gate, 19 to 21, 26, 27 inverter, 22 P-channel MOS transistor (PMOS-FET),
23 ... N-channel MOS transistor (NMOS-FET), 24 ...
Resistance element.

Claims (1)

(57) [Claims] A differential amplifier connected to an output stage; and a correction capacitance circuit having first and second capacitance elements connected to a non-inverting input terminal and an inverting input terminal of the differential amplifier, respectively. An offset correction circuit having an input side connected to an analog signal input source, a reference voltage source, and a control signal source, and an output side connected to the differential amplifier and the correction capacitance circuit, the control circuit including a MOS transistor and an inverter. The control circuit forms a plurality of transfer gates by the MOS transistors, and provides two types of the control signal sources to open and close the plurality of transfer gates of the control circuit, so that the differential amplifier is used in the control circuit. In the first control period, a first control signal source controls the differential amplifier to set the time series control period for the input of the differential amplifier to three. The reference voltage source is connected to the non-inversion input terminal, the inversion input terminal, and the correction output terminal to short-circuit the first and second capacitance elements. In a second control period, a second control signal source is connected. Short-circuits the first capacitive element connected to the non-inverting input terminal of the differential amplifier to supply a reference voltage, and short-circuits the inverting input terminal and the correction output terminal of the differential amplifier; In the third control period, the first and second control signal sources are shut off to connect the analog signal input source to the first capacitive element connected to the non-inverting input terminal of the differential amplifier, and An offset correction circuit, wherein a correction output terminal is connected to the second capacitor connected to the inverting input terminal.