JP2661651B2 - Semiconductor storage device - Google Patents

Description

The present invention relates to a dynamic RAM (random access memory).
And a semiconductor memory device such as a memory.

(Prior Art) Conventionally, as a technique in such a field, for example, there has been the one shown in FIGS. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of a word line selection drive circuit in a conventional dynamic RAM (hereinafter, referred to as DRAM).

This word line selection drive circuit includes a word line selection circuit 10,
It comprises a word line activation circuit 20 and a word line driver 30. The word line selection circuit 10 is activated by a row address strobe signal RAS to convert a row address (row address) A as an external address signal into an output address group AO as an internal address signal, and an output address group. A predecoder group 12 that predecodes AO and outputs a predecode address group PD, and a word line selection signal that decodes the predecode address group PD
And a decoder 13 for outputting AD. The word line activation circuit 20 includes a delay circuit 21 that delays the row address strobe signal RAS for a predetermined time, and a signal that receives an output of the delay circuit 21 and outputs a word line activation signal S22 having a level equal to or higher than the power supply potential Vcc, for example. And an arrangement circuit 22. Here, the delay circuit 21 is configured by, for example, a circuit in which a plurality of inverters are connected in cascade, a circuit including a resistor and a capacitor, and the like.

The word line driver 30 includes a cut-off N-channel MOS transistor (hereinafter, referred to as an NMOS) 31 having a threshold voltage Vt and a gate connected to the power supply potential Vcc.
And an NMOS 32 for driving the word line 35.
Is the word line select signal AD and its source is the NMOS
Each is connected to 32 gates. The drain of the NMOS 32 is connected to the word line activation signal S22, and its source is connected to the word line 3
5 connected to each.

FIG. 3 is a timing chart of FIG. 2, and the operation of FIG. 2 will be described with reference to FIG.

When the circuit operation state is entered and the row address strobe signal RAS becomes "H" level at time t1, the address buffer group 11 takes in the row address A and outputs the output address group AO. This output address group AO is
The predecode address group PD is decoded by the decoder 13, and a word line selection signal AD of “H” level (for example, power supply potential Vcc) for driving one word line 35 is supplied to the decoder 13. Output from The word line selection signal AD causes NM through the NMOS 31 in the ON state.
The gate of the OS 32 becomes (Vcc-Vt) potential, and the NMOS 32 is turned on.

On the other hand, when the row address strobe signal RAS attains the “H” level at time t1, it is delayed by the time T by the delay circuit 21 and its output is input to the signal generation circuit 22. The signal generation circuit 22 receives the output of the delay circuit 21 and outputs a word line activation signal S22 of, for example, Vcc level or higher at time t2, to raise the drain potential of the NMOS 32. Then, NMOS32
Self-boost, the gate potential of the NMOS32 becomes Vc
The level rises above the c level, the NMOS31 turns off, and the NMOS3
The word line 35 on the source side of No. 2 becomes higher than the Vcc level, and the word line 35 is activated.

When the word line 35 is activated, a memory cell in a row direction in a memory cell array (not shown) connected thereto is selected, and thereafter, a bit line is selected by a column (column) decoder (not shown), and a memory in the memory cell array is selected. A cell is selected, and data is read or written for the selected cell.

(Problems to be Solved by the Invention) However, the conventional semiconductor memory device has the following problems.

(A) The most important thing in the circuit of FIG. 2 is the mutual timing between the word line selection signal AD and the word line activation signal S22. The word line selection signal AD is output from the input of the row address A, the output address group AO, the predecode address group PD,
Then, the word line selection signal AD is decoded, but the selection of the word line selection signal AD is slow, and the word line activation signal S22 is input to the NMOS 32 before the gate potential of the NMOS 32 is sufficiently charged. In this case, the word line 35 is not sufficiently boosted and malfunctions. Therefore, the delay time T must be determined such that the output of the word line activation signal S22 is simultaneously with or after the output of the word line selection signal AD.

However, when adjusting the mutual timing between the two independent word line selection circuits 10 and the word line activation circuit 20,
Due to changes in device parameters, voltage, temperature, etc., the operating speed in the two circuits 10 and 20 changes, causing a timing shift, and there is a risk that the word line driver 30 malfunctions and the word line 35 is not boosted sufficiently. . Further, even in the word line selection circuit 10, a difference occurs in the output speed of each word line selection signal AD with respect to the row address A. That is, the load such as the output address load and the predecode address load for each word line selection signal AD is unlikely to be equal, and a speed difference occurs due to the word line selection signal AD. Therefore, it is very difficult to set the delay time T.

(B) Considering changes in device parameters, voltage, temperature, etc. in (a) and the speed difference due to the word line selection signal AD, the timing between the output of the word line selection signal AD and the output of the word line activation signal S22 If the output timing of the word line activation signal S22 is adjusted to the slowest selection signal in the word line selection signal AD, the above problem (a) can be solved. However, if the delay time T is made too long in order to provide a margin for the timing, there is a problem that the activation of the word line 35 under the worst conditions is delayed and the access time is delayed.

An object of the present invention is that it is difficult to set the timing of a word line selection signal and a word line activation signal to an optimum value without reducing the speed of word line activation. It is intended to provide a semiconductor memory device which solves the above.

(Means for Solving the Problems) In order to solve the above problems, a first invention of the present invention relates to a semiconductor memory device, comprising: a memory cell in which predetermined information is stored; A plurality of predecoders for outputting a predecode address signal in response to the internal address signal; a plurality of predecoders for outputting a predecode address signal in response to the internal address signal; A decoder that outputs a word line selection signal in response to a signal, a word line activation signal transfer circuit that transfers a word line activation signal to the word line in response to the word line selection signal, and a plurality of the predecoders A detection circuit that receives all of the predecode address signals output by the detection circuit and outputs a detection signal;
A word line activation signal output circuit for outputting the word line activation signal in response to the detection signal.

In the semiconductor memory device of the second invention, the first and second memory cell arrays each including a memory cell storing predetermined information and a word line electrically connected to the memory cell, and responding to an external address signal An address buffer for outputting an internal address signal, a first predecoder for outputting a first predecode address signal in response to the internal address signal, and a second predecode in response to the internal address signal A second predecoder for outputting an address signal, a circuit for selecting one of the first and second memory cell arrays in response to the first predecode address signal, and a second predecode address signal And a decoder for outputting a word line selection signal in response to the word line selection signal, and a word line activation signal in response to the word line selection signal to the word line. A word line activation signal transfer circuit for transmitting the first predecode address signal and the second predecode address signal, and a detection circuit for outputting a detection signal; A word line activation signal output circuit for outputting a line activation signal.

(Operation) According to the first and second aspects of the present invention, it is impossible to predict in advance which signal of the output of the predecoder is most delayed due to the presence of changes in device parameters, voltage, temperature, and the like. Receive all of the predecode address signals output from the plurality of predecoders (first and second predecoders) at the time of access, and detect, for example, the slowest predecode address signal among the signals. This detection signal is applied to a word line activation signal output circuit. The word line activation signal output circuit generates a word line activation signal from the input detection signal, and supplies the word line activation signal to the word line activation signal transfer circuit. Then, the word line activation signal transfer circuit reliably transfers the word line activation signal to the word line without a loss time in response to the word line selection signal, and drives the word line. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 shows a first embodiment of the present invention and is a configuration block diagram of a word line selection drive circuit in a DRAM.

The word line selection drive circuit 40 selects a word line selection signal AD for driving one word line 65 from a row address A which is an external address signal.
And a word line activation circuit 50 that outputs a word line activation signal S52, and a word line driver (word line activation that is turned on and off by a word line selection signal AD and drives a word line 65 by a word line activation signal S52 Signal transfer circuit) 60.

The word line selection circuit 40 outputs a row address strobe signal
M address buffers 41-11 to 41-1m,..., 41-n1 to 41-nm which are activated by the RAS and take in the row address A
Address buffer groups 41-1 to 41-n consisting of
N output from each address buffer group 41-1 to 41-n
N predecoders 42-that predecode a set of output address groups AO1 to AOn and output n sets of predecode address groups PD1 to PDn in which at least four or more become one set
And a decoder 43 for outputting a word line selection signal AD by decoding the predecode address groups PD1-PDn.
And it is comprised.

The word line activation circuit 50 detects the latest predecode address in the n sets of predecode address groups PD1 to PDn, and outputs, for example, a detection signal WO of “H” level, and the detection signal WO And a signal generating circuit (word line activating signal output circuit) 52 for generating a word line activating signal S52 of Vcc level or higher, for example. The signal generating circuit 52 is configured by, for example, a bootstrap circuit using a transistor and a capacitor.

2, the gate of the word line driver 60 is connected to the power supply potential Vcc, the drain of the NMOS 61 is connected to the word line selection signal AD, the gate is connected to the source of the NMOS 61, and the drain is connected to the word line active line. The source is connected to the word line 65 and the NMOS 62 whose source is connected to the word line 65, respectively. The word line 65 is connected to a memory cell array (not shown).

FIG. 4 is a circuit diagram showing a configuration example of the detection circuit 51 of FIG.

This detection circuit 51 inverts the n predecode address detection circuits 70-1 to 70-α, the α gate NAND gate 80 connected to the outputs NO1 to NOα, and the output of the NAND gate 80. And an inverter 85 that outputs the detection signal WO. Each predecode address detection circuit 70-1
70-n is a group of predecode addresses PD1 (= PD1-1 to PD1-1).
1-1), PD2 (= PD2-1 to PD2-1) to PD (n-1)
(= PD (n-1) -1 to PD (n-1) -1), PDn (= PD
n-1 to PDn-1), respectively, and 2 sets of NOR gates 71-1 to 72-1..., 71-n to 72-n, and α 2-input NORs for inputting their outputs And gates 73-1 to 73-α. The NAND gate 80 includes a plurality of P-channel MOS transistors (hereinafter, referred to as PMOS) 81, 82, and NMOSs 83, 84,.

FIG. 5 is a timing chart of FIG. 1. The operation of FIGS. 1 and 4 will be described with reference to FIG.

In FIG. 1, when an unillustrated memory cell array is accessed, the row address strobe signal RAS is set to "H".
At the level, each of the address buffer groups 41-1 to 41-n
Captures the row address A and outputs the output address groups AO1 to AOn
Is output. The output address groups AO1 to AOn are predecoded at the time t11 by the predecoders 42-1 to 42-n to decode the word line selection signal AD.
After decoding to 1 to PDn, the decoder 43 and the detection circuit
Supplied to 51. The decoder 43 decodes the predecode address groups PD1 to PDn, outputs a word line selection signal AD for activating one word line 65, and supplies it to the word line driver 60. In the word line driver 60, for example, Vc
NMOS6 is turned on by the word line selection signal AD of c level.
The source of 1, ie, the gate of the NMOS 62, rises to the potential (Vcc-Vt) (where Vt is the threshold voltage of the NMOS 61), and the NMOS 62 is turned on.

On the other hand, the detection circuit 51 includes the predecode address groups PD1 to PDn
, And outputs the detection signal WO to the signal generation circuit 52. Here, the operation of the detection circuit 51 will be described with reference to FIG.

In FIG. 4, when resetting the row address strobe signal RAS to the “L” state, the predecode address PD
1 (= PD1-1 to PD1-1), ..., PDn (= PDn-1 to PDn-
l) is fixed at "L". When the row address strobe signal RAS is active in the “H” state, the row address A causes the predecode address PD1 (= PD1-1 to PD1-
l),..., PDn (= PDn−1 to PDn−1), only one address changes from “L” to “H”. That is, l, that is, one predecode address group is composed of, for example, four or more predecode addresses, and only one address is changed from "L" to "L". When the predecode addresses “L” and “H” are determined, the NOR gates 71-1 and 72-1 to 71-n,
72-n and NOR gates 73-1 to 73-α, the NOR
The outputs NO1 to NOα of the gates 73-1 to 73-α become “H”.
When the outputs NO1 to NOα all become “H”, the detection signal WO output from the inverter 85 becomes “H” by the NAND gate 80 and the inverter 85, and the decoder 43 enters the decoding state of the word line selection signal AD. That signal generator
Transmit to 52. At time t12 in FIG. 5, the signal generation circuit 52 receives the detection signal WO and outputs, for example, a word line activation signal S52 of Vcc level or higher. As described above, when the word line selection signal AD is decoded and the word line activation signal S52 is output thereafter, the N in the word line driver 60 is
The drain potential of the MOS62 rises to, for example, the Vcc level
The gate potential of the NMOS 62 rises above the Vcc level and the NMO
S61 is turned off. Therefore, one word line 65 connected to the source side of the NMOS 62 is activated to the Vcc level or higher.

Here, it is conceivable that an address speed difference occurs due to a difference in the load of the word line selection signal AD (including the load of the output address groups AO1 to AOn and the predecode address groups PD1 to PDn). However, the detection circuit 51 is configured to transmit the detection signal WO to the signal generation circuit 52 after outputting "H" of the slowest predecode address for any row address A. Therefore, the word line activation signal S52 is not output before the word line selection signal AD is decoded, thereby preventing a malfunction.

As is clear from the timing charts of FIGS. 3 and 5, in the conventional circuit, a delay circuit 21 is provided, the timing is adjusted by the delay time T, and a margin is provided for the timing to prevent malfunction. So
The delay time T is long. On the other hand, in the present embodiment, since the detection circuit 51 is provided in place of the conventional delay circuit 21, the detection of the row address trobe signal RAS (t1
The delay time Ta from 1) to the rise (t12) of the word line activation signal S52 is short, and the delay time Ta is also set appropriately by the word line activation circuit 50. Further, deviations in device parameters, voltage, temperature, and the like can be reduced because the delay time Ta is short, so that characteristics such as temperature are good, and high-speed word line activation can be expected.

In addition, in this embodiment, there are advantages that the word line activation circuit 50, that is, the timing circuit can be simplified, and that the circuit and the timing can be shared.

FIG. 6 shows a second embodiment of the present invention and is a configuration diagram of a word line selection drive circuit in a DRAM.

This word line selection drive circuit is applied to memory cell arrays 90-1 to 90-1 divided into l (for example, ≧ 4) blocks, and for simplicity of description, the elements in FIG. Common elements are denoted by common reference numerals. However, while the circuit of FIG. 1 is applied to a single memory cell array, the circuit of FIG. 6 is applied to a plurality of divided memory cell arrays 90-1 to 90-1. Therefore, the numbers of the address buffer groups 41-1 to 41-n and the like are denoted by the same reference numerals, but the numbers can be appropriately changed so as to conform to the divided operation type structure.

The word line selection drive circuit includes n address buffer groups 41-1 to 41-n that receive a row address A and output output address groups AO1 to AOn, and output address groups AO1 to AO.
Predecode (n-1) to predecode address group
(N-1) predecoders 42-1 to 42- (n-1) for outputting PD1 to PD (n-1) and an output address group for enabling divided read / write operation of the memory cell array A pre-decoder 42-n for pre-decoding AOn and outputting a pre-decode address group PDn, and a word line selection signal A for decoding pre-decode address groups PD1 to PD (n-1).
And a decoder 43 for outputting D, and these constitute a word line selection circuit.

The word line activation circuit is connected to each predecode address group PD
1 detection circuits 51-1 to 51-1 that input 1 to PDn and output a detection signal WO, respectively, and 1 signal generation circuit that outputs a word line activation signal S52 from each detection signal WO ( (Word line activation signal output circuit) 52-1 to 52-1. n predecode address groups PD1 to PDn
Among them, the n-th address group PDn is, as described above,
For example, it is composed of four or more predecode addresses, and only one address changes from "L" to "H" when active. The same applies to PD1 to PD (n-1). Each one of the n-th predecode address group PDn is connected to each of the detection circuits 51-1 to 51-1.

One word line driver (word line activation signal transfer circuit) 60-1 to 60-1 connected to the decoder 43 and the signal generation circuits 52-1 to 52-1 is connected to the word lines 65-1 to 65-l. l
Are connected to the memory cell arrays 90-1 to 90-1 respectively.

In the above configuration, the row address strobe signal RA
When S is active in the "H" state, the memory cell array 90-1 divided into l blocks by one address from "L" to "H" among the predecode addresses PDn output from the predecoder 62-n. One memory cell array to be accessed is selected from .about.90-1. A detection circuit 51- provided for each of the memory cell arrays 90-1 to 90-1
1 is a group of predecoded addresses PD1 to PD (n-n) pre-decoded by the predecoders 42-1 to 42- (n-1).
The slowest address is detected from the address that has changed from “L” to “H” in 1) and one address that has changed from “L” to “H” in the predecode address group PDn. WO
Is transmitted to the signal generation circuits 52-1 to 52-1. Then, the signal generating circuits 52-1 to 52-1 and the word line driver 60-
1 to 60-l activates one of the word lines 65-1 to 65-1 and has the same advantages as the first embodiment.

As in semiconductor storage devices such as DRAMs, when splitting a memory cell array to reduce current consumption,
By using the second embodiment, the memory cell array 90-1
No matter which of the blocks 90-1 is selected, the word lines 65-1 to 65-1 can be activated at high speed without malfunction.

The present invention is not limited to the illustrated embodiment. For example, the detection circuits 51, 51-1 to 51-1 may be constituted by circuits other than those shown in FIG. 4, or the word line drivers 60, 60-1 to 60-1 may be used. Can be variously modified, for example, by using another transistor configuration such as a PMOS, or by applying the present invention to another semiconductor memory device such as a static RAM.

(Effects of the Invention) As described in detail above, according to the first and second inventions, a detection circuit is provided, and a predecode address signal output from a plurality of predecoders (first and second predecoders) And outputs a detection signal. Therefore, the timing shift between the word line selection signal and the word line activation signal can be performed without predicting in advance which signal among the outputs of the predecoder is delayed most due to the presence of changes in device parameters, voltage, temperature, and the like. And the word line can be activated at a high speed because an extra delay time for timing adjustment is not required.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a word line selection drive circuit in a DRAM showing a first embodiment of the present invention, FIG. 2 is a configuration diagram of a word line selection drive circuit in a conventional DRAM, and FIG. FIG. 4 is a timing chart of FIG. 1, FIG. 5 is a timing chart of FIG. 1, and FIG.
FIG. 3 is a configuration diagram of a word line selection drive circuit in a DRAM showing the embodiment of FIG. 40 word line selection circuits, 41-1 to 41-n address buffer groups, 42-1 to 42-n predecoders, 43
Word line, 50 ... Word line activation circuit, 51, 51-1 to 51
-L detection circuit, 52, 52-1 to 52-1 ... signal generation circuit, 60, 60-1 to 60 to l ... word line driver, 65, 65-
1 to 65-1 word line, 90-1 to 90-1 memory cell array, A row address, AO1 to AOn output address group, AD word line selection signal, PD1 to PDn Predecode address group, S52 ... word line activation signal, WO ...
... Detection signal.

Claims (2)

(57) [Claims] A memory cell storing predetermined information; a word line electrically connected to the memory cell; an address buffer outputting an internal address signal in response to an external address signal; A plurality of predecoders for outputting a predecode address signal in response to a signal; a decoder for outputting a word line selection signal in response to the predecode address signal; and a word line activation in response to the word line selection signal A word line activation signal transfer circuit that transfers a signal to the word line; a detection circuit that receives all of the predecode address signals output from the plurality of predecoders and outputs a detection signal; A word line activation signal output circuit for outputting the word line activation signal. A memory cell storing predetermined information and first and second memory cell arrays each including a word line electrically connected to the memory cell; and an internal address signal in response to an external address signal. , An output buffer that outputs a first predecode address signal in response to the internal address signal, and an output buffer that outputs a second predecode address signal in response to the internal address signal A second predecoder, a circuit for selecting one of the first and second memory cell arrays in response to the first predecode address signal, and a word in response to the second predecode address signal A decoder for outputting a line selection signal; and a word line for transferring a word line activation signal to the word line in response to the word line selection signal. Activating signal transfer circuit; a detection circuit that receives the first predecode address signal and the second predecode address signal and outputs a detection signal; and the word line activation signal in response to the detection signal. And a word line activating signal output circuit for outputting a signal.