JP2555135B2 - Arithmetic circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology (Figs. 5 and 6) Problem to be solved by the invention Means for solving the problem Action Example Example of the present invention (FIGS. 1 to 4) Effects of the Invention [Summary] An arithmetic circuit for performing arithmetic operation on a numerical value in floating point notation, with the purpose of providing an arithmetic circuit capable of speeding up arithmetic processing. An arithmetic circuit that performs an operation of two numbers by the represented floating-point notation, has a predetermined number of additional bits in the lower digit of the mantissa, and performs normalization and rounding processing according to the operation result of the mantissa. In, when the shift amount of the normalization based on the operation result of the mantissa exceeds the number of additional bits, the mantissa is shifted and the least significant bit of the mantissa is rounded in parallel, and both are processed. First to synthesize Execution means, shift means for shifting the mantissa part for normalization within the range of the additional bit number based on the operation result of the mantissa part, and the shift amount for normalization based on the operation result of the mantissa part is the additional bit or less , The digit shift of the mantissa part caused by the rounding process is
The second execution means is set in advance as a rounding processing result, and one of them is selected, and the first execution is performed depending on whether the shift amount for normalization based on the operation result of the mantissa exceeds the additional bit. Means or selecting means for selectively selecting the output of the second executing means.

[Industrial applications]

The present invention relates to an arithmetic circuit, and more particularly, to an arithmetic circuit that operates on a numerical value in floating point notation.

Fixed-point representation cannot represent very large numbers because the range of numbers that can be represented is narrow. In addition, the fixed-point representation usually handles only integers in many cases, and thus a notation for expressing real numbers required for scientific and technological calculations is separately required. For this reason, the floating point notation (floating notation) that combines two numbers called the mantissa and exponent is used.
point representation) was considered.

A general floating-point number is represented as follows when the radix is R.

(−1) ^s · m · R ^e Here, s is a sign, and s = 0 when it is positive and s = 1 when it is negative. In addition, m and e are mantissas (mant
issa), exponent, which is a combination of fixed-point representations of these is the floating-point representation in the computer. In the floating-point representation, the length of the mantissa m determines the length of the effective digit. Therefore, when an accurate numerical value is required, an expression with a large mantissa length is used.

Such floating point arithmetic has a wider dynamic range and higher accuracy than integer arithmetic, and in particular, recently there is a tendency to demand high speed arithmetic so as to meet various sophisticated arithmetic demands.

[Conventional technology]

Currently, the most widely used binary floating point standards are IEEE, DEC, IBM and MIL-Std-1750A. Each represents a single-precision floating point with a 32-bit word length. Both standards support double precision data,
Some of them support other data formats such as extended format single precision and extended format double precision. Of these, the IEEE working group is ANSI / IEEE Std 754-198.
5 (Standards) (The standard was finalized in 1985.)
The following specifications are proposed as a powerful standard for highly portable floating point software. This standard proposal has received widespread support and is considered to be the basis for most of the future hardware.

As a conventional arithmetic circuit of this type of IEEE floating point format, there is one as shown in FIG. 5, for example. This example is an example of performing addition of two normalized input numbers (input data) between normalized numbers or between normalized numbers and non-normalized numbers. In particular, FIG. 5 shows addition processing. 4 is a block diagram after the addition of the mantissa part by the adder is completed and the mantissa part is stored in the pipeline register 1. 2 is a register of the exponent part.
The calculation of the sign bit is omitted in the figure. The operations of post-normalization (normalization) and round (rounding) will be described with reference to FIG.

Note that normalization is to prevent the most significant digit of the mantissa part from being "0", and rounding is to reduce the overflowed part of the lower part when the operation result exceeds the predetermined number of digits and cannot be stored. It is processing, that is, rounding by a method such as truncation. Since the cumulative error may be greatly affected by the rounding method, there are methods such as rounding toward a neighboring value and rounding toward 0. The format of the data stored in the pipeline register 1 is shown in FIG. 6, and the main symbols have the following meanings.

V: Mantissa overflow bit G: Guard bit R: Round bit S: Sticky bit Now, in post normalization, it is necessary to shift the mantissa so that V = φ and N = 1. First,
The priority encoder (PE) 3 counts the number of consecutive "φ" from the V bit, and the value is shifted (shifte).
r) 4, and also inputs to the adder 5 of the exponent part. Then, the shifter 4 shifts only the necessary bits to complete the post normalization.

Next, a round is performed. The round is executed by the round circuit 6 by rounding down or rounding up the R bit as necessary. At this time, if the data of the mantissa part is, for example, [1 · 11 to 110] and R = 1, an overflow occurs, so that it is necessary to shift the value by 1 bit to the right again and to add “1” to the adder 5. There is. The data of the mantissa part after the round is completed is stored in the register 7 on the output side, and the data of the exponent part is similarly stored in the register 8.

[Problems to be Solved by the Invention]

However, in such a conventional arithmetic circuit, since the round is performed after the normalization, the whole arithmetic processing time is long and there is a problem that it is difficult to meet the recent demand for high speed. .

Therefore, an object of the present invention is to provide an arithmetic circuit that can speed up arithmetic processing.

[Means for solving the problem]

In order to achieve the above object, the arithmetic circuit according to the present invention calculates two numbers by a floating point notation represented by an exponent part and a mantissa part, and has a predetermined number of additional bits in the lower digit of the mantissa part. In an arithmetic circuit that performs normalization and rounding processing according to the calculation result of the mantissa part, when the shift amount for normalization based on the calculation result of the mantissa part exceeds the number of additional bits, the mantissa part is shifted, First execution means for processing the rounding of the least significant bit of the mantissa in parallel and synthesizing the two, and the mantissa for normalization within the range of the additional bit number based on the operation result of the mantissa. When the shift means for shifting and the shift amount for normalization based on the operation result of the mantissa part are less than or equal to the additional bits, the digit shift of the mantissa part caused by the rounding process is preset as the rounding process result for each mode. And, depending on whether or not the second execution means for selecting one from among them, the shift amount of the normalization based on the operation result of the mantissa exceeds the additional bits, the first
And an selecting means for selectively selecting the output of the executing means or the second executing means.

[Work]

In the present invention, when the shift amount for normalization based on the operation result of the mantissa exceeds the number of additional bits, rounding processing is performed in parallel for the shift of the mantissa for normalization and the least significant bit. On the other hand, when the normalization shift amount is equal to or less than the additional bits, the digit shift of the mantissa part generated by the rounding process is preset for each mode, and the corresponding one is selected from them. Also in this case, rounding and mantissa shift are performed in parallel.

Therefore, unlike the sequential processing, since the normalization and the rounding are performed in parallel, the calculation speed is significantly improved.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 4 are diagrams showing an embodiment of an arithmetic circuit according to the present invention. FIG. 1 is a diagram showing a calculation block for performing round processing after the addition of the mantissa part is completed. First, the configuration will be described. In FIG. 1, reference numeral 11 denotes a register, which is composed of, for example, a pipeline register and stores 28-bit data in the arrangement shown in the figure, of which three bits G, R and S ( Additional bits), which is the same as the conventional one. Reference numeral 12 is a sign register, and the sign register 12 indicates whether the data is positive or negative. Stores 1-bit code data (SGN). For example, "0" represents positive and "1" represents negative.

The output of register 11 is taken out as 28 bits, and shifter 1
3, 14, a priority encoder PE15, a 4-bit priority encoder (4bPE) 16 and an LSB circuit 17. The priority encoder PE15 counts the number of consecutive "0" s from the V bit, sends the value to the shifter 13, and sends it to an exponent adder (not shown) (not shown). The shifter 13 performs a shift operation on 27 bits of the 28-bit mantissa excluding S based on the output from the priority encoder PE15, and sends the shifted 23-bit data to the selector 18. LSB circuit 17 is register 1
The LSB is determined based on the mode request RP, RM from 5 data of V, N ₁ , N ₂ , N ₃ and S bits of the 28-bit data of 1. The detailed circuit is shown in FIG. As shown.

That is, as shown in FIG. 2, the LSB circuit 17 has V, N ₁ , and N
₂ , NOR gate 21 for each bit of N ₃ and mode R
OR gate 22a to which M, S bit and SGN are input,
Inverter 22b that inverts the S bit and modes RP and S
OR gate 22c to which inverted signal of bit and SGN is input
And a NAND gate 23a for obtaining a NAND between the OR gate 22a and the OR gate 22c, and a NAND gate 23a and a NAND gate 21.
And an AND gate 23b for determining AND of 2 and 1. The determination of LSB is specifically shown in a separate table, and 1-bit data indicating the determined LSB is input to the selector 18. The shifter 13, the priority encoder 15 and
The LSB circuit 17 constitutes the first executing means 19 as a whole.

The 4-bit priority encoder 16 is
Of the 28-bit data, the number of consecutive "0" from the V bit is counted for 4 bits of V, N ₁ , N ₂ and N ₃ and the value is sent to the shifter 14. The concrete circuit is shown in FIG. As shown. That is, as shown in FIG. 3, the 4-bit priority encoder 16 is composed of gates 24 to 26 having at least one low active terminal, and R ₁ : right according to the value of “0” consecutive from the V bit. 1 bit shift R ₂ : No shift L ₁ : Left 1 bit shift L ₂ : Left 2 bit shift Determines four states and sends the shift request to the shifter 14, and sends the shift request to the exponent adder. Shifter
14 shifts the 28-bit data from the register 11 by a predetermined amount in accordance with the shift request from the 4-bit priority encoder 16, and outputs the shifted data to the LSB addition circuit 31,
Send to round circuit 32 and selector 33. Shifter 14 above
And the 4-bit priority encoder 16 constitutes a shift means 27.

The LSB adder circuit 31 increments “1” in advance with respect to the shifted data sent by the shifter 14, and the incremented data is a 24-bit selector 33.
And the overflow signal OVF is sent to the exponent partial adder. Further, the round circuit 32 uses the 4-bit data from the register 11, that is, LSB, G ',
Mode request R from R ', S' (dash represents data after shift) and code bit SGN from code register 12
Round processing is performed based on N, RP, RM, and RZ, and a specific circuit is shown in FIG. That is, the fourth
In the figure, a round circuit 32 includes gates 41 to 46 having at least one low active terminal and an OR gate.
47 to 50, an inverter 51, and AND gates 52 to 56. The round processing is shown in a separate table. Either rounding down or adding +1 to LSB is executed, and the output from the round circuit 32 is 2 The bits are control signals of the selector 33 and are sent to the selector 33 which has nothing to do with the G and R bits.

The higher-order 24-bit data from the shifter 14 and the 24-bit data from the LSB adder circuit 31 are input to the selector 18, and the selector 33 outputs the LSB adder circuit 31 or the shifter 14 based on the 2-bit data from the round circuit 32. The data is selected and output to the selector 18. The selector 18 selects the 24-bit data from the shifter 13 and the LSB circuit 17 from the selector 33 according to the control request for the post normalization round.
Alternatively, the 24-bit data is selected and the selected data is output and sent to the register 57. As shown in FIG. 1, the output register 57 stores 24-bit data which has been subjected to normalization and round processing represented by [1, m ₂₃ , ..., M ₂ , m ₁ ].

The LSB adder circuit 31, the round circuit 32, and the selector 33 constitute the second executing means 58 as a whole, and the selector 18 constitutes the selecting means.

 Next, the operation will be described.

In the data in which 3 bits are added to the lower digit of the LSB as in the present embodiment, the data content of the lower bit including the LSB depends on the round processing of the 3 bits even after normalization. However, since the additional bits are 3 bits, only a maximum shift of 3 bits is performed. For example, in post-normalization, when a 3-bit left shift operation is performed, no carry occurs when the round is executed no matter which round the round is performed after the left shift operation is performed. Therefore, only the shift operation is required.

Therefore, in the present embodiment, paying attention to the above facts, a shift that exceeds 3 bits and a shift that is within 3 bits and that has undergone round processing (including all round processing in this embodiment) The calculation processing time is shortened by performing the calculation in parallel processing in advance and then simply selecting the corresponding processed data by the selector 18.

Normalization with more than 3 bits The shift amount is detected by the priority encoder 15 and shifted by the shifter 13. At the same time, the LSB value is determined by the LSB circuit 17 based on the round processing request, and both are combined. And sent to the selector 18 as 24-bit data. Then, the 24-bit data is directly selected by the selector 18,
It is stored in the output register 57. It should be noted that the storage register of the output register 57 does not include the V bit and is always V = 0.
Is hidden. Therefore, in the case of normalization of more than 3 bits in this way, normalization and round processing are executed in parallel and only knitting is required. Therefore, the overall operation processing time is shortened compared to the conventional case, and the speed is increased. be able to.

In case of normalization within 3 bits Since the shift amount is within 3 bits, first register
Of the 28 bits stored in 11, the number of consecutive "0" from V bit for V ₁ , N ₁ , N ₂ and N ₃ is counted by the 4-bit priority encoder 16 and is registered by the shifter 14 according to the value. 27-bit data excluding S bits from 11 is pre-shifted by a predetermined amount within 4 bits. After that, a value assuming all situations for the round process is created in advance. Specifically, the following four cases can be considered.

(I) When V ₁ N ₁ N ₂ N ₃ = 1XXX However, X is 1 or 0. Since V = 0 in this case, a 1-bit right shift operation is required.

(II) VN ₁ N ₂ N ₃ = 01XX Normalized, no shift (III) VN ₁ N ₂ N ₃ = 001X 1-bit left shift required (IV) VN ₁ N ₂ N ₃ = 0001 2-bit left shift is required. These round processes are preliminarily performed by the round circuit 32 by the mode requests RN, RP, RM, and RZ as shown in a separate table, and then the selector 33 based on the output of the round circuit 32.
Thus, either +1 is added to LSB or truncation is selected, and 24-bit data is output to the selector 18. Then, according to the control request, the output data from the selector 33 is selected by the selector 18 and stored in the output register 57.

In such a case, since the normalization is within 3 bits, the shift amount is limited to a maximum of 4 bits or less, so that the process can be performed by a 4-bit logic circuit and the shift time is short. In addition, all round-cases that have been assumed in advance are set for round processing, and it is only necessary to select one of them, and this round processing is performed by logic circuits arranged in parallel. Therefore, unlike the prior art, the entire calculation processing time is shortened and the speed can be increased.

In this embodiment, GRS is added as an additional bit in the last digit of LSB.
Is an example of adding 3 bits, but the number of additional bits is 3
The number is not limited to bits and may be another number. Further, the round mode request is not limited to the mode of the above embodiment, and may be another example. Further, the description has been given using the IEEE standard single precision floating point data format, but other examples such as double precision may be used. Further, it may be a data format such as IBM or DEC format.

[Effect]

According to the present invention, since the normalization and rounding processes are executed in parallel while considering the additional bits, the delay can be reduced, the operation time can be shortened, and the processing speed can be increased. .

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 4 are diagrams showing an embodiment of an arithmetic circuit according to the present invention, FIG. 1 is an overall block diagram thereof, and FIG. 2 is a circuit diagram of its LSB circuit. 3 is a circuit diagram of the 4-bit priority encoder, FIG. 4 is a circuit diagram of the round circuit, FIGS. 5 and 6 are diagrams showing a conventional arithmetic circuit, FIG. 5 is a block diagram thereof, and FIG. FIG. 6 is a diagram showing data formation of the register. 11 …… Register, 12 …… Sign register, 13,14 …… Shifter, 15 …… Priority encoder, 16 …… 4-bit priority encoder, 17 …… LSB circuit, 18 …… Selector, 19 …… First execution Means, 27 ... Shift means, 57 ... Output register, 58 ... Second execution means.

Claims (1)

(57) [Claims] 1. A floating point notation represented by an exponent part and a mantissa part is used to calculate two numbers, and a predetermined number of additional bits are provided in the lower digit of the mantissa part according to the result of the mantissa part calculation. In an arithmetic circuit that performs normalization and rounding processing, when the shift amount of normalization based on the operation result of the mantissa exceeds the number of additional bits, the mantissa is shifted and the least significant bit of the mantissa is calculated. First execution means for processing the rounding of the numbers in parallel and synthesizing them, shift means for shifting the mantissa part for normalization within the range of the additional bit number based on the operation result of the mantissa part, and mantissa When the normalization shift amount based on the calculation result of the part is equal to or less than the additional bit, the digit shift of the mantissa part generated by the rounding process is preset as a rounding process result for each mode, and one of them is set. Choice The second execution means for performing the first execution means or the second execution means depending on whether the shift amount for normalization based on the operation result of the mantissa exceeds the additional bit.
And a selecting means for selectively selecting the output of the executing means.