[go: up one dir, main page]

JP2025121584A - Silicon epitaxial substrate and method for heat treatment of silicon substrate - Google Patents

Silicon epitaxial substrate and method for heat treatment of silicon substrate

Info

Publication number
JP2025121584A
JP2025121584A JP2024017105A JP2024017105A JP2025121584A JP 2025121584 A JP2025121584 A JP 2025121584A JP 2024017105 A JP2024017105 A JP 2024017105A JP 2024017105 A JP2024017105 A JP 2024017105A JP 2025121584 A JP2025121584 A JP 2025121584A
Authority
JP
Japan
Prior art keywords
silicon substrate
heat treatment
substrate
temperature
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2024017105A
Other languages
Japanese (ja)
Other versions
JP7694736B1 (en
Inventor
剛 大槻
真彩 久保田
温 鈴木
寿樹 松原
達夫 阿部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP2024017105A priority Critical patent/JP7694736B1/en
Priority to PCT/JP2025/001240 priority patent/WO2025169680A1/en
Application granted granted Critical
Publication of JP7694736B1 publication Critical patent/JP7694736B1/en
Publication of JP2025121584A publication Critical patent/JP2025121584A/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02Heat treatment

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Thermal Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

【課題】
窪み状の欠陥の生成が抑制されたSi{110}基板及びSi{110}基板の熱処理方法を提供することを目的とする。
【解決手段】
主面の面方位が{110}のシリコン基板であって、表面に長手方向の長さが50nm以上2000nm以下の窪み状欠陥を含まないものであることを特徴とするシリコン基板。
【選択図】図1

【assignment】
An object of the present invention is to provide a Si{110} substrate in which the generation of depression-like defects is suppressed, and a method for heat treating a Si{110} substrate.
[Solution]
A silicon substrate having a principal surface with a {110} plane orientation, characterized in that the silicon substrate does not contain depression-like defects having a longitudinal length of 50 nm or more and 2000 nm or less on the surface.
[Selected Figure] Figure 1

Description

本発明は、シリコン基板及びシリコン基板の熱処理方法に関する。 The present invention relates to a silicon substrate and a method for heat treating a silicon substrate.

現在のロジックICに採用されているFin構造に代わり、次世代以降の半導体ではGAA(Gate-All-Around)構造や、さらにNMOSとCMOSを積層するCFET(Complementary Field Effect Transistor)が提案され、積極的に研究開発がなされている。この際、正孔移動度を向上させる手法として、シリコン(以下、「Si」ともいう)のいくつかある面方位のうち(110)を利用することが検討されている(非特許文献1)。 In place of the Fin structure currently used in logic ICs, next-generation semiconductors are being proposed with GAA (Gate-All-Around) structures and even CFETs (Complementary Field Effect Transistors) stacking NMOS and CMOS, and these structures are being actively researched and developed. In this regard, one method of improving hole mobility is to use the (110) plane orientation of silicon (hereinafter also referred to as "Si"), one of several available plane orientations (Non-Patent Document 1).

特開2008-091887号公報JP 2008-091887 A 特開2006-100596号公報Japanese Patent Application Laid-Open No. 2006-100596 特開2008-088045号公報Japanese Patent Application Laid-Open No. 2008-088045 特開2014-239184号公報JP 2014-239184 A 特開2008-091891号公報Japanese Patent Application Laid-Open No. 2008-091891 特開2001-253797号公報Japanese Patent Application Laid-Open No. 2001-253797

応用物理学会 半導体の結晶成長と加工および評価に関する産学連携委員会 第1回研究会 「半導体復権を支える結晶技術」The 1st Workshop of the Industry-Academia Collaboration Committee on Crystal Growth, Processing, and Evaluation of Semiconductors, Japan Society of Applied Physics, "Crystal Technology Supporting the Revival of Semiconductors" 山田他、「Si(110)-16×2単一ドメイン表面の作製」、 表面科学、29(7)、 401(2008)Yamada et al., "Fabrication of Si(110)-16x2 Single Domain Surface," Surface Science, 29(7), 401 (2008) 宮地他、「超高真空非接触原子間顕微鏡によるSi(110)再構成表面の観察」、 日本金属学会誌、 72(4)、 290(2008)Miyaji et al., "Observation of Si(110) reconstructed surface using ultra-high vacuum non-contact atomic force microscope," Journal of the Japan Institute of Metals, 72(4), 290 (2008)

しかしながら、Si(110)基板は、表面ラフネス、ヘイズが大きいという問題が指摘されている(非特許文献1)。ここでヘイズは、表面の曇り度合いとも言われ、表面粗さを光の散乱度合いで表したものであり、ヘイズが大きいほど表面が粗いことを意味する。また、Si(110)最表面の最安定構造が確認されたのは比較的最近(非特許文献2、3)である。 However, problems with Si(110) substrates have been pointed out, such as high surface roughness and haze (Non-Patent Document 1). Haze, also known as the degree of cloudiness of the surface, represents surface roughness as a measure of the degree of light scattering, with higher haze indicating a rougher surface. Furthermore, the most stable structure of the Si(110) outermost surface was only identified relatively recently (Non-Patent Documents 2 and 3).

また非特許文献2、3に記載されている通り、Si(110)の表面構造においては、その最安定構造である16×2ドメイン(構造上の1つのまとまりをもつ領域)は、例えば図2に示すように、温度によって相転換を起こし、600~800℃の範囲で構造が変化するとされている。 Furthermore, as described in Non-Patent Documents 2 and 3, the most stable structure of the Si(110) surface, the 16x2 domain (a region with a single structural unity), undergoes a phase transformation depending on the temperature, as shown in Figure 2, and the structure changes in the range of 600 to 800°C.

また、この構造の変化に伴い、ステップバンチング現象も発生する。ステップバンチングとは、シリコンなどの半導体材料において、ウェーハ表面にステップと呼ばれる原子レベルの段差が存在し、熱処理などにより表面の原子が移動することによりステップが集まり、より大きな段差を形成する現象である。さらに例えば、GAAやCFETで積層されるSiGeのようなものはちょうどこの温度帯の処理を伴うことが多く、より表面構造の理解を困難にしていることが容易に想像でき、この相変化に伴う現象が大きなバイアスとなって、他の現象(欠陥や汚染挙動など)の理解を妨げる原因となっている。 This structural change also leads to the phenomenon of step bunching. Step bunching is a phenomenon in which atomic-level irregularities called steps exist on the wafer surface in semiconductor materials such as silicon, and when surface atoms move due to heat treatment or other processes, the steps gather together, forming larger irregularities. Furthermore, for example, materials such as SiGe, which are stacked in GAA and CFETs, often require processing in this exact temperature range, making it easy to imagine that this makes understanding the surface structure even more difficult. The phenomenon associated with this phase change creates a large bias, hindering understanding of other phenomena (such as defects and contamination behavior).

このSi(110)面独特の最表面構造は、エッチング後の表面構造にも影響を及ぼす。16×2ドメインの表面構造のステップ端はSi(100)のような単原子構造ではなく、2原子分の段差があり、反応系のエネルギーが小さい(平衡反応)場合は、最表面の原子で反応が進行することでエッチング後の表面形状は表面第一近接のSi(111)に囲まれた線状構造になる。一方で、反応系エネルギーが大きい場合は、最表面及びその下の原子まで反応に関与することになり、表面第二近接のSi(111)に囲まれた四角形の形状が現れることになる。 This unique outermost surface structure of the Si(110) surface also affects the surface structure after etching. The step edges of the 16x2 domain surface structure are not single-atom structures like Si(100), but have a two-atom step. When the energy of the reaction system is low (equilibrium reaction), the reaction proceeds at the outermost surface atoms, resulting in a linear surface shape surrounded by the first-nearest neighbor Si(111) atoms after etching. On the other hand, when the energy of the reaction system is high, the outermost surface and atoms below it become involved in the reaction, resulting in a square shape surrounded by the second-nearest neighbor Si(111) atoms.

このような面状態のSi(110)に対して、特許文献1では、エピタキシャル成長時の方位を傾けることで面荒れを低減する手法が公開されている。特許文献2では、同じエピタキシャル成長でも冷却速度の規定と表面保護に関して公開されている。さらに、特許文献3では、エピタキシャル成長時でなく結晶成長時に面方位を規定し、同じように面荒れを低減する方法が公開されている。特許文献4では、エピタキシャル面を研磨することが公開されている。特許文献5には、特許文献1のLPD検出サイズが異なる技術が公開されている。また、特許文献6には、30μm以上と非常に厚いエピタキシャル膜厚であるが、スライス時のオフ角を0.5~7°とすることで、周辺部に円環状に形成される面荒れを低減する方法が開示されている。 For Si(110) with this type of surface state, Patent Document 1 discloses a method for reducing surface roughness by tilting the orientation during epitaxial growth. Patent Document 2 discloses the same epitaxial growth method, but with the specification of the cooling rate and surface protection. Furthermore, Patent Document 3 discloses a method for similarly reducing surface roughness by specifying the surface orientation during crystal growth rather than during epitaxial growth. Patent Document 4 discloses polishing the epitaxial surface. Patent Document 5 discloses a technology that differs from Patent Document 1 in LPD detection size. Furthermore, Patent Document 6 discloses a method for reducing surface roughness that forms in a circular ring shape around the periphery, even when the epitaxial film thickness is very thick at 30 μm or more, by setting the off-angle during slicing to 0.5 to 7 degrees.

一方で本発明者らは、このような面荒れや結晶欠陥に起因する欠陥以外に、特に、Si(110)基板は、Si(100)基板と異なり、最安定構造が16×2の特殊な構造であるために、最安定構造16×2の隣接部は不安定な領域(非特許文献2では、「ディスオーダ領域」と表現されている)があり、この部分から、エピタキシャル成長前の水素ベイクやエピタキシャル成長をはじめとした熱処理によって微小な突起状の欠陥が生成し、Si(110)基板の面内分布が形成されることを明らかにし、この対策を示してきた。 However, the inventors have clarified that in addition to defects caused by such surface roughness and crystal defects, Si(110) substrates, unlike Si(100) substrates, have a special 16x2 most stable structure, and therefore have unstable regions (referred to as "disordered regions" in Non-Patent Document 2) adjacent to the most stable 16x2 structure, and that minute protrusion-like defects are generated from these regions by heat treatments such as hydrogen baking before epitaxial growth and epitaxial growth, forming an in-plane distribution on the Si(110) substrate, and have proposed countermeasures for this.

このように、Si(110)基板表面は、非常に複雑な形状となり、面粗さの緩和に向けて種々の手法が公開されている。しかしながら、特にSi(110)基板は、上述したとおり、Si(100)基板と異なり最安定構造が16×2の特殊な構造であるために、最安定構造16×2の隣接部は不安定な領域があり、この部分を起点として、エピタキシャル成長前の水素ベイクやエピタキシャル成長等の熱処理を行うことで、比較的大きな窪み状の欠陥が生成することを本発明者らは見出した。 As such, the surface of a Si (110) substrate has a very complex shape, and various methods have been published to reduce surface roughness. However, as mentioned above, unlike a Si (100) substrate, the most stable structure of a Si (110) substrate is a special 16x2 structure. Therefore, there are unstable regions adjacent to the most stable 16x2 structure. The inventors have discovered that these regions are the starting point for the generation of relatively large depression-shaped defects when subjected to heat treatments such as hydrogen baking before epitaxial growth or epitaxial growth.

本発明は、上記問題を解決するためになされたものであり、窪み状の欠陥の生成が抑制されたSi{110}基板及びSi{110}基板の熱処理方法を提供することを目的とする。 The present invention was made to solve the above problems, and aims to provide a Si{110} substrate and a heat treatment method for a Si{110} substrate in which the generation of pit-like defects is suppressed.

本発明は、上記目的を達成するためになされたものであり、主面の面方位が{110}のシリコン基板であって、表面に長手方向の長さが50nm以上2000nm以下の窪み状欠陥を含まないものであることを特徴とするシリコン基板を提供する。 The present invention has been made to achieve the above-mentioned objective, and provides a silicon substrate characterized by a principal surface having a {110} plane orientation and containing no depression-like defects on the surface with a longitudinal length of 50 nm or more and 2000 nm or less.

このようなシリコン基板によれば、窪み状欠陥がなく表面粗さが改善された高品質なものとなり、デバイス特性の向上が図れるものとなる。 Such silicon substrates are of high quality, free of pit-like defects and with improved surface roughness, resulting in improved device characteristics.

このとき、前記シリコン基板は、主面{110}の面方位のオフ角が0.23°以上のものとすることができる。 In this case, the silicon substrate may have an off-angle of 0.23° or more in the plane orientation of the {110} principal surface.

これにより、表面粗さがより改善され、さらにデバイス特性の向上が図れるものとなる。 This will further improve surface roughness and further enhance device characteristics.

本発明はまた、上記目的を達成するためになされたものであり、主面の面方位が{110}のシリコン基板の熱処理方法であって、前記熱処理方法は、前記シリコン基板を570℃より高い熱処理温度まで昇温する昇温工程と、該熱処理温度で熱処理を行う熱処理工程と、570℃より低い温度まで冷却する冷却工程とを有し、前記昇温工程において前記シリコン基板の温度が570℃に達した時点から前記冷却工程において前記シリコン基板の温度が570℃に達した時点までの期間中の前記シリコン基板の温度と時間の積の総和を60000(℃・sec)以下とすることを特徴とするシリコン基板の熱処理方法を提供する。 The present invention has also been made to achieve the above-mentioned object, and provides a heat treatment method for a silicon substrate having a {110} principal surface orientation, the heat treatment method comprising a heating step of heating the silicon substrate to a heat treatment temperature higher than 570°C, a heat treatment step of performing heat treatment at that heat treatment temperature, and a cooling step of cooling the silicon substrate to a temperature lower than 570°C, wherein the sum of the product of the temperature and time of the silicon substrate during the period from when the temperature of the silicon substrate reaches 570°C in the heating step to when the temperature of the silicon substrate reaches 570°C in the cooling step is 60,000 (°C·sec) or less.

このようなシリコン基板の熱処理方法によれば、窪み状の欠陥の生成を抑制することが可能になる。 This type of heat treatment method for silicon substrates makes it possible to suppress the formation of pit-like defects.

このとき、前記シリコン基板の主面のオフ角を0.23°以上とすることができる。 In this case, the off-angle of the main surface of the silicon substrate can be set to 0.23° or more.

これにより、窪み状の欠陥の生成をより抑制することができる。 This further reduces the occurrence of dent-like defects.

以上のように、本発明のシリコン基板によれば、窪み状欠陥がなく表面粗さが改善された高品質なものとなり、デバイス特性の向上が図れるものとなる。また、本発明のシリコン基板の熱処理方法によれば、窪み状の欠陥の生成を抑制することが可能になる。 As described above, the silicon substrate of the present invention is of high quality, free of pit-like defects and with improved surface roughness, leading to improved device characteristics. Furthermore, the heat treatment method for silicon substrates of the present invention makes it possible to suppress the formation of pit-like defects.

実施例のSi(110)基板の表面をAFM測定した観察結果を示す。1 shows the results of AFM measurement of the surface of a Si(110) substrate of an example. 比較例1のSi(110)基板の表面をAFM測定した観察結果を示す。1 shows the results of AFM measurement of the surface of the Si(110) substrate of Comparative Example 1. 比較例2のSi(110)基板の表面をAFM測定した観察結果を示す。1 shows the results of AFM measurement of the surface of the Si(110) substrate of Comparative Example 2. Si(110)(Si{110})基板の一例の断面構造図を示す。1 shows a cross-sectional structure diagram of an example of a Si(110) (Si{110}) substrate.

以下、本発明を詳細に説明するが、本発明はこれらに限定されるものではない。 The present invention is described in detail below, but is not limited to these.

上述のように、窪み状の欠陥の生成が抑制されたSi{110}基板及びSi{110}基板の熱処理方法が求められていた。 As described above, there is a need for a Si{110} substrate and a heat treatment method for a Si{110} substrate that suppresses the formation of pit-like defects.

本発明者らは、上記課題について鋭意検討を重ねた結果、主面の面方位が{110}のシリコン基板であって、表面に長手方向の長さが50nm以上2000nm以下の窪み状欠陥を含まないものであることを特徴とするシリコン基板により、窪み状欠陥がなく表面粗さが改善された高品質なものとなり、デバイス特性の向上が図れるものとなることを見出し、本発明を完成した。 After extensive research into the above-mentioned problems, the inventors discovered that a silicon substrate having a principal surface with a {110} orientation and free of depression-like defects measuring 50 nm to 2000 nm in length in the longitudinal direction on the surface can be made into a high-quality substrate with no depression-like defects and improved surface roughness, thereby improving device characteristics, and thus completed the present invention.

本発明者らはまた、上記課題について鋭意検討を重ねた結果、主面の面方位が{110}のシリコン基板の熱処理方法であって、前記熱処理方法は、前記シリコン基板を570℃より高い熱処理温度まで昇温する昇温工程と、該熱処理温度で熱処理を行う熱処理工程と、570℃より低い温度まで冷却する冷却工程とを有し、前記昇温工程において前記シリコン基板の温度が570℃に達した時点から前記冷却工程において前記シリコン基板の温度が570℃に達した時点までの期間中の前記シリコン基板の温度と時間の積の総和を60000(℃・sec)以下とすることを特徴とするシリコン基板の熱処理方法により、窪み状の欠陥の生成を抑制することが可能になることを見出し、本発明を完成した。 After extensive research into the above-mentioned problems, the inventors discovered that a heat treatment method for a silicon substrate having a {110} principal surface orientation, comprising a heating step of heating the silicon substrate to a heat treatment temperature higher than 570°C, a heat treatment step of performing heat treatment at that heat treatment temperature, and a cooling step of cooling the silicon substrate to a temperature lower than 570°C, wherein the sum of the product of the temperature and time of the silicon substrate from the time the temperature of the silicon substrate reaches 570°C in the heating step to the time the temperature of the silicon substrate reaches 570°C in the cooling step is 60,000 (°C·sec) or less, can suppress the generation of dent-like defects, and thus completed the present invention.

[シリコン基板]
本発明において、面方位が{110}とは、面方位が(110)と等価な面を含む。また、{110}面から0.23~0.5度のオフ角を有するものを含む。
[Silicon substrate]
In the present invention, a plane orientation of {110} includes a plane whose orientation is equivalent to (110), and also includes a plane having an off angle of 0.23 to 0.5 degrees from the {110} plane.

図4に、Si(110)基板の一例の断面構造図を示す。図4に示すように、Si(110)基板2は表面3(表面安定構造の最表面)を有している。本発明の対象とする、長手方向の長さが50nm以上2000nm以下の窪み状欠陥(以下、単に「窪み状欠陥」ともいう)が存在するのは表面3である。 Figure 4 shows a cross-sectional structure diagram of an example of a Si(110) substrate. As shown in Figure 4, Si(110) substrate 2 has surface 3 (the outermost surface of the surface stable structure). It is on surface 3 that pit-like defects with longitudinal lengths of 50 nm to 2000 nm (hereinafter simply referred to as "pit-like defects"), which are the subject of the present invention, exist.

Si(110)基板にエピタキシャル成長前の水素アニールを行ったり、エピタキシャル成長(シリコンやSiGeなど)や熱処理を行うと、図2に示すような窪み状欠陥が生じることがある。 When hydrogen annealing is performed on a Si(110) substrate before epitaxial growth, or when epitaxial growth (silicon, SiGe, etc.) or heat treatment is performed, depression-like defects such as those shown in Figure 2 may occur.

この欠陥は、特許文献2や非特許文献2、3に記載の通り、Si(110)の安定構造の違いによって生成する。特にこのように長い欠陥が存在できるのは、16×2ドメインのような安定構造がつながったときに生成することが、本研究者らの調査・研究で明らかになった。 As described in Patent Document 2 and Non-Patent Documents 2 and 3, this defect is generated due to differences in the stable structure of Si(110). The researchers' research and studies have revealed that such long defects can exist in particular when stable structures such as 16x2 domains are connected.

このような長い欠陥が生成するには、長距離にわたって原子の相互作用が生じる必要がある。すなわち、窪み状欠陥を考える際に、(表面エネルギー)×(熱エネルギー)の相互作用が必要である。 For such long defects to form, atomic interactions must occur over a long distance. In other words, when considering a pit-like defect, an interaction of (surface energy) x (thermal energy) is required.

図4に示すように本発明のシリコン{110}基板2は、表面安定構造の表面3にこのような窪み状欠陥を含まないものである。 As shown in Figure 4, the silicon {110} substrate 2 of the present invention does not contain such depression-like defects on the surface 3 of the surface stable structure.

また、窪み状欠陥は、熱処理条件だけでなく、基板の主面のオフ角にも影響を受ける。すなわち、窪み状欠陥を考える際に、(表面エネルギー)×(熱エネルギー)の相互作用であることを理解していれば欠陥を抑制できる。 In addition, pit-like defects are affected not only by heat treatment conditions but also by the off-angle of the substrate's main surface. In other words, when considering pit-like defects, understanding that they are an interaction of (surface energy) x (thermal energy) can help prevent defects.

ここで、表面エネルギーは、シリコン(110)基板のオフ角によって形成されるステップテラス幅に相当し、オフ角が小さくテラス幅が小さくなると表面エネルギーが相対的に大きくなる。 Here, the surface energy corresponds to the step-terrace width formed by the off-angle of the silicon (110) substrate, and as the off-angle becomes smaller and the terrace width becomes smaller, the surface energy becomes relatively larger.

本発明においては、シリコン{110}基板2の主面のオフ角が0.23°以上のものとすることができる。なお、オフ角の上限は特に限定されないが、0.5°としてよい。 In the present invention, the off-angle of the principal surface of the silicon {110} substrate 2 can be 0.23° or greater. There is no particular upper limit to the off-angle, but it may be set to 0.5°.

このようなシリコン基板によれば、表面粗さがより改善され、さらにデバイス特性の向上が図れるものとなる。これは、オフ角が大きいことでES効果(アーリック・シュウェーベル効果:テラスが広い方が原子の拡散量が多く取れるので、ステップの運動を抑制できる)が発生し、欠陥の生成が抑制されるためである。 Such silicon substrates result in improved surface roughness and improved device characteristics. This is because the large off-angle generates the ES effect (Ahrlich-Schwebel effect: wider terraces allow for greater atomic diffusion, thereby suppressing step movement), which suppresses the generation of defects.

[シリコン基板の熱処理方法]
本発明に係るシリコン{110}基板の熱処理方法は、シリコン基板を570℃より高い熱処理温度まで昇温する昇温工程と、該熱処理温度で熱処理を行う熱処理工程と、570℃より低い温度まで冷却する冷却工程とを有する。
[Silicon substrate heat treatment method]
The heat treatment method for a silicon {110} substrate according to the present invention includes a heating step of heating the silicon substrate to a heat treatment temperature higher than 570°C, a heat treatment step of performing heat treatment at the heat treatment temperature, and a cooling step of cooling the silicon substrate to a temperature lower than 570°C.

ここで熱処理とは、シリコン基板が570℃以上の温度で処理される熱処理を指し、アニール処理、エピタキシャル成長などの層形成処理を含む。また、熱処理は一定の温度でなくともよい。 Here, heat treatment refers to heat treatment in which the silicon substrate is treated at a temperature of 570°C or higher, and includes layer formation processes such as annealing and epitaxial growth. Heat treatment does not have to be performed at a constant temperature.

上述の窪み状欠陥の低減のために、昇温工程においてシリコン基板の温度が570℃に達した時点から冷却工程においてシリコン基板の温度が570℃に達した時点までの期間中の、シリコン基板の温度と時間の積の総和を60000(℃・sec)以下とすることが必要である。 To reduce the above-mentioned pit-like defects, it is necessary to keep the sum of the product of the silicon substrate temperature and time, from the time when the silicon substrate temperature reaches 570°C in the heating process until the time when the silicon substrate temperature reaches 570°C in the cooling process, to 60,000 (°C·sec) or less.

すなわち、主面のオフ角が0.26°のSi(110)基板を、熱処理工程において温度を1080℃、時間を60secで水素アニールを行うと、図2のような、長手方向の長さが1μmの窪み状の欠陥が生成した。このとき、昇温工程においてシリコン基板の温度が570℃に達した時点から冷却工程においてシリコン基板の温度が570℃に達した時点までの期間中の、シリコン基板の温度と時間の積の総和は65000(℃・sec)であった。 In other words, when a Si (110) substrate with an off-angle of 0.26° on the principal surface was subjected to hydrogen annealing at a temperature of 1080°C for 60 seconds in the heat treatment process, depression-shaped defects with a longitudinal length of 1 μm, as shown in Figure 2, were generated. In this case, the sum of the product of the silicon substrate temperature and time from the time when the silicon substrate temperature reached 570°C in the heating process to the time when the silicon substrate temperature reached 570°C in the cooling process, was 65,000 (°C·sec).

次に、上記と同じ主面のオフ角が0.26°のSi(110)基板を、熱処理工程において温度が900℃、時間を60secで水素アニールを行うと、図1のように窪み状の欠陥は発生しなかった。このとき、昇温工程においてシリコン基板の温度が570℃に達した時点から冷却工程においてシリコン基板の温度が570℃に達した時点までの期間中の、シリコン基板の温度と時間の積の総和は57000(℃・sec)であった。 Next, when a Si (110) substrate with the same principal surface off-angle of 0.26° as above was subjected to hydrogen annealing at a temperature of 900°C for 60 seconds in the heat treatment process, no pit-like defects were generated, as shown in Figure 1. In this case, the sum of the product of the silicon substrate temperature and time from the time when the silicon substrate temperature reached 570°C in the heating process to the time when the silicon substrate temperature reached 570°C in the cooling process was 57,000 (°C·sec).

このように、熱処理温度と時間を考慮し、昇温工程においてシリコン基板の温度が570℃に達した時点から冷却工程においてシリコン基板の温度が570℃に達した時点までの期間中の、シリコン基板の温度と時間の積の総和を60000(℃・sec)以下にして熱処理を行うことで、窪み状欠陥の生成を抑制することが可能になる。 In this way, by taking into consideration the heat treatment temperature and time, and performing heat treatment with the sum of the product of the silicon substrate temperature and time during the period from when the silicon substrate temperature reaches 570°C in the heating process to when the silicon substrate temperature reaches 570°C in the cooling process set to 60,000 (°C·sec) or less, it is possible to suppress the generation of pit-like defects.

なお、上記温度と時間の積の総和の下限値は、特に限定されないが、5400(℃・sec)としてよい。 The lower limit of the sum of the products of the above temperatures and times is not particularly limited, but may be set to 5400 (°C·sec).

本発明に係るSi{110}基板の熱処理方法においては、シリコン基板の主面のオフ角を0.23°以上とすることができる。これにより、窪み状の欠陥の生成をより抑制することができる。なお、オフ角の上限は特に限定されないが、0.5°としてよい。 In the heat treatment method for a Si {110} substrate according to the present invention, the off-angle of the principal surface of the silicon substrate can be set to 0.23° or more. This further suppresses the formation of pit-like defects. The upper limit of the off-angle is not particularly limited, but may be set to 0.5°.

以下、実施例を挙げて本発明について具体的に説明するが、これは本発明を限定するものではない。 The present invention will be explained in more detail below using examples, but these examples are not intended to limit the scope of the present invention.

(実施例)
直径300mm、面方位(110)、ボロンドープ、抵抗10Ω・cm、主面(110)面のオフ角0.26°のシリコン単結晶基板を準備し、これを900℃の温度で60sec、常圧にて水素アニールを行った。このとき、昇温工程においてシリコン基板の温度が570℃に達した時点から冷却工程においてシリコン基板の温度が570℃に達した時点までの期間中の、シリコン基板の温度と時間の積の総和は57000(℃・sec)であった。
(Example)
A silicon single crystal substrate with a diameter of 300 mm, a (110) orientation, boron doping, a resistivity of 10 Ω·cm, and an off-angle of 0.26° from the (110) principal surface was prepared and subjected to hydrogen annealing at a temperature of 900°C for 60 seconds at atmospheric pressure. During this time, the sum of the product of the temperature and time of the silicon substrate from the time when the temperature of the silicon substrate reached 570°C in the heating step to the time when the temperature of the silicon substrate reached 570°C in the cooling step was 57,000 (°C·sec).

このあと取得画像の一辺が、1μmとなるように画角を調整してAFM測定を行った。測定結果を図1に示す。図1に示すように、シリコン基板の表面に窪み状欠陥は観察されなかった。 Then, the angle of view was adjusted so that one side of the captured image was 1 μm, and AFM measurement was performed. The measurement results are shown in Figure 1. As shown in Figure 1, no dent-like defects were observed on the surface of the silicon substrate.

(比較例1)
実施例と同じシリコン単結晶基板を準備し、これを1080℃の温度で60sec、常圧にて水素アニールを行った。このとき、昇温工程においてシリコン基板の温度が570℃に達した時点から冷却工程においてシリコン基板の温度が570℃に達した時点までの期間中の、シリコン基板の温度と時間の積の総和は65000(℃・sec)であった。
(Comparative Example 1)
The same silicon single crystal substrate as in the example was prepared and subjected to hydrogen annealing at atmospheric pressure for 60 seconds at a temperature of 1080°C. During this time, the sum of the product of the temperature of the silicon substrate and the time from the time when the temperature of the silicon substrate reached 570°C in the heating step to the time when the temperature of the silicon substrate reached 570°C in the cooling step was 65000 (°C·sec).

このあと取得画像の一辺が、1μmとなるように画角を調整してAFM測定を行った。測定結果を図2に示す。シリコン基板の表面に、図2に示すような、長手方向の長さが1μmの窪み状欠陥が観察された。 Then, the angle of view was adjusted so that one side of the captured image was 1 μm, and AFM measurement was performed. The measurement results are shown in Figure 2. A depression-shaped defect with a longitudinal length of 1 μm, as shown in Figure 2, was observed on the surface of the silicon substrate.

(比較例2)
主面のオフ角を0.24°とした以外は実施例と同じシリコン単結晶基板を準備し、これを1030℃の温度で60sec、常圧にて水素アニールを行った。このとき、昇温工程においてシリコン基板の温度が570℃に達した時点から冷却工程においてシリコン基板の温度が570℃に達した時点までの期間中の、シリコン基板の温度と時間の積の総和は65000(℃・sec)であった。
(Comparative Example 2)
A silicon single crystal substrate identical to that of the example was prepared, except that the off-angle of the main surface was 0.24°, and this was subjected to hydrogen annealing at a temperature of 1030°C for 60 seconds at atmospheric pressure. During this time, the sum of the product of the temperature of the silicon substrate and the time from the time when the temperature of the silicon substrate reached 570°C in the heating step to the time when the temperature of the silicon substrate reached 570°C in the cooling step was 65,000 (°C·sec).

このあと取得画像の一辺が、1μmとなるように画角を調整してAFM測定を行った。測定結果を図3に示す。シリコン基板の表面に、図3に示すような0.8μmの窪み状欠陥が観察された。 Then, the angle of view was adjusted so that one side of the captured image was 1 μm, and AFM measurement was performed. The measurement results are shown in Figure 3. A 0.8 μm depression-like defect, as shown in Figure 3, was observed on the surface of the silicon substrate.

以上のとおり、本発明の実施例によれば、Si(110)基板の熱処理において、表面に窪み状欠陥を生成させることなく熱処理を行うことができ、表面に50nm以上2000nmの窪み状欠陥を有しないSi(110)基板を得ることができた。 As described above, according to the examples of the present invention, heat treatment of a Si(110) substrate can be performed without generating pit-like defects on the surface, and a Si(110) substrate can be obtained that does not have pit-like defects of 50 nm to 2000 nm on the surface.

なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。 The present invention is not limited to the above-described embodiments. The above-described embodiments are merely examples, and anything that has substantially the same configuration as the technical concept described in the claims of the present invention and exhibits similar effects is within the technical scope of the present invention.

1…窪み状欠陥、2…Si(110)(Si{110})基板、
3…表面(表面安定構造)。
1... pit-like defect, 2... Si(110) (Si{110}) substrate,
3...Surface (surface stable structure).

Claims (4)

主面の面方位が{110}のシリコン基板であって、表面に長手方向の長さが50nm以上2000nm以下の窪み状欠陥を含まないものであることを特徴とするシリコン基板。 A silicon substrate having a principal surface with a {110} orientation and containing no depression-like defects with a longitudinal length of 50 nm or more and 2000 nm or less on the surface. 主面のオフ角が0.23°以上のものであることを特徴とする請求項1に記載の主面の面方位が{110}のシリコン基板。 The silicon substrate of claim 1, characterized in that the principal surface has a {110} plane orientation and the off-angle of the principal surface is 0.23° or greater. 主面の面方位が{110}のシリコン基板の熱処理方法であって、
前記熱処理方法は、前記シリコン基板を570℃より高い熱処理温度まで昇温する昇温工程と、該熱処理温度で熱処理を行う熱処理工程と、570℃より低い温度まで冷却する冷却工程とを有し、
前記昇温工程において前記シリコン基板の温度が570℃に達した時点から前記冷却工程において前記シリコン基板の温度が570℃に達した時点までの期間中の前記シリコン基板の温度と時間の積の総和を60000(℃・sec)以下とすることを特徴とするシリコン基板の熱処理方法。
A method for heat treating a silicon substrate having a principal surface with a {110} plane orientation, comprising the steps of:
The heat treatment method includes a heating step of heating the silicon substrate to a heat treatment temperature higher than 570°C, a heat treatment step of performing heat treatment at the heat treatment temperature, and a cooling step of cooling the silicon substrate to a temperature lower than 570°C,
A heat treatment method for a silicon substrate, characterized in that the sum of the product of the temperature and time of the silicon substrate during the period from the time when the temperature of the silicon substrate reaches 570°C in the heating step to the time when the temperature of the silicon substrate reaches 570°C in the cooling step is 60,000 (°C·sec) or less.
前記シリコン基板の主面のオフ角を0.23°以上とすることを特徴とする請求項3に記載のシリコン基板の熱処理方法。 The heat treatment method for a silicon substrate according to claim 3, characterized in that the off-angle of the main surface of the silicon substrate is 0.23° or more.
JP2024017105A 2024-02-07 2024-02-07 Silicon epitaxial substrate and method for heat treatment of silicon substrate Active JP7694736B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2024017105A JP7694736B1 (en) 2024-02-07 2024-02-07 Silicon epitaxial substrate and method for heat treatment of silicon substrate
PCT/JP2025/001240 WO2025169680A1 (en) 2024-02-07 2025-01-17 Silicon substrate and heat treatment method for silicon substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2024017105A JP7694736B1 (en) 2024-02-07 2024-02-07 Silicon epitaxial substrate and method for heat treatment of silicon substrate

Publications (2)

Publication Number Publication Date
JP7694736B1 JP7694736B1 (en) 2025-06-18
JP2025121584A true JP2025121584A (en) 2025-08-20

Family

ID=96055088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024017105A Active JP7694736B1 (en) 2024-02-07 2024-02-07 Silicon epitaxial substrate and method for heat treatment of silicon substrate

Country Status (2)

Country Link
JP (1) JP7694736B1 (en)
WO (1) WO2025169680A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205218A (en) * 2007-02-20 2008-09-04 Covalent Materials Corp Semiconductor substrate
JP2010001210A (en) * 2008-06-04 2010-01-07 Siltronic Ag Epitaxially coated silicon wafer having <110> orientation and method for producing the same
JP2023108951A (en) * 2022-01-26 2023-08-07 信越半導体株式会社 Method for producing silicon epitaxial wafer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008177529A (en) * 2006-12-21 2008-07-31 Covalent Materials Corp Semiconductor substrate and manufacturing method thereof
WO2009157040A1 (en) * 2008-06-25 2009-12-30 富士通マイクロエレクトロニクス株式会社 Semiconductor device and process for producing the semiconductor device
JP2010245433A (en) * 2009-04-09 2010-10-28 Panasonic Corp Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205218A (en) * 2007-02-20 2008-09-04 Covalent Materials Corp Semiconductor substrate
JP2010001210A (en) * 2008-06-04 2010-01-07 Siltronic Ag Epitaxially coated silicon wafer having <110> orientation and method for producing the same
JP2023108951A (en) * 2022-01-26 2023-08-07 信越半導体株式会社 Method for producing silicon epitaxial wafer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
松下ステファン悠: "高品位水素終端Si(110)−(1×1)表面の開発と一次元電子状態及び一次元表面フォノンの解明", 博士論文(東北大学), JPN7024003228, 2014, pages 1 - 3, ISSN: 0005486528 *
横山有太: "Si(110)、Ge(110)表面の一次元ナノテンプレートに関する微視的研究", 博士論文(筑波大), JPN7024003227, 2012, pages 46, ISSN: 0005486529 *

Also Published As

Publication number Publication date
WO2025169680A1 (en) 2025-08-14
JP7694736B1 (en) 2025-06-18

Similar Documents

Publication Publication Date Title
JP6122704B2 (en) SiC epitaxial wafer and manufacturing method thereof
CN102656297B (en) SiC epitaxial wafer and method for manufacturing same
CN102576666B (en) SiC epitaxial wafer and manufacturing method thereof
JP5076020B2 (en) SiC epitaxial wafer
WO2013035691A1 (en) Sic epitaxial wafer and method for manufacturing same
JP2008004888A (en) Manufacturing method for silicon carbide semiconductor epitaxial substrate
JP2008508696A5 (en)
TW201041029A (en) A method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side
US7198997B2 (en) Method for producing semiconductor substrate, method for producing field effect transistor, semiconductor substrate, and field effect transistor
Wang et al. Self-assembly of tin wires via phase transformation of heteroepitaxial germanium-tin on germanium substrate
JP2025087793A (en) How to Select a Silicon Carbide Semiconductor Epitaxial Substrate
JP7694736B1 (en) Silicon epitaxial substrate and method for heat treatment of silicon substrate
Li et al. Hydrogen etching of 4H–SiC (0001) facet and step formation
Dojima et al. Macro Step Bunching/Debunching Engineering on 4° off 4H-SiC (0001) to Control the BPD-TED Conversion Ratio by Dynamic AGE-Ing®
Hanafusa et al. Ge flat layer growth on heavily phosphorus-doped Si (001) by sputter epitaxy
JP2025141255A (en) Silicon substrate heat treatment method
Toda et al. A Novel Contactless SiC Wafer Planarization Processing after Mechanical Slicing by Dynamic Thermal Annealing Processes
JP6399171B2 (en) Silicon member and method for manufacturing silicon member
Hamasaki et al. Hydrogen etching of the SiC (0001) surface at moderate temperature
CN105019030B (en) Height crystal orientation matching stacked structure of graphene/hexagonal boron nitride and preparation method thereof
TW202510044A (en) Silicon single crystal substrate and method for manufacturing the same
JP2025124415A (en) Silicon substrate evaluation method
Okada et al. Crystallization of a-Si films with smooth surfaces by using Blue Multi-Laser Diode Annealing
Razzhivina et al. Kinetics of transformation of the atomic step bunches shape under electromigration conditions on the Si (001) surface
Jousseaume et al. Transport phenomena during liquid Si-induced 4H-SiC surface structuring in a sandwich configuration

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20240628

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20240628

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20240806

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20240927

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20241217

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250205

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250507

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250520

R150 Certificate of patent or registration of utility model

Ref document number: 7694736

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150