JP2021168322A - Solar cells and their manufacturing methods - Google Patents

Abstract

A back electrode type solar cell is manufactured using a p-type semiconductor substrate, and the characteristics of the solar cell are improved. A solar cell (1) includes a p-type semiconductor substrate (2), an n-type semiconductor region (3) formed on the back surface (2b) side of the semiconductor substrate (2), and a semiconductor substrate (2) formed on the back surface (2b) side of the semiconductor substrate. and a negative charge layer 5 formed on the back surface 2 b of the semiconductor substrate 2 and in contact with the p-type semiconductor substrate 2 . The solar cell further has an electrode 7 connected to the n-type semiconductor region 3 and an electrode 8 connected to the p-type semiconductor region 4 . The electrode 8 penetrates the negative charge layer 5, and the negative charge layer 5 consists of an insulator containing negative fixed charges. [Selection drawing] Fig. 1

Description

The present invention relates to a solar cell and a method for manufacturing the same, for example, a back electrode type solar cell in which an electrode is provided on the back surface side opposite to the light receiving surface of the semiconductor substrate and a method for manufacturing the same.

Renewable energy can be used without depleting energy resources and does not emit carbon dioxide that causes global warming during power generation, so it can be used as a clean energy alternative to fossil fuels such as oil, coal, and natural gas. Attention has been paid.

Sunlight is one of the renewable energies. A power generation method that uses solar cells to directly convert sunlight into electricity is called photovoltaic power generation. A solar cell is a photoelectric conversion element that absorbs light energy and changes it into electrical energy.

There are various types of solar cells such as organic solar cells and multi-junction solar cells, but crystalline silicon solar cells are the most widespread. The biggest challenges of crystalline silicon solar cells are high efficiency and low cost. Research, development, and mass production of various cells such as PERC type cells (Passivated Emitter and Rear Cell) and double-sided light receiving type cells are underway to improve the efficiency of crystalline silicon solar cells, but the electrodes are placed only on the back surface of the semiconductor substrate. The back electrode type cell in which the light receiving area on the front surface side of the semiconductor substrate is increased by forming the cell exhibits the highest conversion efficiency.

For example, Non-Patent Document 1 describes a technique relating to a back electrode type solar cell using a back electrode type cell.

International Technology Roadmap for Photovoltaic (ITRPV), Eighth Edition, September 2017.

The present inventor is studying the manufacture of a back electrode type solar cell using a p-type semiconductor substrate. Even when a back electrode type solar cell is manufactured using a p-type semiconductor substrate, it is desired to improve the characteristics of the solar cell as much as possible.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

According to one embodiment, the solar cell includes a p-type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and the second main surface in the semiconductor substrate. An n-type first semiconductor region formed on the side and a p-type second semiconductor region formed on the second main surface side of the semiconductor substrate and having a higher p-type impurity concentration than the semiconductor substrate. ,have. The solar cell further includes a negative charge layer formed on the second main surface and in contact with the p-type semiconductor substrate, a first electrode connected to the first semiconductor region, and the second semiconductor region. It has a second electrode to be connected. The second electrode penetrates the negative charge layer, and the negative charge layer is made of an insulator containing a negative fixed charge.

According to one embodiment, the method for manufacturing a solar cell is (a) a step of preparing a p-type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface. b) A step of forming an n-type first semiconductor region on the second main surface side in the semiconductor substrate, (c) a negative charge layer in contact with the p-type semiconductor substrate on the second main surface. It has a step of forming. The method for manufacturing a solar cell further comprises (d) a step of forming a first insulating film on the second main surface so as to cover the first semiconductor region and the negative charge layer, and (e) the first. A step of forming a first electrode that penetrates the insulating film and connects to the first semiconductor region, and a second electrode that penetrates the first insulating film and the negative charge layer and connects to the semiconductor substrate. Have. The negative charge layer is made of an insulator containing a negative fixed charge. The second electrode contains aluminum as a main component. The step (e) includes a heat treatment step. In the heat treatment step, aluminum diffuses from the second electrode to the semiconductor substrate, so that a p-type impurity concentration higher than that of the semiconductor substrate is formed at a position adjacent to the second electrode in the semiconductor substrate. A second semiconductor region is formed.

According to one embodiment, the characteristics of the solar cell can be improved.

It is sectional drawing of the main part of the solar cell of one Embodiment. It is a main part plan view of the solar cell of one embodiment. It is a main part plan view of the solar cell of one embodiment. It is a main part plan view of the modification of the solar cell of one Embodiment. It is a main part plan view of another modification of the solar cell of one embodiment. It is sectional drawing which shows the manufacturing process of the solar cell of one Embodiment. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing of the main part of the solar cell of the 1st study example. It is sectional drawing of the main part of the solar cell of the 2nd study example. It is a table which shows the characteristic of a solar cell. It is sectional drawing which shows the manufacturing process of the solar cell of another embodiment. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell of another embodiment. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG. It is sectional drawing which shows the manufacturing process of the solar cell following FIG.

Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment, the members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. Further, in the following embodiments, the description of the same or similar parts is not repeated in principle except when it is particularly necessary.

(Embodiment 1)
<About the structure of solar cells>
A solar cell according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a main part of the solar cell 1 according to the embodiment of the present invention, and FIGS. 2 and 3 are plan views of the main part of the solar cell 1. The cross-sectional views taken along the line AA in FIGS. 2 and 3 substantially correspond to FIG. FIG. 2 shows a plan view of the n-type semiconductor region 3, the p-type semiconductor region 4, and the negative charge layer 5 when viewed from the surface 2a side of the semiconductor substrate 2. Further, FIG. 3 shows a plan view in which the p-type semiconductor region 4 is seen through in FIG. 2 and the formation positions of the electrodes 7 and 8 are added. Although the electrode 8 penetrates the negative charge layer 5, the electrode 7 does not penetrate the n-type semiconductor region 3, so that the position of the electrode 7 is shown by a dotted line in FIG.

The solar cell 1 of the present embodiment is a back electrode type solar cell (back electrode type crystalline silicon solar cell).

As shown in FIGS. 1 to 3, the solar cell 1 of the present embodiment has a p-type semiconductor substrate 2 into which p-type impurities have been introduced. The semiconductor substrate 2 is preferably a silicon substrate made of crystalline silicon. The semiconductor substrate 2 has a front surface (main surface) 2a which is a light receiving surface and a back surface (main surface) 2b opposite to the surface 2a. The front surface 2a and the back surface 2b are the main surfaces of the semiconductor substrate 2. Sunlight is incident on the semiconductor substrate 2 from the surface 2a side of the semiconductor substrate 2.

The structure of the semiconductor substrate 2 on the surface 2a side can be variously changed. For example, in the case of FIG. 1, the surface 2a of the semiconductor substrate 2 is drawn as a substantially flat surface, but as another form, a concavo-convex structure called a texture structure can be provided on the surface 2a of the semiconductor substrate 2. Further, a p-type high-concentration semiconductor region (not shown) in which p-type impurities are introduced at a higher concentration than that of the semiconductor substrate 2 can be provided on the surface 2a side of the semiconductor substrate 2. Further, an insulating film (not shown) for antireflection may be provided on the surface 2a of the semiconductor substrate 2.

Further, in the present embodiment, the back surface 2b of the semiconductor substrate 2 is a substantially flat surface, but as another embodiment, a concavo-convex structure called a texture structure can be provided on the back surface 2b of the semiconductor substrate 2.

As shown in FIGS. 1 to 3, in the semiconductor substrate 2, the n-type semiconductor region (emitter region) 3 in which the n-type impurity is introduced and the p-type impurity are high on the back surface 2b side of the semiconductor substrate 2. The p-type semiconductor region 4 introduced into the concentration is formed. The n-type semiconductor region 3 and the p-type semiconductor region 4 are formed in the semiconductor substrate 2 so as to be separated from each other. A negative charge layer 5, an insulating film 6, an electrode (emitter electrode) 7, and an electrode (BSF electrode) 8 are formed on the back surface 2b of the semiconductor substrate 2. In a plan view, the electrode 7 overlaps the n-type semiconductor region 3, and the electrode 8 overlaps the p-type semiconductor region 4. The electrode 7 is connected to the n-type semiconductor region 3, and the electrode 8 is connected to the p-type semiconductor region 4 through the negative charge layer 5. These components will be specifically described below.

The p-type semiconductor region 4 is formed in the semiconductor substrate 2 so as to be adjacent to the electrode 8. The electrode 8 (BSF electrode) penetrates the insulating film 6 and the negative charge layer 5, and is in contact with the p-type semiconductor region 4 (BSF region) and is electrically connected. The p-type semiconductor region 4 and the electrode 8 are adjacent to each other in the thickness direction of the semiconductor substrate 2, and the p-type semiconductor region is above the electrode 8 when the side close to the surface 2a of the semiconductor substrate 2 is facing upward. 4 exists. In a plan view, the p-type semiconductor region 4 overlaps with the electrode 8. Both the p-type semiconductor region 4 and the semiconductor substrate 2 show a p-type conductive type, but the impurity concentration in the p-type semiconductor region 4 (p-type impurity concentration) is the impurity concentration of the semiconductor substrate 2 (p-type impurity concentration). ) Higher than. Therefore, the p-type semiconductor region 4 is a p-type high-concentration semiconductor region having a higher p-type impurity concentration than the semiconductor substrate 2. The p-type semiconductor region 4 has a function of reducing the connection resistance of the electrode 8 and a function of a BSF (Back Surface Field) region.

The n-type semiconductor region 3 is formed in the semiconductor substrate 2 so as to be in contact with the back surface 2b of the semiconductor substrate 2 and therefore to be exposed on the back surface 2b of the semiconductor substrate 2. Except for the back surface 2b, the n-type semiconductor region 3 is surrounded by a p-type substrate region, and a PN junction is formed between the n-type semiconductor region 3 and the p-type substrate region. The p-type substrate region corresponds to the semiconductor substrate 2 in the portion where the p-type is maintained.

The n-type semiconductor region 3 functions as an emitter region. The electrode (emitter electrode) 7 is in contact with the n-type semiconductor region 3 (emitter region) and is electrically connected to the n-type semiconductor region 3.

A negative charge layer 5 is arranged on a part of the back surface 2b of the semiconductor substrate 2 so as to be in contact with the semiconductor substrate 2. The negative charge layer 5 is composed of an insulating layer containing a negative fixed charge (electrons in this case) inside. That is, the negative charge layer 5 itself is made of an insulator material, but a negative fixed charge is stored (retained) inside the negative charge layer 5 made of an insulator material.

Specifically, the negative charge layer 5 is selected from the group consisting of aluminum (Al), titanium (Ti), tantalum (Ta), magnesium (Mg), hafnium (Hf), zirconium (Zr) and scandium (Sc). It is composed of an insulating layer containing at least one of the above and oxygen (O) as a main component. Therefore, the negative charge layer 5 is made of a metal oxide, and the metal elements constituting the metal oxide are aluminum (Al), titanium (Ti), tantalum (Ta), magnesium (Mg), and hafnium (Hf). Consists of at least one selected from the group consisting of, zirconium (Zr) and scandium (Sc). The negative charge layer 5 may further contain silicon (Si), hydrogen (H), and the like. When the negative charge layer 5 also contains silicon (Si), the negative charge layer 5 is made of a metal silicate, and the metal elements constituting the metal silicate are aluminum (Al), titanium (Ti), tantalum (Ta), and so on. It consists of at least one selected from the group consisting of magnesium (Mg), hafnium (Hf), zirconium (Zr) and scandium (Sc).

The negative charge layer 5 can be formed by using a film forming method such as a CVD (Chemical Vapor Deposition) method or an ALD (Atomic layer Deposition) method. The above-mentioned material is selected as the insulator material constituting the negative charge layer 5, and the negative charge layer 5 is formed so that a negative fixed charge (electrons in this case) is stored in the film formed at the time of film formation. By performing the membrane step, a negative charge layer 5 made of an insulating layer containing a negative fixed charge can be formed.

The thickness of the negative charge layer 5 can be, for example, about 2 to 20 nm. The charge density (effective fixed charge density) of the negative charge layer 5 can be, for example, about 1.0 × 10 ^{11 to} 1.0 × 10 ¹⁴ / cm ² . The charge density shown here is indicated by the value obtained by dividing the effective fixed charge by the elementary charge.

In a plan view, the n-type semiconductor region 3 is not formed on the entire back surface 2b of the semiconductor substrate 2, but is partially formed in the back surface 2b of the semiconductor substrate 2. The back surface 2b of the semiconductor substrate 2 is composed of a p-type substrate region except for a portion that is an n-type semiconductor region 3. The negative charge layer 5 is formed on the back surface 2b of the semiconductor substrate 2, but is formed on the p-shaped portion (p-type substrate region) of the back surface 2b of the semiconductor substrate 2. The negative charge layer 5 is not formed on the lower surface of the n-type semiconductor region 3, and the lower surface of the n-type semiconductor region 3 is not in contact with the negative charge layer 5. The negative charge layer 5 is in contact with the p-type substrate region. The lower surface of the n-type semiconductor region 3 is a surface that forms a part of the back surface 2b of the semiconductor substrate 2.

In the case of FIGS. 1 to 3, the negative charge layer 5 is formed so as to be adjacent to the n-type semiconductor region 3 in a plan view. As another form, the negative charge layer 5 can be formed so as to be separated from the n-type semiconductor region 3 in a plan view, and in that case, the negative charge layer 5 and the n-type semiconductor region 3 are formed in a plan view. There will be a predetermined interval between them.

Further, a plurality of n-type semiconductor regions 3 are formed in the semiconductor substrate 2, and the plurality of n-type semiconductor regions 3 are separated from each other in a plan view. In a plan view, the negative charge layer 5 and the p-type semiconductor region 4 are arranged between the adjacent n-type semiconductor regions 3. Therefore, in a plan view, the set of the negative charge layer 5 and the p-type semiconductor region 4 and the n-type semiconductor region 3 are arranged alternately.

An insulating film 6 is formed on almost the entire back surface 2b of the semiconductor substrate 2 so as to cover the negative charge layer 5. The electrode 7 penetrates the insulating film 6 and reaches the n-type semiconductor region 3, and is in contact with the n-type semiconductor region 3 and electrically connected to the n-type semiconductor region 3. Further, the electrode 8 penetrates the insulating film 6 and the negative charge layer 5 to reach the p-type semiconductor region 4, and is in contact with the p-type semiconductor region 4 and electrically connected to the p-type semiconductor region 4. Since the electrode 7 is connected to the n-type semiconductor region 3 which is an emitter region, it can function as an emitter electrode. Further, since the electrode 8 is connected to the p-type semiconductor region 4 which is a BSF region, it can function as a BSF electrode. In the solar cell 1 of the present embodiment, the emitter electrode (electrode 7) and the BSF electrode (electrode 8) are formed on the back surface 2b side of the semiconductor substrate 2, and the surface 2a which is the light receiving surface of the semiconductor substrate 2 is formed. No electrodes (electrodes for extracting electric charges generated by sunlight) are formed on the side. Therefore, the solar cell 1 of the present embodiment is a back electrode type solar cell, and the light receiving area can be increased without being disturbed by the electrodes, so that the photoelectric conversion efficiency can be improved.

FIG. 4 is a plan view of a main part showing a modified example of the solar cell 1 of the present embodiment, and FIG. 5 is a plan view of a main part showing another modified example of the solar cell 1 of the present embodiment. Corresponds to FIG. 2 above. The X and Y directions shown in FIGS. 2 to 5 are directions orthogonal to each other. In any of FIGS. 2 to 5, the structure of the unit cell CL is repeated in a plurality of X directions, and a part of the semiconductor substrate 2 constituting the solar cell 1 is shown.

In the case of FIG. 2, the n-type semiconductor region 3, the p-type semiconductor region 4, and the negative charge layer 5 each have a substantially rectangular planar shape with the Y direction as the long side direction. A plurality of n-type semiconductor regions 3 are arranged apart from each other in the X direction, and a negative charge layer 5 and a p-type semiconductor region 4 are arranged between n-type semiconductor regions 3 adjacent to each other in the X direction in a plan view. ing. That is, the negative charge layer 5 is arranged between the n-type semiconductor regions 3 adjacent to each other in the X direction, the electrode 8 penetrates the negative charge layer 5, and the electrode 8 overlaps the electrode 8 penetrating the negative charge layer 5 in a plan view. The p-type semiconductor region 4 is arranged in. Further, the n-type semiconductor regions 3 that are separated from each other in the X direction and adjacent to each other may be connected at both ends in the Y direction. In that case, the negative charge layer 5 and the p-type semiconductor region 4 are connected. In a plan view, the periphery is surrounded by the n-type semiconductor region 3.

The width W1 of the n-type semiconductor region 3 shown in FIG. 2 in the X direction can be, for example, about 30 to 2500 μm. The width W2 of the p-type semiconductor region 4 shown in FIG. 2 in the X direction can be, for example, about 10 to 150 μm. The width W3 of the negative charge layer 5 shown in FIG. 2 in the X direction can be, for example, about 10 to 500 μm. The ratio of W1 to W3 (W1: W3) can be, for example, about 1: 1 to 9: 1.

In the case of FIG. 2, a line-shaped p-type semiconductor region 4 extending in the Y direction is arranged between the n-type semiconductor regions 3 adjacent to each other in the X direction. On the other hand, in the case of FIG. 4, a plurality of p-type semiconductor regions 4 separated from each other in the Y direction are arranged between the n-type semiconductor regions 3 adjacent to each other in the X direction, as in the case of FIG. It is different. In the case of FIG. 4, the planar shape of each p-type semiconductor region 4 is substantially rectangular, and each p-type semiconductor region 4 is arranged so as to overlap the electrode 8 penetrating the negative charge layer 5 in a plan view. ..

The case of FIG. 5 is different from the case of FIG. 2 in that a plurality of p-type semiconductor regions 4 separated from each other in the Y direction are arranged between the n-type semiconductor regions 3 adjacent to each other in the X direction. .. In the case of FIG. 5, the planar shape of each p-type semiconductor region 4 is substantially circular (dot-shaped), and each p-type semiconductor region 4 overlaps the electrode 8 penetrating the negative charge layer 5 in a plan view. Have been placed.

The planar shape of each p-type semiconductor region 4 can be variously changed. For example, the planar shape of the p-type semiconductor region 4 can be set according to the planar shape of the electrode 8 penetrating the negative charge layer 5.

<About the operation of solar cells>
The operation of the solar cell 1 of the present embodiment will be described with reference to FIG.

First, in FIG. 1, when the surface 2a of the semiconductor substrate 2 which is the light receiving surface of the solar cell 1 is irradiated with sunlight including visible light or infrared light from above, the semiconductor substrate 2 constituting the solar cell 1 Sunlight is incident inside. The sunlight incident on the semiconductor substrate 2 also incidents on the n-type semiconductor region 3 and the p-type semiconductor region 4 in the semiconductor substrate 2. At this time, among sunlight, light having an energy larger than the band gap of silicon is absorbed. Specifically, the electrons existing in the valence band receive the light energy supplied from sunlight and are excited to the conduction band. As a result, electrons are accumulated in the conduction band and holes are generated in the valence band. In this way, when sunlight is incident on the solar cell 1, light having a light energy larger than the band gap of silicon contained in the sunlight is absorbed, electrons are excited in the conduction band, and the valence band is excited. Holes are generated in the electron band. Then, electrons are accumulated in the n-type semiconductor region 3 constituting one of the PN junctions, and holes are accumulated in the p-type substrate region and the p-type semiconductor region 4 of the semiconductor substrate 2 constituting the other of the PN junctions. As a result, an electromotive force is generated between the electrode 7 and the electrode 8. Then, for example, when a load is connected between the electrode 7 and the electrode 8 outside the solar cell 1, electrons flow from the electrode 7 through the load to the electrode 8. In other words, a current flows from the electrode 8 through the load to the electrode 7.

By operating the solar cell 1 in this way, the load can be driven.

By the way, as described above, when sunlight is incident on the semiconductor substrate 2 from the surface 2a side of the semiconductor substrate 2, the light energy of the sunlight is absorbed by the semiconductor substrate 2 and the electrons existing in the valence band are conducted in the conduction band. As a result of being excited by, electron-hole pairs are formed inside the semiconductor substrate 2. When the electrons, which are the minority carriers generated at this time, recombine with the holes and disappear, the photoelectric conversion efficiency of the solar cell decreases.

Here, the negative charge layer 5 contains a negative fixed charge (here, an electron) inside. Therefore, since a large number of negative fixed charges exist inside the negative charge layer 5, the electric repulsive force between the negative fixed charges in the negative charge layer 5 and the electrons in the semiconductor substrate 2 causes the inside of the semiconductor substrate 2 to be repulsed. Electrons are kept away from the negatively charged layer 5. This suppresses the recombination of electrons and holes. Therefore, the negative charge layer 5 has a function of keeping the electrons in the semiconductor substrate 2 away from the negative charge layer 5 and suppressing the recombination of electrons and holes. By providing the negative charge layer 5, recombination of electrons and holes is suppressed, so that the photoelectric conversion efficiency of the solar cell can be improved.

Further, the p-type semiconductor region 4 contains an acceptor (here, aluminum), and the acceptor is negatively charged. Therefore, since there are many negatively charged acceptors (aluminum in this case) in the p-type semiconductor region 4, the energy band potential for a small number of carriers (electrons in this case) in the p-type semiconductor region 4 Will be higher. As a result, the p-type semiconductor region 4 has a function of keeping electrons in the semiconductor substrate 2 away from the vicinity of the p-type semiconductor region 4 and suppressing recombination of electrons and holes. By providing the p-type semiconductor region 4, recombination of electrons and holes is suppressed, so that the photoelectric conversion efficiency of the solar cell can be improved.

Therefore, both the negative charge layer 5 and the p-type semiconductor region 4 have a function of moving electrons away and suppressing recombination between electrons and holes. Further, the p-type semiconductor region 4 also has a function of reducing the contact resistance of the electrode 8.

<Solar cell manufacturing method>
An example of the method for manufacturing the solar cell 1 of the present embodiment will be described with reference to FIGS. 6 to 14. 6 to 14 are cross-sectional views showing the manufacturing process of the solar cell 1 of the present embodiment, and the cross section corresponding to FIG. 1 is shown.

First, as shown in FIG. 6, a semiconductor substrate having a front surface 2a and a back surface 2b is prepared. The semiconductor substrate 2 is made of p-type crystalline silicon into which p-type impurities (for example, boron (B)) have been introduced.

Next, as shown in FIG. 7, an n-type semiconductor region 3a is formed on the back surface 2b side of the semiconductor substrate 2. For example, the n-type semiconductor region 3a can be formed by introducing (doping) an n-type impurity into the semiconductor substrate 2 using an ion implantation method, but other methods (for example, a thermal diffusion method) can be used. It is also possible to form the n-type semiconductor region 3a. The n-type semiconductor region 3a is formed from the back surface 2b of the semiconductor substrate 2 over a predetermined depth. The n-type impurity introduced into the semiconductor substrate 2 to form the n-type semiconductor region 3a is, for example, phosphorus (P). The n-type semiconductor region 3a has a concentration gradient in which the phosphorus (P) concentration gradually decreases from the back surface 2b of the semiconductor substrate 2 toward the inside, and n-type impurities are high in the vicinity of the back surface 2b of the semiconductor substrate 2. The n-type semiconductor region 3a is formed as the n-type high-concentration semiconductor region introduced into the concentration. At this stage, an n-type semiconductor region 3a having a predetermined thickness is formed on the entire back surface 2b of the semiconductor substrate 2.

Next, as shown in FIG. 8, the n-type semiconductor region 3a is partially removed. That is, the n-type semiconductor region 3a other than the portion left as the n-type semiconductor region 3 is removed. The remaining n-type semiconductor region 3a forms an n-type semiconductor region 3 as an emitter region. In the region where the n-type semiconductor region 3a is left as the n-type semiconductor region 3, the back surface 2b of the semiconductor substrate 2 is formed by the n-type semiconductor region 3, and in the region where the n-type semiconductor region 3a is removed, the back surface 2b of the semiconductor substrate 2 is formed. 2b is formed by a p-type substrate region. As a method for partially removing the n-type semiconductor region 3a, for example, an etching method can be used, but other methods (for example, laser processing) can also be used.

Further, in the present embodiment, after the n-type semiconductor region 3a is formed on the entire back surface 2b of the semiconductor substrate 2, the n-type semiconductor region 3a is partially removed to form the n-type on the back surface 2b side of the semiconductor substrate 2. It forms the semiconductor region 3. As another form, the n-type semiconductor region 3a can be partially formed on the back surface 2b of the semiconductor substrate 2 without forming the n-type semiconductor region 3a on the entire back surface 2b of the semiconductor substrate 2. In this case, the n-type semiconductor region 3 can be formed by, for example, an ion injection method using a mask.

Next, the negative charge layer 5 is formed. The negative charge layer 5 can be formed, for example, as follows.

That is, first, as shown in FIG. 9, the insulating film 5a is formed on the entire back surface 2b of the semiconductor substrate 2. The insulating film 5a can be formed by using a CVD method, an ALD method, or the like, but when the insulating film 5a is formed, a negative fixed charge (electrons in this case) is stored in the formed insulating film 5a. In addition, a film forming step of the insulating film 5a is performed. As a result, the insulating film 5a containing a negative fixed charge is formed inside.

The insulating film 5a includes at least one selected from the group consisting of aluminum (Al), titanium (Ti), tantalum (Ta), magnesium (Mg), hafnium (Hf), zirconium (Zr) and scandium (Sc). It is composed of an insulating film containing oxygen (O) as a main component. Therefore, the insulating film 5a is made of a metal oxide, and the metal elements constituting the metal oxide are aluminum (Al), titanium (Ti), tantalum (Ta), magnesium (Mg), hafnium (Hf), and the like. It consists of at least one selected from the group consisting of zirconium (Zr) and scandium (Sc). The insulating film 5a may further contain silicon (Si), hydrogen (H), and the like. When the insulating film 5a also contains silicon (Si), the insulating film 5a is made of a metal silicate, and the metal elements constituting the metal silicate are aluminum (Al), titanium (Ti), tantalum (Ta), magnesium ( It consists of at least one selected from the group consisting of Mg), hafnium (Hf), zirconium (Zr) and scandium (Sc).

Then, as shown in FIG. 10, the insulating film 5a is partially removed. That is, the insulating film 5a other than the portion left as the negative charge layer 5 is removed. The negative charge layer 5 is formed by the remaining insulating film 5a. The insulating film 5a on the n-type semiconductor region 3 is removed. The negative charge layer 5 is located on the back surface 2b of the semiconductor substrate 2 and is in contact with the back surface 2b of the semiconductor substrate 2. In the case of FIG. 10, the negative charge layer 5 is arranged in the region from which the n-type semiconductor region 3a has been removed in the step of FIG. As a method for partially removing the insulating film 5a, for example, an etching method can be used, but other methods (for example, laser processing) can also be used.

Next, as shown in FIG. 11, an insulating film 6 is formed on the entire back surface 2b of the semiconductor substrate 2 so as to cover the n-type semiconductor region 3 and the negative charge layer 5.

The insulating film 6 is preferably made of an insulating material different from that of the insulating film 5a. That is, it is preferable that the insulating film 6 does not use a material suitable for the insulating film 5a as described above. Specifically, the insulating film 6 is selected from the group consisting of aluminum (Al), titanium (Ti), tantalum (Ta), magnesium (Mg), hafnium (Hf), zirconium (Zr) and scandium (Sc). It is preferable that the titanium element is not contained as a main component, and from another viewpoint, the insulating film 6 is preferably not a metal oxide film. This is because the insulating film 5a is an insulating film containing a negative fixed charge, but the insulating film 6 preferably contains as little negative fixed charge as possible. Thereby, in the manufactured solar cell, it is possible to suppress or prevent the insulating film 6 from adversely affecting the n-type semiconductor region 3. As the insulating film 6, for example, a silicon nitride film or a silicon oxide film can be preferably used. The insulating film 6 can be formed by using, for example, a CVD method or the like.

Next, as shown in FIG. 12, an opening 11 penetrating the insulating film 6 and the negative charge layer 5 is formed. The opening 11 can be formed, for example, by using an etching method. At the bottom of the opening 11, the back surface 2b of the semiconductor substrate 2 is exposed. It should be noted that what is exposed at the bottom of the opening 11 is not the n-type semiconductor region 3 but the p-type substrate region (p-type semiconductor substrate 2).

Next, as shown in FIG. 13, an electrode material portion 7a made of an electrode material for the electrode 7 and an electrode material portion 8a made of an electrode material for the electrode 8 are formed. The electrode material portion 7a and the electrode material portion 8a are made of different materials. The electrode material portion 7a and the electrode material portion 8a can be formed by using a printing method, respectively. The electrode material portion 7a is formed on the insulating film 6 and is not in contact with the semiconductor substrate 2. However, the electrode material portion 7a is formed at a position overlapping the n-type semiconductor region 3 in a plan view. On the other hand, the electrode material portion 8a is formed so as to fill the inside of the opening 11, and therefore is formed so as to overlap the opening 11 in a plan view. Therefore, the electrode material portion 8a is in contact with the back surface 2b (p-type substrate region) of the semiconductor substrate 2 exposed from the opening 11.

Next, the electrode material portion 7a and the electrode material portion 8a are sintered by performing a heat treatment. The heat treatment can be performed using, for example, a firing furnace. The electrode 7 is formed by sintering the electrode material portion 7a by heat treatment, and the electrode 8 is formed by sintering the electrode material portion 8a by heat treatment.

The electrode material portion 8a contains aluminum (Al) as a main component (main conductor component). In other words, the electrode material portion 8a contains, as a main component, a metal that functions as a p-type impurity when diffused in the semiconductor substrate 2, that is, aluminum (Al). Therefore, the electrode 8 formed by sintering the electrode material portion 8a is an aluminum (Al) electrode containing aluminum (Al) as a main component. By the heat treatment, the electrode material constituting the electrode material portion 8a can form an alloy layer (Al—Si alloy layer) with the semiconductor substrate 2. Therefore, an Al—Si alloy layer may exist at the interface between the electrode 8 and the semiconductor substrate 2. Further, during the heat treatment for sintering the electrode material portion 8a, aluminum (Al) in the electrode material constituting the electrode material portion 8a diffuses into the semiconductor substrate 2, so that it can function as a p-type impurity. The p-type semiconductor region 4 into which aluminum (Al) is introduced is formed. Therefore, the electrodes 7 and 8 and the p-type semiconductor region 4 can be formed by a common heat treatment. The p-type semiconductor region 4 is larger than the p-type substrate region (p-type semiconductor substrate 2) around the p-type semiconductor region 4 due to the introduction (doping) of aluminum (Al) that can function as a p-type impurity. , The p-type impurity concentration becomes high. The p-type semiconductor region 4 is formed at a position adjacent to the electrode 8 on the semiconductor substrate 2, but even if the above-mentioned Al—Si alloy layer is interposed between the p-type semiconductor region 4 and the electrode 8. good. The electrode 8 is electrically connected to the p-type semiconductor region 4.

Further, the electrode material portion 7a contains a metal other than aluminum (Al) as a main component (main conductor component), and here, silver (Ag) is contained as a main component. In other words, the electrode material portion 7a contains a metal as a main component, which does not function as a p-type impurity when diffused into the semiconductor substrate 2. Therefore, the electrode 7 formed by sintering the electrode material portion 7a is an electrode whose main component is a metal other than aluminum (Al), and here, a silver (Ag) electrode whose main component is silver (Ag). Is. In the heat treatment, the electrode material constituting the electrode material portion 7a penetrates the insulating film 6 to reach the n-type semiconductor region 3 and causes a sintering reaction with the n-type semiconductor region 3. Therefore, the electrode 7 is in a state of penetrating the insulating film 6, is in contact with the n-type semiconductor region 3, and is electrically connected to the n-type semiconductor region 3. Since the main component (main conductor component) of the electrode material portion 7a is not aluminum (Al), it can function as a p-type impurity in the n-type semiconductor region 3 during the heat treatment for sintering the electrode material portion 7a. It is possible to prevent aluminum (Al) from being diffused. Therefore, the optimum impurity concentration in the n-type semiconductor region 3 can be maintained.

As another form, the electrode material portion 7a may contain aluminum (Al) as a main component (main conductor component). In that case, not only the electrode 8 but also the electrode 7 becomes an aluminum electrode. However, in that case, a device for preventing aluminum (Al), which can function as a p-type impurity, from being diffused into the n-type semiconductor region 3 during the heat treatment for sintering the electrode material portion 7a. Need to be applied.

On the other hand, in the present embodiment, since the main component (main conductor component) of the electrode material portion 7a (electrode 7) is a metal other than aluminum (Al), the electrode material portion 7a is fired without any special measures. It is possible to prevent aluminum (Al), which can function as a p-type impurity, from being diffused into the n-type semiconductor region 3 during the heat treatment for binding. Therefore, the manufacturing process of the solar cell 1 can be easily performed.

In this way, the solar cell 1 of the present embodiment can be manufactured.

<Background of examination>
In general, solar cells are often manufactured using a p-type semiconductor substrate, and therefore, as manufacturing equipment for solar cells, manufacturing equipment premised on a p-type semiconductor substrate is widespread.

By the way, in recent years, a backside electrode type solar cell in which an electrode is formed only on the back surface of a semiconductor substrate has been developed because the light receiving area can be increased without being disturbed by the electrode and the photoelectric conversion efficiency can be improved. Is underway.

However, the back electrode type solar cell is being developed on the premise that an n-type semiconductor substrate is used. In a back electrode type solar cell using an n-type semiconductor substrate, a structure in which a p-type emitter region and an n-type BSF region are arranged on the back surface side of the n-type semiconductor substrate is adopted. However, when manufacturing a back electrode type solar cell using an n-type semiconductor substrate, it is difficult to use conventional manufacturing equipment premised on a p-type semiconductor substrate. However, it is not a good idea to introduce a new manufacturing facility based on an n-type semiconductor substrate because it increases the manufacturing cost of the solar cell.

Therefore, the present inventor is studying the manufacture of a back electrode type solar cell using a p-type semiconductor substrate. If a back electrode type solar cell can be manufactured using a p-type semiconductor substrate, the conventional manufacturing equipment based on the p-type semiconductor substrate can be diverted, so that capital investment can be suppressed and the manufacturing cost of the solar cell can be suppressed. can do.

Even when a back electrode type solar cell is manufactured using a p-type semiconductor substrate, it is desired to improve the characteristics of the solar cell as much as possible.

<About study examples>
FIG. 15 is a cross-sectional view of a main part of the solar cell 101 of the first study example examined by the present inventor, and the cross section corresponding to FIG. 1 is shown.

As shown in FIG. 15, the solar cell 101 of the first study example has an n-type semiconductor substrate 102 into which n-type impurities have been introduced, and the semiconductor substrate 102 is a silicon substrate made of crystalline silicon. .. The semiconductor substrate 102 has a front surface 102a, which is a light receiving surface, and a back surface 102b, which is opposite to the front surface 102a.

As shown in FIG. 15, in the n-type semiconductor substrate 102, the p-type emitter region (p-type semiconductor region) 103 in which the p-type impurity is introduced and the n-type impurity are contained in the semiconductor substrate 102 on the back surface 102b side. An n-type BSF region (n-type semiconductor region) 104 introduced at a higher concentration is formed. An insulating film 106, an emitter electrode 107, and a BSF electrode 108 are formed on the back surface 102b of the semiconductor substrate 102. The emitter electrode 107 penetrates the insulating film 106 and is connected to the p-type emitter region 103, and the BSF electrode 108 penetrates the insulating film 106 and is connected to the n-type BSF region 104.

In the solar cell 101 of the first study example shown in FIG. 15, when sunlight is incident on the inside of the semiconductor substrate 102 from the surface 102a of the semiconductor substrate 102, the light energy is larger than the band gap of silicon contained in the sunlight. The light it has is absorbed and electrons are excited in the conduction band, and holes are generated in the valence band. Then, holes are accumulated in the p-type emitter region 103 that constitutes one of the PN junctions, and electrons are accumulated in the n-type substrate region and the n-type BSF region 104 of the semiconductor substrate 102 that constitutes the other of the PN junctions. As a result, an electromotive force is generated between the emitter electrode 107 and the BSF electrode 108. Then, by connecting a load between the emitter electrode 107 and the BSF electrode 108 outside the solar cell 101, a current can flow from the emitter electrode 107 to the BSF electrode 108 through the load. The n-type BSF region 104 also has a function of alienating holes, which are minority carriers, and suppressing recombination of holes and electrons.

FIG. 16 is a cross-sectional view of a main part of the solar cell 201 of the second study example examined by the present inventor, and shows a cross section corresponding to the above FIGS. 1 and 15.

The solar cell 201 of the second study example shown in FIG. 16 corresponds to the solar cell 101 of the first study example shown in FIG. 15 in which the n-type and the p-type are interchanged. The solar cell 101 of the first study example of FIG. 15 is manufactured by using the n-type semiconductor substrate 102, but the n-type semiconductor substrate is based on the structure of the solar cell 101 of the first study example of FIG. If a p-type semiconductor substrate is to be applied instead of 102, the structure of the solar cell 201 of the second study example of FIG. 16 is assumed.

As shown in FIG. 16, the solar cell 201 of the second study example has a p-type semiconductor substrate 202 into which p-type impurities have been introduced, and the semiconductor substrate 202 is a silicon substrate made of crystalline silicon. .. The semiconductor substrate 202 has a front surface 202a, which is a light receiving surface, and a back surface 202b, which is opposite to the front surface 202a.

As shown in FIG. 16, in the p-type semiconductor substrate 202, on the back surface 202b side, an n-type emitter region (n-type semiconductor region) 203 in which n-type impurities are introduced and a p-type impurity are semiconductor substrate 202. A p-type BSF region (p-type semiconductor region) 204 introduced at a higher concentration is formed. An insulating film 206, an emitter electrode 207, and a BSF electrode 208 are formed on the back surface 202b of the semiconductor substrate 202. The emitter electrode 207 penetrates the insulating film 206 and is connected to the n-type emitter region 203, and the BSF electrode 208 penetrates the insulating film 206 and is connected to the p-type BSF region 204.

In the solar cell 201 of the second study example shown in FIG. 16, when sunlight is incident on the inside of the semiconductor substrate 202 from the surface 202a of the semiconductor substrate 202, the light energy is larger than the band gap of silicon contained in the sunlight. The light it has is absorbed and electrons are excited in the conduction band, and holes are generated in the valence band. Then, electrons are accumulated in the n-type emitter region 203 that constitutes one of the PN junctions, and holes are accumulated in the p-type substrate region and the p-type BSF region 204 of the semiconductor substrate 202 that constitutes the other of the PN junctions. As a result, an electromotive force is generated between the emitter electrode 207 and the BSF electrode 208. Then, by connecting a load between the emitter electrode 207 and the BSF electrode 208 outside the solar cell 201, a current can flow from the BSF electrode 208 to the emitter electrode 207 through the load. The p-type BSF region 204 also has a function of alienating electrons, which are minority carriers, and suppressing recombination of electrons and holes.

<Main features and effects>
In the solar cell 1 of the present embodiment, the p-type semiconductor substrate 2 is used, and on the back surface 2b side of the semiconductor substrate 2, the n-type semiconductor region 3 which is an n-type emitter region and the p-type BSF region p. A type semiconductor region 4 is provided, and a negative charge layer 5 is provided on the back surface 2b of the semiconductor substrate 2. The electrode 8 penetrates the negative charge layer 5 and is connected to the p-type semiconductor region 4. The negative charge layer 5 is made of an insulator containing a negative fixed charge.

When sunlight is incident on the inside of the semiconductor substrate 2 from the surface 2a of the semiconductor substrate 2, light having a light energy larger than the band gap of silicon contained in the sunlight is absorbed and electrons are excited in the conduction band, and at the same time, electrons are excited. Holes are generated in the valence band. In this embodiment, since the p-type semiconductor substrate 2 is used, the minority carriers are electrons. When electrons, which are minority carriers generated by sunlight incident on the semiconductor substrate 2, recombine with holes and disappear, the photoelectric conversion efficiency of the solar cell decreases. Therefore, it is desirable to suppress or prevent electrons from recombination with holes.

In the present embodiment, the p-type semiconductor region 4 is provided as the p-type BSF region in the p-type semiconductor substrate 2, the negative charge layer 5 is provided on the back surface 2b of the p-type semiconductor substrate 2, and the electrode 8 is negative. It penetrates the charge layer 5 and connects to the p-type semiconductor region 4.

Since the negative charge layer 5 contains a negative fixed charge (electrons in this case) inside, it has a function of keeping the electrons in the semiconductor substrate 2 away from the negative charge layer 5 and suppressing the recombination of electrons and holes. Have. Further, the p-type semiconductor region 4 has a function of keeping electrons in the semiconductor substrate 2 away from the p-type semiconductor region 4 and suppressing recombination of electrons and holes. That is, both the negative charge layer 5 and the p-type semiconductor region 4 have a function of moving electrons away and suppressing recombination between electrons and holes. In the present embodiment, by providing the negative charge layer 5 and the p-type semiconductor region 4, recombination of electrons and holes is suppressed, so that the photoelectric conversion efficiency of the solar cell can be improved. ..

In the case of the solar cell 201 of the second study example, the p-type BSF region 204 is formed on the back surface 202b side of the p-type semiconductor substrate 202, but the one corresponding to the negative charge layer 5 of the present embodiment is Not formed. In the case of the second study example, the p-type BSF region 204 is responsible for the function of suppressing the recombination of electrons, which are minority carriers, with the holes, and in the case of the present embodiment, the negative charge layer 5 and the p-type. Both of the semiconductor regions 4 are responsible. Therefore, it is easier to suppress the recombination of electrons, which are minority carriers, with holes in the present embodiment than in the second study example, so that the photoelectric conversion efficiency of the solar cell can be further improved. can. Therefore, the characteristics of the solar cell can be improved.

Further, in the present embodiment, the function of suppressing the recombination of electrons, which are minority carriers, with holes is borne by both the negative charge layer 5 and the p-type semiconductor region 4. It also has advantages such as.

That is, in the case of the second study example, the p-type BSF region 204 is responsible for the function of suppressing the recombination of electrons, which are minority carriers, with holes, but the p-type BSF region 204 is the electrode for BSF. It also has the function of reducing the contact resistance of 208. However, in order to reduce the contact resistance of the BSF electrode 208, it is desirable to increase the p-type impurity concentration in the p-type BSF region 204 as much as possible, but the p-type impurity concentration in the p-type BSF region 204 is too high. If this happens, the function of suppressing the recombination of electrons and holes by the p-type BSF region 204 may be reduced. That is, regarding the p-type impurity concentration in the p-type BSF region 204, the optimum concentration for reducing the contact resistance of the BSF electrode 208 and the optimum concentration for suppressing the recombination of electrons and holes are determined. It's different. Therefore, in the case of the second study example, it is difficult to achieve both reduction of the contact resistance of the BSF electrode 208 and suppression of recombination of electrons and holes.

In the present embodiment, the p-type semiconductor region 4 has not only a function of suppressing recombination of electrons and holes but also a function of reducing the contact resistance of the electrode 8 which is a BSF electrode. In order to reduce the contact resistance of the electrode 8, it is desirable to increase the p-type impurity concentration in the p-type semiconductor region 4 as much as possible. However, if the p-type impurity concentration in the p-type semiconductor region 4 is too high, p The action of suppressing the recombination of electrons and holes by the type semiconductor region 4 may be reduced. Therefore, regarding the concentration of the p-type semiconductor region 4p-type impurity, the optimum concentration for reducing the contact resistance of the electrode 8 and the optimum concentration for suppressing the recombination of electrons and holes are different. There is.

However, in the present embodiment, both the negative charge layer 5 and the p-type semiconductor region 4 have a function of suppressing recombination of electrons and holes. Therefore, the p-type impurity concentration in the p-type semiconductor region 4 is set to a concentration suitable for reducing the contact resistance of the electrode 8, thereby suppressing the recombination of electrons and holes in the p-type semiconductor region 4. Even if the action of the negative charge layer 5 is reduced to some extent, the function of suppressing the recombination of electrons and holes by the negative charge layer 5 can be obtained. It is possible to sufficiently secure the action of suppressing the binding. Therefore, in the present embodiment, both the negative charge layer 5 and the p-type semiconductor region 4 have a function of suppressing recombination of electrons and holes, thereby reducing the contact resistance of the electrode 8. , Suppression of recombination of electrons and holes can be compatible. Therefore, the characteristics of the solar cell can be improved, and the overall performance of the solar cell can be improved.

Further, the electrode 8 needs to be electrically connected to the p-type semiconductor substrate 2, but since the negative charge layer 5 is made of an insulator, the electrode 8 and the p-type semiconductor substrate 2 are electrically connected to each other. , It is necessary to prevent the negative charge layer 5 from interfering with it. In the present embodiment, since the electrode 8 penetrates the negative charge layer 5, the electrode 8 and the p-type semiconductor region 4 can be connected without the negative charge layer 5 getting in the way.

Further, when the electrode 8 penetrates the negative charge layer 5, the negative charge layer 5 does not exist at a position where the connection portion between the electrode 8 and the semiconductor substrate 2 overlaps in a plan view, but instead, the p-type The semiconductor region 4 exists at a position where it overlaps the connection portion between the electrode 8 and the semiconductor substrate 2 in a plan view. Preferably, the p-type semiconductor region 4 includes a connection portion between the electrode 8 and the semiconductor substrate 2 in a plan view. Therefore, in a plan view, the p-type semiconductor region 4 can be arranged in a region where the negative charge layer 5 cannot be arranged (that is, a region overlapping the electrode 8), and the negative charge layer 5 and the p-type semiconductor region 4 can be arranged. Since both have a function of suppressing the recombination of electrons and holes, the action of suppressing the recombination of electrons and holes can be efficiently obtained.

Further, as another feature of the present embodiment, the p-type semiconductor region 4 can be formed by diffusing aluminum (Al) from the electrode material portion 8a. As a result, the following advantages can be obtained.

That is, the p-type semiconductor region 4 has a function of alienating electrons and suppressing recombination of electrons and holes, but it is desirable that the plane size (flat area) of the p-type semiconductor region 4 is small to some extent. .. This is because, even though the p-type semiconductor region 4 has a function of suppressing the recombination of electrons and holes, the p-type semiconductor region 4 itself contains a large number of conductive impurities that are acceptors. This is because there is a concern that this acceptor will function as a recombination center. That is, from the viewpoint of reducing the recombination center, it is desirable that the plane dimension (flat area) of the p-type semiconductor region 4 is small to some extent.

On the other hand, in the present embodiment, the p-type semiconductor region 4 is formed by diffusing aluminum (Al) from the electrode material portion 8a. Therefore, the plane dimension (flat area) of the p-type semiconductor region 4 can be about the same as or slightly larger than the connection (contact) area between the electrode 8 and the semiconductor substrate 2. Therefore, since the plane size (flat area) of the p-type semiconductor region 4 can be suppressed to a certain extent, the action of suppressing the recombination of electrons and holes by the p-type semiconductor region 4 can be accurately obtained. Can be done.

On the other hand, unlike the p-type semiconductor region 4, the negative charge layer 5 does not contain a large number of conductive impurities that can function as recombination centers. Therefore, it is not necessary to reduce the plane size (flat area) of the p-type semiconductor region 4, and in order to increase the effect of suppressing the recombination of electrons and holes by the negative charge layer 5, the plane of the negative charge layer 5 is increased. Larger dimensions (flat area) are more advantageous. In the present embodiment, the electrode 8 penetrates the negative charge layer 5, but since the negative charge layer 5 can be arranged around the connection portion between the electrode 8 and the semiconductor substrate 2 in a plan view, the negative charge layer 5 can be arranged. The plane dimension (flat area) of the layer 5 can be increased, and the plane dimension (flat area) of the negative charge layer 5 can be made larger than the plane dimension (flat area) of the p-type semiconductor region 4. Therefore, the action of suppressing the recombination of electrons and holes by the p-type semiconductor region 4 and the action of suppressing the recombination of electrons and holes by the negative charge layer 5 can be accurately obtained.

Further, since the electrode 8 penetrates the negative charge layer 5, the negative charge layer 5 exists around the electrode 8 in a plan view. Further, in a plan view, the p-type semiconductor region 4 exists at a position overlapping the electrode 8. Therefore, even when the plane dimension of the p-type semiconductor region 4 is small (when it is about the same as or slightly larger than the connection area between the electrode 8 and the semiconductor substrate 2), it is negative around the p-type semiconductor region 4 in a plan view. The charge layer 5 will be present. Therefore, the p-type semiconductor region 4 and the negative charge layer 5 can efficiently obtain the effect of suppressing the recombination of electrons and holes.

Further, in the present embodiment, since the p-type semiconductor region 4 is formed by diffusing aluminum (Al) from the electrode material portion 8a to the semiconductor substrate 2, p is at a position where it overlaps with the electrode 8 in a plan view. The type semiconductor region 4 can be formed in a self-aligned manner. Therefore, the electrode 8 can be reliably connected to the p-type semiconductor region 4 having a high impurity concentration, and the electrode 8 can be electrically connected to the p-type substrate region via the p-type semiconductor region 4. When the plane dimension (flat area) of the p-type semiconductor region 4 is small, if the positions of the electrode 8 and the p-type semiconductor region 4 are displaced, the reliability of the connection between the electrode 8 and the p-type semiconductor region 4 is reliable. However, in the present embodiment, the p-type semiconductor region 4 can be self-consistently formed at a position where it overlaps with the electrode 8 in a plan view, so that the plane dimension (flat) of the p-type semiconductor region 4 can be formed. Even if the area) is small, the positions of the electrode 8 and the p-type semiconductor region 4 do not shift. Therefore, in the present embodiment, the electrode 8 and the p-type semiconductor region 4 can be reliably connected, and the plane dimension (flat area) of the p-type semiconductor region 4 can be suppressed. In other words, in the present embodiment, both the electrode 8 and the p-type semiconductor region 4 can be reliably connected and the plane dimension (flat area) of the p-type semiconductor region 4 can be suppressed at the same time. .. As a result, the contact resistance of the electrode 8 can be accurately reduced, and the effect of suppressing the recombination of electrons and holes by the p-type semiconductor region 4 can be accurately obtained.

FIG. 17 is a table showing the results of examining the characteristics of the solar cell. The table of FIG. 17 shows the maximum recombination rate (Smax) and the potential open circuit voltage (Implied-Voc) in each of the present embodiment (structure of FIG. 1) and the second study example (structure of FIG. 16). The result of investigating and is shown. The smaller the maximum recombination rate (Smax), the better the characteristics of the solar cell, and the larger the potential open circuit voltage (Implied-Voc), the better the characteristics of the solar cell.

As can be seen from the table of FIG. 17, when the structure of FIG. 16 (second study example) is applied, the maximum recombination rate (Smax) is relatively large at about 1950 cm / s, and the potential open voltage (potential open voltage) ( Implied-Voc) is relatively small, about 576 mV. On the other hand, when the structure of FIG. 1 (the present embodiment) is applied, the maximum recombination rate (Smax) is relatively small at about 57 cm / s, and the potential open circuit voltage (Implied-Voc) is about 664 mV. Relatively large. This is because the effect of suppressing the recombination of electrons and holes is more effective when the structure of FIG. 1 (the present embodiment) is applied than when the structure of FIG. 16 (second study example) is applied. It is probable that it was large. In the case of the present embodiment, it is easy to suppress the recombination of electrons, which are minority carriers, with holes, so that the characteristics of the solar cell can be improved.

(Embodiment 2)
In the second embodiment, a modified example of the method for manufacturing the solar cell of the first embodiment will be described with reference to FIGS. 18 and 19. 18 and 19 are cross-sectional views showing the manufacturing process of the solar cell of the second embodiment, and the cross section corresponding to FIG. 1 is shown.

Until the structure of FIG. 11 is obtained, the manufacturing process of the second embodiment is the same as that of the first embodiment, and thus the repeated description thereof will be omitted here.

After obtaining the structure of FIG. 11 in the same manner as in the first embodiment, in the second embodiment, the step of FIG. 12 (that is, the step of forming the opening 11 in the insulating film 6 and the negative charge layer 5). As shown in FIG. 18, the electrode material portion 7a and the electrode material portion 8a are formed on the insulating film 6. Each material of the electrode material portion 7a and the electrode material portion 8a and the forming method are the same as those described in the first embodiment.

Further, in the case of the first embodiment, since the electrode material portion 7a and the electrode material portion 8a are formed after the opening 11 is formed, the inside of the opening 11 is filled with the electrode material portion 8a. The electrode material portion 8a was in contact with the back surface 2b of the semiconductor substrate 2 exposed from the opening 11. On the other hand, in the second embodiment, since the electrode material portion 7a and the electrode material portion 8a are formed without forming the opening 11, the electrode material portion 7a and the electrode material portion 8a are present on the insulating film 6. , It is not in contact with the semiconductor substrate 2. The electrode material portion 7a is formed at a position overlapping the n-type semiconductor region 3 in a plan view, and is therefore formed so as to be included in the n-type semiconductor region 3 in a plan view. Further, the electrode material portion 8a is formed at a position overlapping the negative charge layer 5 in a plan view, and is therefore formed so as to be included in the negative charge layer 5 in a plan view.

Next, the electrode material portion 7a and the electrode material portion 8a are sintered by performing a heat treatment. The electrode material portion 7a is sintered by heat treatment to form the electrode 7 as shown in FIG. 19, and the electrode material portion 8a is sintered by heat treatment to form the electrode 8 as shown in FIG. Will be done.

Similar to the first embodiment, in the second embodiment as well, in the heat treatment, the electrode material constituting the electrode material portion 7a penetrates the insulating film 6 and reaches the n-type semiconductor region 3, and the n-type semiconductor region. A sintering reaction occurs with 3. Therefore, similarly to the first embodiment, in the second embodiment as well, the electrode 7 is in a state of penetrating the insulating film 6 and is in contact with the n-type semiconductor region 3 and electrically with the n-type semiconductor region 3. Be connected.

Further, in the second embodiment, the opening 11 was not formed before the electrode material portion 8a was formed, but in the heat treatment, the electrode materials constituting the electrode material portion 8a were the insulating film 6 and the negative charge layer. It penetrates 5 and reaches the semiconductor substrate 2, and causes a sintering reaction with the semiconductor substrate 2. Therefore, the electrode 8 is in a state of penetrating the insulating film 6 and the negative charge layer 5, is in contact with the semiconductor substrate 2, and is electrically connected to the semiconductor substrate 2. Further, during the heat treatment for sintering the electrode material portion 8a, when the electrode material constituting the electrode material portion 8a penetrates the insulating film 6 and the negative charge layer 5 and reaches the semiconductor substrate 2, the electrode material portion By diffusing aluminum (Al) in the electrode material constituting 8a into the semiconductor substrate 2, a p-type semiconductor region 4 in which aluminum (Al) capable of functioning as a p-type impurity is introduced is formed. Therefore, the electrodes 7 and 8 and the p-type semiconductor region 4 can be formed by a common heat treatment. The p-type semiconductor region 4 is formed at a position adjacent to the electrode 8 on the semiconductor substrate 2, and the Al—Si alloy layer described in the first embodiment is between the p-type semiconductor region 4 and the electrode 8. May intervene. The electrode 8 is electrically connected to the p-type semiconductor region 4.

In this way, the solar cell 1 can be manufactured. Since the structure of the solar cell manufactured in the second embodiment is basically the same as that of the solar cell 1 of the first embodiment, the repeated description will be omitted here.

In the case of the second embodiment, since the step of FIG. 12 (that is, the step of forming the opening 11 in the insulating film 6 and the negative charge layer 5) is unnecessary, the number of manufacturing steps can be reduced and the solar cell can be manufactured. The cost can be reduced.

On the other hand, in the case of the first embodiment, since the electrode material portion 7a is formed after the opening 11 is formed, the electrode material portion 8a is formed during the heat treatment for sintering the electrode material portion 8a. Since the aluminum (Al) in the electrode material is easily diffused into the semiconductor substrate 2, the p-type semiconductor region 4 can be formed more easily and accurately. Further, it becomes easy to control the heat treatment process for sintering the electrode material portions 7a and 8a.

(Embodiment 3)
In the third embodiment, a further modification of the method for manufacturing the solar cell of the first embodiment will be described with reference to FIGS. 20 to 25. 20 to 25 are cross-sectional views showing the manufacturing process of the solar cell of the third embodiment, and the cross section corresponding to FIG. 1 is shown.

Until the structure of FIG. 7 is obtained, the manufacturing process of the third embodiment is the same as the manufacturing process of the first embodiment, and thus the repeated description thereof will be omitted here. After obtaining the structure of FIG. 7 in the same manner as in the first embodiment, in the third embodiment, as shown in FIG. 20, on the back surface 2b of the semiconductor substrate 2, that is, on the n-type semiconductor region 3a. In addition, the insulating film 21 is formed. The insulating film 21 is made of, for example, a silicon oxide film or a silicon nitride film, and can be formed by using a CVD method or the like. The n-type semiconductor region 3a is covered with the insulating film 21.

The insulating film 21 and the insulating film 5a are made of different insulating materials. As the insulating film 21, a material suitable for the insulating film 5a as described in the first embodiment is not used. Specifically, the insulating film 21 is selected from the group consisting of aluminum (Al), titanium (Ti), tantalum (Ta), magnesium (Mg), hafnium (Hf), zirconium (Zr) and scandium (Sc). It is preferable that the titanium element is not contained as a main component, and from another viewpoint, the insulating film 21 is preferably not a metal oxide film. This is because the insulating film 5a is an insulating film containing a negative fixed charge, but the insulating film 21 preferably contains as little negative fixed charge as possible. Thereby, in the manufactured solar cell, it is possible to suppress or prevent the insulating film 21 from adversely affecting the n-type semiconductor region 3.

Next, as shown in FIG. 21, the laminated structure of the n-type semiconductor region 3a and the insulating film 21 is patterned. That is, the n-type semiconductor region 3a other than the portion left as the n-type semiconductor region 3 and the insulating film 21 on the n-type semiconductor region 3a are removed. For this step, for example, an etching method can be used, but other methods (for example, laser processing) can also be used.

The remaining n-type semiconductor region 3a forms an n-type semiconductor region 3 as an emitter region, and an insulating film 21 having the same planar shape as the n-type semiconductor region 3 remains on the n-type semiconductor region 3. In the region where the n-type semiconductor region 3a is removed, the insulating film 21 is also removed. The structure at this stage (the structure of FIG. 21) is different from the structure of FIG. 8 in that the n-type semiconductor region 3 is covered with the insulating film 21 having the same planar shape as the n-type semiconductor region 3.

Next, as shown in FIG. 22, an insulating film 5a is formed on the back surface 2b of the semiconductor substrate 2 so as to cover the insulating film 21. Similar to the first embodiment, the insulating film 5a is an insulating film containing a negative fixed charge (here, an electron) inside. As for the material of the insulating film 5a and the film forming method, the third embodiment is the same as that of the first embodiment, and thus the repeated description will be omitted here.

An insulating film 21 is interposed between the n-type semiconductor region 3 and the insulating film 5a. Therefore, since the lower surface of the n-type semiconductor region 3 is covered with the insulating film 21, it is not in contact with the insulating film 5a. The portion of the insulating film 5a located on the p-type substrate region becomes the negative charge layer 5. That is, the portion of the insulating film 5a located on the p-type substrate region functions as a negative charge layer 5 and has a function of alienating electrons in the semiconductor substrate 2 and suppressing recombination of electrons and holes. ing.

Since the portion of the insulating film 5a located on the insulating film 21 is separated from the n-type semiconductor region 3 by the insulating film 21, it has almost no function of alienating electrons in the semiconductor substrate 2. Therefore, the portion of the insulating film 5a located on the insulating film 21 (shown as the connecting portion 5b in FIG. 22) does not have a function of suppressing the recombination of electrons and holes. It does not function as a negative charge layer. In other words, in the insulating film 5a, the portion (connecting portion 5b) located on the insulating film 21 is separated from the semiconductor substrate 2 by the insulating film 21, and therefore has a negative charge that affects the carriers in the semiconductor substrate 2. It does not function as a layer.

In the third embodiment, the insulating film 5a is not patterned, and the insulating film 5a remains on the insulating film 21. However, as another embodiment, the insulating film 21 of the insulating films 5a is formed. The portion located above may be removed. However, since the insulating film 5a on the insulating film 21 is separated from the semiconductor substrate 2 by the insulating film 21, the possibility of adversely affecting the n-type semiconductor region 3 is small. Therefore, as in the present embodiment, the insulating film 5a may remain on the insulating film 21, and when the insulating film 5a remains on the insulating film 21, the patterning step of the insulating film 5a is unnecessary. There is an advantage. On the other hand, when the portion of the insulating film 5a located on the insulating film 21 is removed, the risk that the insulating film 5a on the insulating film 21 adversely affects the n-type semiconductor region 3 can be eliminated.

Next, as shown in FIG. 23, the insulating film 6 is formed on the entire back surface 2b of the semiconductor substrate 2, that is, on the insulating film 5a.

Next, as shown in FIG. 24, the electrode material portion 7a and the electrode material portion 8a are formed on the insulating film 6. Each material of the electrode material portion 7a and the electrode material portion 8a and the forming method are the same as those described in the first embodiment.

Next, the electrode material portion 7a and the electrode material portion 8a are sintered by performing a heat treatment. The electrode 7 is formed by sintering the electrode material portion 7a by heat treatment, and the electrode 8 is formed by sintering the electrode material portion 8a by heat treatment.

Similar to the first and second embodiments, in the third embodiment as well, the electrode material constituting the electrode material portion 7a penetrates the insulating film 6 and reaches the n-type semiconductor region 3 in the heat treatment, and the n-type semiconductor A sintering reaction occurs with the region 3. Therefore, similarly to the first embodiment, in the second embodiment as well, the electrode 7 is in a state of penetrating the insulating film 6 and is in contact with the n-type semiconductor region 3 and electrically with the n-type semiconductor region 3. Be connected.

Further, as in the second embodiment, in the third embodiment as well, in the heat treatment, the electrode material constituting the electrode material portion 8a penetrates the insulating film 6 and the negative charge layer 5 (insulating film 5a) to form a semiconductor substrate. 2 is reached and a sintering reaction is generated with the semiconductor substrate 2. Therefore, the electrode 8 is in a state of penetrating the insulating film 6 and the negative charge layer 5 (insulating film 5a), is in contact with the semiconductor substrate 2, and is electrically connected to the semiconductor substrate 2. Further, during the heat treatment for sintering the electrode material portion 8a, when the electrode material constituting the electrode material portion 8a penetrates the insulating film 6 and the negative charge layer 5 and reaches the semiconductor substrate 2, the electrode material portion The p-type semiconductor region 4 is formed by diffusing aluminum (Al) in the electrode material constituting 8a into the semiconductor substrate 2.

In the third embodiment, the electrode material portion 8a is formed without forming the opening 11 as described in the first embodiment.

As another form, after forming an opening (corresponding to the opening 11) penetrating the insulating film 6 and the insulating film 5a (negative charge layer 5), the electrode material portion 7a and the electrode material portion 8a are formed. You can also do it. In this case, the inside of the opening penetrating the insulating film 6 and the insulating film 5a (negative charge layer 5) is filled with the electrode material portion 8a, and the electrode material portion 8a is the back surface 2b (p type) of the semiconductor substrate 2 exposed from the opening. It is in contact with the substrate area). After that, when heat treatment is performed, the electrode material constituting the electrode material portion 8a undergoes a sintering reaction with the semiconductor substrate 2, and aluminum (Al) in the electrode material constituting the electrode material portion 8a is a semiconductor. The p-type semiconductor region 4 is formed by diffusing into the substrate 2. The p-type semiconductor region 4 is formed at a position adjacent to the electrode 8 on the semiconductor substrate 2, and the Al—Si alloy layer described in the first embodiment is between the p-type semiconductor region 4 and the electrode 8. May intervene. The electrode 8 is electrically connected to the p-type semiconductor region 4.

Therefore, the electrodes 7 and 8 and the p-type semiconductor region 4 can be formed by a common heat treatment.

In this way, the solar cell 1a of the third embodiment can be manufactured. The difference between the structure of the solar cell 1a manufactured in the third embodiment and the structure of the solar cell 1 described in the first embodiment will be mainly described below.

The negative charge layer 5 is formed of an insulator containing a negative fixed charge, the negative charge layer 5 is formed on the back surface of the semiconductor substrate 2, and is in contact with the p-type substrate region (p-type semiconductor substrate 2). The points and the points at which the electrode 8 penetrates the negative charge layer 5 and connects the p-type semiconductor region 4 are common to the first embodiment and the third embodiment.

The differences between the first embodiment and the third embodiment are as follows.

That is, in the first embodiment, the negative charge layer 5 separated from each other is formed by patterning the insulating film 5a. Therefore, in the first embodiment, the negative charge layers 5 are not connected to each other, and the individual negative charge layers 5 are formed by independent insulating film portions.

On the other hand, in the third embodiment, the insulating film 5a is not patterned, and the common insulating film 5a constitutes a plurality of negative charge layers 5. Therefore, in the third embodiment, the plurality of negative charge layers 5 are not separated from each other but are integrally connected. That is, in the third embodiment, the insulating film 5a has a portion that is a negative charge layer 5 and a portion (connecting portion 5b) that connects the negative charge layers 5 to each other, and they are integrally formed. It is formed. In addition, in FIGS. 22 to 25, the portion connecting the negative charge layers 5 to each other is indicated by reference numeral 5b as a connecting portion 5b. An insulating film 21 is interposed between the connecting portion 5b connecting the negative charge layers 5 and the n-type semiconductor region 3. Therefore, the n-type semiconductor region 3 does not have to be in contact with the connecting portion 5b. Since the negative charge layer 5 is in contact with the p-type substrate region (p-type semiconductor substrate 2), the insulating film 21 is placed between the negative charge layer 5 and the p-type substrate region (p-type semiconductor substrate 2). Is not intervening. In other words, the negative charge layer 5 in the insulating film 5a is the portion in contact with the p-type substrate region (p-type semiconductor substrate 2), and is on the insulating film 21 in the insulating film 5a. The portion located in is not the negative charge layer 5 but the connecting portion 5b. Other than that, the structure of the solar cell 1a of the third embodiment is almost the same as the structure of the solar cell 1 described in the first embodiment, and thus the repeated description thereof will be omitted here.

Also in the case of the solar cell 1a of the third embodiment, both the negative charge layer 5 and the p-type semiconductor region 4 have a function of moving electrons away and suppressing recombination of electrons and holes. The photoelectric conversion efficiency of the solar cell can be improved.

Further, in the case of the third embodiment, since the step of patterning the insulating film 5a is unnecessary, the number of manufacturing steps of the solar cell can be suppressed, and the manufacturing cost of the solar cell can be suppressed.

Further, in the third embodiment, the portion of the insulating film 5a that is the negative charge layer 5 is in contact with the p-type substrate region (p-type semiconductor substrate 2), and keeps electrons that are minority carriers away. It has a function of suppressing the recombination of electrons and holes. On the other hand, the portion of the insulating film 5a that overlaps with the n-type semiconductor region 3 in a plan view (corresponding to the connecting portion 5b) is located on the insulating film 21. By interposing the insulating film 21 between the n-type semiconductor region 3 and the insulating film 5a (connecting portion 5b), the insulating film 5a (connecting portion 5b) can be prevented from adversely affecting the n-type semiconductor region 3. It can be prevented.

Although the invention made by the present inventor has been specifically described above based on the embodiment thereof, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say.

1,1a Solar cell 2 Semiconductor substrate 2a Front surface 2b Back surface 3 n-type semiconductor region 4 p-type semiconductor region 5 Negative charge layer 5a Insulation film 6 Insulation film 7, 8 Electrodes 7a, 8a Electrode material part 11 Opening 21 Insulation film 101 Sun Battery 102 Semiconductor substrate 102a Front surface 102b Back surface 103 p-type emitter region 104 n-type BSF region 106 Insulating film 107 Emitter electrode 108 BSF electrode 201 Solar cell 202 Semiconductor substrate 202a Front surface 202b Back surface 203 n-type emitter region 204 p-type BSF region 206 Insulating film 207 Emitter electrode 208 BSF electrode

Claims (16)

A p-type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface,
An n-type first semiconductor region formed on the second main surface side in the semiconductor substrate,
A p-type second semiconductor region formed on the second main surface side of the semiconductor substrate and having a higher p-type impurity concentration than the semiconductor substrate.
A negative charge layer formed on the second main surface and in contact with the p-type semiconductor substrate, and
The first electrode connected to the first semiconductor region and
The second electrode connected to the second semiconductor region and
Have,
The second electrode penetrates the negative charge layer and
The negative charge layer is a solar cell made of an insulator containing a negative fixed charge. In the solar cell according to claim 1,
The negative charge layer is a solar cell composed of at least one selected from the group consisting of aluminum, titanium, tantalum, magnesium, hafnium, zirconium and scandium, and an insulator containing oxygen as a main component. In the solar cell according to claim 1 or 2.
A solar cell in which an electrode is not formed on the first main surface side of the semiconductor substrate. In the solar cell according to any one of claims 1 to 3.
The first main surface of the semiconductor substrate is a solar cell, which is a light receiving surface. In the solar cell according to any one of claims 1 to 4.
A solar cell in which the second semiconductor region overlaps the second electrode in a plan view. In the solar cell according to any one of claims 1 to 5.
The second semiconductor region contains aluminum as a p-type impurity and contains aluminum.
The second electrode is a solar cell containing aluminum as a main component. In the solar cell according to claim 6.
The first electrode is a solar cell containing a metal other than aluminum as a main component. In the solar cell according to any one of claims 1 to 7.
It further has a first insulating film formed on the second main surface so as to cover the first semiconductor region and the negative charge layer.
The first electrode penetrates the first insulating film and penetrates.
The second electrode is a solar cell that penetrates the first insulating film and the negative charge layer. In the solar cell according to claim 8.
The first insulating film is a solar cell made of a silicon oxide film or a silicon nitride film. In the solar cell according to any one of claims 1 to 7.
Further having a second insulating film formed on the first semiconductor region,
The negative charge layer is composed of a part of the third insulating film.
The other part of the third insulating film is formed on the second insulating film.
A solar cell in which the second insulating film is interposed between the first semiconductor region and the third insulating film. In the solar cell according to claim 10.
The second insulating film is a solar cell made of a silicon oxide film or a silicon nitride film. In the solar cell according to claim 10 or 11.
Further having a first insulating film formed on the third insulating film,
The first electrode penetrates the first insulating film, the third insulating film, and the second insulating film.
The second electrode is a solar cell that penetrates the first insulating film and the negative charge layer. In the solar cell according to claim 12,
The first insulating film is a solar cell made of a silicon oxide film or a silicon nitride film. (A) A step of preparing a p-type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface.
(B) A step of forming an n-type first semiconductor region on the second main surface side in the semiconductor substrate.
(C) A step of forming a negative charge layer in contact with the p-type semiconductor substrate on the second main surface.
(D) A step of forming a first insulating film on the second main surface so as to cover the first semiconductor region and the negative charge layer.
(E) A first electrode that penetrates the first insulating film and connects to the first semiconductor region, and a second electrode that penetrates the first insulating film and the negative charge layer and connects to the semiconductor substrate. The process of forming,
Have,
The negative charge layer is composed of an insulator containing a negative fixed charge.
The second electrode contains aluminum as a main component and contains aluminum as a main component.
The step (e) includes a heat treatment step.
In the heat treatment step, aluminum diffuses from the second electrode to the semiconductor substrate, so that a p-type second semiconductor region having a higher p-type impurity concentration than the semiconductor substrate is formed in the semiconductor substrate. How to make a battery. In the method for manufacturing a solar cell according to claim 14,
The heat treatment step is a method for manufacturing a solar cell, which is performed to sinter the electrode material for the first electrode and the electrode material for the second electrode, respectively. In the method for manufacturing a solar cell according to claim 14 or 15.
The first electrode is a method for manufacturing a solar cell, which comprises a metal other than aluminum as a main component.

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