JP2020120068A - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of stabilizing the capacitance value of a capacitor is provided. A semiconductor device includes a semiconductor substrate, a first germanium film formed on the semiconductor substrate, a capacitor formed on the first germanium film, and a capacitor formed on the semiconductor substrate so as to cover the capacitor. and a formed interlayer insulating film. The capacitor has a lower electrode formed on the first germanium film, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film. [Selection drawing] Fig. 3

Description

The present invention relates to a semiconductor device.

A semiconductor device is described in Patent Document 1 (JP-A-2017-49504). The semiconductor device described in Patent Document 1 has a semiconductor substrate. The semiconductor substrate has a base body made of single crystal silicon, an insulating layer made of silicon oxide, and a semiconductor layer made of single crystal silicon. The insulating layer is formed on the base. The semiconductor layer is formed on the insulating layer and is a p-type semiconductor.

The semiconductor device described in Patent Document 1 has a photodiode. The photodiode has a germanium film formed on the semiconductor layer and a silicon film formed on the germanium film. The germanium film is an i-type semiconductor. The silicon film is an n-type semiconductor. That is, in the semiconductor device described in Patent Document 1, a pin type photodiode is formed by the semiconductor layer, the germanium film, and the silicon film. In the semiconductor device described in Patent Document 1, an interlayer insulating film is formed on a semiconductor substrate so as to cover the photodiode.

JP, 2017-49504, A

In order to stabilize the process of forming the germanium film and the silicon film, a germanium film is formed (hereinafter referred to as “dummy germanium film”) in a portion other than the portion where the photodiode is formed. When the semiconductor device described in Patent Document 1 requires a capacitor, the wiring formed on the interlayer insulating film and the silicon film formed on the dummy germanium film (hereinafter referred to as “dummy silicon film”) It is possible to form a capacitor by sandwiching an interlayer insulating film.

A step remains on the surface of the interlayer insulating film covering the dummy germanium film and the dummy silicon film. Therefore, the thickness of the interlayer insulating film between the wiring and the dummy silicon film varies, and as a result, the capacitance value of the capacitor also varies.

Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

A semiconductor device according to an embodiment is formed on a semiconductor substrate, a first germanium film formed on the semiconductor substrate, a capacitor formed on the first germanium film, and a semiconductor substrate so as to cover the capacitor. And an interlayer insulating film. The capacitor has a lower electrode formed on the first germanium film, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film.

According to the semiconductor device of one embodiment, it is possible to stabilize the capacitance value of the capacitor.

FIG. 3 is a schematic plan view of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view of the semiconductor device according to the first embodiment in a first region R1. FIG. 6 is a cross-sectional view of the semiconductor device according to the first embodiment in a second region R2. FIG. 6 is a plan view of the semiconductor device according to the first embodiment in a second region R2. FIG. 6 is a cross-sectional view of the semiconductor device according to the first embodiment in a third region R3. FIG. 6 is a process diagram showing the manufacturing method of the semiconductor device according to the first embodiment. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in semiconductor substrate preparation process S1. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in semiconductor layer patterning process S2. FIG. 6 is a cross-sectional view of the semiconductor device according to the first embodiment in an impurity diffusion region forming step S3. FIG. 9 is a cross-sectional view of the semiconductor device according to the first embodiment in an insulating film forming step S4. FIG. 11 is a cross-sectional view of the semiconductor device according to the first embodiment in first step S51 of epitaxial growth step S5. FIG. 11 is a cross-sectional view of the semiconductor device according to the first embodiment in a second step S52 of the epitaxial growth step S5. FIG. 9 is a cross-sectional view of the semiconductor device according to the first embodiment in a dielectric film forming step S6. FIG. 9 is a sectional view of the semiconductor device according to the first embodiment in an upper electrode forming step S7. FIG. 9 is a cross-sectional view of the semiconductor device according to the first embodiment in an interlayer insulating film forming step S8. It is sectional drawing of the semiconductor device which concerns on a comparative example in 2nd area|region R2. FIG. 11 is a cross-sectional view of the semiconductor device according to the first embodiment in the second region R2 when the value obtained by dividing the height H by the width W is 1/6 or more. It is a top view of the semiconductor device concerning a 2nd embodiment in the 2nd field R2. It is sectional drawing in XIX-XIX of FIG. It is a top view of the semiconductor device concerning a 2nd embodiment in the 2nd field R2. It is sectional drawing in XXI-XXI of FIG.

The details of the embodiment will be described with reference to the drawings. In the following drawings, the same or corresponding parts will be denoted by the same reference symbols and redundant description will not be repeated.

(First embodiment)
The configuration of the semiconductor device according to the first embodiment will be described below.

As shown in FIG. 1, the semiconductor device according to the first embodiment has a semiconductor substrate SUB. The semiconductor substrate SUB has a first region R1, a second region R2, and a third region R3 in plan view. A germanium film GF1 is formed in the first region R1. A germanium film GF2 is formed in the second region R2. The optical waveguide WG is formed in the third region R3. In the third region R3, optical elements such as a coupler and an optical modulator are formed in addition to the optical waveguide WG.

As shown in FIG. 2, the semiconductor substrate SUB has a support substrate SSUB and an insulating layer BOX. The support substrate SSUB is formed of single crystal silicon (Si). The insulating layer BOX is made of, for example, silicon oxide. The semiconductor substrate SUB further has a semiconductor layer SOI1 in the first region R1. The semiconductor layer SOI1 is formed of single crystal silicon. The semiconductor layer SOI1 is formed on the insulating layer BOX.

An impurity diffusion region DIF is formed on the surface of the semiconductor layer SOI1. The impurity diffusion region DIF is a p-type semiconductor. That is, the semiconductor layer SOI1 contains an acceptor such as boron (B) as an impurity in the impurity diffusion region DIF.

A germanium film GF1 is formed on the impurity diffusion region DIF. The germanium film GF1 is a film made of single crystal germanium (Ge) not doped with impurities. That is, the germanium film GF1 is an intrinsic semiconductor (i-type semiconductor).

The germanium film GF1 has an upper surface GF1a, a side surface GF1b and a side surface GF1c, an inclined surface GF1d and an inclined surface GF1e. The side surface GF1b and the side surface GF1c are the side surfaces of the germanium film GF1 facing each other. The inclined surface GF1d is connected to the upper surface GF1a and the side surface GF1b, and the inclined surface GF1e is connected to the upper surface GF1a and the side surface GF1c. The inclined surface GF1d and the inclined surface GF1e face each other. The distance between the inclined surface GF1d and the inclined surface GF1e increases as the distance from the upper surface GF1a increases.

A silicon film SIF1 is formed on the germanium film GF1. Specifically, the silicon film SIF1 is formed on the upper surface GF1a, the inclined surface GF1d, and the inclined surface GF1e. The silicon film SIF1 is a film made of single crystal silicon doped with impurities. The silicon film SIF1 is an n-type semiconductor. That is, the silicon film SIF1 contains a donor such as phosphorus (P) as an impurity.

As described above, since the impurity diffusion region DIF is a p-type semiconductor, the germanium film GF1 is an i-type semiconductor, and the silicon film SIF1 is an n-type semiconductor, the impurity diffusion region DIF, the germanium film GF1, and the silicon film SIF1 A pin type photodiode PD is configured.

The semiconductor device according to the first embodiment has the insulating film IF. The insulating film IF is formed so as to cover the semiconductor layer SOI1 in the first region R1. An opening OP1 that exposes the impurity diffusion region DIF is formed in the insulating film IF (see FIG. 10). The insulating film IF is formed of, for example, silicon oxide.

The semiconductor device according to the first embodiment has an interlayer insulating film ILD. The interlayer insulating film ILD is formed of, for example, silicon oxide. The interlayer insulating film ILD is formed on the semiconductor substrate SUB so as to cover the photodiode PD in the first region R1.

A contact plug CP1 and a contact plug CP2 are formed in the interlayer insulating film ILD. The contact plug CP1 and the contact plug CP2 are formed of, for example, tungsten (W). The contact plug CP1 and the contact plug CP2 are buried in the contact hole formed in the interlayer insulating film ILD.

The contact plug CP1 is electrically connected to the impurity diffusion region DIF, and the contact plug CP2 is electrically connected to the silicon film SIF1. A higher potential than that of the contact plug CP1 is applied to the contact plug CP2. That is, the photodiode PD is reverse biased. Although not shown, the contact plugs CP1 and CP2 are electrically connected to the wiring formed on the interlayer insulating film ILD.

The light supplied to the photodiode PD via the optical waveguide WG (or from above the photodiode PD) is photoelectrically converted inside the photodiode PD to generate electrons and holes. Due to the reverse bias, the generated electrons move toward the contact plug CP2, and the generated holes move toward the contact plug CP1. As a result, a photocurrent flows, so that the photodiode PD can detect the incidence of light by detecting this photocurrent.

As shown in FIG. 3, the semiconductor substrate SUB has a semiconductor layer SOI2 in the second region R2. The semiconductor layer SOI2 is formed of single crystal silicon. The semiconductor layer SOI2 is formed on the insulating layer BOX. The insulating film IF covers the semiconductor layer SOI2 in the second region R2. An opening OP2 (see FIG. 10) that partially exposes the semiconductor layer SOI2 is formed in the insulating film IF.

A germanium film GF2 is formed on the surface of the semiconductor layer SOI2 exposed from the opening OP2. The germanium film GF2 is a film made of single crystal germanium which is not doped with impurities. That is, the germanium film GF2 is made of the same material as the germanium film GF1. The germanium film GF2 is an i-type semiconductor.

The germanium film GF2 has an upper surface GF2a, a side surface GF2b and a side surface GF2c, an inclined surface GF2d and an inclined surface GF2e. The side surface GF2b and the side surface GF2c are the side surfaces of the germanium film GF2 facing each other. The inclined surface GF2d is connected to the upper surface GF2a and the side surface GF2b, and the inclined surface GF2e is connected to the upper surface GF2a and the side surface GF2c. The inclined surface GF2d and the inclined surface GF2e face each other. The distance between the inclined surface GF2d and the inclined surface GF2e increases as the distance from the upper surface GF2a increases.

The germanium film GF2 has a height H and a width W. The height H is the distance between the upper surface GF2a and the surface of the semiconductor layer SOI2. The width W is the distance between the side surface GF2b and the side surface GF2c. The height H is preferably smaller than the width W. A value obtained by dividing the height H by the width W is preferably 1/6 or more.

The germanium film GF2 is a dummy (germanium film not used for the photodiode PD) of the germanium film GF1. When such a dummy is formed, the area of the germanium film in plan view becomes too small compared to the area of the semiconductor substrate SUB in plan view when the dummy is not formed. As a result, the germanium film is slightly changed due to a slight change in process conditions. This is because the film thickness of GF1 and the like change greatly. The total area of the germanium film GF1 and the germanium film GF2 in plan view is preferably adjusted to about 30% of the area of the semiconductor substrate SUB in plan view.

The lower electrode LEL is formed on the germanium film GF2. The lower electrode LEL is, for example, the silicon film SIF2. Specifically, the silicon film SIF2 is formed on the upper surface GF2a, the inclined surface GF2d, and the inclined surface GF2e. The silicon film SIF2 is a film made of single crystal silicon doped with impurities. The silicon film SIF2 is an n-type semiconductor. The silicon film SIF2 contains a donor such as phosphorus as an impurity. That is, the lower electrode LEL is formed of the same material as the silicon film SIF1.

A dielectric film DF is formed on the silicon film SIF2 (lower electrode LEL). The dielectric film DF is formed of, for example, silicon oxide. That is, the dielectric film DF is formed of the same material as the interlayer insulating film ILD. The dielectric film DF may be formed over the entire surface of the semiconductor substrate SUB so as to cover the silicon film SIF2. The dielectric film DF may be formed of silicon nitride (SiN) or silicon oxynitride (SiON).

The upper electrode UEL is formed on the dielectric film DF. The upper electrode UEL is formed of, for example, titanium nitride (TiN). The upper electrode UEL may be formed of titanium (Ti), aluminum (Al), or the like. The upper electrode UEL sandwiches the dielectric film DF with the lower electrode LEL (silicon film SIF2). That is, the lower electrode LEL, the dielectric film DF, and the upper electrode UEL form the capacitor C.

The interlayer insulating film ILD is formed on the semiconductor substrate SUB so as to cover the capacitor C in the second region R2. The portion of the surface of the dielectric film DF closest to the semiconductor layer SOI2 is below the upper surface GF2a, while the portion of the interlayer insulating film ILD closest to the semiconductor layer SOI2 is the upper surface. It is above GF2a. In this respect, the interlayer insulating film ILD and the dielectric film DF are distinguished from each other.

As shown in FIGS. 3 and 4, a contact plug CP3 and a contact plug CP4 are formed in the interlayer insulating film ILD. The contact plug CP3 and the contact plug CP4 are buried in the contact hole formed in the interlayer insulating film ILD. The contact plug CP3 and the contact plug CP4 are electrically connected to the lower electrode LEL and the upper electrode UEL, respectively. Although not shown, the contact plugs CP3 and CP4 are electrically connected to the wiring formed on the interlayer insulating film ILD.

As shown in FIG. 5, the semiconductor substrate SUB further includes a semiconductor layer SOI3 in the third region R3. The semiconductor layer SOI3 is formed of single crystal silicon. The semiconductor layer SOI3 is formed on the insulating layer BOX.

In the third region R3, the interlayer insulating film ILD is formed on the semiconductor substrate SUB so as to cover the semiconductor layer SOI3. As described above, since the semiconductor layer SOI3 is formed on the insulating layer BOX, its upper surface, both side surfaces and lower surface are covered with the interlayer insulating film ILD and the insulating layer BOX formed of silicon oxide. .. The refractive index of silicon oxide is smaller than that of silicon. Due to this refractive index difference, the light propagating in the semiconductor layer SOI3 is confined in the semiconductor layer SOI3. Thus, the optical waveguide WG is composed of the semiconductor layer SOI3, the insulating layer BOX, and the interlayer insulating film ILD.

The method of manufacturing the semiconductor device according to the first embodiment will be described below.
As shown in FIG. 6, the semiconductor device manufacturing method according to the first embodiment includes a semiconductor substrate preparing step S1, a semiconductor layer patterning step S2, an impurity diffusion region forming step S3, and an insulating film forming step S4. An epitaxial growth step S5, a dielectric film forming step S6, an upper electrode forming step S7, an interlayer insulating film forming step S8, and a contact plug forming step S9 are included.

As shown in FIG. 7, in the semiconductor substrate preparing step S1, the semiconductor substrate SUB is prepared. The semiconductor substrate SUB includes a support substrate SSUB, an insulating layer BOX formed on the support substrate SSUB, and a semiconductor layer SOI formed on the insulating layer BOX. The semiconductor layer SOI is formed of single crystal silicon. That is, the semiconductor substrate SUB prepared in the semiconductor substrate preparing step S1 is an SOI (Silicon On Insulator) substrate.

As shown in FIG. 8, in the semiconductor layer patterning step S2, the semiconductor layer SOI is patterned. By patterning the semiconductor layer SOI, the semiconductor layer SOI1, the semiconductor layer SOI2, and the semiconductor layer SOI3 are formed. The patterning of the semiconductor layer SOI is performed by photolithography and etching.

As shown in FIG. 9, in the impurity diffusion region forming step S3, the impurity diffusion region DIF is formed. The impurity diffusion region DIF is formed by ion implantation.

As shown in FIG. 10, in the insulating film forming step S4, the insulating film IF is formed. In forming the insulating film IF, first, the material forming the insulating film IF is formed by, for example, CVD (Chemical Vapor Deposition). Secondly, in the insulating film IF, patterning of the material forming the formed insulating film IF is performed by photolithography and etching. As a result, the insulating film IF having the openings OP1 and OP2 is formed.

The epitaxial growth step S5 has a first step S51 and a second step S52. As shown in FIG. 11, in the first step S51, the germanium film GF1 and the germanium film GF2 are formed. The germanium film GF1 and the germanium film GF2 are epitaxially grown on the semiconductor layer SOI1 exposed from the opening OP1 and on the semiconductor layer SOI2 exposed from the opening OP2, for example, by performing CVD.

When the germanium film GF1 is epitaxially grown on the semiconductor layer SOI1, the growth rate differs between the portion near the edge of the opening OP1 and the portion away from the edge of the opening OP2. As a result, the inclined surface GF1d and the inclined surface GF1e are formed on the germanium film GF1. For the same reason, the inclined surface GF2d and the inclined surface GF2e are formed on the germanium film GF2.

As shown in FIG. 12, in the second step S52, the silicon film SIF1 and the silicon film SIF2 (lower electrode LEL) are formed. The silicon film SIF1 and the silicon film SIF2 are epitaxially grown on the germanium film GF1 and the germanium film GF2, respectively, by performing CVD. The CVD in the first step S51 and the CVD in the second step S52 are preferably performed by switching the reaction gas in the same chamber.

As shown in FIG. 13, in the dielectric film forming step S6, the dielectric film DF is formed. The dielectric film DF is formed by, for example, CVD.

As shown in FIG. 14, in the upper electrode forming step S7, the upper electrode UEL is formed. In forming the upper electrode UEL, first, the material forming the upper electrode UEL is deposited by sputtering or the like. In forming the upper electrode UEL, secondly, the material forming the deposited upper electrode UEL is patterned using photolithography and etching.

As shown in FIG. 15, in the interlayer insulating film forming step S8, the interlayer insulating film ILD is formed. In forming the interlayer insulating film ILD, firstly, the material forming the interlayer insulating film ILD is deposited by CVD or the like. In forming the interlayer insulating film ILD, secondly, the material forming the deposited interlayer insulating film ILD is planarized by CMP (Chemical Mechanical Polishing) or the like.

In the contact plug forming step S9, the contact plugs CP1 to CP4 are formed. In forming the contact plugs CP1 to CP4, first, a contact hole is formed in the interlayer insulating film ILD. The contact hole is formed by photolithography and etching.

In forming the contact plugs CP1 to CP4, secondly, the material forming the contact plugs CP1 to CP4 is deposited by CVD or the like. As a result, the material forming the contact plugs CP1 to CP4 is embedded in the contact hole. In forming the contact plugs CP1 to CP4, thirdly, the material forming the contact plugs CP1 to CP4 protruding from the contact hole is removed by CMP or the like.

After the contact plug forming step S9 is performed, the wiring forming step is performed. As described above, the semiconductor device according to the first embodiment having the structure shown in FIGS. 2 to 5 is manufactured.

The effects of the semiconductor device according to the first embodiment will be described below in comparison with a comparative example.
As shown in FIG. 16, the semiconductor substrate SUB of the semiconductor device according to the comparative example is formed on the supporting substrate SSUB, the insulating layer BOX formed on the supporting substrate SSUB, and the insulating layer BOX in the second region R2. And the semiconductor layer SOI2.

The semiconductor device according to the comparative example has a germanium film GF2 formed on the semiconductor layer SOI2 and a silicon film SIF2 formed on the germanium film GF2. The semiconductor device according to the comparative example does not have the dielectric film DF and the upper electrode UEL. In the semiconductor device according to the comparative example, the interlayer insulating film ILD is formed so as to cover the germanium film GF2 and the silicon film SIF2, and the wiring WL sandwiches the interlayer insulating film ILD with the silicon film SIF2. It is formed on the film ILD. In the semiconductor device according to the comparative example, the capacitor C1 is configured by the silicon film SIF2, the wiring WL, and the interlayer insulating film ILD between the silicon film SIF2 and the wiring WL.

Although planarization is performed by CMP or the like, a step remains on the surface of the interlayer insulating film ILD above the germanium film GF2 and the silicon film SIF2. As a result, the thickness of the interlayer insulating film ILD between the silicon film SIF2 and the wiring WL varies, and as a result, the capacitance value of the capacitor C1 varies. Further, since the thickness and film quality of the interlayer insulating film ILD need to be optimized in consideration of the incidence efficiency to the photodiode PD, it is difficult to optimize in consideration of the capacitance value of the capacitor C1. ..

On the other hand, in the semiconductor device according to the first embodiment, the dielectric film of the capacitor C does not use the interlayer insulating film ILD but uses the dielectric film DF. Therefore, the capacitance value of the capacitor C is not affected by the step on the surface of the interlayer insulating film ILD. Therefore, according to the semiconductor device of the first embodiment, the capacitance value of the capacitor C can be stabilized.

In the semiconductor device according to the first embodiment, since the thickness and film quality of the dielectric film DF can be selected independently of the interlayer insulating film ILD, the thickness and film quality of the dielectric film DF can be set to the capacitance value of the capacitor C. Can be taken into consideration and optimized.

In the semiconductor device according to the first embodiment, since the germanium film GF2 has the inclined surface GF2d and the inclined surface GF2e, the capacitor C per unit area in plan view is larger than that in the case where these are not provided. It is possible to improve the capacitance value of.

As shown in FIG. 17, in the semiconductor device according to the first embodiment, when the value obtained by dividing the height H by the width W is 1/6 or more, the ratio of the inclined surface GF2d and the inclined surface GF2e to the upper surface GF2a. Is relatively large. As a result, it is possible to improve the capacitance value of the capacitor C per unit area in plan view.

In the semiconductor device according to the first embodiment, when the interlayer insulating film ILD and the dielectric film DF are formed of the same material (more specifically, both the interlayer insulating film ILD and the dielectric film DF are formed of silicon oxide). However, since there is no difference between the refractive index of the interlayer insulating film ILD and the refractive index of the dielectric film DF, the optical waveguide can be obtained without patterning to remove the dielectric film DF in the third region R3. It does not affect the light confinement effect in the WG. Therefore, in this case, since the patterning process of the dielectric film DF can be omitted, the manufacturing process of the semiconductor device according to the first embodiment can be simplified.

When the upper electrode UEL is formed of aluminum, the surface of the upper electrode UEL is covered with a barrier metal in order to prevent aluminum, which is a material forming the upper electrode UEL, from diffusing into the interlayer insulating film ILD. There is a need to. However, when the upper electrode UEL is made of titanium nitride, it is not necessary to form the barrier metal, so that the manufacturing process of the semiconductor device according to the first embodiment can be simplified.

(Second embodiment)
The configuration of the semiconductor device according to the second embodiment will be described below. Here, the difference from the configuration of the semiconductor device according to the first embodiment will be mainly described, and repeated description will not be repeated.

The semiconductor device according to the second embodiment has a semiconductor substrate SUB. The semiconductor substrate SUB has a support substrate SSUB and an insulating layer BOX formed on the support substrate SSUB. The semiconductor substrate SUB has a semiconductor layer SOI1, a semiconductor layer SOI2, and a semiconductor layer SOI3 in the first region R1, the second region R2, and the third region R3, respectively.

In the semiconductor device according to the second embodiment, in the first region R1, the impurity diffusion region DIF formed on the surface of the semiconductor layer SOI1, the germanium film GF1 formed on the impurity diffusion region DIF, and the germanium film GF1. It has a photodiode PD constituted by a silicon film SIF1 formed thereover.

In the semiconductor device according to the second embodiment, in the second region R2, the germanium film GF2 formed on the semiconductor layer SOI2, the lower electrode LEL (silicon film SIF2) and the lower electrode formed on the germanium film GF2. The capacitor C includes a dielectric film DF formed on the LEL and an upper electrode UEL formed on the dielectric film DF.

The semiconductor device according to the second embodiment has the optical waveguide WG including the semiconductor layer SOI3 and the interlayer insulating film ILD formed so as to cover the semiconductor layer SOI3 in the third region R3. With respect to these points, the configuration of the semiconductor device according to the second embodiment is common to the configuration of the semiconductor device according to the first embodiment.

However, the configuration of the semiconductor device according to the second embodiment differs from the configuration of the semiconductor device according to the first embodiment with respect to the shape of the germanium film GF2 in plan view.

As shown in FIG. 18, in the germanium film GF2, the germanium film GF2 extends along the first direction DR1 when seen in a plan view, and is arranged at intervals in the second direction DR2 that intersects the first direction DR1 when seen in a plan view. A plurality of slits SL are formed. As shown in FIG. 19, the slit SL penetrates the germanium film GF2 in the thickness direction.

As shown in FIG. 20, in the germanium film GF2, instead of the slits SL, a plurality of openings OP3 arranged in a matrix in a plan view may be formed. As shown in FIG. 21, the opening OP3 penetrates the germanium film GF2 in the thickness direction.

The effects of the semiconductor device according to the second embodiment will be described below. Here, differences from the effects of the semiconductor device according to the first embodiment will be mainly described, and repeated description will not be repeated.

As shown in FIGS. 19 and 21, by forming the slit SL or the opening OP3 as described above, in the germanium film GF2, the ratio of the inclined surface to the upper surface becomes relatively large. As a result, according to the semiconductor device of the second embodiment, the capacitance value of the capacitor C per unit area in plan view can be further improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BOX insulating layer, C, C1 capacitor, CP1, CP2, CP3, CP4 contact plug, DF dielectric film, DIF impurity diffusion region, DR1 first direction, DR2 second direction, GF1 germanium film, GF1a upper surface, GF1b, GF1c side surface, GF1d, GF1e inclined surface, GF2 germanium film, GF2a upper surface, GF2b, GF2c side surface, GF2d, GF2e inclined surface, H height, IF insulating film, ILD interlayer insulating film, LEL lower electrode, OP1, OP2, OP3 opening, PD photo Diode, R1 first region, R2 second region, R3 third region, S1 semiconductor substrate preparing step, S2 semiconductor layer patterning step, S3 impurity diffusion region forming step, S4 insulating film forming step, S5 epitaxial growth step, S6 dielectric film Forming step, S7 upper electrode forming step, S8 interlayer insulating film forming step, S9 contact plug forming step, S51 first step, S52 second step, SIF1, SIF2 silicon film, SL slit, SOI, SOI1, SOI2, SOI3 semiconductor layer , SSUB support substrate, SUB semiconductor substrate, UEL upper electrode, W width, WG optical waveguide, WL wiring.

Claims (10)

A semiconductor substrate,
A first germanium film formed on the semiconductor substrate;
A capacitor formed on the first germanium film;
An interlayer insulating film formed on the semiconductor substrate so as to cover the capacitor,
The semiconductor device, wherein the capacitor has a lower electrode formed on the first germanium film, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film. The first germanium film has an upper surface and a first inclined surface and a second inclined surface that are continuous with the upper surface and that face each other,
The semiconductor device according to claim 1, wherein a distance between the first inclined surface and the second inclined surface increases as the distance from the upper surface increases. The semiconductor device according to claim 2, wherein a value obtained by dividing the height of the first germanium film by the width of the first germanium film is 1/6 or more. The semiconductor device according to claim 1, wherein the first germanium film is formed with a slit penetrating the first germanium film in a thickness direction. The first germanium film has a plurality of openings arranged in a matrix in a plan view,
The semiconductor device according to claim 1, wherein the opening penetrates the first germanium film in a thickness direction. The semiconductor device according to claim 1, wherein the interlayer insulating film and the dielectric film are formed of the same material. The semiconductor device according to claim 6, wherein the dielectric film is formed of silicon oxide. The semiconductor device according to claim 1, wherein the upper electrode is made of titanium nitride. Further equipped with a photodiode,
The photodiode is formed on the impurity diffusion region formed on the surface of the semiconductor substrate, a second germanium film formed on the impurity diffusion region, and on the second germanium film, and is doped with impurities. Has a silicon film that is
The conductivity type of the impurity diffusion region is p-type,
The semiconductor device according to claim 1, wherein the conductivity type of the silicon film is n-type. The first germanium film and the second germanium film are formed of the same material,
The semiconductor device according to claim 9, wherein the lower electrode and the silicon film are formed of the same material.