[go: up one dir, main page]

JP2018195641A - Polishing method of silicon wafer - Google Patents

Polishing method of silicon wafer Download PDF

Info

Publication number
JP2018195641A
JP2018195641A JP2017096563A JP2017096563A JP2018195641A JP 2018195641 A JP2018195641 A JP 2018195641A JP 2017096563 A JP2017096563 A JP 2017096563A JP 2017096563 A JP2017096563 A JP 2017096563A JP 2018195641 A JP2018195641 A JP 2018195641A
Authority
JP
Japan
Prior art keywords
polishing
silicon wafer
pad
slurry
colloidal silica
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017096563A
Other languages
Japanese (ja)
Other versions
JP6747376B2 (en
Inventor
正彬 大関
Masaaki Ozeki
正彬 大関
三千登 佐藤
Michito Sato
三千登 佐藤
薫 石井
Kaoru Ishii
薫 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP2017096563A priority Critical patent/JP6747376B2/en
Priority to PCT/JP2018/016132 priority patent/WO2018211903A1/en
Priority to TW107113771A priority patent/TWI727165B/en
Publication of JP2018195641A publication Critical patent/JP2018195641A/en
Application granted granted Critical
Publication of JP6747376B2 publication Critical patent/JP6747376B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/24—Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

【課題】 硬質のパッドを用いても低欠陥性を達成することができるシリコンウエーハの研磨方法を提供する。【解決手段】 シリコンウェーハと研磨パッドとの間に研磨スラリーを介在させて、前記シリコンウエーハを研磨するシリコンウエーハの研磨方法であって、前記研磨スラリーとして、コロイダルシリカとアルカリを含み、（前記研磨スラリー中の水酸化物イオン濃度［ＯＨ−］（ｍｏｌ／ｌ））／（前記研磨スラリーの質量中の前記コロイダルシリカの質量分率）≧０．１（ｍｏｌ／ｌ）を満たすものを用いて研磨することを特徴とするシリコンウェーハの研磨方法。【選択図】図１PROBLEM TO BE SOLVED: To provide a silicon wafer polishing method capable of achieving low defectivity even when a hard pad is used. A silicon wafer polishing method for polishing a silicon wafer by interposing a polishing slurry between a silicon wafer and a polishing pad, the polishing slurry containing colloidal silica and an alkali (the polishing Hydroxide ion concentration in the slurry [OH-] (mol / l)) / (mass fraction of the colloidal silica in the mass of the polishing slurry) ≧ 0.1 (mol / l) A method for polishing a silicon wafer, comprising polishing. [Selection] Figure 1

Description

本発明は、シリコンウエーハの研磨方法に関する。   The present invention relates to a method for polishing a silicon wafer.

半導体デバイスの細線化が進むにつれ、基板となるシリコンウェーハにはより一層の平坦性、低欠陥が求められる。一般的に、シリコンウェーハはチョクラルスキー（ＣＺ）法により引き上げられた単結晶インゴットをスライスした後、多段研磨を行うことで作製される（特許文献１参照）。   As semiconductor devices become thinner, silicon wafers that serve as substrates are required to have even more flatness and lower defects. Generally, a silicon wafer is manufactured by slicing a single crystal ingot pulled up by the Czochralski (CZ) method and then performing multi-stage polishing (see Patent Document 1).

特に、樹脂製のパッドを用いた研磨工程では、エッジ・ロールオフ等により外周平坦性が損なわれやすく、その結果、ウェーハ外周部のデバイス歩留まりが悪化してしまう。同時に、スクラッチ等の表面欠陥の導入もデバイスの歩留まりが悪化してしまう原因となるため、研磨工程には、外周平坦性、低欠陥性が求められている。   In particular, in a polishing process using a resin pad, the outer peripheral flatness is likely to be impaired by edge / roll-off, and as a result, the device yield at the outer peripheral portion of the wafer is deteriorated. At the same time, since the introduction of surface defects such as scratches also causes the device yield to deteriorate, the polishing process requires outer peripheral flatness and low defectivity.

特開２００８−２０５１４７号公報JP 2008-205147 A

上記のように研磨工程には平坦性と低欠陥性が求められるが、一般的にその両立は極めて困難であることが分かっている。研磨工程で良好な外周平坦性を維持するためには硬質の研磨パッドを用いることが重要である。硬質の研磨パッドを用いることで外周のパッド変位を抑制し、ウェーハ外周部の圧力集中を抑制できるためである。   As described above, the polishing step is required to have flatness and low defect, but it has been found that it is generally very difficult to achieve both. In order to maintain good peripheral flatness in the polishing process, it is important to use a hard polishing pad. This is because by using a hard polishing pad, the displacement of the pad on the outer periphery can be suppressed, and the pressure concentration on the outer periphery of the wafer can be suppressed.

しかし、硬質の研磨パッドを用いた場合には低欠陥性の達成が困難である。パッドが硬質であるためパッド自体がウェーハにスクラッチを導入する可能性や、異物がウェーハ／パッド間に侵入した場合、同じ異物でも軟質パッドよりも硬質パッドの方がウェーハへのダメージは大きくなるため、スクラッチの導入可能性が高まる。   However, when a hard polishing pad is used, it is difficult to achieve low defectivity. Because the pad is hard, the pad itself may introduce scratches into the wafer, and if a foreign object enters between the wafer and the pad, the damage to the wafer will be greater with the hard pad than with the soft pad even with the same foreign object. This increases the possibility of introducing scratches.

以上のことから、外周平坦性と低欠陥性は研磨パッドの硬度においてトレードオフの関係になっていることがわかり、硬質のパッドを用いても低欠陥性を達成することが課題となっている。   From the above, it can be seen that the outer peripheral flatness and the low defect have a trade-off relationship in the hardness of the polishing pad, and it is an issue to achieve the low defect even when using a hard pad. .

本発明は、上記問題点に鑑みてなされたものであって、平坦性の向上と低欠陥性を達成することができるシリコンウエーハの研磨方法を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for polishing a silicon wafer that can achieve improved flatness and low defectivity.

上記課題を解決するために、本発明は、シリコンウェーハと研磨パッドとの間に研磨スラリーを介在させて、前記シリコンウエーハを研磨するシリコンウエーハの研磨方法であって、前記研磨スラリーとして、コロイダルシリカとアルカリを含み、（前記研磨スラリー中の水酸化物イオン濃度［ＯＨ−］（ｍｏｌ／ｌ））／（前記研磨スラリーの質量中の前記コロイダルシリカの質量分率）≧０．１（ｍｏｌ／ｌ）を満たすものを用いて研磨することを特徴とするシリコンウェーハの研磨方法を提供する。 In order to solve the above-described problems, the present invention provides a method for polishing a silicon wafer by interposing a polishing slurry between a silicon wafer and a polishing pad, wherein the polishing slurry includes colloidal silica. And alkali, (hydroxide ion concentration [OH − ] (mol / l) in the polishing slurry) / (mass fraction of the colloidal silica in the mass of the polishing slurry) ≧ 0.1 (mol / A method for polishing a silicon wafer is provided, wherein polishing is performed using a material satisfying l).

このように、上記条件を満たす研磨スラリーを用いてシリコンウェーハを研磨することで、例え硬質のパッドを用いても低欠陥性を達成することが可能となる。   Thus, by polishing a silicon wafer using a polishing slurry that satisfies the above conditions, low defects can be achieved even with a hard pad.

またこの場合、前記研磨パッドとして、ショアＡ硬度６０以上の研磨パッドを用いることが好ましい。   In this case, it is preferable to use a polishing pad having a Shore A hardness of 60 or more as the polishing pad.

更に、前記研磨パッドとして、ショアＡ硬度７０以上の研磨パッドを用いることが好ましい。   Furthermore, it is preferable to use a polishing pad having a Shore A hardness of 70 or more as the polishing pad.

このように硬質な研磨パッドを用いて研磨することにより、平坦性と低欠陥性の両立が達成されたシリコンウェーハを得ることができる。   By polishing using such a hard polishing pad, a silicon wafer in which both flatness and low defectivity are achieved can be obtained.

本発明のシリコンウエーハの研磨方法であれば、研磨における機械的作用に対する化学的作用の強さの指標として、研磨スラリー中の水酸化物イオン濃度［ＯＨ−］を研磨スラリーの質量中のコロイダルシリカの質量分率で割った値に着目し、その値が０．１以上となるような研磨スラリーを用いることで、低欠陥性を達成することができる。そのため、例え硬質な研磨パッドを用いても、低欠陥とできることから、平坦性と低欠陥性の両立が達成されたシリコンウェーハを得ることができる。 In the silicon wafer polishing method of the present invention, the hydroxide ion concentration [OH − ] in the polishing slurry is used as an indicator of the strength of the chemical action relative to the mechanical action in polishing. By paying attention to the value divided by the mass fraction of and using a polishing slurry whose value is 0.1 or more, low defectivity can be achieved. For this reason, even if a hard polishing pad is used, it is possible to obtain a low defect. Therefore, it is possible to obtain a silicon wafer in which both flatness and low defect are achieved.

実施例１〜４及び比較例１における、［ＯＨ−］／コロイダルシリカの質量分率の値と、ＬＬＳ欠陥個数との関係を示すグラフである。It is a graph which shows the relationship between the value of the mass fraction of [OH < - >] / colloidal silica, and the number of LLS defects in Examples 1-4 and Comparative Example 1. 実施例５〜８、比較例２、３における、［ＯＨ−］／コロイダルシリカの質量分率の値と、ＬＬＳ欠陥個数との関係を示すグラフである。It is a graph which shows the relationship between the value of the mass fraction of [OH < - >] / colloidal silica, and the number of LLS defects in Examples 5-8 and Comparative Examples 2 and 3. 本発明のシリコンウエーハの研磨方法において用いることができる片面研磨装置の一例を示す概略図である。It is the schematic which shows an example of the single-side polish apparatus which can be used in the grinding | polishing method of the silicon wafer of this invention.

上述したように、従来、硬質のパッドを用いても低欠陥性を達成することができるシリコンウエーハの研磨方法が求められていた。   As described above, conventionally, there has been a demand for a method for polishing a silicon wafer that can achieve low defectivity even when a hard pad is used.

本発明者らは、課題解決にあたり研磨における化学的作用に着目した。従来、パッド硬度、パッド表面粗さ、砥粒径、研磨圧力、又は研磨回転数など、研磨における機械的作用に着目した技術は多いが、化学的作用に着目した例はほとんどない。   The present inventors paid attention to the chemical action in polishing in solving the problem. Conventionally, there are many techniques that focus on mechanical action in polishing, such as pad hardness, pad surface roughness, abrasive grain size, polishing pressure, or polishing rotation speed, but there are few examples that focus on chemical action.

研磨における化学的作用とは、シリコンとアルカリによる反応を期待したもので、具体的には、Ｓｉ＋ＯＨ−→ＳｉＯＨの反応に起因し、これは、アルカリに接液しているＳｉの結晶がＯＨ基により変質することを示している。 The chemical action in polishing is the expectation of a reaction between silicon and alkali. Specifically, it is caused by the reaction of Si + OH − → SiOH. This is because the Si crystal in contact with alkali is an OH group. It shows that it changes in quality.

本発明者らは、研磨における化学的作用を増大させ、ウェーハ表面を変質させることにより、研磨パッドとＳｉ結晶部との間に緩衝層を設け、硬質パッド、又は硬質パッドに保持された異物によるダメージを軽減できると発想した。   The present inventors have provided a buffer layer between the polishing pad and the Si crystal part by increasing the chemical action in polishing and altering the wafer surface, and the hard pad or the foreign matter held by the hard pad. I thought I could reduce the damage.

そして、本発明者らは、化学的作用により形成された変質層（緩衝層）は、機械的作用により速やかに除去されるため、研磨における化学的作用の強さは、ｐＨなどの絶対的な強さを指標にするのではなく、機械的作用に対しての化学的作用の強さを指標にするべきであると考えた。そこで、本発明では、化学的作用の強さを水酸化物イオンの濃度、機械的作用の強さを研磨スラリーの質量中のコロイダルシリカの質量分率（以下、砥粒濃度ともいう）とし、水酸化物イオンの濃度を砥粒濃度で割った値を機械的作用に対する化学的作用の指標として用い、硬質パッドを用いた際にこの指標がどのような範囲に入っていればよいか求めた。   The inventors of the present invention have found that the altered layer (buffer layer) formed by the chemical action is quickly removed by the mechanical action, so that the strength of the chemical action in polishing is absolute such as pH. Instead of using strength as an indicator, we thought that the strength of chemical action relative to mechanical action should be used as an indicator. Therefore, in the present invention, the strength of chemical action is the concentration of hydroxide ions, and the strength of mechanical action is the mass fraction of colloidal silica in the mass of the polishing slurry (hereinafter also referred to as abrasive concentration), The value obtained by dividing the hydroxide ion concentration by the abrasive concentration was used as an indicator of the chemical action for the mechanical action, and the range that this indicator should be in when using a hard pad was determined. .

そして、本発明者らは、研磨における化学的作用の強さの指標として、研磨スラリー中の水酸化物イオン濃度［ＯＨ−］を砥粒濃度で割った値に着目し、その値が０．１以上になるように研磨スラリーを調製し、研磨に用いることで、例え硬質な研磨パッドを用いても低欠陥性を達成することができることを見出し、本発明に到達した。 Then, the inventors pay attention to a value obtained by dividing the hydroxide ion concentration [OH − ] in the polishing slurry by the abrasive concentration as an index of the strength of chemical action in polishing, and the value is 0. It was found that by preparing a polishing slurry so as to be 1 or more and using it for polishing, even if a hard polishing pad is used, low defect can be achieved, and the present invention has been achieved.

即ち、本発明は、シリコンウェーハと研磨パッドとの間に研磨スラリーを介在させて、前記シリコンウエーハを研磨するシリコンウエーハの研磨方法であって、前記研磨スラリーとして、コロイダルシリカとアルカリを含み、（前記研磨スラリー中の水酸化物イオン濃度［ＯＨ−］（ｍｏｌ／ｌ））／（前記研磨スラリーの質量中の前記コロイダルシリカの質量分率）≧０．１（ｍｏｌ／ｌ）を満たすものを用いて研磨することを特徴とするシリコンウェーハの研磨方法を提供する。 That is, the present invention is a silicon wafer polishing method for polishing the silicon wafer by interposing a polishing slurry between a silicon wafer and a polishing pad, the polishing slurry containing colloidal silica and alkali, What satisfies the hydroxide ion concentration [OH − ] (mol / l)) / (mass fraction of the colloidal silica in the mass of the polishing slurry) ≧ 0.1 (mol / l) in the polishing slurry A method for polishing a silicon wafer is provided.

以下、本発明のシリコンウエーハの研磨方法について詳細に説明する。   The silicon wafer polishing method of the present invention will be described in detail below.

本発明のシリコンウェーハの研磨方法で用いる研磨装置としては、両面研磨装置、片面研磨装置のいずれでも良い。例えば、図３に示すような、研磨パッド１が貼り付けられた定盤２と、シリコンウェーハＷを保持するための研磨ヘッド３を具備した、片面研磨装置１０を使用することができる。この片面研磨装置１０は、研磨パッド１上にノズル４から研磨スラリーを供給しつつ、その研磨パッド１に研磨ヘッド３が保持するシリコンウェーハＷの表面を摺接させて研磨するものである。   The polishing apparatus used in the silicon wafer polishing method of the present invention may be either a double-side polishing apparatus or a single-side polishing apparatus. For example, as shown in FIG. 3, a single-side polishing apparatus 10 including a surface plate 2 on which a polishing pad 1 is attached and a polishing head 3 for holding a silicon wafer W can be used. The single-side polishing apparatus 10 polishes the polishing pad 1 by supplying the polishing slurry from the nozzle 4 while sliding the surface of the silicon wafer W held by the polishing head 3 on the polishing pad 1.

本発明では、シリコンウェーハＷと研磨パッド１との間に研磨スラリーを介在させて、シリコンウエーハを研磨するが、このノズル４から供給する研磨スラリーとして、コロイダルシリカとアルカリを含み、（研磨スラリー中の水酸化物イオン濃度［ＯＨ−］（ｍｏｌ／ｌ））／（研磨スラリーの質量中の前記コロイダルシリカの質量分率）≧０．１（ｍｏｌ／ｌ）を満たすものを用いる。 In the present invention, the silicon wafer is polished by interposing a polishing slurry between the silicon wafer W and the polishing pad 1. The polishing slurry supplied from the nozzle 4 includes colloidal silica and alkali (in the polishing slurry). Of the hydroxide ion concentration [OH − ] (mol / l)) / (mass fraction of the colloidal silica in the mass of the polishing slurry) ≧ 0.1 (mol / l) is used.

このように、化学的作用の強さを水酸化物イオンの濃度、機械的作用の強さを研磨スラリーの質量中のコロイダルシリカの質量分率とし、水酸化物イオンの濃度を砥粒濃度で割った値を機械的作用に対する化学的作用の指標として用い、この値が０．１以上の研磨スラリーを用いることで、低欠陥性を達成することができる。   In this way, the chemical action strength is the hydroxide ion concentration, the mechanical action strength is the mass fraction of colloidal silica in the mass of the polishing slurry, and the hydroxide ion concentration is the abrasive concentration. By using the divided value as an index of the chemical action with respect to the mechanical action and using a polishing slurry having this value of 0.1 or more, low defectivity can be achieved.

従来の研磨スラリーは、（研磨スラリー中の水酸化物イオン濃度［ＯＨ−］（ｍｏｌ／ｌ））／（研磨スラリーの質量中の前記コロイダルシリカの質量分率）の値が０．１未満のものであり、上記値が０．１以上である研磨スラリー、即ち、砥粒濃度に対する水酸化物イオンの濃度が高い研磨スラリーは用いられていなかった。 In the conventional polishing slurry, the value of (hydroxide ion concentration in the polishing slurry [OH − ] (mol / l)) / (mass fraction of the colloidal silica in the mass of the polishing slurry) is less than 0.1. A polishing slurry having the above value of 0.1 or more, that is, a polishing slurry having a high hydroxide ion concentration relative to the abrasive concentration was not used.

（研磨スラリー中の水酸化物イオン濃度［ＯＨ−］（ｍｏｌ／ｌ））／（研磨スラリーの質量中の前記コロイダルシリカの質量分率）の値が０．１未満の研磨スラリーであると、機械的作用に対する化学的作用が弱くなるため、硬質の研磨パッドを用いた場合にスクラッチ等の表面欠陥が導入されてしまい、低欠陥性を達成することができない。 When the value of (hydroxide ion concentration in the polishing slurry [OH − ] (mol / l)) / (mass fraction of the colloidal silica in the mass of the polishing slurry) is less than 0.1, Since the chemical action with respect to the mechanical action becomes weak, surface defects such as scratches are introduced when a hard polishing pad is used, and low defectivity cannot be achieved.

上記条件を満たす研磨スラリーであれば、アルカリの種類やｐＨ、コロイダルシリカの濃度や粒径は特に限定されない。例えば、ｐＨ９〜１３、コロイダルシリカ粒径１５〜７０ｎｍ、コロイダルシリカ濃度０．０１〜１ｗｔ％のもので、上記値を満たすものを用いることができる。アルカリとしては、ＫＯＨ、水酸化テトラメチルアンモニウム（ＴＭＡＨ）等を用いることができる。   As long as the polishing slurry satisfies the above conditions, the type of alkali, pH, colloidal silica concentration, and particle size are not particularly limited. For example, those having a pH of 9 to 13, a colloidal silica particle size of 15 to 70 nm, and a colloidal silica concentration of 0.01 to 1 wt% that satisfy the above values can be used. As the alkali, KOH, tetramethylammonium hydroxide (TMAH), or the like can be used.

（研磨スラリー中の水酸化物イオン濃度［ＯＨ−］（ｍｏｌ／ｌ））／（研磨スラリーの質量中のコロイダルシリカの質量分率）の上限は特に限定されないが、例えば、１０ｍｏｌ／ｌ以下とすることができる。 The upper limit of (hydroxide ion concentration in the polishing slurry [OH − ] (mol / l)) / (mass fraction of colloidal silica in the mass of the polishing slurry) is not particularly limited, but is, for example, 10 mol / l or less. can do.

研磨パッド１としては、特に限定されないが、ショアＡ硬度６０以上、特には７０以上の研磨パッド（例えば、不織布）を用いることが好ましい。このように硬質の研磨パッドを用いて研磨することにより、平坦性と低欠陥性の両立が達成されたシリコンウェーハを得ることができる。但し、本発明により低欠陥性は達成されるため、必ずしもこのような硬質の研磨パッドを用いなければならないわけではない。目的に応じ、軟質のパッドを用いる場合にも適用可能である。   Although it does not specifically limit as the polishing pad 1, It is preferable to use a polishing pad (for example, nonwoven fabric) having a Shore A hardness of 60 or more, particularly 70 or more. By polishing using such a hard polishing pad, a silicon wafer in which both flatness and low defectivity are achieved can be obtained. However, since a low defect is achieved by the present invention, it is not always necessary to use such a hard polishing pad. Depending on the purpose, the present invention can also be applied when using a soft pad.

また、研磨の際の研磨圧力、定盤回転数、ヘッド回転数、研磨時間は、一般の条件を採用することができ、目的に応じて選択すれば良く、特に限定されない。   Further, the polishing pressure, the platen rotation speed, the head rotation speed, and the polishing time at the time of polishing can adopt general conditions and may be selected according to the purpose, and are not particularly limited.

以下、実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれらの実施例に限定されるものではない。   EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these Examples.

（実施例１〜４、比較例１）
ショアＡ硬度６０の硬質パッドを用いた片面研磨装置を使用し、機械的作用に対する化学的作用の検証評価を行った。まず、粒径３５ｎｍの高純度コロイダルシリカの研磨スラリー中の質量分率（砥粒濃度）を０．０１（即ち１％）で一定として、研磨スラリーのアルカリ濃度（水酸化物イオン濃度）を変え、シリコンウェーハの研磨を行った。ｐＨの調整は水酸化カリウムおよび水酸化テトラメチルアンモニウム（ＴＭＡＨ）により行った。研磨圧力は２０ｋＰａとし、定盤回転数、ヘッド回転数は３０ｒｐｍとし、研磨は３分間行った。 (Examples 1-4, Comparative Example 1)
A single-side polishing apparatus using a hard pad with a Shore A hardness of 60 was used to verify and evaluate the chemical action against the mechanical action. First, the mass fraction (abrasive grain concentration) in the polishing slurry of high purity colloidal silica having a particle size of 35 nm is made constant at 0.01 (ie 1%), and the alkali concentration (hydroxide ion concentration) of the polishing slurry is changed. The silicon wafer was polished. The pH was adjusted with potassium hydroxide and tetramethylammonium hydroxide (TMAH). The polishing pressure was 20 kPa, the platen rotation speed and the head rotation speed were 30 rpm, and polishing was performed for 3 minutes.

硬質研磨パッドによる研磨工程を経た後、軟質研磨パッドにより最終仕上げ研磨工程を行った後、研磨評価を行った。研磨評価はＫＬＡテンコール社製ＳＰ２によりＬＬＳ（Ｌｏｃａｌｉｚｅｄ Ｌｉｇｈｔ Ｓｃａｔｔｅｒｉｎｇ）欠陥（３７ｎｍ以上）の個数を測定することにより行った。   After passing through a polishing process with a hard polishing pad, a final finish polishing process was performed with a soft polishing pad, and then polishing evaluation was performed. Polishing evaluation was performed by measuring the number of LLS (Localized Light Scattering) defects (37 nm or more) using SP2 manufactured by KLA Tencor.

表１に各条件を示し、図１に［ＯＨ−］／コロイダルシリカの質量分率の値と、ＬＬＳ欠陥個数との関係を示すグラフを示す。［ＯＨ−］／コロイダルシリカの質量分率の値が０．１ｍｏｌ／ｌ以上であれば、ＬＬＳ欠陥数が減少していることが判った。 Table 1 shows the conditions, and FIG. 1 is a graph showing the relationship between the value of the mass fraction of [OH − ] / colloidal silica and the number of LLS defects. It was found that when the value of the mass fraction of [OH-] / colloidal silica was 0.1 mol / l or more, the number of LLS defects was reduced.

Figure 2018195641
Figure 2018195641

（実施例５〜８、比較例２、３）
次に、研磨スラリーのアルカリ濃度を一定（ＰＨ１０．５）とし、コロイダルシリカの質量分率（砥粒濃度）を変えて研磨評価を行った。その他の条件は実施例１〜４、比較例１と同様とした。表２に各条件を示し、図２に［ＯＨ−］／コロイダルシリカの質量分率の値と、ＬＬＳ欠陥個数との関係を示すグラフを示す。こちらも、［ＯＨ−］／砥粒濃度が０．１ｍｏｌ／ｌ以上であればＬＬＳ欠陥が減少していることが判った。 (Examples 5 to 8, Comparative Examples 2 and 3)
Next, polishing evaluation was performed by changing the mass fraction (abrasive grain concentration) of colloidal silica while keeping the alkali concentration of the polishing slurry constant (PH10.5). Other conditions were the same as in Examples 1 to 4 and Comparative Example 1. Each condition is shown in Table 2, and the graph which shows the relationship between the value of the mass fraction of [OH < - >] / colloidal silica, and the number of LLS defects is shown in FIG. Also here, it was found that LLS defects were reduced when the [OH − ] / abrasive grain concentration was 0.1 mol / l or more.

Figure 2018195641
Figure 2018195641

以上の結果から、硬質パッドを用いたにも関わらず、研磨における機械的作用に対する化学的作用の指標である［ＯＨ−］／砥粒濃度の値が０．１以上である研磨スラリーを用いることで（実施例１〜８）、比較例１〜３に比べ、ＬＬＳ欠陥が減少していることが判った。しかも、上記のように、得られたウェーハの平坦度（ＳＦＱＲ）も高いものであった。 From the above results, a polishing slurry having a value of [OH − ] / abrasive grain concentration of 0.1 or more, which is an index of chemical action against mechanical action in polishing, despite using a hard pad is used. (Examples 1 to 8), it was found that LLS defects were reduced as compared with Comparative Examples 1 to 3. Moreover, as described above, the flatness (SFQR) of the obtained wafer was also high.

なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。   The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

１…研磨パッド、 ２…定盤、 ３…研磨ヘッド、 ４…ノズル、 １０…片面研磨機。   DESCRIPTION OF SYMBOLS 1 ... Polishing pad, 2 ... Surface plate, 3 ... Polishing head, 4 ... Nozzle, 10 ... Single-side polishing machine.

Claims (3)

シリコンウェーハと研磨パッドとの間に研磨スラリーを介在させて、前記シリコンウエーハを研磨するシリコンウエーハの研磨方法であって、
前記研磨スラリーとして、コロイダルシリカとアルカリを含み、（前記研磨スラリー中の水酸化物イオン濃度［ＯＨ−］（ｍｏｌ／ｌ））／（前記研磨スラリーの質量中の前記コロイダルシリカの質量分率）≧０．１（ｍｏｌ／ｌ）を満たすものを用いて研磨することを特徴とするシリコンウェーハの研磨方法。 A method for polishing a silicon wafer, wherein a polishing slurry is interposed between a silicon wafer and a polishing pad to polish the silicon wafer,
The polishing slurry contains colloidal silica and alkali, (hydroxide ion concentration in the polishing slurry [OH − ] (mol / l)) / (mass fraction of the colloidal silica in the mass of the polishing slurry) A method for polishing a silicon wafer, comprising polishing using a material satisfying ≧ 0.1 (mol / l). 前記研磨パッドとして、ショアＡ硬度６０以上の研磨パッドを用いることを特徴とする請求項１に記載のシリコンウェーハの研磨方法。   2. The method for polishing a silicon wafer according to claim 1, wherein a polishing pad having a Shore A hardness of 60 or more is used as the polishing pad. 前記研磨パッドとして、ショアＡ硬度７０以上の研磨パッドを用いることを特徴とする請求項１又は請求項２に記載のシリコンウェーハの研磨方法。
The method for polishing a silicon wafer according to claim 1, wherein a polishing pad having a Shore A hardness of 70 or more is used as the polishing pad.
JP2017096563A 2017-05-15 2017-05-15 Silicon wafer polishing method Active JP6747376B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2017096563A JP6747376B2 (en) 2017-05-15 2017-05-15 Silicon wafer polishing method
PCT/JP2018/016132 WO2018211903A1 (en) 2017-05-15 2018-04-19 Silicon wafer polishing method
TW107113771A TWI727165B (en) 2017-05-15 2018-04-24 Method for polishing silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017096563A JP6747376B2 (en) 2017-05-15 2017-05-15 Silicon wafer polishing method

Publications (2)

Publication Number Publication Date
JP2018195641A true JP2018195641A (en) 2018-12-06
JP6747376B2 JP6747376B2 (en) 2020-08-26

Family

ID=64274094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017096563A Active JP6747376B2 (en) 2017-05-15 2017-05-15 Silicon wafer polishing method

Country Status (3)

Country Link
JP (1) JP6747376B2 (en)
TW (1) TWI727165B (en)
WO (1) WO2018211903A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023119951A1 (en) * 2021-12-21 2023-06-29 信越半導体株式会社 Double side polishing apparatus, double side polishing method for semiconductor silicon wafer, double side polished silicon wafer and method for producing same
JP2023092412A (en) * 2021-12-21 2023-07-03 信越半導体株式会社 Double-side Polishing Apparatus, Double-side Polishing Method for Semiconductor Silicon Wafer, Method for Manufacturing Double-side Polished Silicon Wafer, and Double-side Polishing Silicon Wafer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010076075A (en) * 2008-09-29 2010-04-08 Fujibo Holdings Inc Polishing sheet used in polishing pad for use in polishing, and the polishing pad
JP2010082707A (en) * 2008-09-29 2010-04-15 Fujibo Holdings Inc Polishing pad
WO2010122985A1 (en) * 2009-04-20 2010-10-28 日立化成工業株式会社 Polishing liquid for semiconductor substrate and method for polishing semiconductor substrate
JP2013258227A (en) * 2012-06-12 2013-12-26 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 Semiconductor wafer manufacturing method
JP2015193060A (en) * 2014-03-31 2015-11-05 富士紡ホールディングス株式会社 Polishing pad and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013204839A1 (en) * 2013-03-19 2014-09-25 Siltronic Ag Method of polishing a wafer of semiconductor material

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010076075A (en) * 2008-09-29 2010-04-08 Fujibo Holdings Inc Polishing sheet used in polishing pad for use in polishing, and the polishing pad
JP2010082707A (en) * 2008-09-29 2010-04-15 Fujibo Holdings Inc Polishing pad
WO2010122985A1 (en) * 2009-04-20 2010-10-28 日立化成工業株式会社 Polishing liquid for semiconductor substrate and method for polishing semiconductor substrate
JP2013258227A (en) * 2012-06-12 2013-12-26 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 Semiconductor wafer manufacturing method
JP2015193060A (en) * 2014-03-31 2015-11-05 富士紡ホールディングス株式会社 Polishing pad and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023119951A1 (en) * 2021-12-21 2023-06-29 信越半導体株式会社 Double side polishing apparatus, double side polishing method for semiconductor silicon wafer, double side polished silicon wafer and method for producing same
JP2023092412A (en) * 2021-12-21 2023-07-03 信越半導体株式会社 Double-side Polishing Apparatus, Double-side Polishing Method for Semiconductor Silicon Wafer, Method for Manufacturing Double-side Polished Silicon Wafer, and Double-side Polishing Silicon Wafer
JP7435634B2 (en) 2021-12-21 2024-02-21 信越半導体株式会社 Double-sided polishing device, double-sided polishing method for semiconductor silicon wafers, and method for manufacturing double-sided polished silicon wafers

Also Published As

Publication number Publication date
JP6747376B2 (en) 2020-08-26
TW201900333A (en) 2019-01-01
WO2018211903A1 (en) 2018-11-22
TWI727165B (en) 2021-05-11

Similar Documents

Publication Publication Date Title
US20110223840A1 (en) Polishing Composition and Polishing Method Using The Same
JP5332249B2 (en) Glass substrate polishing method
JP5557506B2 (en) Polishing both sides of a semiconductor wafer
JP5853041B2 (en) Method for polishing a semiconductor material wafer
JP5493956B2 (en) Manufacturing method of semiconductor wafer
JP5622124B2 (en) Polishing method of silicon wafer
JP5907081B2 (en) Method for producing synthetic quartz glass substrate
JP4696086B2 (en) Final polishing method for silicon single crystal wafer and silicon single crystal wafer
JP4608856B2 (en) Wafer polishing method
JP2006128269A (en) Semiconductor wafer and method for manufacturing the same
US20130130595A1 (en) Polishing agent and polishing method
JP5516594B2 (en) CMP polishing liquid, and polishing method and semiconductor substrate manufacturing method using the same
US10066128B2 (en) Method for preparing an aluminum oxide polishing solution
JP6747376B2 (en) Silicon wafer polishing method
JP4852302B2 (en) Method for producing abrasive, abrasive produced thereby and method for producing silicon wafer
JPWO2019043890A1 (en) Method for manufacturing semiconductor wafer
CN114450376B (en) Grinding composition
US6211088B1 (en) Manufacturing method for semiconductor gas-phase epitaxial wafer
JP2006205265A (en) Polishing method and polishing composition
JP5803601B2 (en) Polishing slurry supply method and supply apparatus, and polishing apparatus
US20130149941A1 (en) Method Of Machining Semiconductor Substrate And Apparatus For Machining Semiconductor Substrate
JP2000038572A (en) Glass or quartz abrasive composition and preparation thereof
WO2012176377A1 (en) Polishing method for silicon wafer
KR101581469B1 (en) Wafer polishing method
JP2014068044A (en) Substrate and light emitting element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190415

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20191126

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200107

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20200225

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200501

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20200518

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200707

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200720

R150 Certificate of patent or registration of utility model

Ref document number: 6747376

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250