JP2018156963A - FIELD EFFECT TRANSISTOR, DISPLAY ELEMENT, DISPLAY DEVICE, SYSTEM, AND MANUFACTURING METHOD THEREOF - Google Patents

Abstract

A field effect transistor capable of suppressing dissolution of electrodes and wiring of a field effect transistor is provided. In a field effect transistor, a gate electrode is formed on an insulating substrate, and a gate insulating layer is formed so as to cover the gate electrode. Further, a source electrode 14 and a drain electrode 15 are formed on the gate insulating layer, and a semiconductor layer 16 is formed so as to cover a part of the source electrode and the drain electrode. A passivation layer 17 is formed on the gate insulating layer so as to cover at least part of the source and drain electrodes and the entire semiconductor layer. In addition, at least part of the wiring connected to the source electrode and at least part of the wiring connected to the drain electrode are exposed from the passivation layer. With the above formation, it is possible to reduce the variation amount of the threshold voltage with respect to the BTS test. [Selection] Figure 1

Description

  The present invention relates to a field effect transistor, a display element, a display device, a system, and a manufacturing method thereof.

In recent years, liquid crystal displays, electronic paper, and the like have been put into practical use as flat panel displays (FPD). These FPDs are driven by a drive circuit including a field effect transistor using, for example, amorphous silicon, polycrystalline silicon or the like as a semiconductor layer. A field effect transistor using an oxide semiconductor such as InGaZnO ₄ as a semiconductor layer has also been proposed.

By the way, a passivation layer is provided in the field effect transistor. Examples of the material for the passivation layer include SiO ₂ , Si ₃ N ₄ , SiON, Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , HfO ₂ , A single layer film of ZrO ₂ or Y ₂ O ₃ , or a laminated film thereof is used. Among them, an insulating film (SiO ₂ , Si ₃ N ₄ , SiON) containing silicon is widely used as a passivation layer.

  As a configuration for improving the reliability of a field effect transistor, a field effect transistor including a passivation layer containing an oxide containing Si and alkaline earth has been proposed (see, for example, Patent Document 1). ).

  When patterning a passivation layer containing silicon by wet etching, a hydrofluoric acid-based etching solution is generally used. Examples of hydrofluoric acid-based etching solutions include hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride.

  However, Ti and Al used for electrodes (source electrode, drain electrode, gate electrode) of the field-effect transistor and wiring connected to them are dissolved by hydrofluoric acid. Therefore, it is necessary to make it difficult for the electrodes and wirings of the field effect transistor to be dissolved by wet etching of the passivation layer.

  Accordingly, an object of the present invention is to provide a method of manufacturing a field effect transistor capable of suppressing dissolution of electrodes and / or wirings of the field effect transistor during wet etching of a passivation layer containing silicon. And

  The field effect transistor manufacturing method includes a source electrode, a drain electrode, and a gate electrode, a wiring connected to the source electrode, a wiring connected to the drain electrode, a wiring connected to the gate electrode, and the source electrode. And a passivation layer covering at least a part of a wiring connected to the one electrode and the drain electrode and the gate electrode, and a fluorination method. Forming the one electrode and the wiring connected to the one electrode with a first material that dissolves in a solution containing at least one of hydrogen acid, ammonium fluoride, and ammonium hydrogen fluoride; After the step of performing heat treatment on the electrode connected to the electrode and the wiring connected to the one electrode and the step of performing the heat treatment, the solution A step of forming a passivation layer covering the one electrode and the wiring connected to the one electrode by the second material to be dissolved; and etching the contact layer by contacting the passivation layer with the solution; from the passivation layer And exposing a part of the one electrode and / or at least a part of the wiring connected to the one electrode.

  According to the disclosed technology, it is possible to provide a method of manufacturing a field effect transistor capable of suppressing dissolution of electrodes and / or wirings of the field effect transistor during wet etching of a passivation layer containing silicon. it can.

1 is a cross-sectional view illustrating a field effect transistor according to a first embodiment. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the field effect transistor according to the first embodiment; FIG. 6 is a diagram (No. 2) for exemplifying the manufacturing process of the field effect transistor according to the first embodiment; It is sectional drawing which illustrates the field effect transistor which concerns on the modification of 1st Embodiment. It is sectional drawing explaining the structure and manufacturing method of the organic electroluminescent display element which concern on 2nd Embodiment. It is sectional drawing explaining the structure and manufacturing method of the organic electroluminescent display element which concern on the modification of 2nd Embodiment. It is a block diagram which shows the structure of the television apparatus which concerns on 3rd Embodiment. It is explanatory drawing (the 1) of the television apparatus which concerns on 3rd Embodiment. It is explanatory drawing (the 2) of the television apparatus which concerns on 3rd Embodiment. It is explanatory drawing (the 3) of the television apparatus which concerns on 3rd Embodiment. It is explanatory drawing of the display element which concerns on 3rd Embodiment. It is explanatory drawing of organic EL which concerns on 3rd Embodiment. It is explanatory drawing (the 4) of the television apparatus which concerns on 3rd Embodiment. It is explanatory drawing (the 1) of the other display element which concerns on 3rd Embodiment. It is explanatory drawing (the 2) of the other display element which concerns on 3rd Embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

<First Embodiment>
[Structure of field effect transistor]
FIG. 1 is a cross-sectional view illustrating a field effect transistor according to the first embodiment. Referring to FIG. 1, the field effect transistor 10 includes a substrate 11, a gate electrode 12, a gate insulating layer 13, a source electrode 14, a drain electrode 15, a semiconductor layer 16, and a passivation layer 17. This is a bottom-gate / bottom-contact field effect transistor. The field effect transistor 10 is a typical example of a semiconductor device according to the present invention.

  In the field effect transistor 10, a gate electrode 12 is formed on an insulating substrate 11, and a gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, a source electrode 14 and a drain electrode 15 are formed on the gate insulating layer 13, and a semiconductor layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. The source electrode 14 and the drain electrode 15 are formed at a predetermined interval that becomes a channel region of the semiconductor layer 16.

  A passivation layer 17 that covers at least a part of the source electrode 14, at least a part of the drain electrode 15, and the entire semiconductor layer 16 is formed on the gate insulating layer 13. A wiring connected to the source electrode 14 (hereinafter referred to as a source wiring) is formed in the same layer as the source electrode 14. A wiring connected to the drain electrode 15 (hereinafter referred to as a drain wiring) is formed in the same layer as the drain electrode 15. However, the source wiring and the drain wiring do not appear in the cross section of FIG.

  Note that the wiring is appropriately formed as necessary, and electrically connects a conductive film serving as a terminal for measuring electric characteristics of the field effect transistor or a field effect transistor included in a driver circuit described later. A conductive film or a conductive film that electrically connects a field effect transistor included in a drive circuit and a light control element, or a conductive film that electrically connects a field effect transistor included in an image data creation device and a drive circuit. A membrane or the like.

  In the present embodiment, for the sake of convenience, the passivation layer 17 side is defined as the upper side or one side, and the substrate 11 side is defined as the lower side or the other side. In addition, the surface on the passivation layer 17 side of each part is the upper surface or one surface, and the surface on the substrate 11 side is the lower surface or the other surface. However, the field effect transistor 10 can be used upside down, or can be arranged at an arbitrary angle. Further, the planar view refers to viewing the object from the normal direction of the upper surface of the substrate 11, and the planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the substrate 11. Hereinafter, each component of the field effect transistor 10 will be described in detail.

<substrate>
There is no restriction | limiting in particular as a shape of the board | substrate 11, a structure, and a magnitude | size, According to the objective, it can select suitably. There is no restriction | limiting in particular as a material of the board | substrate 11, Although it can select suitably according to the objective, For example, a glass base material, a ceramic base material, a plastic base material, a film base material etc. can be used.

  There is no restriction | limiting in particular as a glass base material, Although it can select suitably according to the objective, For example, an alkali free glass, a silica glass, etc. are mentioned. Moreover, there is no restriction | limiting in particular as a plastic base material or a film base material, Although it can select suitably according to the objective, For example, a polycarbonate (PC), a polyimide (PI), a polyethylene terephthalate (PET), a polyethylene naphthalate (PEN) and the like.

<Gate electrode>
The gate electrode 12 is formed in a predetermined region on the substrate 11. The gate electrode 12 is an electrode for applying a gate voltage. The gate electrode 12 is in contact with the gate insulating layer 13 and faces the semiconductor layer 16 with the gate insulating layer 13 interposed therebetween. A wiring connected to the gate electrode 12 (hereinafter referred to as a gate wiring) is formed in the same layer as the gate electrode 12. However, the gate wiring does not appear in the cross section of FIG.

  The material of the gate electrode 12 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, molybdenum (Mo), titanium (Ti), aluminum (Al), gold (Au), silver (Ag) ), Metals such as copper (Cu), alloys thereof, mixtures of these metals, and the like.

  Further, as the material of the gate electrode 12, a conductive oxide such as indium tin oxide (ITO) or antimony-doped tin oxide (ATO), a composite compound thereof, a mixture thereof, or the like may be used. Further, an organic conductor such as polyethylene dioxythiophene (PEDOT) or polyaniline (PANI) may be used. There is no restriction | limiting in particular as an average film thickness of the gate electrode 12, Although it can select suitably according to the objective, 10 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

<Gate insulation layer>
The gate insulating layer 13 is not particularly limited as long as it is an insulating layer formed between the substrate 11 and the passivation layer 17 and can be appropriately selected according to the purpose. In the example of FIG. 1, the gate insulating layer 13 is provided between the gate electrode 12 and the semiconductor layer 16 and insulates the gate electrode 12 and the semiconductor layer 16.

The gate insulating layer 13 is not particularly limited and may be appropriately selected depending on the purpose, for _example, SiO 2, SiNx, materials and, La being utilized already widely mass of _Al 2 _{O 3} or the like Examples thereof include high dielectric constant materials such as ₂ O ₃ and HfO ₂ , and organic materials such as polyimide (PI) and fluorine-based resins. There is no restriction | limiting in particular as an average film thickness of the gate insulating layer 13, Although it can select suitably according to the objective, 50 nm-3 micrometers are preferable, and 100 nm-1 micrometer are more preferable.

<Source electrode, drain electrode, source wiring, drain wiring>
The source electrode 14 and the drain electrode 15 as well as the source wiring and the drain wiring are formed on the gate insulating layer 13. The source electrode 14 and the drain electrode 15 are formed at a predetermined interval so as to be in contact with the gate insulating layer 13. The source electrode 14 and the drain electrode 15 are electrodes for taking out a current in response to application of a gate voltage to the gate electrode 12.

  The materials of the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring are not particularly limited and can be appropriately selected according to the purpose. For example, molybdenum (Mo), titanium (Ti), aluminum (Al ), Gold (Au), silver (Ag), copper (Cu) and other metals and alloys thereof, transparent conductive oxides such as indium tin oxide (ITO) and antimony-doped tin oxide (ATO), polyethylene dioxythiophene Examples thereof include organic conductors such as (PEDOT) and polyaniline (PANI).

  Among these, Ti and Al metals, and alloys thereof are preferable because they have good electrical contact with the semiconductor layer 16. There is no restriction | limiting in particular as an average film thickness of the source electrode 14 and the drain electrode 15, and source wiring and drain wiring, Although it can select suitably according to the objective, 20 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

<Semiconductor layer>
The semiconductor layer 16 is formed at least between the source electrode 14 and the drain electrode 15 and is in contact with the gate insulating layer 13, the source electrode 14, and the drain electrode 15. Here, “between” is a position where the semiconductor layer 16 together with the source electrode 14 and the drain electrode 15 allows the field-effect transistor 10 to function. Can be selected as appropriate.

  There is no restriction | limiting in particular as a material of the semiconductor layer 16, According to the objective, it can select suitably, For example, a silicon semiconductor, an oxide semiconductor, an organic semiconductor etc. are mentioned. Examples of the silicon semiconductor include amorphous silicon and polycrystalline silicon. Examples of the oxide semiconductor include InGa—Zn—O, In—Zn—O, In—Mg—O, and the like. Examples of the organic semiconductor include pentacene.

  Among these, it is preferable to use an oxide semiconductor from the viewpoint of stability of the interface with the gate insulating layer 13 and the passivation layer 17. There is no restriction | limiting in particular as an average film thickness of the semiconductor layer 16, Although it can select suitably according to the objective, 5 nm-1 micrometer are preferable and 10 nm-0.5 micrometer are more preferable.

<Passivation layer>
One of the functions of the passivation layer in the present invention is a layer having a function of isolating and protecting at least the semiconductor layer (semiconductor layer) from moisture, oxygen, hydrogen, etc. in the atmosphere. Further, the passivation layer in the present invention may protect not only the semiconductor layer but also other components of the field effect transistor (for example, the gate insulating layer, the source electrode, the drain electrode, and the gate electrode). Good. One of the functions of the passivation layer in the present invention is to protect (at least a part of) the field effect transistor from the material of the layer formed on the field effect transistor and the formation process thereof. Further, the passivation layer is sometimes called a protective layer.

  The passivation layer is usually formed above the substrate 11. In FIG. 1, as an example, the passivation layer 17 is formed on the gate insulating layer 13 so as to cover a part of the source electrode 14, a part of the drain electrode 15, and the entire semiconductor layer 16.

  The passivation layer 17 may be formed so as to cover the entire source electrode 14, the entire drain electrode 15, and the entire semiconductor layer 16. Even in this case, at least part of the source wiring and at least part of the drain wiring are exposed from the passivation layer 17.

  The average film thickness of the passivation layer 17 is preferably 10 to 1,000 nm, and more preferably 20 to 500 nm. Hereinafter, the passivation layer 17 will be described in detail.

-Passivation layer 17-
The passivation layer 17 contains an oxide containing Si, a nitride containing Si, or an oxynitride containing Si. The oxide containing Si is, for example, SiO ₂ . The oxide containing Si may be, for example, an oxide containing Si and an alkaline earth metal. The nitride containing Si is, for example, Si ₃ N ₄ . The oxynitride containing Si is, for example, SiON.

  The case where the passivation layer 17 is an oxide containing Si and an alkaline earth metal (hereinafter referred to as a first oxide) will be described in detail below.

-First oxide-
The first oxide preferably contains at least one of Al (aluminum) and B (boron), and further contains other components as necessary.

In the first oxide, SiO ₂ formed of Si forms an amorphous structure. The alkaline earth metal has a function of cutting the Si—O bond. Therefore, it is possible to control the relative dielectric constant and the linear expansion coefficient of the first oxide formed by the composition ratio of Si and alkaline earth metal.

The first oxide preferably contains at least one of Al and B. _Al 2 _{O 3} formed by Al, and _B 2 _{O 3} formed by B, in order to form a similarly amorphous structure and SiO _2, in the first oxide, a more stable amorphous structure is obtained As a result, a more uniform insulating layer can be formed. In addition, since the alkaline earth metal changes the coordination structure of Al and B depending on the composition ratio, it is possible to control the relative dielectric constant and the linear expansion coefficient of the first oxide formed.

  In the first oxide, examples of the alkaline earth metal include Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium). These may be used individually by 1 type and may use 2 or more types together.

  There is no restriction | limiting in particular as composition ratio of Si in a 1st oxide, and an alkaline-earth metal, Although it can select suitably according to the objective, It is preferable that it is the following ranges.

In the first oxide, the composition ratio between Si and the alkaline earth metal (Si: alkaline earth metal) is 50. In terms of oxide (SiO ₂ , BeO, MgO, CaO, SrO, BaO). 0 mol%-90.0 mol%: 10.0 mol%-50.0 mol% are preferable.

  The composition ratio of Si, alkaline earth metal, and at least one of Al and B in the first oxide is not particularly limited and may be appropriately selected depending on the intended purpose, but is in the following range. It is preferable.

In the first oxide, the composition ratio (Si: alkaline earth metal: at least one of Al and B) of Si, an alkaline earth metal, and at least one of Al and B is an oxide (SiO ₂ , BeO, MgO, CaO, SrO , BaO, with _{Al 2 O 3, B 2 O} 3) in terms of, 50.0mol% ~90.0mol%: 5.0mol% ~20.0mol%: 5.0mol% ~30 0.0 mol% is preferable.

The ratio of the oxide (SiO ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ) in the first oxide is, for example, fluorescent X-ray analysis, electron micro analysis (EPMA) It can be calculated by analyzing the cation element of the first oxide by dielectric coupled plasma emission spectroscopy (ICP-AES) or the like.

  There is no restriction | limiting in particular as a dielectric constant of the passivation layer 17, According to the objective, it can select suitably.

  The relative dielectric constant of the passivation layer 17 can be measured using, for example, an LCR meter or the like by fabricating a capacitor in which a lower electrode, a dielectric layer (passivation layer), and an upper electrode are stacked.

  There is no restriction | limiting in particular as a linear expansion coefficient of the passivation layer 17, According to the objective, it can select suitably.

  The linear expansion coefficient of the passivation layer 17 can be measured using, for example, a thermomechanical analyzer. In this measurement, the linear expansion coefficient can be measured by separately preparing and measuring a measurement sample having the same composition as that of the passivation layer 17 without producing a field effect transistor.

  The inventors have found that the passivation layer 17 exhibits excellent barrier properties against moisture, oxygen, and nitrogen in the air by containing Si and an alkaline earth metal. Therefore, the field-effect transistor including the passivation layer 17 can provide a field-effect transistor exhibiting high reliability because the amount of variation in threshold voltage with respect to a BTS (Bias Temperature Stress) test is reduced.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be described. 2 and 3 are diagrams illustrating the manufacturing process of the field effect transistor according to the first embodiment.

  First, in the step shown in FIG. 2A, the substrate 11 is prepared, and the gate electrode 12 having a predetermined shape is formed on the substrate 11. From the viewpoint of cleaning the surface of the substrate 11 and improving adhesion, it is preferable to perform pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning before forming the gate electrode 12.

  The method for forming the gate electrode 12 is not particularly limited and may be appropriately selected depending on the purpose. For example, after film formation by sputtering, vacuum deposition, dip coating, spin coating, die coating, or the like, There is a method of patterning by photolithography. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure. The material and thickness of the substrate 11 and the gate electrode 12 can be appropriately selected as described above.

  Next, in the step shown in FIG. 2B, the gate insulating layer 13 that covers the gate electrode 12 is formed on the substrate 11. There is no restriction | limiting in particular as a formation method of the gate insulating layer 13, According to the objective, it can select suitably, For example, a sputter | spatter, chemical vapor deposition (CVD), atomic layer deposition (ALD), dip coating method, spin Examples include a method of patterning by photolithography as necessary after film formation by a coating method, a die coating method, or the like. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure. The material and thickness of the gate insulating layer 13 can be appropriately selected as described above.

  Next, in the step shown in FIG. 2C, a source electrode 14 and a drain electrode 15 having a predetermined shape are formed on the gate insulating layer 13, and a source wiring and a drain wiring are formed. From the viewpoint of cleaning the surface of the gate insulating layer 13 and improving the adhesion, before the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring are formed, a pretreatment such as oxygen plasma, UV ozone, UV irradiation cleaning or the like is performed. Preferably, it is done.

  A method for forming the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring is not particularly limited and can be appropriately selected according to the purpose. For example, sputtering, vacuum deposition, dip coating, spin coating Examples thereof include a method of patterning by photolithography after film formation by a method, a die coating method, or the like. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure. The materials and thicknesses of the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring can be appropriately selected as described above.

  Next, in a step shown in FIG. 2D, a semiconductor layer 16 having a predetermined shape is formed on the gate insulating layer 13. The method for forming the semiconductor layer 16 is not particularly limited and can be appropriately selected depending on the purpose. For example, after film formation by sputtering, vacuum deposition, dip coating, spin coating, die coating, or the like, There is a method of patterning by photolithography. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure. The material and thickness of the semiconductor layer 16 can be appropriately selected as described above.

  Next, in the process shown in FIG. 3A, a heat treatment process is performed before the passivation layer 17 is formed. By performing a heat treatment step before the formation of the passivation layer 17, the surface of the source electrode 14 and the drain electrode 15 in a region not covered with the semiconductor layer 16 and the surface of the source wiring and the drain wiring can be oxidized.

  That is, in FIG. 3A, an oxide film of an element constituting the source electrode 14 and the drain electrode 15 is formed on the surface of the portion indicated by A. In addition, an oxide film of an element constituting the source wiring and the drain wiring is formed on the surface of the source wiring and the drain wiring.

  By oxidizing the surface of the source electrode 14 and the drain electrode 15 in the region not covered with the semiconductor layer 16 and the surface of the source wiring and the drain wiring, the passivation layer 170 (etched to become the passivation layer 17 is etched) in the next step. The source electrode 14 and the drain electrode 15 in the region finally exposed from the passivation layer 17 and the source wiring by hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride, which are etchants for the passivation layer 170, are etched. And it is possible to prevent the drain wiring from being dissolved.

For example, when Ti is used for the source electrode 14 and the drain electrode 15 as well as the source wiring and the drain wiring, the surface of Ti is oxidized to become TiO ₂ by performing a heat treatment process. Since TiO ₂ is not dissolved by hydrofluoric acid, ammonium fluoride, or ammonium hydrogen fluoride, the etching solution of the passivation layer 170 does not dissolve the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring.

  Without the heat treatment step, the source electrode 14 and the drain electrode 15 in the region finally exposed from the passivation layer 17 are constituted by hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride, which are etching solutions for the passivation layer 170. Ti and Ti constituting the source wiring and the drain wiring are dissolved.

  The temperature of the heat treatment step is not particularly limited, and can be appropriately selected depending on the purpose as long as it is a temperature at which the surfaces of the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring are oxidized. It is preferably less than 500 ° C.

  Note that the thickness of the oxide film formed on the surface of the source and drain electrodes 15 and the source and drain wirings can be controlled by the temperature and / or time and / or atmosphere of the heat treatment step.

  The thickness of the oxide film can prevent the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring from being dissolved during etching, and the through hole in which the source wiring and the drain wiring are formed in an interlayer insulating layer or the like. The contact resistance when connected to other parts via the control is controlled within a range in which the contact resistance can be maintained at a low value. From such a viewpoint, it is preferable to control the thickness of the oxide film to about several nm.

  Next, in the step shown in FIG. 3B, a passivation layer 170 that covers the entire source electrode 14, the entire drain electrode 15, and the entire semiconductor layer 16 is formed on the entire surface of the gate insulating layer 13.

  There is no restriction | limiting in particular as a formation method of the passivation layer 170, According to the objective, it can select suitably, For example, a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method, an atomic layer Examples include film formation by a vacuum process such as vapor deposition (ALD).

  In the case where the passivation layer 170 is formed from an oxide (first oxide) containing Si and an alkaline earth metal, a coating solution containing a precursor of the first oxide (coating solution for forming a passivation layer). It is possible to form a film by preparing the above, applying or printing it on an object to be coated, and baking it under appropriate conditions. This method will be described in detail below.

--- Passivation layer forming coating liquid-
The coating liquid for forming a passivation layer contains at least a silicon-containing compound, an alkaline earth metal compound, and a solvent, preferably contains at least one of an aluminum-containing compound and a boron-containing compound, and further if necessary. And other ingredients.

--- Silicon-containing compound ---
Examples of the silicon-containing compound include inorganic silicon compounds and organic silicon compounds.

  Examples of the inorganic silicon compound include tetrachlorosilane, tetrabromosilane, tetraiodosilane, and the like.

  The organosilicon compound is not particularly limited as long as it is a compound having silicon and an organic group, and can be appropriately selected according to the purpose. The silicon and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. Examples thereof include an acyloxy group which may have a phenyl group which may have a substituent. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. As an acyloxy group, a C1-C10 acyloxy group etc. are mentioned, for example.

  Examples of the organosilicon compound include tetramethoxysilane, tetraethoxysilane, tetraisopropoxysilane, tetrabutoxysilane, 1,1,1,3,3,3-hexamethyldisilazane (HMDS), and bis (trimethylsilyl) acetylene. , Triphenylsilane, silicon 2-ethylhexanoate, tetraacetoxysilane and the like.

  There is no restriction | limiting in particular as content of the silicon-containing compound in the coating liquid for passivation layer formation, According to the objective, it can select suitably.

--- Alkaline earth metal-containing compound ---
Examples of the alkaline earth metal-containing compound include inorganic alkaline earth metal compounds and organic alkaline earth metal compounds. Examples of the alkaline earth metal in the alkaline earth metal-containing compound include Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  Examples of inorganic alkaline earth metal compounds include alkaline earth metal nitrates, alkaline earth metal sulfates, alkaline earth metal chlorides, alkaline earth metal fluorides, alkaline earth metal bromides, and alkaline earth metal iodides. Etc.

  Examples of the alkaline earth metal nitrate include magnesium nitrate, calcium nitrate, strontium nitrate, and barium nitrate.

  Examples of the alkaline earth metal sulfate include magnesium sulfate, calcium sulfate, strontium sulfate, and barium sulfate.

  Examples of the alkaline earth metal chloride include magnesium chloride, calcium chloride, strontium chloride, barium chloride and the like.

  Examples of the alkaline earth metal fluoride include magnesium fluoride, calcium fluoride, strontium fluoride, and barium fluoride.

  Examples of the alkaline earth metal bromide include magnesium bromide, calcium bromide, strontium bromide, barium bromide and the like.

  Examples of the alkaline earth metal iodide include magnesium iodide, calcium iodide, strontium iodide, barium iodide and the like.

  The organic alkaline earth metal compound is not particularly limited as long as it is a compound having an alkaline earth metal and an organic group, and can be appropriately selected according to the purpose. The alkaline earth metal and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. An acyloxy group which may have, a phenyl group which may have a substituent, an acetylacetonate group which may have a substituent, a sulfonic acid group which may have a substituent, and the like. It is done. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms, an acyloxy group partially substituted with a benzene ring such as benzoic acid, an acyloxy group partially substituted with a hydroxy group such as lactic acid, Examples include acids and acyloxy groups having two or more carbonyl groups such as citric acid.

  Examples of the organic alkaline earth metal compound include magnesium methoxide, magnesium ethoxide, diethyl magnesium, magnesium acetate, magnesium formate, acetylacetone magnesium, magnesium 2-ethylhexanoate, magnesium lactate, magnesium naphthenate, magnesium citrate, and salicylic acid. Magnesium, magnesium benzoate, magnesium oxalate, magnesium trifluoromethanesulfonate, calcium methoxide, calcium ethoxide, calcium acetate, calcium formate, acetylacetone calcium, calcium dipivaloylmethanate, calcium 2-ethylhexanoate, calcium lactate , Calcium naphthenate, calcium citrate, calcium salicylate, calcium neodecanoate, repose Calcium oxide, calcium oxalate, strontium isopropoxide, strontium acetate, strontium formate, acetylacetone strontium, strontium 2-ethylhexanoate, strontium lactate, strontium naphthenate, strontium salicylate, strontium oxalate, barium ethoxide, barium isopoxide , Barium acetate, barium formate, barium acetylacetone, barium 2-ethylhexanoate, barium lactate, barium naphthenate, barium neodecanoate, barium oxalate, barium benzoate, barium trifluoromethanesulfonate, bis (acetylacetonate) beryllium, etc. Is mentioned.

  There is no restriction | limiting in particular as content of the alkaline-earth metal containing compound in the coating liquid for passivation layer formation, According to the objective, it can select suitably.

--- Aluminum-containing compound ---
Examples of the aluminum-containing compound include inorganic aluminum compounds and organic aluminum compounds.

  Examples of the inorganic aluminum compound include aluminum chloride, aluminum nitrate, aluminum bromide, aluminum hydroxide, aluminum borate, aluminum trifluoride, aluminum iodide, aluminum sulfate, aluminum phosphate, and ammonium ammonium sulfate.

  There is no restriction | limiting in particular as long as it is a compound which has aluminum and an organic group as an organoaluminum compound, According to the objective, it can select suitably. Aluminum and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. Examples thereof include an acyloxy group which may have, an acetylacetonate group which may have a substituent, and a sulfonic acid group which may have a substituent. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. Examples of the acyloxy group include an acyloxy group having 1 to 10 carbon atoms, an acyloxy group partially substituted with a benzene ring such as benzoic acid, an acyloxy group partially substituted with a hydroxy group such as lactic acid, Examples include acids and acyloxy groups having two or more carbonyl groups such as citric acid.

  Examples of the organoaluminum compound include aluminum isopropoxide, aluminum-sec-butoxide, triethylaluminum, diethylaluminum ethoxide, aluminum acetate, acetylacetone aluminum, hexafluoroacetylacetonate aluminum, 2-ethylhexanoate aluminum, aluminum lactate, benzoic acid Examples thereof include aluminum acid, aluminum di (s-butoxide) acetoacetate chelate, and aluminum trifluoromethanesulfonate.

  There is no restriction | limiting in particular as content of the aluminum containing compound in the coating liquid for passivation layer formation, According to the objective, it can select suitably.

--- Boron-containing compound ---
Examples of the boron-containing compound include inorganic boron compounds and organic boron compounds.

  Examples of the inorganic boron compound include orthoboric acid, boron oxide, boron tribromide, tetrafluoroboric acid, ammonium borate, magnesium borate and the like. Examples of boron oxide include diboron dioxide, diboron trioxide, tetraboron trioxide, and tetraboron pentoxide.

  The organic boron compound is not particularly limited as long as it is a compound having boron and an organic group, and can be appropriately selected according to the purpose. Boron and the organic group are bonded by, for example, an ionic bond, a covalent bond, or a coordinate bond.

  The organic group is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include an alkyl group which may have a substituent, an alkoxy group which may have a substituent, and a substituent. Examples thereof include an acyloxy group which may have, a phenyl group which may have a substituent, a sulfonic acid group which may have a substituent, and a thiophene group which may have a substituent. As an alkyl group, a C1-C6 alkyl group etc. are mentioned, for example. As an alkoxy group, a C1-C6 alkoxy group etc. are mentioned, for example. An alkoxy group includes two or more oxygen atoms, and two of the two or more oxygen atoms are bonded to boron and form an organic ring structure together with boron. included. Moreover, the alkoxy group by which the alkyl group contained in the alkoxy group was substituted by the organic silyl group is also included. As an acyloxy group, a C1-C10 acyloxy group etc. are mentioned, for example.

  Examples of the organic boron compound include (R) -5,5-diphenyl-2-methyl-3,4-propano-1,3,2-oxazaborolidine, triisopropyl borate, and 2-isopropoxy-4. , 4,5,5-tetramethyl-1,3,2-dioxaborolane, bis (hexylene glycolato) diboron, 4- (4,4,5,5-tetramethyl-1,3,2-dioxaborolane-2 -Yl) -1H-pyrazole, (4,4,5,5-tetramethyl-1,3,2-dioxaborolan-2-yl) benzene, tert-butyl-N- [4- (4,4,5,5) 5-tetramethyl-1,2,3-dioxaborolan-2-yl) phenyl] carbamate, phenylboronic acid, 3-acetylphenylboronic acid, boron trifluoride acetic acid complex, boron trifluoride sulfolane complex , 2-thiophene boronic acid, tris (trimethylsilyl) borate and the like.

  There is no restriction | limiting in particular as content of the boron-containing compound in the coating liquid for passivation layer formation, According to the objective, it can select suitably.

--- Solvent ---
The solvent is not particularly limited as long as it is a solvent that stably dissolves or disperses various compounds, and can be appropriately selected according to the purpose. For example, toluene, xylene, mesitylene, cymene, pentylbenzene, dodecylbenzene, Bicyclohexyl, cyclohexylbenzene, decane, undecane, dodecane, tridecane, tetradecane, pentadecane, tetralin, decalin, isopropanol, ethyl benzoate, N, N-dimethylformamide, propylene carbonate, 2-ethylhexanoic acid, mineral spirits, dimethylpropylene urea 4-butyrolactone, 2-methoxyethanol, propylene glycol, water and the like.

  There is no restriction | limiting in particular as content of the solvent in the coating liquid for passivation layer formation, According to the objective, it can select suitably.

  The composition ratio between the silicon-containing compound and the alkaline earth metal-containing compound in the passivation layer-forming coating solution (silicon-containing compound: alkaline earth metal-containing compound) is not particularly limited and should be appropriately selected according to the purpose. However, the following range is preferable.

In the coating solution for forming a passivation layer, the composition ratio of Si to alkaline earth metal (Si: alkaline earth metal) is 50 in terms of oxide (SiO ₂ , BeO, MgO, CaO, SrO, BaO). 0.0 mol% to 90.0 mol%: 10.0 mol% to 50.0 mol% is preferable.

  Composition ratio of silicon-containing compound, alkaline earth metal-containing compound, and aluminum-containing compound and boron-containing compound in the passivation layer forming coating solution (silicon-containing compound: alkaline earth metal-containing compound: aluminum-containing compound and There is no restriction | limiting in particular as at least any one of a boron containing compound), Although it can select suitably according to the objective, It is preferable that it is the following ranges.

In the coating solution for forming a passivation layer, the composition ratio of Si, alkaline earth metal, and at least one of Al and B (Si: alkaline earth metal: at least one of Al and B) is an oxide (SiO 2 ₂ , BeO, MgO, CaO, SrO, BaO, Al ₂ O ₃ , B ₂ O ₃ ) 50.0 mol% to 90.0 mol%: 5.0 mol% to 20.0 mol%: 5.0 mol% to 30.0 mol% is preferable.
--- Passivation layer forming method using passivation layer forming coating solution ---
An example of a method for forming the passivation layer 17 using the passivation layer forming coating solution will be described. The method for forming the passivation layer 17 includes a step of applying the passivation layer 17 and a heat treatment step of the passivation layer 17, and further includes other steps as necessary.

  The step of applying the passivation layer 17 is not particularly limited as long as it is a step of applying a passivation layer forming coating solution to an object to be coated, and can be appropriately selected according to the purpose. The application method is not particularly limited and can be appropriately selected depending on the purpose. For example, a desired method can be selected by a method of patterning by photolithography after film formation by a solution process, a printing method such as inkjet, nanoimprint, or gravure. And a method of directly forming a film of the above shape. Examples of the solution process include dip coating, spin coating, die coating, and nozzle printing.

  The heat treatment step for the passivation layer 17 is not particularly limited as long as it is a step for heat treating the passivation layer forming coating solution applied to the article to be coated, and can be appropriately selected according to the purpose. Note that when the heat treatment is performed, the passivation layer-forming coating solution applied to the object to be coated may be dried by natural drying or the like. By the heat treatment, drying of the solvent, generation of the first oxide, and the like are performed.

  In the heat treatment step of the passivation layer 17, the solvent is dried (hereinafter referred to as “drying process”) and the first oxide is generated (hereinafter referred to as “generation process”) at different temperatures. Is preferred. That is, it is preferable to generate the first oxide by raising the temperature after drying the solvent. In the production of the first oxide, for example, decomposition of at least one of a silicon-containing compound, an alkaline earth metal-containing compound, an aluminum-containing compound, and a boron-containing compound occurs.

  There is no restriction | limiting in particular as temperature of a drying process, According to the solvent to contain, it can select suitably, For example, 80 to 180 degreeC is mentioned. In drying, it is effective to use a vacuum oven or the like for lowering the temperature. There is no restriction | limiting in particular as time of a drying process, According to the objective, it can select suitably, For example, 1 minute-1 hour are mentioned.

  There is no restriction | limiting in particular as temperature of a production | generation process, Although it can select suitably according to the objective, 100 degreeC or more and less than 550 degreeC are preferable, and 200 to 500 degreeC is more preferable. There is no restriction | limiting in particular as time of a production | generation process, According to the objective, it can select suitably, For example, 1 hour-5 hours are mentioned.

  In the heat treatment step, the drying process and the generation process may be performed continuously, or may be divided into a plurality of processes.

  There is no restriction | limiting in particular as the method of heat processing, According to the objective, it can select suitably, For example, the method etc. which heat a to-be-coated article are mentioned. There is no restriction | limiting in particular as atmosphere in heat processing, Although it can select suitably according to the objective, Oxygen atmosphere is preferable. By performing the heat treatment in an oxygen atmosphere, the decomposition product can be quickly discharged out of the system, and the generation of the first oxide can be promoted.

  In the heat treatment, it is effective to irradiate the material after the drying treatment with ultraviolet light having a wavelength of 400 nm or less in order to accelerate the reaction of the generation treatment. By irradiating ultraviolet light having a wavelength of 400 nm or less, chemical bonds such as organic substances contained in the material after the drying treatment can be broken and the organic substances can be decomposed, so that the first oxide can be efficiently formed. it can. The ultraviolet light having a wavelength of 400 nm or less is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include ultraviolet light having a wavelength of 222 nm using an excimer lamp. It is also preferable to apply ozone instead of or in combination with ultraviolet light irradiation. By applying ozone to the material after the drying treatment, the generation of the first oxide is promoted.

  Next, in the step shown in FIG. 3C, a mask 300 is formed in a predetermined region on the passivation layer 170. The mask 300 is not particularly limited as long as it is a material that functions as a protective layer in the etching process of the passivation layer 170 and can be appropriately selected depending on the purpose. There is no restriction | limiting in particular as a material of the mask 300, According to the objective, it can select suitably, For example, a positive type photoresist and a negative photoresist are mentioned.

  Next, in the step shown in FIG. 3D, the passivation layer 170 is etched to form a passivation layer 17 having a predetermined shape. The passivation layer 170 containing the first oxide can be etched with a solution containing at least one of hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride. As an etching method, a dipping method in which the passivation layer 170 is immersed in a solution, a spray method in which the solution is sprayed on the passivation layer 170, or a spin method in which the solution is dropped on the passivation layer 170 and the substrate including the passivation layer 170 is rotated. Can be mentioned.

  As a density | concentration of hydrofluoric acid in said solution, 0.1-10 wt% is preferable. The concentration of ammonium fluoride in the above solution is preferably 5 to 25 wt%. The concentration of ammonium hydrogen fluoride in the above solution is preferably 1 to 25 wt%.

  As said solution, the solution of hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride is preferable.

  By etching the passivation layer 170, a part of the source electrode 14, a part of the drain electrode 15, a source wiring, and a drain wiring are exposed from the passivation layer 17. The portion exposed from the passivation layer 17 is in contact with the above-described etching solution, but the surface is oxidized in the prior heat treatment process and has etching resistance, so that it is not dissolved in the etching solution.

  After the step shown in FIG. 3D, the mask 300 is removed. There is no restriction | limiting in particular as a removal method of the mask 300, According to the objective, it can select suitably. For example, when a photoresist is used for the mask 300, the mask 300 can be removed by dissolving the mask 300 with a solution such as a resist stripping solution. Further, as a method for removing the mask 300, it is preferable to select a method that does not damage the passivation layer. Through the above steps, a bottom-gate / bottom-contact field effect transistor 10 can be manufactured.

  As described above, in the manufacturing process of the field effect transistor according to the first embodiment, the process of performing the heat treatment on the source electrode and the drain electrode and the source wiring and the drain wiring is performed before the step of forming the passivation layer. Provided. As a result, oxide films of elements constituting them are formed on the surfaces of the source and drain electrodes and the source and drain wirings.

  As a result, even when the passivation layer containing silicon is used and the source electrode and the drain electrode and the source wiring and the drain wiring are formed using a material that can be dissolved with a hydrofluoric acid-based etching solution, the passivation layer is formed with a hydrofluoric acid-based etching solution. When etching is performed, etching resistance is generated by the oxide film, so that the source electrode and the drain electrode, the source wiring and the drain wiring can be prevented from being dissolved.

<Modification of First Embodiment>
The modification of the first embodiment shows an example of a field effect transistor having a layer structure different from that of the first embodiment. In the modification of the first embodiment, the description of the same components as those of the already described embodiments may be omitted.

  FIG. 4 is a cross-sectional view illustrating a field effect transistor according to a modification of the first embodiment. Each field effect transistor shown in FIG. 4 is a typical example of the semiconductor device according to the present invention.

  A field effect transistor 10A shown in FIG. 4A is a bottom gate / top contact field effect transistor. In the field effect transistor 10 </ b> A, a gate electrode 12 is formed on an insulating substrate 11, and a gate insulating layer 13 is formed so as to cover the gate electrode 12. Further, the semiconductor layer 16 is formed on the gate insulating layer 13, and the source electrode 14 and the drain electrode 15 are formed on the semiconductor layer 16 with a predetermined interval to be a channel region of the semiconductor layer 16.

  A passivation layer 17 that covers at least a part of the source electrode 14, at least a part of the drain electrode 15, and the entire semiconductor layer 16 is formed on the gate insulating layer 13. A source wiring is formed in the same layer as the source electrode 14. A drain wiring is formed in the same layer as the drain electrode 15. However, the source wiring and the drain wiring do not appear in the cross section of FIG.

  The field effect transistor 10 </ b> A shown in FIG. 4A can be manufactured by the same manufacturing process as the field effect transistor 10, although the manufacturing process order is partially different.

  A field effect transistor 10B shown in FIG. 4B is a top gate / bottom contact field effect transistor. In the field effect transistor 10 </ b> B, a source electrode 14 and a drain electrode 15 are formed on an insulating substrate 11, and a semiconductor layer 16 is formed so as to cover a part of the source electrode 14 and the drain electrode 15. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the semiconductor layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. A gate wiring is formed in the same layer as the gate electrode 12. However, the gate wiring does not appear in the cross section of FIG.

  A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the entire gate electrode 12 and a part of the gate wiring. However, a part of the gate electrode 12 may be exposed from the passivation layer 17.

  A field effect transistor 10C shown in FIG. 4C is a top gate / top contact field effect transistor. In the field effect transistor 10 </ b> C, a semiconductor layer 16 is formed on an insulating substrate 11, and a source electrode 14 and a drain electrode 15 are formed on the semiconductor layer 16 at a predetermined interval to be a channel region of the semiconductor layer 16. Is formed. Further, a gate insulating layer 13 is formed so as to cover the source electrode 14, the drain electrode 15, and the semiconductor layer 16, and the gate electrode 12 is formed on the gate insulating layer 13. A gate wiring is formed in the same layer as the gate electrode 12. However, the gate wiring does not appear in the cross section of FIG.

  A passivation layer 17 is formed on the gate insulating layer 13 so as to cover the entire gate electrode 12 and a part of the gate wiring. However, a part of the gate electrode 12 may be exposed from the passivation layer 17.

  The field-effect transistor 10B shown in FIG. 4B and the field-effect transistor 10C shown in FIG. 4C can be manufactured by the same manufacturing process as the field-effect transistor 10 although the order of manufacturing processes is partially different. .

  However, in the heat treatment step performed before the formation of the passivation layer 17, the surfaces of the gate electrode 12 and the gate wiring are oxidized. That is, an oxide film of an element constituting the gate electrode 12 and the gate wiring is formed on the surfaces of the gate electrode 12 and the gate wiring.

  By oxidizing the gate electrode 12 and the gate wiring, when the passivation layer 170 is etched, the gate electrode 12 and the gate wiring are finally exposed from the passivation layer 17 by hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride, which are etchants for the passivation layer 170. It is possible to prevent the gate wiring in the region to be melted. Further, when a part of the gate electrode 12 is finally exposed from the passivation layer 17, it is possible to prevent the gate electrode 12 in a region finally exposed from the passivation layer 17 from being dissolved.

For example, when Al is used for the gate electrode 12 and the gate wiring, the Al surface is oxidized to Al ₂ O ₃ by performing a heat treatment process. Since Al ₂ O ₃ is not dissolved by hydrofluoric acid, ammonium fluoride, or ammonium hydrogen fluoride, the gate electrode 12 and the gate wiring are not dissolved by the etching solution of the passivation layer 170.

  Without the heat treatment step, the gate electrode 12 and the gate wiring in the region finally exposed from the passivation layer 17 are formed by hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride, which are etching solutions for the passivation layer 170. Will dissolve.

  The temperature of the heat treatment step is not particularly limited, and can be appropriately selected depending on the purpose as long as it is a temperature at which the surfaces of the gate electrode 12 and the gate wiring are oxidized, but is preferably 350 ° C. or higher and lower than 500 ° C.

  Note that the thickness of the oxide film formed on the surfaces of the gate electrode 12 and the gate wiring can be controlled by the temperature and / or time and / or atmosphere of the heat treatment step.

  The thickness of the oxide film can prevent the gate electrode 12 and the gate wiring from being dissolved during etching, and the gate wiring is connected to other portions through through holes formed in the interlayer insulating layer or the like. It is controlled within a range where the contact resistance can be maintained at a low value. From such a viewpoint, it is preferable to control the thickness of the oxide film to about several nm.

  As described above, the layer structure of the field effect transistor according to the present invention is not particularly limited, and the structure shown in FIGS. 1 and 4 can be appropriately selected according to the purpose. In the field effect transistors 10 </ b> A, 10 </ b> B, and 10 </ b> C shown in FIG. 4, the passivation layer 17 can be manufactured by the same manufacturing method as the field effect transistor 10. The field effect transistors 10A, 10B, and 10C have the same effect as the field effect transistor 10.

<Second Embodiment>
In the second embodiment, an example of an organic electroluminescence (organic EL) display element will be described. In the second embodiment, description of the same components as those of the already described embodiments may be omitted.

  FIG. 5 is a cross-sectional view for explaining the structure and manufacturing method of the organic EL display element according to the second embodiment.

  An organic EL display element 30 shown in FIG. 5 is a display element in which a drive circuit 320 and an organic EL element 350 are combined, and the drive circuit 320 includes a bottom contact / bottom gate type field effect transistor.

  The drive circuit 320 includes a substrate 31, a first gate electrode 32 and a second gate electrode 33, a gate insulating layer 34, a first source electrode 35 and a second source electrode 36, and a first drain electrode. 37, a second drain electrode 38, a first semiconductor layer 39 and a second semiconductor layer 40, and passivation layers 41 and 42.

  The first drain electrode 37 and the second gate electrode 33 are connected through a through hole formed in the gate insulating layer 34. A drain wiring or a gate wiring may be interposed between the first drain electrode 37 and the second gate electrode 33. The passivation layers 41 and 42 correspond to the passivation layer 17 of the field effect transistor 10 or the like.

  In the case of FIG. 5, a capacitor is formed between the second gate electrode 33 and the second drain electrode 38. However, the location where the capacitor is formed is not limited, and a capacitor having a necessary capacity is appropriately provided. Can be designed and formed.

  A substrate 31, a first gate electrode 32 and a second gate electrode 33, a gate insulating layer 34, a first source electrode 35 and a second source electrode 36, a first drain electrode 37 and a second drain electrode 38, The first semiconductor layer 39, the second semiconductor layer 40, and the passivation layers 41 and 42 can be formed by the materials, processes, and the like described in the description of the field effect transistor 10 according to the first embodiment. .

  The organic EL element 350 includes a second drain electrode 38 that functions as an anode, an organic EL thin film layer 45, and a cathode 46.

  There is no restriction | limiting in particular as a material of the 2nd drain electrode 38 which functions as an anode, According to the objective, it can select suitably, For example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), silver (Ag) ) -Neodymium (Nd) alloy and the like. In addition, when a silver alloy is used, it becomes a high reflectance electrode and is suitable when taking out light from the cathode side.

  The organic EL thin film layer 45 includes an electron transport layer, a light emitting layer, and a hole transport layer. The electron transport layer is connected to the cathode 46, and the hole transport layer is connected to the anode (second drain electrode 38). When a predetermined voltage is applied between the anode (second drain electrode 38) and the cathode 46, the light emitting layer emits light.

  Here, the electron transport layer and the light emitting layer may form one layer, an electron injection layer may be provided between the electron transport layer and the cathode 46, and A hole injection layer may be provided between the anode (second drain electrode 38).

  There is no restriction | limiting in particular as a material of the cathode 46, According to the objective, it can select suitably, For example, aluminum (Al), magnesium (Mg) -silver (Ag) alloy, aluminum (Al) -lithium (Li) An alloy, ITO (Indium Tin Oxide), etc. are mentioned. A magnesium (Mg) -silver (Ag) alloy becomes a high reflectance electrode if it is sufficiently thick, and a semitransparent electrode if it is an extremely thin film (less than about 20 nm). Although light is extracted from the anode side in FIG. 5, light can be extracted from the cathode side by using a transparent or semi-transparent electrode for the cathode.

  There is no restriction | limiting in particular as a preparation method of the organic electroluminescent thin film layer 45 and the cathode 46, According to the objective, it can select suitably, For example, vacuum film-forming methods, such as a vacuum evaporation method and a sputtering method, an inkjet, nozzle coating, etc. Solution process.

  An interlayer insulating layer 43 is provided on the drive circuit 320, and the cathode 46 of the organic EL element 350 extends on the drive circuit 320 through the interlayer insulating layer 43.

  There is no restriction | limiting in particular as a material of the interlayer insulation layer 43 (planarization layer), According to the objective, it can select suitably, For example, an organic material, an inorganic material, an organic inorganic composite material etc. are mentioned.

  Examples of the organic material include polyimide, acrylic resin, fluorine resin, non-fluorine resin, olefin resin, silicone resin, and other photosensitive resins.

  Examples of the inorganic material include SOG (spin on glass) materials such as Aquamica manufactured by AZ Electronic Materials.

  As an organic inorganic composite material, the organic inorganic composite compound etc. which consist of a silane compound currently disclosed by the patent document (Unexamined-Japanese-Patent No. 2007-158146) are mentioned, for example.

  The interlayer insulating layer 43 preferably has a barrier property against moisture, oxygen, and hydrogen in the atmosphere.

  There is no restriction | limiting in particular as a formation process of the interlayer insulation layer 43, According to the objective, it can select suitably, For example, it is desired by spin coating, inkjet printing, slit coating, nozzle printing, gravure printing, dip coating method etc. A method of directly forming the film shape, and a method of patterning by a photolithography method if a photosensitive material is used.

  It is also effective to stabilize the characteristics of the field effect transistor constituting the display element by performing a heat treatment as a post process after the formation of the interlayer insulating layer 43.

  This makes it possible to manufacture so-called “bottom emission” organic EL display elements 30 and 30A that extract light emission from the substrate 31 side. In this case, the substrate 31, the gate insulating layer 34, and the second drain electrode 38 (anode) are required to be transparent.

  However, in FIG. 5, the case of the so-called “bottom emission” organic EL element 350 that extracts light from the substrate 31 side has been described as the light control element, but the light control element extracts light from the side opposite to the substrate 31. The organic EL element of "top emission" may be sufficient.

  In the manufacturing process of the organic EL display element 30, a heat treatment process is performed before the formation of the passivation layers 41 and 42, as in the first embodiment. Therefore, the surface of the source electrode 35 and the drain electrode 37 in the region not covered with the semiconductor layer 39 and the surface of the source wiring and the drain wiring can be oxidized. Similarly, the surfaces of the second source electrode 36 and the second drain electrode 38 in the region not covered with the semiconductor layer 40 and the surfaces of the source wiring and the drain wiring can be oxidized.

  As a result, even when the passivation layer containing silicon is used and the source electrode and the drain electrode and the source wiring and the drain wiring are formed using a material that can be dissolved with a hydrofluoric acid-based etching solution, the passivation layer is formed with a hydrofluoric acid-based etching solution. When etching is performed, etching resistance is generated by the oxide film, so that the source electrode and the drain electrode, the source wiring and the drain wiring can be prevented from being dissolved.

<Modification of Second Embodiment>
In the modification of the second embodiment, an example of an organic EL display element having a layer structure different from that of the second embodiment is shown. In the modification of the second embodiment, the description of the same components as those of the already described embodiments may be omitted.

  In the organic EL display element 30 illustrated in FIG. 5, the configuration in which the organic EL element 350 is disposed beside the drive circuit 320 has been described. However, the organic EL display element 30 </ b> A illustrated in FIG. A configuration in which the EL element 350A is arranged may be employed.

Also in this case, so-called “bottom emission” in which light emission is extracted from the substrate 31 side, and the drive circuit 320 is required to be transparent. The source electrode, the drain electrode, and the anode have conductive conductivity such as ITO, In ₂ O ₃ , SnO ₂ , ZnO, ZnO added with Ga, ZnO added with Al, SnO ₂ added with Sb, or the like. It is preferable to use a simple oxide.

  The organic EL element 350 </ b> A has an anode 44, an organic EL thin film layer 45, and a cathode 46. The anode 44 extends into a through hole 43 x provided in the interlayer insulating layer 43 and is connected to the second drain electrode 38 of the drive circuit 320. The anode 44 may be connected to the drain wiring connected to the second drain electrode 38 through the through hole 43x.

  In the manufacturing process of the organic EL display element 30A, a heat treatment process is performed before the formation of the passivation layers 41 and 42, as in the first embodiment. Therefore, the surface of the source electrode 35 and the drain electrode 37 in the region not covered with the semiconductor layer 39 and the surface of the source wiring and the drain wiring can be oxidized. Similarly, the surfaces of the second source electrode 36 and the second drain electrode 38 in the region not covered with the semiconductor layer 40 and the surfaces of the source wiring and the drain wiring can be oxidized.

  As a result, even when the passivation layer containing silicon is used and the source electrode and the drain electrode and the source wiring and the drain wiring are formed using a material that can be dissolved with a hydrofluoric acid-based etching solution, the passivation layer is formed with a hydrofluoric acid-based etching solution. When etching is performed, etching resistance is generated by the oxide film, so that the source electrode and the drain electrode, the source wiring and the drain wiring can be prevented from being dissolved.

  When a material containing silicon is used for the interlayer insulating layer 43, the interlayer insulating layer 43 is etched with a hydrofluoric acid-based etchant to form a through hole 43x. The surface of the second drain electrode 38 and the drain wiring Is oxidized by the heat treatment, the second drain electrode 38 or the drain wiring exposed at the bottom of the through hole 43x is not dissolved.

  The thickness of the oxide film formed on the surfaces of the second drain electrode 38 and the drain wiring is controlled to about several nm, and the contact resistance is maintained at a low value. Good contact can be made with the drain electrode 38 or the drain wiring.

<Third Embodiment>
In the third embodiment, an example of an image display apparatus and system using the field effect transistor according to the first embodiment will be described. Note that in the third embodiment, description of the same components as those of the already described embodiments may be omitted.

  FIG. 7 shows a schematic configuration of a television apparatus 500 as a system according to the fourth embodiment. In addition, the connection line in FIG. 7 shows the flow of a typical signal and information, and does not represent all the connection relations of each block.

  A television apparatus 500 according to the fourth embodiment includes a main controller 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, and a DA converter (DAC). 512, audio output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, image display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541 A hard disk device 542, an optical disk device 543, an IR light receiver 551, a communication control device 552, and the like.

  The main control device 501 controls the entire television device 500 and includes a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program written in a code readable by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

  The tuner 503 selects a preset channel broadcast from the broadcast waves received by the antenna 610. The ADC 504 converts the output signal (analog information) of the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information from the ADC 504.

  The TS decoder 506 performs TS decoding on the output signal of the demodulation circuit 505 and separates audio information and video information. The audio decoder 511 decodes the audio information from the TS decoder 506. The DA converter (DAC) 512 converts the output signal of the audio decoder 511 into an analog signal.

  The audio output circuit 513 outputs the output signal of the DA converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video / OSD synthesis circuit 522 synthesizes the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

  The video output circuit 523 outputs the output signal of the video / OSD synthesis circuit 522 to the image display device 524. The OSD drawing circuit 525 includes a character generator for displaying characters and figures on the screen of the image display device 524, and a signal including display information in response to an instruction from the operation device 532 or the IR light receiver 551. Generate.

  The memory 531 temporarily stores AV (Audio-Visual) data and the like. The operating device 532 includes an input medium (not shown) such as a control panel, for example, and notifies the main controller 501 of various information input by the user. The drive IF 541 is a bi-directional communication interface, and is compliant with ATAPI (AT Attachment Packet Interface) as an example.

  The hard disk device 542 includes a hard disk and a drive device for driving the hard disk. The drive device records data on the hard disk and reproduces data recorded on the hard disk. The optical disk device 543 records data on an optical disk (for example, DVD) and reproduces data recorded on the optical disk.

  The IR light receiver 551 receives the optical signal from the remote control transmitter 620 and notifies the main controller 501 of it. The communication control device 552 controls communication with the Internet. Various information can be acquired via the Internet.

  The image display device 524 includes a display 700 and a display control device 780 as shown in FIG. 8 as an example. As shown in FIG. 9 as an example, the display 700 includes a display 710 in which a plurality of (here, n × m) display elements 702 are arranged in a matrix.

  Further, as shown in FIG. 10 as an example, the display 710 includes n scanning lines (X0, X1, X2, X3,..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction, in the Y-axis direction M current supply lines (Y0i, Y1i, Y2i, Y3i,..., Ym-1i) arranged at equal intervals along the line. The display element 702 can be specified by the scan line and the data line.

  As shown in FIG. 11 as an example, each display element 702 includes an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a color-compatible 32-inch display. The size is not limited to this.

  As an example, the organic EL element 750 includes an organic EL thin film layer 740, a cathode 712, and an anode 714, as shown in FIG.

The organic EL element 750 can be disposed beside a field effect transistor, for example. In this case, the organic EL element 750 and the field effect transistor can be formed on the same substrate. However, it is not limited to this, For example, the organic EL element 750 may be arrange | positioned on a field effect transistor. In this case, since the gate electrode needs to be transparent, the gate electrode was added with ITO (Indium Tin Oxide), In ₂ O ₃ , SnO ₂ , ZnO, Ga added ZnO, Al. A transparent oxide having conductivity such as SnO ₂ to which ZnO or Sb is added is used.

In the organic EL element 750, Al is used for the cathode 712. Note that an Mg—Ag alloy, an Al—Li alloy, ITO, or the like may be used. ITO is used for the anode 714. Note that a conductive oxide such as In ₂ O ₃ , SnO ₂ , or ZnO, an Ag—Nd alloy, or the like may be used.

  The organic EL thin film layer 740 includes an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. A cathode 712 is connected to the electron transport layer 742, and an anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

  Here, the electron transport layer 742 and the light-emitting layer 744 may form one layer, or an electron injection layer may be provided between the electron transport layer 742 and the cathode 712. A hole injection layer may be provided between the transport layer 746 and the anode 714.

  In FIG. 12, the case of a so-called “bottom emission” organic EL element that extracts light from the substrate side is described as the light control element, but the light control element is “top emission” that extracts light from the side opposite to the substrate. The organic EL element may be used.

  As shown in FIG. 11, the drive circuit 720 includes two field effect transistors 810 and 820 and a capacitor 830. The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to one terminal of the capacitor 830.

  The capacitor 830 is for storing the state of the field effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

  The field effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. The drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

  Therefore, when the field effect transistor 810 is turned on, the organic EL element 750 is driven by the field effect transistor 820.

  As an example, the display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG. The image data processing circuit 782 determines the brightness of the plurality of display elements 702 in the display 710 based on the output signal of the video output circuit 523. The scanning line driving circuit 784 individually applies voltages to the n scanning lines in accordance with an instruction from the image data processing circuit 782. The data line driving circuit 786 individually applies voltages to the m data lines in accordance with an instruction from the image data processing circuit 782.

  As is clear from the above description, in the television apparatus 500 according to the present embodiment, the video decoder 521, the video / OSD synthesis circuit 522, the video output circuit 523, and the OSD drawing circuit 525 constitute an image data creation apparatus. ing.

  In the above description, the light control element is an organic EL element. However, the present invention is not limited to this, and a liquid crystal element, an electrochromic element, an electrophoretic element, or an electrowetting element may be used.

  For example, when the light control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 14, the current supply line in the display element 703 is not necessary.

  In this case, as shown in FIG. 15 as an example, the drive circuit 730 is composed of only one field effect transistor 840 similar to the field effect transistor (810, 820) shown in FIG. Can do. In the field effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Note that reference numerals 762 and 772 in FIG. 15 denote counter electrodes (common electrodes) of the capacitor 760 and the liquid crystal element 770, respectively.

  In the above embodiment, the case where the system is a television apparatus has been described. However, the present invention is not limited to this. In short, the image display device 524 may be provided as a device for displaying images and information. For example, a computer system in which a computer (including a personal computer) and an image display device 524 are connected may be used.

  In addition, an image display device 524 is provided as a display means in a portable information device such as a mobile phone, a portable music playback device, a portable video playback device, an electronic BOOK, a PDA (Personal Digital Assistant), or an imaging device such as a still camera or a video camera. Can be used. Further, the image display device 524 can be used as a display unit for various information in a mobile system such as a car, an aircraft, a train, and a ship. Furthermore, the image display device 524 can be used as a display unit for various information in a measurement device, an analysis device, a medical device, and an advertising medium.

  Examples of the present invention will be described below, but the present invention is not limited to the following examples. “%” Represents “% by mass” unless otherwise specified.

Example 1
<Fabrication of field effect transistor>
−Preparation of passivation layer forming coating solution−
To 1 mL of toluene, 0.16 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and magnesium 2-ethylhexanoate toluene solution (Mg content 3%, Strem 12-1260, manufactured by Strem Chemicals) (0.25 mL) was mixed to obtain a passivation layer forming coating solution. The oxide formed by the passivation layer forming coating solution has the composition shown in Table 1.

  Next, a bottom contact / bottom gate type field effect transistor as shown in FIG. 1 was fabricated.

−ゲート電極の形成−
最初にガラス基材（基板１１）に、ゲート電極１２を形成した。具体的には、ガラス基材上に、ＤＣスパッタリングによりＭｏ（モリブデン）膜を平均膜厚が約１００ｎｍとなるように成膜した。この後、Ｍｏ膜上に、フォトレジストを塗布し、プリベーク、露光装置による露光、及び現像により、形成されるゲート電極１２のパターンと同様のレジストパターンを形成した。更に、エッチングにより、レジストパターンが形成されていない領域のＭｏ膜を除去した。この後、レジストパターンも除去することにより、Ｍｏ膜からなるゲート電極１２を形成した。

-Formation of gate electrode-
First, the gate electrode 12 was formed on the glass substrate (substrate 11). Specifically, a Mo (molybdenum) film was formed on a glass substrate by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mo film, and a resist pattern similar to the pattern of the gate electrode 12 to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mo film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a gate electrode 12 made of a Mo film.

-Formation of gate insulation layer-
Next, a gate insulating layer 13 was formed on the substrate 11 and the gate electrode 12. Specifically, an Al ₂ O ₃ film was formed on the substrate 11 and the gate electrode 12 by RF sputtering so as to have an average film thickness of about 300 nm.

-Formation of source and drain electrodes and source and drain wirings-
Next, the source electrode 14 and the drain electrode 15, and the source wiring and the drain wiring were formed over the gate insulating layer 13. Specifically, a Ti (titanium) film was formed on the substrate 11 by DC sputtering so that the average film thickness was about 100 nm. After that, a photoresist is applied on the Ti film, and a resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring to be formed is formed by pre-baking, exposure by an exposure apparatus, and development. did. Further, the Ti film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a source electrode 14 and a drain electrode 15 made of a Ti film, and a source wiring and a drain wiring.

-Formation of semiconductor layer-
Next, a semiconductor layer 16 made of an oxide was formed. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the formed semiconductor layer 16 was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by etching. Thereafter, the semiconductor layer 16 was formed by removing the resist pattern. As a result, the semiconductor layer 16 was formed so that a channel was formed between the source electrode 14 and the drain electrode 15.

-Heat treatment process-
Next, a heat treatment step was performed to oxidize the source electrode 14 and the drain electrode 15 and the surface of the Ti film which is the source wiring and the drain wiring. Specifically, the surface of the Ti film was oxidized by a heat treatment at 350 ° C. for 1 hour in an air atmosphere.

-Formation of passivation layer-
Next, 0.4 mL of the passivation layer forming coating solution is dropped onto the gate insulating layer 13, the source electrode 14 and the drain electrode 15, the source wiring and the drain wiring, and the semiconductor layer 16 and spin-coated under predetermined conditions (3 The rotation was stopped for 20 seconds at 1,000 rpm, and the rotation was stopped so that it became 0 rpm for 5 seconds). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form an oxide film as the passivation layer 170. The average film thickness of the passivation layer 170 was about 25 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the passivation layer 170, and a resist pattern similar to the pattern of the passivation layer 17 formed by pre-baking, exposure with an exposure apparatus, and development is formed. Formed.

-Etching of passivation layer-
Next, the passivation layer 170 was immersed in 2.5 wt% hydrofluoric acid for 15 seconds, and the oxide film in the region where the resist pattern was not formed was removed by etching to form the passivation layer 17.
-Mask removal-
Thereafter, the resist pattern is also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes to cover part of the source electrode 14, part of the drain electrode 15, and all of the semiconductor layer 16. Thus, a passivation layer 17 was formed. The source wiring and drain wiring are exposed from the passivation layer 17.

(Example 2)
<Fabrication of field effect transistor>
−Preparation of passivation layer forming coating solution−
To 1 mL of toluene, 0.11 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and calcium 2-ethylhexanoate 2-ethylhexanoic acid solution (Ca content) 3% -8%, Alfa36657, manufactured by Alfa Aesar) 0.27 mL and 2-ethylhexanoic acid strontium toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 2.10 mL, A coating solution for forming a passivation layer was obtained. The oxide formed by the passivation layer forming coating solution has the composition shown in Table 1.

  Next, a top contact / bottom gate type field effect transistor as shown in FIG.

-Formation of semiconductor layer-
After forming the gate electrode 12 and the gate insulating layer 13 in the same manner as in Example 1, a semiconductor layer 16 made of an oxide was formed on the gate insulating layer 13. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the formed semiconductor layer 16 was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by etching. Thereafter, the semiconductor layer 16 was formed by removing the resist pattern.

-Formation of source and drain electrodes and source and drain wirings-
Next, the source electrode 14 and the drain electrode 15, and the source wiring and the drain wiring were formed over the gate insulating layer 13. Specifically, an Al (aluminum) film was formed on the substrate 11 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist is coated on the Al film, and a resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 and the source wiring and the drain wiring to be formed is formed by pre-baking, exposure with an exposure apparatus, and development. did. Further, the Al film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a source electrode 14 and a drain electrode 15 made of an Al film, and a source wiring and a drain wiring.

-Heat treatment process-
Next, a heat treatment process was performed to oxidize the surfaces of the source electrode 14 and the drain electrode 15 and the Al film which is the source wiring and the drain wiring. Specifically, the surface of the Al film was oxidized by a heat treatment at 500 ° C. for 1 hour in an air atmosphere.

-Etching of passivation layer-
After forming the passivation layer 170 and the mask in the same manner as in Example 1, the resist pattern was formed by immersing in a mixed solution of 19 wt% ammonium fluoride and 18 wt% ammonium hydrogen fluoride for 15 seconds and etching. The non-existing region of the oxide film was removed, and a passivation layer 17 was formed.

-Mask removal-
Thereafter, the resist pattern is also removed by immersing in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes to cover part of the source electrode 14, part of the drain electrode 15, and all of the semiconductor layer 16. Thus, a passivation layer 17 was formed.

(Example 3)
<Fabrication of field effect transistor>
−Preparation of passivation layer forming coating solution−
1 mL of toluene, 0.12 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.), aluminum di (s-butoxide) acetoacetate chelate (Al content 8) .4%, Alfa 89349, made by Alfa Aesar) 0.11 mL and 2-ethylhexanoate strontium toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 1.58 mL were mixed, and the passivation layer A forming coating solution was obtained. The oxide formed by the passivation layer forming coating solution has the composition shown in Table 1.

  Next, a bottom contact / top gate type field effect transistor as shown in FIG.

-Formation of source and drain electrodes and source and drain wirings-
First, a source electrode 14 and a drain electrode 15 as well as a source wiring and a drain wiring were formed on a glass substrate (substrate 11). Specifically, a Mo (molybdenum) film was formed on the substrate 11 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist is applied on the Mo film, and a resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 and the source wiring and drain wiring to be formed is formed by pre-baking, exposure by an exposure apparatus, and development. did. Further, the Mo film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a source electrode 24 and a drain electrode 25 made of a Mo film, and a source wiring and a drain wiring.
-Formation of semiconductor layer-
Next, a semiconductor layer 16 made of an oxide was formed. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the formed semiconductor layer 16 was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by etching. Thereafter, the semiconductor layer 16 was formed by removing the resist pattern. As a result, the semiconductor layer 16 was formed so that a channel was formed between the source electrode 14 and the drain electrode 15.

-Formation of gate insulation layer-
Next, the gate insulating layer 13 was formed over the source electrode 14, the drain electrode 15, and the semiconductor layer 16. Specifically, an Al ₂ O ₃ film was formed on the source electrode 14, the drain electrode 15, and the semiconductor layer 16 by RF sputtering so that the average film thickness was about 300 nm.

-Formation of gate electrode and gate wiring-
Next, the gate electrode 12 and the gate wiring were formed on the gate insulating layer 13. Specifically, a Ti (titanium) alloy film was formed on the gate electrode so as to have an average film thickness of about 100 nm by DC sputtering. Thereafter, a photoresist was applied on the Ti alloy film, and a resist pattern similar to the pattern of the gate electrode 12 and the gate wiring to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Ti alloy film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a gate electrode 12 and a gate wiring made of a Ti alloy film.

-Heat treatment process-
Next, a heat treatment step was performed to oxidize the surface of the gate electrode 12 and the Ti alloy film as the gate wiring. Specifically, the surface of the Ti alloy film was oxidized by a heat treatment at 400 ° C. for 1 hour in an air atmosphere.

-Formation of passivation layer-
Next, 0.4 mL of a passivation layer forming coating solution was dropped onto the gate insulating layer 13, the gate electrode 12, and the gate wiring, and spin-coated under predetermined conditions (rotated at 3,000 rpm for 20 seconds, and in 5 seconds). The rotation was stopped so that it became 0 rpm). Subsequently, after drying at 120 ° C. for 1 hour in the air, baking was performed at 400 ° C. for 3 hours in an O ₂ atmosphere to form an oxide film as the passivation layer 170. The average film thickness of the passivation layer 170 was about 25 nm.

-Mask formation-
Next, a photoresist (TSMR-8800BE, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the passivation layer 170, and a resist pattern similar to the pattern of the passivation layer 17 formed by pre-baking, exposure with an exposure apparatus, and development is formed. Formed.

-Etching of passivation layer-
Next, it is immersed in a mixed solution of 14 wt% ammonium fluoride and 3.2 wt% ammonium hydrogen fluoride for 1 minute, and the oxide film in the region where the resist pattern is not formed is removed by etching, and a passivation layer is formed. 17 was formed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

Example 4
<Fabrication of field effect transistor>
−Preparation of passivation layer forming coating solution−
1 mL of toluene, 0.11 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.), aluminum di (s-butoxide) acetoacetate chelate (Al content 8) .4%, Alfa 89349, manufactured by Alfa Aesar) 0.10 mL, (4,4,5,5-tetramethyl-1,3,2-dioxaborolan-2-yl) benzene (Wako 325-59912, Wako Corporation) Chemical) 0.07g, 2-ethylhexanoic acid calcium 2-ethylhexanoic acid solution (Ca content 3% -8%, Alfa36657, Alfa Aesar) 0.09mL, 2-ethylhexanoic acid strontium toluene solution (Sr Content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.19 mL Were mixed to obtain a coating solution for forming a passivation layer. The oxide formed by the passivation layer forming coating solution has the composition shown in Table 1.

  Next, a field effect transistor of a top contact / top gate type as shown in FIG.

-Formation of semiconductor layer-
First, the semiconductor layer 16 made of an oxide was formed on the substrate 11. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Mg—In-based oxide film, and a resist pattern similar to the pattern of the formed semiconductor layer 16 was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by etching. Thereafter, the semiconductor layer 16 was formed by removing the resist pattern.

-Formation of source and drain electrodes and source and drain wirings-
Next, the source electrode 14 and the drain electrode 15 were formed on the substrate 11 and the semiconductor layer 16. In addition, source wiring and drain wiring were formed on the substrate 11. Specifically, a Mo (molybdenum) film was formed on the substrate 11 by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist is applied on the Mo film, and a resist pattern similar to the pattern of the source electrode 14 and the drain electrode 15 and the source wiring and drain wiring to be formed is formed by pre-baking, exposure by an exposure apparatus, and development. did. Further, the Al film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a source electrode 14 and a drain electrode 15 made of a Mo film, and a source wiring and a drain wiring.

-Formation of gate electrode and gate wiring-
After forming the gate insulating layer 13 in the same manner as in Example 3, the gate electrode 12 and the gate wiring were formed on the gate insulating layer 13. Specifically, an Al (aluminum) alloy film was formed on the gate electrode by DC sputtering so that the average film thickness was about 100 nm. Thereafter, a photoresist was applied on the Al alloy film, and a resist pattern similar to the pattern of the gate electrode 12 and the gate wiring to be formed was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Al alloy film in the region where the resist pattern was not formed was removed by etching. Thereafter, the resist pattern was also removed to form a gate electrode 12 and a gate wiring made of an Al alloy film.

-Heat treatment process-
Next, a heat treatment step was performed to oxidize the surfaces of the gate electrode 12 and the Al alloy film as the gate wiring. Specifically, the surface of the Al alloy film was oxidized by a heat treatment at 450 ° C. for 1 hour in an air atmosphere.

-Etching of passivation layer-
After forming the passivation layer 170 and the mask in the same manner as in Example 3, it was immersed in a mixed solution of 14 wt% ammonium fluoride and 3.2 wt% ammonium hydrogen fluoride for 1 minute, and a resist pattern was formed by etching. The oxide film in the region that was not formed was removed, and a passivation layer 17 was formed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

(Comparative Example 1)
<Fabrication of field effect transistor>
−Preparation of passivation layer forming coating solution−
To 1 mL of toluene, 0.17 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and strontium 2-ethylhexanoate toluene solution (Sr content 2%, Wako) 195-09561 (manufactured by Wako Chemical Co., Ltd.) (0.95 mL) was mixed to obtain a passivation layer forming coating solution. The oxide formed by the passivation layer forming coating solution has the composition shown in Table 1.

  Next, a bottom contact / bottom gate type field effect transistor as shown in FIG. 1 was fabricated.

-Etching of passivation layer-
Except that the heat treatment process was not performed, the same process as in Example 1 was performed to form the passivation layer 170. Then, the passivation layer 170 was immersed in 2.5 wt% hydrofluoric acid for 15 seconds, and etched. The passivation film 17 was formed by removing the oxide film in the region where the resist pattern was not formed. At this time, due to the etching of the passivation layer 170, the source electrode 14 and the drain electrode 15 that were finally exposed from the passivation layer 17 and the dissolution of the Ti film as the source wiring and the drain wiring were observed.
-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

(Comparative Example 2)
<Fabrication of field effect transistor>
−Preparation of passivation layer forming coating solution−
1 mL of toluene, 0.12 mL of HMDS (1,1,1,3,3,3-hexamethyldisilazane, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and (4,4,5,5-tetramethyl-1,3 , 2-dioxaborolan-2-yl) benzene (Wako 325-59912, manufactured by Wako Chemical Co., Ltd.) 0.07 g, calcium 2-ethylhexanoate 2-ethylhexanoic acid solution (Ca content 3% -8%, Alfa 36657, Alfa Aesar (0.30 mL) was mixed to obtain a passivation layer forming coating solution. The oxide formed by the passivation layer forming coating solution has the composition shown in Table 1.

  Next, a field effect transistor of a top contact / top gate type as shown in FIG.

-Etching of passivation layer-
Except that the heat treatment process was not performed, the same process as in Example 4 was performed to form the passivation layer 170, and then the passivation layer 170 was mixed with 14 wt% ammonium fluoride and 12 wt% ammonium hydrogen fluoride. Then, the oxide film in the region where the resist pattern was not formed was removed by etching, and a passivation layer 17 was formed. At this time, due to the etching of the passivation layer 170, dissolution of the Al film as the gate electrode 12 and the gate wiring finally exposed from the passivation layer 17 was observed.

-Mask removal-
Thereafter, the resist pattern was also removed by immersion in a stripping solution (stripping solution 104 manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes.

<Evaluation of transistor characteristics of field effect transistor>
The transistor characteristics of the field effect transistors fabricated in Examples 1 to 4 and Comparative Examples 1 and 2 were evaluated. The transistor characteristics of Examples 1 to 4 and Comparative Examples 1 and 2 are as follows: the voltage (Vgs) between the gate electrode 12 and the source electrode 14 and the drain when the voltage (Vds) between the drain electrode 15 and the source electrode 14 is + 10V. The relationship (Vgs-Ids) with the current (Ids) between the electrode 15 and the source electrode 14 was measured.

  Further, the field effect mobility in the saturation region was calculated from the evaluation result of the transistor characteristics (Vgs−Ids). Further, the ratio (on / off ratio, on / off ratio) of Ids between the on state (for example, Vgs = + 10 V) and the off state (for example, Vgs = −10 V) of the transistor was calculated. Further, the S value was calculated as an index of the sharpness of the rise of Ids with respect to the Vgs application. Further, the threshold voltage (Vth) was calculated as the voltage value of the rise of Ids with respect to the Vgs application.

Table 2 shows the mobility, on / off ratio, S value, and Vth calculated from the transistor characteristics of the field effect transistors manufactured in Examples 1 to 4 and Comparative Examples 1 and 2. In the following, excellent transistor characteristics are expressed in the results of transistor characteristics that the mobility is high, the on / off ratio is high, the S value is low, and Vth is around 0V. Specifically, the transistor characteristics are excellent in that the mobility is 3 cm ² / Vs or more, the on / off ratio is 1.0 × 10 ⁸ or more, the S value is 0.7 or less, and Vth is within ± 10 V. It expresses.

  According to Table 2, the field effect transistors manufactured in Examples 1 to 4 have high mobility, high on / off ratio, low S value, Vth is around 0 V, and exhibit excellent transistor characteristics. Recognize. On the other hand, in the field effect transistor manufactured in Comparative Example 1, the source and drain electrodes, the source wiring and the drain wiring were dissolved during etching of the passivation layer, and the transistor characteristics could not be measured.

  In the field effect transistor fabricated in Comparative Example 2, the gate electrode and the gate wiring were dissolved during the etching of the passivation layer, and the transistor characteristics could not be measured.

以上、好ましい実施の形態等について詳説したが、上述した実施の形態等に制限されることはなく、特許請求の範囲に記載された範囲を逸脱することなく、上述した実施の形態等に種々の変形及び置換を加えることができる。

The preferred embodiments and the like have been described in detail above, but the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope described in the claims. Variations and substitutions can be added.

10, 10A to 10C Field effect transistor 11 Substrate 12 Gate electrode 13 Gate insulating layer 14 Source electrode 15 Drain electrode 16 Semiconductor layer 17, 41, 42 Passivation layer

JP 2014-107527 A

Claims (19)

A source electrode, a drain electrode, and a gate electrode;
A wiring connected to the source electrode, a wiring connected to the drain electrode, and a wiring connected to the gate electrode;
A method of manufacturing a field effect transistor comprising: one of the source electrode, the drain electrode, and the gate electrode; and a passivation layer that covers at least part of a wiring connected to the one electrode. ,
Forming a wiring connected to the one electrode and the one electrode with a first material dissolved in a solution containing at least one of hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride;
Heat treating the one electrode and the wiring connected to the one electrode;
After the step of performing the heat treatment, a step of forming a passivation layer that covers the one electrode and the wiring connected to the one electrode with a second material dissolved in the solution;
Etching the passivation layer by bringing it into contact with the solution, and exposing a part of the one electrode and / or at least a part of the wiring connected to the one electrode from the passivation layer. A method for manufacturing a field effect transistor, which is characterized.   2. The method of manufacturing a field effect transistor according to claim 1, wherein the passivation layer is an oxide containing Si and alkaline earth.   3. The method of manufacturing a field effect transistor according to claim 2, wherein the oxide contains at least one of Al and B.   4. The method of manufacturing a field effect transistor according to claim 1, wherein the one electrode contains at least one of Ti, Al, a Ti alloy, and an Al alloy. 5.   5. The method of manufacturing a field effect transistor according to claim 4, wherein a temperature of the heat treatment is 350 ° C. or higher. A semiconductor layer formed between at least the source electrode and the drain electrode and in contact with the source electrode and the drain electrode;
The field effect transistor manufacturing method according to claim 1, wherein the semiconductor layer is an oxide semiconductor. A method for manufacturing a display element, comprising: forming a drive circuit including a field effect transistor; and forming a light control element whose light output is controlled according to a drive signal from the drive circuit,
The method for manufacturing a display element, wherein the step of forming the drive circuit includes each step in the method for manufacturing a field effect transistor according to claim 1.   The method for manufacturing a display element according to claim 7, wherein the light control element is an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoretic element, or an electrowetting element. A method for manufacturing a display device, comprising: a display device in which a plurality of display elements are arranged; and a display control device that individually controls each of the display elements, wherein the step of forming the display elements comprises: Each method in the manufacturing method of the display element of description is included, The manufacturing method of the display apparatus characterized by the above-mentioned. A method for manufacturing a system comprising: a display device; and an image data creation device that supplies image data to the display device, wherein the step of forming the display device comprises: The manufacturing method of the system characterized by including a process. A source electrode, a drain electrode, and a gate electrode;
A wiring connected to the source electrode, a wiring connected to the drain electrode, and a wiring connected to the gate electrode;
And a passivation layer that covers all or a part of one of the source electrode, the drain electrode, and the gate electrode, and exposes at least a part of the wiring connected to the one electrode. Type transistor,
The one electrode and the wiring connected to the one electrode are formed of a first material that is dissolved in a solution containing at least one of hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride.
The passivation layer is formed of a second material that dissolves in a solution containing at least one of hydrofluoric acid, ammonium fluoride, and ammonium hydrogen fluoride.
An oxide film of an element constituting the one electrode and the wiring connected to the one electrode is formed on a surface of the region exposed from the passivation layer of the wiring connected to the one electrode and the one electrode. A field effect transistor.   The field effect transistor according to claim 11, wherein the passivation layer contains an oxide containing Si and an alkaline earth metal.   The field effect transistor according to claim 12, wherein the oxide contains at least one of Al and B.   The field effect transistor according to claim 11, wherein the one electrode contains at least one of Ti, Al, a Ti alloy, and an Al alloy. A semiconductor layer formed between at least the source electrode and the drain electrode and in contact with the source electrode and the drain electrode;
The field effect transistor according to claim 11, wherein the semiconductor layer is an oxide semiconductor. A drive circuit;
A light control element whose light output is controlled according to a drive signal from the drive circuit,
The display device that drives the light control element by the field effect transistor according to claim 11.   The display element according to claim 16, wherein the light control element is an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoretic element, or an electrowetting element. A display device comprising a plurality of display elements according to claim 16 or 17,
A display control device for individually controlling each of the display elements. A display device according to claim 18,
An image data creation device for supplying image data to the display device.

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