JP2018032030A - Semiconductor device, display device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can perform display with excellent visibility.SOLUTION: A semiconductor device controls a display device, and supplies the display device with image data. The semiconductor device has a controller, a frame memory, a register, an image processing unit, and a sensor controller. The image processing unit captures the image data from the frame memory and captures parameters from the register, and uses the parameters to process the image data. The sensor controller is connected to a photosensor, and on the basis of obtained information, the semiconductor device controls the brightness and color tone of the display device. The frame memory holds the image data with power supply interrupted. The register holds the parameters with power supply interrupted.SELECTED DRAWING: Figure 3

Description

One embodiment of the present invention relates to a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Therefore, more specifically, as a technical field of one embodiment of the present invention disclosed in this specification and the like, a semiconductor device, a display device, an electronic device, a driving method thereof, or a manufacturing method thereof can be given as an example. it can. Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

As a display device using a light emitting element, an organic EL (Electro Luminescence) display is known. The basic structure of an organic EL element is that a layer containing a light-emitting organic compound is sandwiched between a pair of electrodes, and light is obtained from the light-emitting organic compound by applying a voltage to this element. Can do.

The organic EL display is known to be an active type having a transistor in each pixel and a passive type having no transistor in each pixel. An oxide semiconductor is used for a transistor in each pixel in the active type. A technique for applying a conventional transistor has been proposed.

Since a transistor using an oxide semiconductor has a very small off-state current, when applied to a pixel of a liquid crystal display or an organic EL display, a refresh frequency when displaying a still image can be reduced and power consumption can be reduced. (Patent Document 1, Patent Document 2). In the present specification, the technique for reducing the power consumption of the above-described display device is referred to as “idling stop” or “IDS driving”.

In addition, an example in which a transistor including an oxide semiconductor is used for a nonvolatile memory device by utilizing a small off-state current is disclosed (Patent Document 3).

JP 2011-141522 A JP 2011-141524 A JP 2011-151383 A

The organic EL display has good display quality with high contrast and excellent visibility at indoor brightness where no external light is inserted. However, in an environment where there is external light, such as outdoors on a sunny day, it is difficult to say that it has sufficient visibility because it loses external light. An object of one embodiment of the present invention is to provide a display device that has sufficient visibility even in an environment where external light exists.

In addition, since the semiconductor device does not need to send image data or signals to the display device while the display device is performing IDS driving, power supply to related circuits can be cut off. An object is to provide a semiconductor device that has low power consumption and has a mechanism that does not affect display quality even when power supply to some circuits is cut off.

An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object is to provide a novel semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a display device including a novel semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device using a display device including a novel semiconductor device.

Note that one embodiment of the present invention is not necessarily required to solve all of the above problems, and may be any form that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will become apparent from the description of the specification, claims, drawings, etc., and other issues may be extracted from the description of the specification, claims, drawings, etc. Is possible.

One embodiment of the present invention is a semiconductor device including a display unit, a first controller, a second controller, a frame memory, a register, an image processing unit, and a sensor. The frame memory has a function of storing image data, the image processing unit has a function of processing image data, and the register has a function of storing parameters for the image processing unit to perform processing. The frame memory has a function of holding image data in a state where power supply to the frame memory is interrupted. The register has a function of holding parameters in a state where power supply to the register is interrupted. The first controller has a function of controlling power supply to the frame memory, the register, and the image processing unit. The second controller has a function of receiving a first signal from the sensor and a function of generating a second signal for the image processing unit to perform processing based on the first signal. The second signal has a predetermined threshold value, and when the second signal does not exceed the threshold value, the image processing unit has a function of displaying the display unit at the first luminance, When the two signals exceed the threshold value, the image processing unit has a function of displaying the display unit with the second luminance.

Moreover, in the said form, a sensor is an optical sensor, It is characterized by the above-mentioned.

In the above embodiment, the first brightness can be selected by the user from a predetermined range, and the second brightness cannot be selected by the user.

Moreover, in the said form, when the 2nd signal exceeds a threshold value, when the predetermined time limit passes, the function to display a display unit with 2nd brightness | luminance has a function which becomes invalid.

Another embodiment of the present invention is a semiconductor device including the source driver in the above embodiment. The source driver has a function of generating a data signal based on the image data processed by the image processing unit, and the display unit includes a light emitting element. The data signal has a function of driving the light emitting element.

In the above embodiment, the light-emitting element is an organic EL element.

Another embodiment of the present invention is a semiconductor device including the source driver in the above embodiment. The source driver has a function of generating a first data signal and a second data signal based on the image data processed by the image processing unit, and the display unit includes a reflective element and a light emitting element. The first data signal has a function of driving the reflective element, and the second data signal has a function of driving the light emitting element.

In the above embodiment, the reflective element is a liquid crystal element and the light emitting element is an organic EL element.

In the above embodiment, the frame memory and the register each include a transistor including a metal oxide in a channel formation region.

One embodiment of the present invention can provide a novel semiconductor device. Alternatively, a novel semiconductor device with low power consumption can be provided.

Alternatively, according to one embodiment of the present invention, a display device including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device using a display device including a novel semiconductor device can be provided.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the above effects and other effects. Accordingly, one embodiment of the present invention may not have the above-described effects depending on circumstances.

FIG. 6 illustrates a configuration example of a display device. The figure which shows the structural example of a touch sensor unit. The block diagram which shows the structural example of controller IC. The figure explaining a parameter. The figure which shows the structural example of a frame memory. FIG. 3 is a block diagram illustrating a configuration example of a register. FIG. 6 is a circuit diagram illustrating a configuration example of a register. The block diagram which shows the structural example of controller IC. FIG. 3 is a block diagram illustrating a configuration example of a register. FIG. 6 is a circuit diagram illustrating a configuration example of a register. 6 is a timing chart showing an example of register operation. The block diagram which shows the structural example of controller IC. The figure which shows the structural example of a hierarchical neural network, and the circuit structure used for a calculation process. The schematic diagram of an error back propagation system, and the figure which shows the circuit structure used for a calculation process. The figure which shows the structural example of a product-sum operation processing circuit. FIG. 6 illustrates a structure of a memory circuit and a reference memory circuit. The figure which shows the circuit structure and connection relation of a memory cell. The figure which shows the structure of the circuit 13, the circuit 14, and a current source circuit. Timing chart. FIG. 7 is a circuit diagram illustrating a configuration example of a pixel and a timing chart illustrating an operation example. FIG. 6 is a circuit diagram illustrating a configuration example of a pixel. Sectional drawing which shows the structural example of a display apparatus. The block diagram which shows the structural example of a display unit. The block diagram which shows the structural example of controller IC. The block diagram which shows the structural example of a display unit. FIG. 6 is a circuit diagram illustrating a configuration example of a pixel. FIG. 6 is a top view illustrating a structure example of a display unit and pixels. Sectional drawing which shows the structural example of a display unit. Sectional drawing which shows the structural example of a display unit. The schematic diagram explaining the shape of a reflecting film. The perspective view which shows the example of an electronic device.

Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms, and that the forms and details can be variously changed without departing from the spirit and scope thereof. The Therefore, the present invention should not be construed as being limited to the description of the following embodiments. In addition, a plurality of embodiments shown below can be combined as appropriate.

Note that the controller IC described in the embodiment is a semiconductor device including a transistor including silicon in a channel formation region, a transistor including an oxide semiconductor in a channel formation region, a capacitor, and the like. Therefore, the controller IC can be rephrased as a semiconductor device.

In the drawings and the like, the size, the thickness of layers, regions, and the like are sometimes exaggerated for clarity. Therefore, it is not necessarily limited to the scale. The drawing schematically shows an ideal example, and is not limited to the shape or value shown in the drawing.

In the drawings and the like, the same element, an element having a similar function, an element of the same material, or an element formed at the same time may be denoted by the same reference numeral, and repeated description thereof may be omitted. is there.

In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

Further, in this specification and the like, terms indicating the arrangement such as “upper” and “lower” do not limit that the positional relationship between the constituent elements is “directly above” or “directly below”. For example, the expression “a gate electrode over a gate insulating layer” does not exclude the case where another component is included between the gate insulating layer and the gate electrode.

Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

Further, in this specification and the like, ordinal numbers such as “first”, “second”, and “third” are given in order to avoid confusion between components, and are not limited numerically.

Further, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes a switching element such as a transistor, a resistance element, an inductor, a capacitance element, and other elements having various functions, as well as electrodes and wirings.

In this specification and the like, the “voltage” often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential). Thus, voltage, potential, and potential difference can be referred to as potential, voltage, and voltage difference, respectively.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. In addition, a channel region is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and between the source and drain through the channel region. It is possible to pass a current through. Note that in this specification and the like, a channel region refers to a region through which a current mainly flows.

In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the gate voltage Vgs relative to the source is lower than the threshold voltage Vth in the n-channel transistor, and the gate voltage Vgs relative to the source in the p-channel transistor is the threshold unless otherwise specified. A state higher than the voltage Vth. In other words, the off-state current of an n-channel transistor may be the drain current when the gate voltage Vgs relative to the source is lower than the threshold voltage Vth.

In the description of the off-state current, the drain may be read as the source. That is, the off-state current may refer to a current that flows through the source when the transistor is off.

In this specification and the like, the term “leakage current” may be used in the same meaning as off-state current. In this specification and the like, off-state current sometimes refers to current that flows between a source and a drain when a transistor is off.

In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. In addition, in the case of describing an OS transistor or an OS FET, it can be said to be a transistor including a metal oxide or an oxide semiconductor.

(Embodiment 1)
In this embodiment, a display device in which each pixel includes a transistor and a light-emitting element will be described. In particular, the controller IC of the display device will be described.

<< Display device >>
FIG. 1 is a diagram illustrating a configuration example of a display device. The display device 100 includes a display unit 110 and a touch sensor unit 120.

<Display unit>
The display unit 110 includes a pixel array 111, a gate driver 113, and a controller IC 115. The pixel array 111 includes a plurality of pixels 10, and each pixel 10 is an active element that is driven using a transistor. A more specific configuration example of the display unit 110 will be described in Embodiment 5.

As a display element used for the display unit 110, a light emitting element is preferably used. For example, a self-luminous light-emitting element such as an organic EL (Electro Luminescence) element, an inorganic EL element, a QLED (Quantum-dot Light Emitting Diode), or a light-emitting diode can be used as the light-emitting element.

The gate driver 113 has a function of driving a gate line for selecting the pixel 10. A source driver that drives a source line that supplies a data signal to the pixel 10 is provided in the controller IC 115. The controller IC 115 has a function of comprehensively controlling the operation of the display device 100. The number of controller ICs 115 is determined according to the number of pixels in the pixel array.

In the example of FIG. 1, an example in which the gate driver 113 is integrated with the pixel array 111 on the same substrate is shown, but the gate driver 113 may be a dedicated IC. Alternatively, the gate driver 113 may be incorporated in the controller IC 115.

Here, the mounting method of the controller IC 115 is a COG (Chip on Glass) method, but the mounting method is not particularly limited, and may be a COF (Chip on Flexible) method, a TAB (Tape Automated Bonding) method, or the like. The same applies to the IC mounting method of the touch sensor unit 120.

Note that the transistor used in the pixel 10 is an OS transistor, and has a lower off-current than a Si transistor.

The OS transistor preferably includes a metal oxide in a channel formation region. The metal oxide applied to the OS transistor is preferably an oxide containing at least one of indium (In) and zinc (Zn).

As such an oxide, an In-M-Zn oxide, an In-M oxide, a Zn-M oxide, an In-Zn oxide (the element M is, for example, aluminum (Al), gallium (Ga), Yttrium (Y), tin (Sn), boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), Typical examples include lanthanum (La), cerium (Ce), neodymium (Nd), vanadium (V), beryllium (Be), hafnium (Hf), tantalum (Ta), and tungsten (W). The OS transistor can reduce an off-current per channel width of 1 μm to 1 yA / μm (y; 10 ⁻²⁴ ) or more and 1 zA / μm (z; zept, 10 ⁻²¹ ) or less.

In addition, it is preferable to use a CAC (Cloud-Aligned Composite) -OS for the OS transistor. Note that details of the CAC-OS will be described in an eighth embodiment to be described later.

Alternatively, as a transistor used for the pixel 10, an OS transistor can be omitted if the off-state current is low. For example, a transistor including a semiconductor with a wide band gap may be used. A semiconductor having a large band gap may refer to a semiconductor having a band gap of 2.2 eV or more. For example, silicon carbide, gallium nitride, diamond, and the like can be given.

By using a transistor with low off-state current for the pixel 10, the gate driver 113 and the source driver can be temporarily stopped when the display screen does not need to be rewritten (that is, when a still image is displayed) (described above). , “Idling stop” or “IDS drive”). The power consumption of the display device 100 can be reduced by the IDS driving.

<Touch sensor unit>
A touch sensor unit 120 illustrated in FIG. 1 includes a sensor array 121 and a peripheral circuit 125. The peripheral circuit 125 includes a touch sensor driver (hereinafter referred to as “TS driver”) 126 and a sense circuit 127. The peripheral circuit 125 can be configured by a dedicated IC.

FIG. 2 shows a configuration example of the touch sensor unit 120. Here, an example in which the touch sensor unit 120 is a mutual capacitance touch sensor unit is shown. The sensor array 121 has m (m is an integer of 1 or more) wirings DRL and n (n is an integer of 1 or more) wirings SNL. The wiring DRL is a drive line, and the wiring SNL is a sense line. Here, the αth (α is an integer from 1 to m) number wiring DRL is referred to as a wiring DRL <α>, and the βth (β is an integer from 1 to n) wiring SNL is the wiring SNL <β>. I will call it. The capacitance CT _αβ is a capacitance formed between the wiring DRL <α> and the wiring SNL <β>.

The m wirings DRL are electrically connected to the TS driver 126. The TS driver 126 has a function of driving the wiring DRL. The n wirings SNL are electrically connected to the sense circuit 127. The sense circuit 127 has a function of detecting a signal of the wiring SNL. The signal of the wiring SNL <β> when the wiring DRL <α> is driven by the TS driver 126 has information on the amount of change in the capacitance value of the capacitor CT _αβ . By analyzing the signals of the n wirings SNL, information such as the presence / absence of touch and the touch position can be obtained.

<< Controller IC >>
FIG. 3 is a block diagram illustrating a configuration example of the controller IC 115. The controller IC 115 includes an interface 150, a frame memory 151, a decoder 152, a sensor controller 153, a controller 154, a clock generation circuit 155, an image processing unit 160, a memory 170, a timing controller 173, a register 175, a source driver 180, and a touch sensor controller 184. Have

Communication between the controller IC 115 and the host 140 is performed via the interface 150. From the host 140, image data, various control signals, and the like are sent to the controller IC 115. Further, the controller IC 115 sends information such as the touch position acquired by the touch sensor controller 184 to the host 140. Each circuit included in the controller IC 115 is appropriately discarded depending on the standard of the host 140, the specification of the display device 100, and the like.

The frame memory 151 is a memory for storing image data input to the controller IC 115. When compressed image data is sent from the host 140, the frame memory 151 can store the compressed image data. The decoder 152 is a circuit for decompressing the compressed image data. When it is not necessary to decompress the image data, the decoder 152 does not perform processing. Alternatively, the decoder 152 can be arranged between the frame memory 151 and the interface 150.

The image processing unit 160 has a function of performing various image processing on image data. For example, the image processing unit 160 includes a gamma correction circuit 161, a light adjustment circuit 162, a color adjustment circuit 163, and an EL correction circuit 164.

The EL correction circuit 164 is provided when the source driver 180 includes a current detection circuit that detects a current flowing through the pixel 10. The EL correction circuit 164 has a function of adjusting the luminance of the pixel 10 based on a signal transmitted from the current detection circuit of the source driver 180.

The image data processed by the image processing unit 160 is output to the source driver 180 via the memory 170. The memory 170 is a memory for temporarily storing image data. The source driver 180 has a function of processing input image data and writing it to the source line of the pixel array 111.

The timing controller 173 has a function of generating timing signals used by the source driver 180, the touch sensor controller 184, and the gate driver 113 of the display unit 110.

The touch sensor controller 184 has a function of controlling the TS driver 126 and the sense circuit 127 of the touch sensor unit 120. A signal including touch information read by the sense circuit 127 is processed by the touch sensor controller 184 and sent to the host 140 via the interface 150. The host 140 generates image data reflecting the touch information and sends it to the controller IC 115. The controller IC 115 may be configured to reflect touch information on the image data.

The clock generation circuit 155 has a function of generating a clock signal used by the controller IC 115. The controller 154 has a function of processing various control signals sent from the host 140 via the interface 150 and controlling various circuits in the controller IC 115. The controller 154 has a function of controlling power supply to various circuits in the controller IC 115. Hereinafter, temporarily shutting off power supply to an unused circuit is referred to as power gating. In FIG. 3, the power supply line is omitted.

The register 175 stores data used for the operation of the controller IC 115. The data stored in the register 175 includes parameters used by the image processing unit 160 to perform correction processing, parameters used by the timing controller 173 to generate waveforms of various timing signals, and the like. The register 175 includes a scan chain register including a plurality of registers.

An optical sensor 143 is electrically connected to the sensor controller 153. The optical sensor 143 detects the light 145 and generates a detection signal. The sensor controller 153 generates a control signal based on the detection signal. The control signal generated by the sensor controller 153 is output to the controller 154, for example.

The image processing unit 160 can adjust the luminance of the pixel 10 according to the brightness of the light 145 measured using the optical sensor 143 and the sensor controller 153. That is, in an environment where the brightness of the light 145 is dark, by reducing the brightness of the pixel 10, glare can be reduced and power consumption can be reduced. Further, in an environment where the brightness of the light 145 is bright, the display quality with excellent visibility can be obtained by increasing the luminance of the pixel 10. These adjustments may be performed around the brightness set by the user. Here, the adjustment is referred to as dimming or dimming processing. A circuit that executes the processing is called a dimming circuit.

Note that, in an environment where there is external light, such as outdoors, the image processing unit 160 can set the luminance of the display unit 110 to a particularly bright luminance. The particularly bright luminance is the highest luminance that can be displayed by the display unit 110, and can be a luminance that cannot be selected by the user of the display device 100, for example.

For example, when a threshold value is determined for the brightness of the light 145 measured using the optical sensor 143 and the sensor controller 153 and the threshold value is not exceeded, the image processing unit 160 sets the brightness of the display unit 110 to the first luminance. When the threshold value is exceeded, the image processing unit 160 can set the luminance of the display unit 110 to the second luminance. Here, the first luminance is a luminance having a range that can be selected by the user of the display device 100 according to preference, and the second luminance is a luminance that cannot be selected by the user of the display device 100. is there. Although it depends on the performance that can be displayed by the display unit 110, the first luminance can be, for example, 10 cd / m 2 or more and 500 cd / m 2 or less. When the first luminance is in the above range, the second luminance may be a numerical value exceeding the first luminance. Specifically, the luminance may exceed 500 cd / m 2, for example, 1,000 cd / m 2 or more and 100,000 cd / m 2 or less.

In the case of performing display with the second luminance, since the pixel 10 may be deteriorated or generate heat, a time limit may be provided. When the brightness of the light 145 measured using the optical sensor 143 and the sensor controller 153 exceeds the threshold value, visibility can be ensured by temporarily setting the brightness to be particularly bright. In other words, when the brightness of the light 145 measured using the optical sensor 143 and the sensor controller 153 exceeds the threshold value, the second brightness is higher than the first brightness, and thus visibility is ensured. Can do.

Further, a function for measuring the color tone of the light 145 can be added to the optical sensor 143 and the sensor controller 153 to correct the color tone. For example, in a reddish environment at dusk, the user's eyes of the display device 100 perform color adaptation and feel the reddish color as white. In this case, since the display on the display device 100 looks pale, the color tone can be corrected by enhancing the R (red) component of the display device 100. Here, the correction is referred to as toning or toning processing. A circuit that executes the processing is called a toning circuit.

The image processing unit 160 may have other processing circuits such as an RGB-RGBW conversion circuit depending on the specifications of the display device 100. The RGB-RGBW conversion circuit is a circuit having a function of converting RGB (red, green, blue) image data into RGBW (red, green, blue, white) image data. That is, when the display device 100 has RGBW four color pixels, the power consumption can be reduced by displaying the W (white) component in the image data using the W (white) pixel. The RGB-RGBW conversion circuit is not limited to this, and may be, for example, an RGB-RGBY (red, green, blue, yellow) conversion circuit.

<Parameter>
Image correction processing such as gamma correction, light adjustment, and color adjustment corresponds to processing for creating output correction data Y for input image data X. The parameters used by the image processing unit 160 are parameters for converting the image data X into correction data Y.

The parameter setting method includes a table method and a function approximation method. The table system shown in FIG. 4 (A), the image data X _n, are stored in a table of correction data Y _n as a parameter. The table method requires a large number of registers for storing parameters corresponding to the table, but has a high degree of freedom in correction. On the other hand, when the correction data Y for the image data X can be determined empirically in advance, a configuration employing a function approximation method as shown in FIG. 4B is effective. a1, a2, b2, etc. are parameters. Here, a method of linear approximation for each section is shown, but a method of approximation with a nonlinear function is also possible. In the function approximation method, the degree of freedom of correction is low, but the number of registers for storing parameters defining the function is small.

The parameter used by the timing controller 173 indicates, for example, the timing at which the generated signal of the timing controller 173 becomes “L” (or “H”) with respect to the reference signal, as shown in FIG. is there. The parameter Ra (or Rb) indicates how many clock cycles the timing of “L” (or “H”) with respect to the reference signal is.

The above parameters for correction can be stored in the register 175. In addition to the above, other parameters that can be stored in the register 175 include the data of the EL correction circuit 164, the brightness, color tone, and energy saving setting of the display device 100 set by the user (time until the display is darkened or the display is turned off ) And the sensitivity of the touch sensor controller 184.

<Power gating>
When there is no change in the image data sent from the host 140, the controller 154 can perform power gating on some circuits in the controller IC 115. Specifically, for example, it indicates a circuit (frame memory 151, decoder 152, image processing unit 160, memory 170, timing controller 173, register 175, source driver 180) in the area 190. A configuration is possible in which a control signal indicating that there is no change in image data is transmitted from the host 140 to the controller IC 115 and power gating is performed when the controller 154 detects the control signal.

Since the circuit in the area 190 is a circuit related to image data and a circuit for driving the display unit 110, the circuit in the area 190 can be temporarily stopped when there is no change in the image data. Note that even when there is no change in the image data, a time during which the transistor used in the pixel 10 can hold the data (a time during which IDS driving is possible) may be considered. For example, by incorporating a timer function in the controller 154, the timing for restarting the power supply to the circuits in the region 190 may be determined based on the time measured by the timer.

Hereinafter, specific circuit configurations of the frame memory 151 and the register 175 will be described. Note that the circuits in the region 190, the sensor controller 153, the touch sensor controller 184, and the like described as circuits that can perform power gating are not limited to this. Various combinations are conceivable depending on the configuration of the controller IC 115, the standard of the host 140, the specifications of the display device 100, and the like.

<Frame memory 151>
FIG. 5A shows a configuration example of the frame memory 151. The frame memory 151 includes a control unit 202, a cell array 203, and a peripheral circuit 208. The peripheral circuit 208 includes a sense amplifier circuit 204, a driver 205, a main amplifier 206, and an input / output circuit 207.

The control unit 202 has a function of controlling the frame memory 151. For example, the control unit 202 controls the driver 205, the main amplifier 206, and the input / output circuit 207.

A plurality of wirings WL and CSEL are electrically connected to the driver 205. The driver 205 generates signals to be output to the plurality of wirings WL and CSEL.

The cell array 203 includes a plurality of memory cells 209. The memory cell 209 is electrically connected to wirings WL, LBL (or LBLB), and BGL. The wiring WL is a word line, and the wirings LBL and LBLB are local bit lines. In the example of FIG. 5A, the structure of the cell array 203 is a folded bit line method, but may be an open bit line method.

FIG. 5B illustrates a configuration example of the memory cell 209. The memory cell 209 includes a transistor NW1 and a capacitor element CS1. The memory cell 209 has a circuit configuration similar to that of a DRAM (dynamic random access memory) memory cell. Here, the transistor NW1 is a transistor having a back gate. The back gate of the transistor NW1 is electrically connected to the wiring BGL. A voltage Vbg_w1 is input to the wiring BGL.

The transistor NW1 is an OS transistor. Since the OS transistor has an extremely small off-state current, the memory cell 209 is configured with the OS transistor, whereby charge leakage from the capacitor CS1 can be suppressed, so that the frequency of the refresh operation of the frame memory 151 can be reduced. Even if the power supply is cut off, the frame memory 151 can hold image data for a long time. In addition, by setting the voltage Vbg_w1 to a negative voltage, the threshold voltage of the transistor NW1 can be shifted to the positive potential side, and the holding time of the memory cell 209 can be extended.

The off-state current here refers to a current that flows between a source and a drain when a transistor is in an off state. In the case where the transistor is an n-channel transistor, for example, when the threshold voltage is about 0 V to 2 V, the current flowing between the source and the drain when the gate voltage with respect to the source is a negative voltage is turned off. Can be called. Further, the extremely small off-state current means that, for example, the off-current per channel width of 1 μm is 100 zA (z; zept, 10 ⁻²¹ ) or less. The smaller the off-current, the better. Therefore, the normalized off-current is preferably 10 zA / μm or less, or 1 zA / μm or less, more preferably 10 yA / μm (y; yoct, 10 ⁻²⁴ ) or less. preferable.

Since the transistor NW1 of the plurality of memory cells 209 included in the cell array 203 is an OS transistor, the transistors in other circuits can be Si transistors formed on a silicon wafer, for example. Accordingly, the cell array 203 can be stacked on the sense amplifier circuit 204. Therefore, the circuit area of the frame memory 151 can be reduced, and the controller IC 115 can be downsized.

The cell array 203 is provided so as to be stacked on the sense amplifier circuit 204. The sense amplifier circuit 204 has a plurality of sense amplifiers SA. The sense amplifier SA is electrically connected to adjacent wirings LBL and LBLB (local bit line pairs), wirings GBL and GBLB (global bit line pairs), and a plurality of wirings CSEL. The sense amplifier SA has a function of amplifying a potential difference between the wiring LBL and the wiring LBLB.

In the sense amplifier circuit 204, one wiring GBL is provided for the four wirings LBL, and one wiring GBLB is provided for the four wirings LBLB. Is not limited to the configuration example of FIG.

The main amplifier 206 is connected to the sense amplifier circuit 204 and the input / output circuit 207. The main amplifier 206 has a function of amplifying a potential difference between the wiring GBL and the wiring GBLB. The main amplifier 206 can be omitted.

The input / output circuit 207 has a function of outputting a potential corresponding to write data to the wiring GBL and the wiring GBLB or the main amplifier 206, reads the potential of the wiring GBL and the wiring GBLB, or the output potential of the main amplifier 206, and outputs the data as data to the outside. Has a function to output. A sense amplifier SA that reads data and a sense amplifier SA that writes data can be selected by a signal of the wiring CSEL. Therefore, since the input / output circuit 207 does not require a selection circuit such as a multiplexer, the circuit configuration can be simplified and the occupied area can be reduced.

<Register 175>
FIG. 6 is a block diagram illustrating a configuration example of the register 175. The register 175 includes a scan chain register unit 175A and a register unit 175B. The scan chain register unit 175A includes a plurality of registers 230. A plurality of registers 230 form a scan chain register. The register unit 175B includes a plurality of registers 231.

The register 230 is a nonvolatile register that does not lose data even when the power supply is shut off. In order to make the register 230 nonvolatile, here, the register 230 includes a holding circuit using an OS transistor.

On the other hand, the register 231 is a volatile register. The circuit configuration of the register 231 is not particularly limited and may be any circuit capable of storing data, and may be configured by a latch circuit, a flip-flop circuit, or the like. The image processing unit 160 and the timing controller 173 access the register unit 175B and take in data from the corresponding register 231. Alternatively, the processing contents of the image processing unit 160 and the timing controller 173 are controlled according to the data supplied from the register unit 175B.

When updating the data stored in the register 175, first, the data in the scan chain register unit 175A is changed. After rewriting the data of each register 230 of the scan chain register unit 175A, the data of each register 230 of the scan chain register unit 175A is loaded into each register 231 of the register unit 175B at once.

As a result, the image processing unit 160, the timing controller 173, and the like can perform various types of processing using the batch updated data. Since simultaneity is maintained in the update of data, stable operation of the controller IC 115 can be realized. By providing the scan chain register unit 175A and the register unit 175B, data in the scan chain register unit 175A can be updated even when the image processing unit 160 and the timing controller 173 are operating.

When the controller IC 115 executes power gating, the register 230 stores (saves) data in the holding circuit and then cuts off the power supply. After the power is restored, the data in the register 230 is restored (loaded) to the register 231 to resume normal operation. If the data stored in the register 230 does not match the data stored in the register 231, the data in the register 231 is saved in the register 230 and then stored again in the holding circuit of the register 230. A configuration is preferred. Examples of cases where the data do not match include inserting update data into the scan chain register unit 175A.

FIG. 7 illustrates a circuit configuration example of the register 230 and the register 231. FIG. 7 shows the two-stage registers 230 of the scan chain register unit 175A and the two registers 231 corresponding to these registers 230. The register 230 receives the signal Scan In and outputs the signal Scan Out.

The register 230 includes a holding circuit 17, a selector 18, and a flip-flop circuit 19. The selector 18 and the flip-flop circuit 19 constitute a scan flip-flop circuit. The selector 18 receives a signal SAVE1.

The holding circuit 17 receives the signals SAVE2 and LOAD2. The holding circuit 17 includes transistors T1 to T6 and capacitive elements C4 and C6. The transistors T1 and T2 are OS transistors. Similarly to the transistor NW1 (see FIG. 5B) of the memory cell 209, the transistors T1 and T2 may be OS transistors with a back gate.

The transistors T1, T3, T4 and the capacitive element C4 constitute a three-transistor gain cell. Similarly, the transistors T2, T5, T6 and the capacitive element C6 constitute a three-transistor gain cell. The complementary data held by the flip-flop circuit 19 is stored by two gain cells. Since the transistors T1 and T2 are OS transistors, the holding circuit 17 can hold data for a long time even when the power supply is cut off. In the register 230, transistors other than the transistors T1 and T2 may be composed of Si transistors.

The holding circuit 17 stores the complementary data held by the flip-flop circuit 19 according to the signal SAVE2, and loads the held data into the flip-flop circuit 19 according to the signal LOAD2.

The output terminal of the selector 18 is electrically connected to the input terminal of the flip-flop circuit 19, and the input terminal of the register 231 is electrically connected to the data output terminal. The flip-flop circuit 19 includes inverters 20 to 25 and analog switches 27 and 28. The conduction state of the analog switches 27 and 28 is controlled by a scan clock (expressed as Scan Clock) signal. The flip-flop circuit 19 is not limited to the circuit configuration of FIG. 7, and various flip-flop circuits 19 can be applied.

One of the two input terminals of the selector 18 is electrically connected to the output terminal of the register 231, and the other is electrically connected to the output terminal of the previous flip-flop circuit 19. Note that data is input from the outside of the register 175 to the input terminal of the selector 18 in the first stage of the scan chain register unit 175A.

The register 231 includes inverters 31 to 33, a clocked inverter 34, an analog switch 35, and a buffer 36. The register 231 loads the data of the flip-flop circuit 19 based on the signal LOAD1. The transistor of the register 231 may be a Si transistor.

<Other configuration examples of controller IC>
Hereinafter, another configuration example of the controller IC will be described.

FIG. 8 shows a configuration example of a controller IC that does not include a source driver. A controller IC 117 shown in FIG. 8 is a modification of the controller IC 115 and has a region 191. The controller 154 controls power supply to the circuits in the area 191.

The controller IC 117 is not provided with a source driver. Therefore, the display unit 110 includes a source driver IC 186. The number of source driver ICs 186 is determined according to the number of pixels in the pixel array 111.

The configuration of the source driver is not limited to this. Similarly to the gate driver 113, a source driver may be manufactured on the substrate of the pixel array 111. Further, the controller IC 117 may be provided with one or both of the TS driver 126 and the sense circuit 127. The same applies to the controller IC 115.

<< Operation example >>
An operation example of the controller IC 115 and the register 175 related to the display device 100 will be described separately before shipment, when the electronic device including the display device 100 is started, and during normal operation.

<Before shipment>
Prior to shipment, parameters relating to the specifications and the like of the display device 100 are stored in the register 175. These parameters include, for example, the number of pixels, the number of touch sensors, parameters used by the timing controller 173 to generate waveforms of various timing signals, and a current detection circuit that detects the current flowing through the pixels 10 in the source driver 180. There are correction data of the EL correction circuit 164 and the like. These parameters may be stored by providing a dedicated ROM in addition to the register 175.

<At startup>
When the electronic apparatus having the display device 100 is activated, parameters such as user settings sent from the host 140 are stored in the register 175. These parameters include, for example, display brightness and tone, touch sensor sensitivity, energy saving settings (time until display is darkened or disappears), gamma correction curves and tables, and the like. Note that when the parameter is stored in the register 175, the controller 154 transmits the scan clock signal and data corresponding to the parameter to the register 175 in synchronization with the scan clock signal.

<Normal operation>
The normal operation is divided into a state in which a moving image or the like is displayed, a state in which a still image is being displayed and IDS driving is possible, and a state in which no display is performed. In a state where a moving image or the like is displayed, the image processing unit 160, the timing controller 173, and the like are operating, but the data change in the register 175 is performed on the scan chain register unit 175A. There is no impact on the above. After the data change in the scan chain register unit 175A is completed, the data change in the register 175 is completed by loading the data in the scan chain register unit 175A into the register unit 175B at once. In addition, the image processing unit 160 and the like are switched to an operation corresponding to the data.

In a state in which a still image is displayed and IDS driving is possible, the register 175 can perform power gating as in other circuits in the area 190, for example. In this case, before the power gating, in the register 230 included in the scan chain register unit 175A, an operation of storing the complementary data held by the flip-flop circuit 19 in the holding circuit 17 is performed according to the signal SAVE2.

When returning from power gating, the data held in the holding circuit 17 is loaded into the flip-flop circuit 19 according to the signal LOAD2, and the data of the flip-flop circuit 19 is loaded into the register 231 according to the signal LOAD1. In this way, the data in the register 175 becomes valid in the same state as before power gating. Even in the power gating state, if there is a parameter change request of the register 175 from the host 140, the power gating of the register 175 can be canceled and the parameter can be changed.

In a state where display is not performed, for example, a circuit (including the register 175) in the region 190 can be power-gated. In this case, the host 140 may also stop, but since the frame memory 151 and the register 175 are non-volatile, when returning from power gating, the display before power gating (without waiting for the host 140 to return) ( Still images).

For example, when the display device 100 is applied to the display unit of a foldable information terminal, the region 190 is detected when the information terminal is folded by the signal of the open / close sensor 144 and the display surface of the display device 100 is not used. In addition to the internal circuit, the sensor controller 153, the touch sensor controller 184, and the like can be power-gated.

When the information terminal is folded, the host 140 may stop depending on the standard of the host 140. Even if the information terminal is deployed again while the host 140 is stopped, the frame memory 151 and the register 175 are non-volatile. Therefore, before the image data, various control signals, etc. are sent from the host 140, Image data can be displayed.

As described above, the register 175 includes the scan chain register unit 175A and the register unit 175B. By changing the data in the scan chain register unit 175A, the image processing unit 160, the timing controller 173, and the like are not affected. Smooth data changes can be made. Each register 230 of the scan chain register unit 175A has the holding circuit 17 and can smoothly shift to and return to the power gating state.

Note that this embodiment can be implemented in combination with any of the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, an example in which the OS transistor is applied to the scan chain register in the register 175 described in Embodiment 1 will be described.

<Register 175>
FIG. 9 is a block diagram illustrating a configuration example of the register 175. The register 175 includes a scan chain register unit 175C and a register unit 175D. The scan chain register unit 175C has a plurality of registers 232. A plurality of registers 232 constitute a scan chain register. The register unit 175D includes a plurality of registers 233.

The register 232 is a nonvolatile register that does not lose data even when the power supply is shut off. In order to make the register 232 nonvolatile, here, the register 232 is configured using an OS transistor. On the other hand, the register 233 includes a volatile register using a Si transistor and a circuit using an OS transistor.

The image processing unit 160 and the timing controller 173 access the register unit 175D and take in data from the corresponding register 233. Alternatively, the processing contents of the image processing unit 160 and the timing controller 173 are controlled according to the data supplied from the register unit 175D.

There is no particular limitation on the circuit configuration of the register 233, and any circuit that can store data, such as a latch circuit or a flip-flop circuit, may be used. Alternatively, as in the register 232, only the OS transistor may be used as the transistor, but it is preferable to have an ability to suppress potential fluctuation when accessed from the image processing unit 160 and the timing controller 173. That is, it is preferable to have the ability to output a signal.

When updating the data stored in the register 175, first, the data in the scan chain register unit 175C is changed. After rewriting the data in each register 232 in the scan chain register unit 175C, the data in each register 232 in the scan chain register unit 175C is loaded into each register 233 in the register unit 175D at once.

As a result, the image processing unit 160, the timing controller 173, and the like can perform various processes using the data updated at once. Since simultaneity is maintained in the update of data, stable operation of the controller IC 115 can be realized. By providing the scan chain register unit 175C and the register unit 175D, the data of the scan chain register unit 175C can be updated even when the image processing unit 160 and the timing controller 173 are operating.

When power gating is executed by the controller IC 115, after the power is restored, the data in the register 232 is restored (loaded) to the register 233 to resume normal operation. Note that when the data stored in the register 232 and the data stored in the register 233 do not match at the start of power gating, the data stored in the register 233 is preferably saved in the register 232. Examples of cases where the data do not match include storing update data in the scan chain register unit 175C.

FIG. 10 illustrates a circuit configuration example of the register 232 and the register 233. FIG. 10 shows the first-stage register 232 [1] and second-stage register 232 [2] of the scan chain register unit 175C, and two registers 233 [1] and 233 [2] corresponding to these registers 232. Show.

The register 232 includes transistors TR1 to TR6 and capacitor elements C7 and C8. The transistors TR1 to TR6 are OS transistors. The transistors TR1 to TR6 may be OS transistors with back gates as in the transistor NW1 (see FIG. 5B) of the memory cell 209.

The register 233 includes transistors TR7 to TR11 and inverters INV1 and INV2. For example, the transistors TR7 to TR11 may be OS transistors, and the inverters INV1 and INV2 in the region 21 may be configured using Si transistors. Alternatively, the transistors constituting the transistors TR7 to TR11 and the inverters INV1 and INV2 can be Si transistors.

In addition, the low power supply potential and the high power supply potential are input to the registers 232 and 233. In FIG. 10, the low power supply potential is represented by the ground potential, and the high power supply potential is represented by VH. Clock signals CK 1 to CK 4 are input to the register 232, and signals LD, RS, and SV are input to the register 233. The first-stage register 232 [1] receives an external data SIN and outputs a signal SO [1], and the second-stage register 232 [2] receives a signal SO [1] and receives a signal SO [2]. Output.

A register 233 [1] corresponding to the register 232 [1] outputs a signal Q [1], and a register 233 [2] corresponding to the register 232 [2] outputs a signal Q [2]. The signal Q [1] and the signal Q [2] are data output to the image processing unit 160, the timing controller 173, and the like.

FIG. 11 shows the relationship among these clock signals CK1 to CK4, signals LD, RS, SV, data SIN, and signals SO [1], SO [2], Q [1], Q [2] related to input / output. . FIG. 11 is a timing chart illustrating an operation example of the register.

In FIG. 11, times T01 to T09 are periods for storing data in the scan chain register unit 175C, times T10 to T12 are periods for loading the data of the scan chain register unit 175C into the register unit 175D, and times T13 to T17 are A period in which data is stored in the scan chain register unit 175C again, times T18 to T20 indicate a period in which the data in the register unit 175D is saved in the scan chain register unit 175C.

At time T01 to T02, the clock signal CK1 is set to “H” (high level), whereby the node N1 [1] of the register 232 [1] and the node N1 [2] of the register 232 [2] are set to “L” ( Reset to low level. At times T02 to T03, by setting the clock signal CK2 to “H”, the node N1 [1] of the register 232 [1] is set to the value “H” corresponding to the data SIN, and the node of the register 232 [2] N1 [2] is set to a value “L” corresponding to SO [1].

At times T03 to T04, the output signal SO [1] of the register 232 [1] and the output signal SO [2] of the register 232 [2] are reset to “L” by setting the clock signal CK3 to “H”. To do. At time T04 to T05, the clock signal CK4 is set to “H”, whereby the output signal SO [1] of the register 232 [1] is set to a value “H” corresponding to the node N1 [1], and the register 232 [ 2] is set to the value “L” corresponding to the node N1 [2].

At times T05 to T06, the clock signal CK1 is set to “H”, so that the node N1 [1] of the register 232 [1] and the node N1 [2] of the register 232 [2] are reset to “L”. At time T06 to T07, the clock signal CK2 is set to “H”, so that the node N1 [1] of the register 232 [1] is set to the value “L” corresponding to the data SIN, and the node of the register 232 [2] N1 [2] is set to a value “H” corresponding to SO [1].

At time T07 to T08, the clock signal CK3 is set to “H” to reset the output signal SO [1] of the register 232 [1] and the output signal SO [2] of the register 232 [2] to “L”. To do. At time T08 to T09, the clock signal CK4 is set to “H” so that the output signal SO [1] of the register 232 [1] is set to a value “L” corresponding to the node N1 [1], and the register 232 [ 2] is set to the value “H” corresponding to the node N1 [2].

As described above, the output signal SO [1] of the register 232 [1] becomes “L” and the output signal SO [2] of the register 232 [2] becomes “H” by the operation from time T01 to T09, and the scan chain register. Data can be stored in the register 232 constituting the unit 175C. By changing the data SIN, the values of SO [1] and SO [2] can be changed.

Next, at time T10 to T11, the signal RS is set to “H” so that the output signal Q [1] of the register 233 [1] and the output signal Q [2] of the register 233 [2] are set to “L”. Reset. At time T11 to T12, by setting the signal LD to “H”, the output signal Q [1] of the register 233 [1] is set to a value “L” corresponding to SO [1], and the register 233 [2]. Output signal Q [2] is set to a value “H” corresponding to SO [2].

By the operation from time T10 to time T12, the output signal Q [1] of the register 233 [1] becomes “L”, the output signal Q [2] of the register 233 [2] becomes “H”, and the registers constituting the register unit 175D The data of the scan chain register unit 175C can be loaded into the H.233.

Note that the capacitor elements C7 and C8 included in the register 232 are electrically connected to an OS transistor with extremely small off-state current, and thus can hold charge for a long time even when power supply is interrupted. Even if the data in the register 233 is lost due to the interruption of the power supply, the data of the scan chain register unit 175C can be loaded into the register unit 175D by performing the operation from the time T10 to T12 after the power supply is resumed. it can.

Next, at time T13 to T17, data is stored again in the scan chain register unit 175C. Since the operation is the same as that at times T01 to T05, the description is omitted. However, the output signal SO [1] of the register 232 [1] is “H”, and the output signal SO [2] of the register 232 [2] is “L”. Become.

Here, when the power supply is cut off, the register unit 233 is different from the signal (Q [1] is “L” and Q [2] is “H”) loaded by the operation from time T10 to T12. It is preferable to save 175D data in the scan chain register unit 175C.

At time T18 to T19, the clock signal CK1 is set to “H”, so that the node N1 [1] of the register 232 [1] and the node N1 [2] of the register 232 [2] are reset to “L”. At times T19 to T20, the signal SV is set to “H”, so that the node N1 [1] of the register 232 [1] is set to a value “L” corresponding to Q [1], and the register 232 [2] The node N1 [2] is set to a value “H” corresponding to Q [2].

After that, since it is the same as the times T07 to T09, description and illustration are omitted. However, by sequentially setting the clock signal CK3 and the clock signal CK4 to “H”, the output signal SO [1] of the register 232 [1] is changed to the node. The value “L” corresponding to N1 [1] can be set, and the output signal SO [2] of the register 232 [2] can be set to the value “H” corresponding to the node N1 [2].

As described above, when the power supply is interrupted while the data in the scan chain register unit 175C is being updated, the data in the scan chain register unit 175C and the data in the register unit 175D are not consistent. When power supply is resumed, unmatched data is loaded into the register unit 175D. Therefore, it is preferable to save the data in the register unit 175D in the scan chain register unit 175C. Alternatively, the power supply can be cut off after waiting for the data update of the scan chain register unit 175C to end.

<< Operation example >>
An operation example will be described because the operation before and after power gating is different from that of the first embodiment.

<Before shipment>
Prior to shipment, parameters relating to the specifications and the like of the display device 100 are stored in the register 175. These parameters include, for example, the number of pixels, the number of touch sensors, parameters used by the timing controller 173 to generate various timing signals, and a current detection circuit that detects the current flowing through the pixels 10 in the source driver 180. There are correction data of the correction circuit 164 and the like. These parameters may be stored by providing a dedicated ROM in addition to the register 175.

<At startup>
When the electronic apparatus having the display device 100 is activated, parameters such as user settings sent from the host 140 are stored in the register 175. These parameters include, for example, display brightness and tone, touch sensor sensitivity, energy saving settings (time until display is darkened or disappears), gamma correction curves and tables, and the like. When the parameter is stored in the register 175, the controller 154 transmits the clock signals CK1 to CK4 and data corresponding to the parameter to the register 175 in synchronization with the clock signals CK1 to CK4.

<Normal operation>
The normal operation is divided into a state in which a moving image or the like is displayed, a state in which a still image is being displayed and IDS driving is possible, and a state in which no display is performed. While the moving image is displayed, the image processing unit 160 and the timing controller 173 are operating, but the data change of the register 175 is performed on the scan chain register unit 175C. There is no impact on the above. After the data change of the scan chain register unit 175C is completed, the data change of the register 175 is completed by loading the data of the scan chain register unit 175C into the register unit 175D at once. In addition, the image processing unit 160 and the like are switched to an operation corresponding to the data.

In a state in which a still image is displayed and IDS driving is possible, the register 175 can perform power gating as in other circuits in the area 190, for example. In this case, if the data in the scan chain register unit 175C is being updated, the data in the register unit 175D is preferably saved in the scan chain register unit 175C.

When returning from power gating, the data of the scan chain register unit 175C is loaded into the register unit 175D in accordance with the signals RS and LD. In this way, the data in the register 175 becomes valid in the same state as before power gating. Even in the power gating state, if there is a parameter change request of the register 175 from the host 140, the power gating of the register 175 can be canceled and the parameter can be changed.

In a state where display is not performed, for example, a circuit (including the register 175) in the region 190 can be power-gated. In this case, the host 140 may also stop, but since the frame memory 151 and the register 175 are non-volatile, when returning from power gating, the display before power gating (without waiting for the host 140 to return) ( Still images).

For example, when the display device 100 is applied to the display unit of a foldable information terminal, the region 190 is detected when the information terminal is folded by the signal of the open / close sensor 144 and the display surface of the display device 100 is not used. In addition to the internal circuit, the sensor controller 153, the touch sensor controller 184, and the like can be power-gated.

When the information terminal is folded, the host 140 may stop depending on the standard of the host 140. Even if the information terminal is deployed again while the host 140 is stopped, the frame memory 151 and the register 175 are non-volatile. Therefore, before the image data, various control signals, etc. are sent from the host 140, Image data can be displayed.

As described above, the register 175 includes the scan chain register unit 175C and the register unit 175D. By changing data in the scan chain register unit 175C, the image processing unit 160, the timing controller 173, and the like are not affected. Smooth data changes can be made. In addition, each register 230 of the scan chain register unit 175C is a nonvolatile register using an OS transistor, so that power gating according to the operation state of the display device is easy. Further, since the frame memory 151 is also non-volatile, the display can be resumed promptly when the power supply is resumed. A system that can smoothly shift to and return to the power gating state and can reduce power consumption can be realized.

Note that this embodiment can be implemented in combination with any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example in which the AI controller 156 is applied to the controller IC 115 described in Embodiment 1 will be described.

A controller IC 118 illustrated in FIG. 12 includes an AI controller 156. The AI controller 156 performs arithmetic processing using a neural network, and can predict the timing at which the transition to power gating can be made based on the current consumption of the frame memory 151, touch information obtained from the touch sensor controller 184, and the like.

In order to perform power gating, the register 175 requires a preparatory operation for storing (saving) data in a nonvolatile register in which data is not lost even when power supply is cut off. It is preferable to perform this preparatory operation immediately before the image data no longer changes because a long power gating time can be secured.

Specifically, the AI controller 156 instructs the timing for performing the operation of storing the complementary data held by the flip-flop circuit 19 in the holding circuit 17 (the “power gating preparation operation”). Power gating can be performed when there is no change in the image data, but immediately before this, a feature can be found regarding the area where the image data is rewritten, the input to the touch sensor unit 120, and the like.

For example, when there is no input to the touch sensor unit 120 and the area in which the image data is rewritten decreases, it can be predicted that there will be no change in the image data soon. Further, for example, it is possible to predict that there is no change in the image data after there is an input to the touch sensor unit 120 and the change in the image data continues for a while.

Specifically, it can be predicted that there will be no change in the image data when the display is completed after there is a processing operation of the application software after a tap or double tap operation corresponding to a mouse click. In addition, since dragging is an operation performed when it is desired to move an image, it can be predicted that display is completed relatively quickly after dragging and that there is no change in image data. In the touch panel, flicking is an operation performed in the case of image scrolling or page turning. Therefore, it can be predicted that there is an image change in a large area for a while during flicking, and that there is no change in image data thereafter. In addition, since pinch-in and pinch-out, which are inputs of two or more points, are operations performed when it is desired to enlarge or reduce an image, the image is changed in a large area at the time of pinch-in and pinch-out, and then the image data is relatively early It can be predicted that there will be no change. After these operations, the user of the display device 100 can predict that the image will be confirmed for a while, so that it can be predicted that there will be no change in the image data.

Regarding the input to the touch sensor unit 120, the number of input points, the movement of coordinates, the speed of movement, and the like can be known from the touch information obtained from the touch sensor controller 184. Regarding the area where the image data is rewritten, the data stored in the frame memory 151 may be directly compared with the data to be rewritten, but the current consumption of the frame memory 151 may be measured. This is because the current consumption of the frame memory 151 is characterized by an increase when data different from the stored data is written.

For example, there is a method of measuring the instantaneous current consumption and the average current consumption of the frame memory 151. The memory cells 209 of the frame memory 151 are sequentially scanned by the word lines (wirings WL). However, when the memory cell 209 storing the image data to be rewritten is selected, the local bit lines (wirings LBL and LBLB) are connected. Thus, since a charge different from the charge stored in the capacitor element CS1 is injected, the current consumption of the frame memory 151 increases instantaneously (see FIG. 5). That is, from the viewpoint of instantaneous current consumption, there are two types of current consumption values when the memory cell 209 that rewrites data is selected and when the memory cell 209 that does not rewrite data is selected. (Here, the former is referred to as current consumption during rewriting, and the latter is referred to as steady-state current consumption).

On the other hand, the current consumption averaged using a capacitor element, a coil or the like shows a value between the current consumption during rewriting and the current consumption during steady state (the averaging is performed for a time of one frame or more). If the number of memory cells 209 to which data is rewritten is large, the instantaneous current consumption increases as the current consumption during rewriting increases, so the average current consumption also approaches the current consumption during rewriting. In addition, when the number of memory cells 209 in which data is not rewritten is large, the instantaneous current consumption increases in many cases indicating the steady-state current consumption, and thus the average current consumption approaches the steady-state current consumption. That is, the state where the area where image data is rewritten decreases can be estimated from the fact that the average current consumption approaches the steady-state current consumption.

As described above, the AI controller 156 can instruct the timing for performing the power gating preparation operation from the current consumption of the frame memory 151, the touch information obtained from the touch sensor controller 184, and the like. Thereafter, when it is confirmed that there is no change in the image data, the controller 154 performs power gating on some circuits in the controller IC 118, and the display device 100 performs IDS driving.

Actually, even if the AI controller 156 instructs the power gating preparation operation, the change of the image data does not stop and power gating may not be performed. In this case, the power consumption of the controller IC 118 is increased by performing the preparation operation. For this reason, the AI controller 156 performs arithmetic processing using a neural network so that the success probability of power gating can be increased. For example, instead of setting a parameter such as how much the average current consumption approaches the steady-state current consumption to perform power gating preparatory operation to a preset value, a certain range is obtained by learning using a neural network. It is good to be able to change with. The neural network will be described in the fourth embodiment.

Note that this embodiment can be implemented in combination with any of the other embodiments as appropriate.

(Embodiment 4)
The AI controller 156 performs arithmetic processing using a neural network so as to increase the success probability of power gating. In the present embodiment, details of the AI controller 156 described in the third embodiment will be described.

<< Neural network >>
A neural network is an information processing system using a neural network as a model. By using a neural network, it is expected that a computer with higher performance than a conventional Neumann computer can be realized. In recent years, various studies for constructing a neural network on an electronic circuit have been advanced.

The neural network has a configuration in which units imitating neurons are connected to each other, and a plurality of data is input to each neuron. The plurality of data input to the neuron is multiplied by a “weighting coefficient” representing the strength of the connection, and the results are added. When the result of the product-sum operation thus obtained exceeds a threshold value, the neuron outputs a high level signal. This phenomenon is called “ignition”.

The AI controller 156 is input with touch information obtained from the touch sensor controller 184 described in Embodiment 3, current consumption of the frame memory 151, and the like. Thereafter, information indicating whether or not power gating is actually performed is input from the controller 154 (see FIG. 12).

The AI controller 156 performs supervised learning using the touch information and the current consumption of the frame memory 151 described above as learning data, and information indicating whether or not power gating is actually performed as teacher data. Learning is performed by changing a “weighting coefficient” or the like representing the strength of coupling.

By performing learning using a neural network, the AI controller 156 can output a signal for predicting whether or not power gating is performed from input data such as touch information and current consumption of the frame memory 151.

When the AI controller 156 outputs a signal predicting that power gating is performed, an operation of storing the complementary data held by the flip-flop circuit 19 in the holding circuit 17 is performed (see FIG. 7). Thereafter, when it is confirmed that there is no change in the image data, power gating is performed.

In this way, by predicting whether or not power gating is performed before the change in image data disappears, power gating can be performed immediately after the change in image data is eliminated. This can ensure a long time for power gating and enhance the power consumption reduction effect.

Hereinafter, a hierarchical neural network and supervised learning will be described as an example of a neural network that can be used for the AI controller 156.

FIG. 13A shows a configuration example of a hierarchical neural network. In FIG. 13A, the neurons of each layer are indicated by circles. In FIG. 13A, the (l-1) th layer having a function as an input layer, the lth layer having a function as an intermediate layer (hidden layer), and a first layer having a function as an output layer ( The configuration example of a hierarchical neural network having neurons (formal neurons) divided into three (l + 1) layers is shown (l is an integer of 2 or more). Then, M neurons (M is an integer of 2 or more), N neurons (N is an integer of 2 or more), and (l + 1) layer neurons of the (l-1) layer. Is K (K is an integer of 2 or more).

In FIG. 13A, five neurons are illustrated among the plurality of neurons of the (l-1) th layer, and four neurons are illustrated among the plurality of neurons of the lth layer. Among the plurality of neurons of the (l-1) th layer, three neurons are illustrated.

FIG. 13A shows a configuration example of a hierarchical neural network in which the intermediate layer is composed of one layer, but the intermediate layer may be composed of a plurality of layers. Therefore, in the case of a hierarchical neural network composed of L layers (L is an integer of 3 or more), the first layer corresponds to the input layer, and the second to (L-1) layers correspond to the intermediate layer. The Lth layer corresponds to the output layer.

In FIG. 13A, the output z _m ^{(l−1) of} the m-th neuron (m is an integer of 1 to M) included in the ^(l−1) -th layer neuron is It is assumed that the signal is input to n neurons (n is an integer of 1 to N). It is also assumed that the output z _n ^{(l) of} the nth neuron is input to the kth neuron (k is an integer of 1 or more and K or less) of the (l + 1) th layer neuron. In addition, the output of the kth neuron is z _k ^{(l + 1)} . The weight coefficient of the n-th neuron in the l-th layer is set to w _nm ^(l) , and the weight coefficient of the k-th neuron in the (l + 1) -th layer is set to w _kn ^{(l + 1)} .

Under the above conditions, the total sum (net value) of inputs to the n-th neuron in the l-th layer is expressed by the following equation a1.

^{_{u n (l) = Σ m}} w nm (l) · z m (l-1) (a1)

The arithmetic processing of Expression a1 can be performed by using a product-sum arithmetic processing circuit described later.

The output z _n ^(l) of the n-th neuron in the l-th layer is expressed by the following expression a2.

_{^{z n (l) = f (}} u n (l)) (a2)

Note that f is an output function of the neuron. As the neuron output function f, a step function, a linear ramp function, a sigmoid function, or the like can be used. For example, the arithmetic processing of Expression a2 can be executed by using a circuit 270 illustrated in FIG. In the circuit 270, the output function f corresponds to the output characteristic of the OP amplifier. In addition, the arithmetic processing of Expression a2 can be realized by performing arithmetic processing in an arithmetic circuit corresponding to a desired output function using the output signal from the OP amplifier.

Similarly, the sum (net value) of the inputs to the kth neuron in the (l + 1) th layer is expressed by the following expression a3.

u _k ^{(l + 1)} = Σ _n w _kn ^{(l + 1)} · z _n ^(l) (a3)

The arithmetic processing of Expression a3 can be performed by using a product-sum arithmetic processing circuit described later.

The output z _k ^{(l + 1)} of the kth neuron in the (l + 1) th layer is expressed by the following expression a4.

z _k ^{(l + 1)} = f (u _k ^{(l + 1)} ) (a4)

For example, the arithmetic processing of Expression a4 can be executed by using a circuit 271 illustrated in FIG. In the circuit 271, the output function f corresponds to the output characteristics of the OP amplifier as in the circuit 270. Further, the arithmetic processing of Expression a4 can be realized by performing arithmetic processing in an arithmetic circuit corresponding to a desired output function using the output signal from the OP amplifier.

With the above configuration, the output z _k ^{(l + 1)} of the k-th neuron can be obtained.

Next, supervised learning will be described. Supervised learning refers to all the weighting factors of a hierarchical neural network when the output result differs from the desired result (sometimes referred to as teacher data or a teacher signal) in the function of the hierarchical neural network described above. Is updated based on the output result and the desired result.

As a specific example of supervised learning, a learning method using an error back propagation method will be described. FIG. 14A is a schematic diagram of the error back propagation method. The error back propagation method is a method of changing the weighting coefficient so that the error between the output of the hierarchical neural network and the teacher data becomes small.

Specifically, the backpropagation method, relative error energy E determined by the output z _{k ^(L)} and teacher data t _k of the output layer, ∂ updating of the weighting coefficients w _nm of the l layer ^_(l) The weighting factor is changed as E / ∂w _nm ^(l) .

For example, if the error δ _n ^(l) of the ^l- _th layer is defined as δ _n ^(l) ≡ ∂E / ∂u _n ^(l) , the error δ _n ^(l) is expressed by the following equation a5, and the update amount ∂E / ∂w _nm ^(l) is represented by the following formula a6. Note that f ′ is a derivative of the output function of the neuron.

δ _n ^(l) = Σ _k δ _k ^{(l + 1)} · w _kn ^{(l + 1)} · f ′ (u _n ^(l) ) (a5)
∂E / ∂w _nm ^(l) = δ _n ^(l) · z _m ^(l-1) (a6)

For example, the arithmetic processing of Expression a5 can be executed by using a circuit 272 illustrated in FIG. Further, the arithmetic processing of the expression a6 can be executed by using a circuit 273 shown in FIG. Note that the derivative can be subjected to arithmetic processing in an arithmetic circuit corresponding to a desired derivative, for example, using an output signal from the OP amplifier.

A part of the arithmetic processing of Expression a5 can be performed by using a product-sum arithmetic processing circuit described later.

Further, the error δ _n ^{(l + 1)} of the ^{(l + 1)} _th layer as the output layer is expressed by the following expression a7, and the update amount ∂E / ∂w _nm ^{(l + 1)} is expressed by the following expression a8.

δ _k ^{(l + 1)} = (z _k ^{(l + 1)} −t _k ) · f ′ (u _k ^{(l + 1)} ) (a7)
∂E / ∂w _kn ^{(l + 1)} = δ _k ^{(l + 1)} · z _n ^(l) (a8)

For example, the arithmetic processing of Expression a7 can be executed by using a circuit 274 illustrated in FIG. The arithmetic processing of Expression a8 can be executed by using a circuit 273 illustrated in FIG.

<< Product-sum operation processing circuit >>
FIG. 15 shows an example of a product-sum operation processing circuit that performs the arithmetic processing represented by the expressions a1 and a3 in the hierarchical neural network shown as an example of the neural network that can be used for the AI controller 156.

An example of the product-sum operation processing circuit illustrated in FIG. 15 has a function of performing analog operation processing using analog data. By having a function of performing analog calculation processing, calculation processing can be performed without converting analog data into digital data or while suppressing the frequency of conversion of analog data into digital data as much as possible. Therefore, a huge amount of arithmetic processing can be reduced, and the scale of the arithmetic circuit can be reduced. Further, the time required for the arithmetic processing can be suppressed.

FIG. 15 is a block diagram of the semiconductor device 107 as an example of a product-sum operation processing circuit. A semiconductor device 107 illustrated in FIG. 15 includes a memory circuit 11 (MEM), a reference memory circuit 12 (RMEM), a circuit 13, and a circuit 14. The semiconductor device 107 may further include a current source circuit 15 (CREF).

The memory circuit 11 (MEM) includes a memory cell MC exemplified by a memory cell MC [i, j] and a memory cell MC [i + 1, j]. Each memory cell MC includes an element having a function of converting an input potential into a current. As an element having the above function, for example, an active element such as a transistor can be used. FIG. 15 illustrates a case where each memory cell MC includes a transistor Tr21.

A first analog potential is input to the memory cell MC from the wiring WD exemplified by the wiring WD [j]. The first analog potential corresponds to the first analog data. The memory cell MC has a function of generating a first analog current corresponding to the first analog potential. Specifically, the drain current of the transistor Tr21 obtained when the first analog potential is supplied to the gate of the transistor Tr21 can be used as the first analog current. Hereinafter, the current flowing through the memory cell MC [i, j] is I [i, j], and the current flowing through the memory cell MC [i + 1, j] is I [i + 1, j].

Note that when the transistor Tr21 operates in the saturation region, the drain current does not depend on the voltage between the source and the drain, but is controlled by the difference between the gate voltage and the threshold voltage. Therefore, it is desirable to operate the transistor Tr21 in the saturation region. In order to operate the transistor Tr21 in the saturation region, it is assumed that the gate voltage and the voltage between the source and the drain are appropriately set to voltages in a range in which the transistor Tr21 operates in the saturation region.

Specifically, in the semiconductor device 107 illustrated in FIG. 15, the first analog potential Vx [i, j] is input to the memory cell MC [i, j] from the wiring WD [j]. The memory cell MC [i, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i, j]. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the first analog current.

Specifically, in the semiconductor device 107 illustrated in FIG. 15, the first analog potential Vx [i + 1, j] is input to the memory cell MC [i + 1, j] from the wiring WD [j]. The memory cell MC [i + 1, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i + 1, j]. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the first analog current.

The memory cell MC has a function of holding the first analog potential. That is, it can be said that the memory cell MC has a function of holding the first analog current corresponding to the first analog potential by holding the first analog potential.

In addition, the second analog potential is input to the memory cell MC from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The second analog potential corresponds to the second analog data. The memory cell MC has a function of adding the second analog potential to the first analog potential that is already held, and a function of holding the third analog potential obtained by the addition. The memory cell MC has a function of generating a second analog current corresponding to the third analog potential. That is, it can be said that the memory cell MC has a function of holding the second analog current corresponding to the third analog potential by holding the third analog potential.

Specifically, in the semiconductor device 107 illustrated in FIG. 15, the second analog potential Vw [i, j] is input to the memory cell MC [i, j] from the wiring RW [i]. The memory cell MC [i, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i, j] and the second analog potential Vw [i, j]. The memory cell MC [i, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the second analog current.

In the semiconductor device 107 illustrated in FIG. 15, the second analog potential Vw [i + 1, j] is input to the memory cell MC [i + 1, j] from the wiring RW [i + 1]. The memory cell MC [i + 1, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1, j]. The memory cell MC [i + 1, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the second analog current.

The current I [i, j] flows between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i, j]. The current I [i + 1, j] flows between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i + 1, j]. Therefore, a current I [j] corresponding to the sum of the current I [i, j] and the current I [i + 1, j] is passed through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. It flows between the wiring BL [j] and the wiring VR [j].

The reference memory circuit 12 (RMEM) includes a memory cell MCR exemplified by a memory cell MCR [i] and a memory cell MCR [i + 1]. A first reference potential VPR is input to the memory cell MCR from the wiring WDREF. The memory cell MCR has a function of generating a first reference current corresponding to the first reference potential VPR. Hereinafter, the current flowing through the memory cell MCR [i] is referred to as IREF [i], and the current flowing through the memory cell MCR [i + 1] is referred to as IREF [i + 1].

Specifically, in the semiconductor device 107 illustrated in FIG. 15, the first reference potential VPR is input to the memory cell MCR [i] from the wiring WDREF. The memory cell MCR [i] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the first reference current.

In the semiconductor device 107 illustrated in FIG. 15, the first reference potential VPR is input to the memory cell MCR [i + 1] from the wiring WDREF. The memory cell MCR [i + 1] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the first reference current.

The memory cell MCR has a function of holding the first reference potential VPR. That is, it can be said that the memory cell MCR has a function of holding the first reference current corresponding to the first reference potential VPR by holding the first reference potential VPR.

In addition, the second analog potential is input to the memory cell MCR from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The memory cell MCR has a function of adding a second analog potential to the first reference potential VPR that is already held, and holding a second reference potential obtained by the addition. The memory cell MCR has a function of generating a second reference current corresponding to the second reference potential. That is, it can be said that the memory cell MCR has a function of holding the second reference potential corresponding to the second reference potential by holding the second reference potential.

Specifically, in the semiconductor device 107 illustrated in FIG. 15, the second analog potential Vw [i, j] is input to the memory cell MCR [i] from the wiring RW [i]. The memory cell MCR [i] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i, j]. The memory cell MCR [i] has a function of generating a second reference current corresponding to the second reference potential. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the second reference current.

In the semiconductor device 107 illustrated in FIG. 15, the second analog potential Vw [i + 1, j] is input to the memory cell MCR [i + 1] from the wiring RW [i + 1]. The memory cell MCR [i + 1] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i + 1, j]. The memory cell MCR [i + 1] has a function of generating a second reference current corresponding to the second reference potential. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the second reference current.

Then, the current IREF [i] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR [i]. The current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR [i + 1]. Therefore, the current IREF corresponding to the sum of the current IREF [i] and the current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1]. Become.

The current source circuit 15 has a function of supplying the wiring BL with a current having the same value as the current IREF flowing through the wiring BLREF or a current corresponding to the current IREF. When setting an offset current, which will be described later, a current flowing between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. When I [j] is different from the current IREF flowing between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1], the difference current flows to the circuit 13 or the circuit 14. The circuit 13 has a function as a current source circuit, and the circuit 14 has a function as a current sink circuit.

Specifically, when the current I [j] is larger than the current IREF, the circuit 13 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. The circuit 13 has a function of supplying the generated current ΔI [j] to the wiring BL [j]. That is, it can be said that the circuit 13 has a function of holding the current ΔI [j].

When the current I [j] is smaller than the current IREF, the circuit 14 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. The circuit 14 has a function of drawing the generated current ΔI [j] from the wiring BL [j]. That is, it can be said that the circuit 14 has a function of holding the current ΔI [j].

Next, an example of the operation of the semiconductor device 107 illustrated in FIG. 15 is described.

First, a potential corresponding to the first analog potential is stored in the memory cell MC [i, j]. Specifically, a potential VPR−Vx [i, j] obtained by subtracting the first analog potential Vx [i, j] from the first reference potential VPR is set to the memory cell MC [i] via the wiring WD [j]. , J]. In the memory cell MC [i, j], the potential VPR−Vx [i, j] is held. In the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR−Vx [i, j] is generated. For example, the first reference potential VPR is a high level potential higher than the ground potential. Specifically, it is desirable that the potential be higher than the ground potential and at the same level as or lower than the high-level potential VDD supplied to the current source circuit 15.

Further, the first reference potential VPR is stored in the memory cell MCR [i]. Specifically, the potential VPR is input to the memory cell MCR [i] through the wiring WDREF. In the memory cell MCR [i], the potential VPR is held. In the memory cell MCR [i], a current IREF [i] corresponding to the potential VPR is generated.

In addition, a potential corresponding to the first analog potential is stored in the memory cell MC [i + 1, j]. Specifically, the potential VPR−Vx [i + 1, j] obtained by subtracting the first analog potential Vx [i + 1, j] from the first reference potential VPR is connected to the memory cell MC [i + 1] via the wiring WD [j]. , J]. In the memory cell MC [i + 1, j], the potential VPR−Vx [i + 1, j] is held. Further, in the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR−Vx [i + 1, j] is generated.

In addition, the first reference potential VPR is stored in the memory cell MCR [i + 1]. Specifically, the potential VPR is input to the memory cell MCR [i + 1] through the wiring WDREF. In the memory cell MCR [i + 1], the potential VPR is held. In the memory cell MCR [i + 1], a current IREF [i + 1] corresponding to the potential VPR is generated.

In the above operation, the wiring RW [i] and the wiring RW [i + 1] are set to the reference potential. For example, a ground potential, a low-level potential VSS lower than the reference potential, or the like can be used as the reference potential. Alternatively, when a potential between the potential VSS and the potential VDD is used as the reference potential, the potential of the wiring RW can be higher than the ground potential even if the second analog potential Vw is positive or negative, so that signal generation is facilitated. This is preferable because product operation can be performed on positive and negative analog data.

Through the above operation, currents that are combined with currents generated in the memory cells MC electrically connected to the wiring BL [j] flow through the wiring BL [j]. Specifically, in FIG. 15, the current I [i, j] generated in the memory cell MC [i, j] and the current I [i + 1, j] generated in the memory cell MC [i + 1, j] are combined. Current I [j] flows. Further, by the above operation, currents that are combined with currents generated in the memory cells MCR electrically connected to the wiring BLREF flow through the wiring BLREF. Specifically, in FIG. 15, a current IREF that is a combination of the current IREF [i] generated in the memory cell MCR [i] and the current IREF [i + 1] generated in the memory cell MCR [i + 1] flows.

Next, from the difference between the current I [j] obtained by the first analog potential and the current IREF obtained by the first reference potential, with the potentials of the wiring RW [i] and the wiring RW [i + 1] being the reference potential. The obtained offset current Ioffset [j] is held in the circuit 13 or the circuit 14.

Specifically, when the current I [j] is larger than the current IREF, the circuit 13 supplies the current Ioffset [j] to the wiring BL [j]. That is, the current ICM [j] flowing through the circuit 13 corresponds to the current Ioffset [j]. Then, the value of the current ICM [j] is held in the circuit 13. When the current I [j] is smaller than the current IREF, the circuit 14 draws the current Ioffset [j] from the wiring BL [j]. That is, the current ICP [j] flowing through the circuit 14 corresponds to the current Ioffset [j]. The value of the current ICP [j] is held in the circuit 14.

Next, the second analog potential is stored in the memory cell MC [i, j] so as to be added to the first analog potential already held in the memory cell MC [i, j]. Specifically, by setting the potential of the wiring RW [i] to a potential higher by Vw [i] than the reference potential, the second analog potential Vw [i] is stored in the memory via the wiring RW [i]. Input to cell MC [i, j]. In the memory cell MC [i, j], the potential VPR−Vx [i, j] + Vw [i] is held. In the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR−Vx [i, j] + Vw [i] is generated.

Further, the second analog potential is stored in the memory cell MC [i + 1, j] so as to be added to the first analog potential already held in the memory cell MC [i + 1, j]. Specifically, by setting the potential of the wiring RW [i + 1] higher by Vw [i + 1] than the reference potential, the second analog potential Vw [i + 1] is stored in the memory through the wiring RW [i + 1]. It is input to the cell MC [i + 1, j]. In the memory cell MC [i + 1, j], the potential VPR−Vx [i + 1, j] + Vw [i + 1] is held. In the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR−Vx [i + 1, j] + Vw [i + 1] is generated.

Note that in the case where the transistor Tr21 that operates in the saturation region is used as an element that converts potential into current, the potential of the wiring RW [i] is Vw [i], and the potential of the wiring RW [i + 1] is Vw [i + 1]. Assuming that the drain current of the transistor Tr21 included in the memory cell MC [i, j] corresponds to the current I [i, j], the second analog current is expressed by the following equation a9. Note that k is a coefficient, and Vth is a threshold voltage of the transistor Tr21.

I [i, j] = k (Vw [i] −Vth + VPR−Vx [i, j]) ² (a9)

Further, since the drain current of the transistor Tr21 included in the memory cell MCR [i] corresponds to the current IREF [i], the second reference current is expressed by the following formula a10.

IREF [i] = k (Vw [i] −Vth + VPR) ² (a10)

The current I [j] corresponding to the sum of the current I [i, j] flowing through the memory cell MC [i, j] and the current I [i + 1, j] flowing through the memory cell MC [i + 1, j] is: I [j] = Σ _i I [i, j], and the current corresponding to the sum of the current IREF [i] flowing through the memory cell MCR [i] and the current IREF [i + 1] flowing through the memory cell MCR [i + 1] IREF becomes IREF = Σ _i IREF [i], and current ΔI [j] corresponding to the difference is expressed by the following equation a11.

ΔI [j] = IREF−I [j] = Σ _i IREF [i] −Σ _i I [i, j] (a11)

From the expressions a9, a10, and a11, the current ΔI [j] is derived as the following expression a12.

ΔI [j]
= Σ _i {k (Vw [i] −Vth + VPR) ² −k (Vw [i] −Vth + VPR−Vx [i, j]) ² }
_{= 2kΣ i (Vw [i]} · Vx [i, j]) - 2kΣ i (Vth-VPR) · Vx [i, j] -kΣ i Vx [i, j] 2 (a12)

In Expression a12, the term represented by 2kΣ _i (Vw [i] · Vx [i, j]) is the product of the first analog potential Vx [i, j] and the second analog potential Vw [i], This corresponds to the sum of the product of the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

Further, Ioffset [j] is when the potential of the wiring RW [i] is all set as the reference potential, that is, when the second analog potential Vw [i] is 0 and the second analog potential Vw [i + 1] is 0. The following equation a13 is derived from the equation a12.

_{Ioffset [j] = - 2kΣ i} (Vth-VPR) · Vx [i, j] -kΣ i Vx [i, j] 2 (a13)

Therefore, 2kΣ _i (Vw [i] · Vx [i, j]) corresponding to the product sum value of the first analog data and the second analog data is expressed by the following expression a14 from the expressions a11 to a13. You can see that

2kΣ _i (Vw [i] · Vx [i, j]) = IREF−I [j] −Ioffset [j] (a14)

When the sum of the currents flowing through the memory cell MC is the current I [j], the sum of the currents flowing through the memory cell MCR is the current IREF, and the current flowing through the circuit 13 or the circuit 14 is the current Ioffset [j], the wiring RW [i ] Is Vw [i] and the wiring RW [i + 1] is Vw [i + 1], the current Iout [j] flowing out of the wiring BL [j] is IREF-I [j] -Ioffset [j]. It is represented by From the equation a14, the current Iout [j] is 2kΣ _i (Vw [i] · Vx [i, j]), and the first analog potential Vx [i, j] and the second analog potential Vw [i]. This is equivalent to the sum of the product of the second analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

Note that the transistor Tr21 is preferably operated in a saturation region, but even if the operation region of the transistor Tr21 is different from an ideal saturation region, the first analog potential Vx [i, j] and the second analog potential are A current corresponding to the sum of the product of Vw [i] and the product of the second analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1] is obtained without any problem with accuracy within a desired range. If it can, the transistor Tr21 can be regarded as operating in the saturation region.

For example, the weight coefficients w _n1 ^{(l) to} w _nM ^(l) of each neuron in the l-th layer are stored as first analog data in the memory cells MC [1, j] to [M, j] in the j-th column, respectively. Then, the outputs z ₁ ^{(l−1) to} z _M ^(l−1) of the neurons in the ^(l−1) -th layer are transferred to the memory cell MC [1, [1-1] through the wirings RW [1] to RW [M]. j] to memory cell MC [M, j] as second analog data. With the above operation, the sum (net value) u _n ^(l) of the inputs to the n-th neuron of the l-th layer can be obtained from the current ΔIout [j]. Therefore, by using the semiconductor device 107, the calculation of Expression a1 can be performed.

For example, the weight coefficients w _n1 ^{(l + 1) to} w _nM ^{(l + 1)} of the neurons in the (l + 1) th layer are used as the first analog data in the memory cells MC [1, j] to [M, j] in the jth column. The outputs z ₁ ^{l to} z _M ^l of the _first layer neurons are stored in the memory cells MC [1, j] to MC [M, j via the wirings RW [1] to RW [M], respectively. ] As second analog data. With the above operation, the sum (net value) u _k ^{(l + 1)} of inputs to the kth neuron in the (l + 1) th layer can be obtained from the current ΔIout [j]. Therefore, by using the semiconductor device 107, the calculation of Expression a3 can be performed.

For example, the weight coefficients w _n1 ^{(l + 1) to} w _nK ^{(l + 1)} of each neuron in the (l + 1) th layer are used as the first analog data in the memory cells MC [1, j] to [K, j] in the jth column. The errors δ ₁ ^{(l + 1) to} δ _K ^{(l + 1)} of the neurons in the ^{(l + 1)} -th layer are stored in the memory cells MC [1, j] to [K through the wirings RW [1] to RW [K], respectively. , J] are input as second analog data. With the above operation, the value of Σ _k δ _k ^{(l + 1)} · w _kn ^{(l + 1) in} the expression a5 can be obtained from the current ΔIout [j]. Therefore, by using the semiconductor device 107, part of the calculation of Expression a5 can be performed.

According to one embodiment of the present invention, arithmetic processing of analog data can be executed without being converted into digital data, so that the circuit scale of the arithmetic circuit can be reduced. Alternatively, according to one embodiment of the present invention, analog data arithmetic processing can be performed without being converted into digital data, so that time required for analog data arithmetic processing can be reduced. Alternatively, according to one embodiment of the present invention, power consumption of an arithmetic circuit can be reduced while suppressing time required for arithmetic processing of analog data.

Next, an example of specific structures of the memory circuit 11 (MEM) and the reference memory circuit 12 (RMEM) will be described with reference to FIGS.

FIG. 16 illustrates a case where the memory circuit 11 (MEM) has a plurality of memory cells MC in y rows and x columns, and the reference memory circuit 12 (RMEM) has a plurality of memory cells MCR in y rows and 1 column. ing.

The memory circuit 11 is electrically connected to the wiring RW, the wiring WW, the wiring WD, the wiring VR, and the wiring BL. In FIG. 16, the wirings RW [1] to RW [y] are electrically connected to the memory cells MC in each row, and the wirings WW [1] to WW [y] are electrically connected to the memory cells MC in each row. The wirings WD [1] to WD [x] are electrically connected to the memory cells MC in each column, and the wirings BL [1] to BL [x] are connected to the memory cells MC in each column. The case where each is electrically connected is illustrated. FIG. 16 illustrates the case where the wirings VR [1] to VR [x] are electrically connected to the memory cells MC in each column. Note that the wirings VR [1] to VR [x] may be electrically connected to each other.

The reference memory circuit 12 is electrically connected to the wiring RW, the wiring WW, the wiring WDREF, the wiring VRREF, and the wiring BLREF. In FIG. 16, the wirings RW [1] to RW [y] are electrically connected to the memory cells MCR in each row, and the wirings WW [1] to WW [y] are electrically connected to the memory cells MCR in each row. , The wiring WDREF is electrically connected to each row of memory cells MCR, the wiring BLREF is electrically connected to each row of memory cells MCR, and the wiring VRREF is electrically connected to each row of memory cells MCR. The case where it is done is illustrated. Note that the wiring VRREF may be electrically connected to the wirings VR [1] to VR [x].

Next, among the plurality of memory cells MC shown in FIG. 16, any two rows and two columns of memory cells MC, and among the plurality of memory cells MCR shown in FIG. 16, any two rows and one column of memory cells MCR. FIG. 17 shows a specific circuit configuration and connection relationship as an example.

Specifically, in FIG. 17, the memory cell MC [i, j] in the i-th row and j-th column, the memory cell MC [i + 1, j] in the i + 1-th row and j-th column, and the memory cell MC [i in the i-th row j + 1-th column. , J + 1] and the memory cell MC [i + 1, j + 1] in the (i + 1) th row and j + 1th column. Specifically, FIG. 17 illustrates the memory cell MCR [i] in the i-th row and the memory cell MCR [i + 1] in the i + 1-th row. Note that i is an arbitrary number from 1 to y-1, and j is an arbitrary number from 1 to x-1.

The i-th row memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i] are electrically connected to the wiring RW [i] and the wiring WW [i]. ing. Further, the memory cell MC [i + 1, j] in the i + 1th row, the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] are electrically connected to the wiring RW [i + 1] and the wiring WW [i + 1]. It is connected.

The memory cell MC [i, j] in the j-th column and the memory cell MC [i + 1, j] are electrically connected to the wiring WD [j], the wiring VR [j], and the wiring BL [j]. Yes. The memory cell MC [i, j + 1] in the j + 1 column and the memory cell MC [i + 1, j + 1] are electrically connected to the wiring WD [j + 1], the wiring VR [j + 1], and the wiring BL [j + 1]. Has been. Further, the memory cell MCR [i] and the memory cell MCR [i + 1] in the (i + 1) th row are electrically connected to the wiring WDREF, the wiring VRREF, and the wiring BLREF.

Each memory cell MC and each memory cell MCR includes a transistor Tr21, a transistor Tr22, and a capacitor C11. The transistor Tr22 has a function of controlling input of the first analog potential to the memory cell MC or the memory cell MCR. The transistor Tr21 has a function of generating an analog current in accordance with the potential input to the gate. The capacitor C11 has a function of adding the second analog potential to the first analog potential held in the memory cell MC or the memory cell MCR.

Specifically, in the memory cell MC illustrated in FIG. 17, the transistor Tr <b> 22 has a gate electrically connected to the wiring WW, one of a source and a drain electrically connected to the wiring WD, and the other of the source and drain is a transistor. It is electrically connected to the gate of Tr21. In the transistor Tr21, one of a source and a drain is electrically connected to the wiring VR, and the other of the source and the drain is electrically connected to the wiring BL. In the capacitor C11, the first electrode is electrically connected to the wiring RW, and the second electrode is electrically connected to the gate of the transistor Tr21.

In the memory cell MCR illustrated in FIG. 17, the transistor Tr22 includes a gate electrically connected to the wiring WW, one of a source and a drain electrically connected to the wiring WDREF, and the other of the source and the drain of the transistor Tr21. It is electrically connected to the gate. In the transistor Tr21, one of a source and a drain is electrically connected to the wiring VRREF, and the other of the source and the drain is electrically connected to the wiring BLREF. In the capacitor C11, the first electrode is electrically connected to the wiring RW, and the second electrode is electrically connected to the gate of the transistor Tr21.

In the memory cell MC, when the gate of the transistor Tr21 is a node N, in the memory cell MC, the first analog potential is input to the node N via the transistor Tr22. Then, when the transistor Tr22 is turned off, the node N is in a floating state. The first analog potential is held at the node N. In the memory cell MC, when the node N is in a floating state, the second analog potential input to the first electrode of the capacitor C11 is applied to the node N. With the above operation, the node N becomes a potential obtained by adding the second analog potential to the first analog potential.

Note that since the potential of the first electrode of the capacitor C11 is applied to the node N via the capacitor C11, in practice, the amount of change in the potential of the first electrode is directly reflected in the amount of change in the potential of the node N. It is not done. Specifically, by multiplying the amount of change in potential of the first electrode by a coupling coefficient that is uniquely determined from the capacitance value of the capacitive element C11, the capacitance value of the gate capacitance of the transistor Tr21, and the capacitance value of the parasitic capacitance. The amount of change in the potential of the node N can be accurately calculated. Hereinafter, in order to make the description easy to understand, it is assumed that the change amount of the potential of the first electrode is reflected in the change amount of the potential of the node N.

The drain current of the transistor Tr21 is determined according to the potential of the node N. Therefore, when the potential of the node N is held by turning off the transistor Tr22, the value of the drain current of the transistor Tr21 is also held. The drain current reflects the first analog potential and the second analog potential.

In addition, when the gate of the transistor Tr21 is the node NREF in the memory cell MCR, the first reference potential is input to the node NREF via the transistor Tr22 in the memory cell MCR, and then the node NREF is in a floating state when the transistor Tr22 is turned off. Thus, the first reference potential is held at the node NREF. In the memory cell MCR, when the node NREF is in a floating state, the second analog potential input to the first electrode of the capacitor C11 is applied to the node NREF. With the above operation, the node NREF becomes a potential obtained by adding the second analog potential to the first reference potential.

The drain current of the transistor Tr21 is determined according to the potential of the node NREF. Therefore, when the potential of the node NREF is held by turning off the transistor Tr22, the value of the drain current of the transistor Tr21 is also held. The drain current reflects the first reference potential and the second analog potential.

If the drain current flowing through the transistor Tr21 of the memory cell MC [i, j] is current I [i, j], and the drain current flowing through the transistor Tr21 of the memory cell MC [i + 1, j] is current I [i + 1, j]. The sum of the currents supplied from the wiring BL [j] to the memory cell MC [i, j] and the memory cell MC [i + 1, j] is the current I [j]. Further, the drain current flowing through the transistor Tr21 of the memory cell MC [i, j + 1] is the current I [i, j + 1], and the drain current flowing through the transistor Tr21 of the memory cell MC [i + 1, j + 1] is the current I [i + 1, j + 1]. Then, a sum of currents supplied from the wiring BL [j + 1] to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] is a current I [j + 1]. Further, when the drain current flowing through the transistor Tr21 of the memory cell MCR [i] is the current IREF [i] and the drain current flowing through the transistor Tr21 of the memory cell MCR [i + 1] is the current IREF [i + 1], the memory cell is connected to the wiring BLREF. The sum of the currents supplied to MCR [i] and memory cell MCR [i + 1] is current IREF.

Next, examples of specific structures of the circuit 13, the circuit 14, and the current source circuit 15 (CREF) will be described with reference to FIG.

18 shows an example of the configuration of the circuit 13, the circuit 14, and the current source circuit 15 corresponding to the memory cell MC and the memory cell MCR shown in FIG. Specifically, the circuit 13 illustrated in FIG. 18 includes a circuit 13 [j] corresponding to the memory cell MC in the jth column and a circuit 13 [j + 1] corresponding to the memory cell MC in the j + 1th column. The circuit 14 illustrated in FIG. 18 includes a circuit 14 [j] corresponding to the memory cell MC in the jth column and a circuit 14 [j + 1] corresponding to the memory cell MC in the j + 1th column.

The circuit 13 [j] and the circuit 14 [j] are electrically connected to the wiring BL [j]. The circuit 13 [j + 1] and the circuit 14 [j + 1] are electrically connected to the wiring BL [j + 1].

The current source circuit 15 is electrically connected to the wiring BL [j], the wiring BL [j + 1], and the wiring BLREF. The current source circuit 15 has a function of supplying the current IREF to the wiring BLREF and a function of supplying the same current as the current IREF or a current corresponding to the current IREF to each of the wiring BL [j] and the wiring BL [j + 1]. Have

Specifically, the circuit 13 [j] and the circuit 13 [j + 1] include transistors Tr27 to Tr29 and a capacitor C13, respectively. In setting the offset current, in the circuit 13 [j], the transistor Tr27 causes the current ICM [corresponding to the difference between the current I [j] and the current IREF when the current I [j] is larger than the current IREF. j]. In the circuit 13 [j + 1], the transistor Tr27 has a function of generating a current ICM [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is larger than the current IREF. Have. The current ICM [j] and the current ICM [j + 1] are supplied from the circuit 13 [j] and the circuit 13 [j + 1] to the wiring BL [j] and the wiring BL [j + 1].

In the circuit 13 [j] and the circuit 13 [j + 1], in the transistor Tr27, one of the source and the drain is electrically connected to the corresponding wiring BL, and the other of the source and the drain is supplied with a predetermined potential. Is electrically connected to the wiring. In the transistor Tr28, one of the source and the drain is electrically connected to the wiring BL, and the other of the source and the drain is electrically connected to the gate of the transistor Tr27. In the transistor Tr29, one of a source and a drain is electrically connected to the gate of the transistor Tr27, and the other of the source and the drain is electrically connected to a wiring to which a predetermined potential is supplied. In the capacitor C13, the first electrode is electrically connected to the gate of the transistor Tr27, and the second electrode is electrically connected to a wiring to which a predetermined potential is supplied.

The gate of the transistor Tr28 is electrically connected to the wiring OSM, and the gate of the transistor Tr29 is electrically connected to the wiring ORM.

Note that FIG. 18 illustrates the case where the transistor Tr27 is a p-channel type and the transistors Tr28 and Tr29 are n-channel type.

The circuit 14 [j] and the circuit 14 [j + 1] include transistors Tr24 to Tr26 and a capacitor C12, respectively. When setting the offset current, in the circuit 14 [j], the transistor Tr24 causes the current ICP [corresponding to the difference between the current I [j] and the current IREF when the current I [j] is smaller than the current IREF. j]. In the circuit 14 [j + 1], the transistor Tr24 has a function of generating a current ICP [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is smaller than the current IREF. Have. The current ICP [j] and the current ICP [j + 1] are drawn from the wiring BL [j] and the wiring BL [j + 1] to the circuit 14 [j] and the circuit 14 [j + 1].

Note that the current ICM [j] and the current ICP [j] correspond to Ioffset [j]. Note that the current ICM [j + 1] and the current ICP [j + 1] correspond to Ioffset [j + 1].

In the circuit 14 [j] and the circuit 14 [j + 1], in the transistor Tr24, one of the source and the drain is electrically connected to the corresponding wiring BL, and the other of the source and the drain is supplied with a predetermined potential. Is electrically connected to the wiring. In the transistor Tr25, one of a source and a drain is electrically connected to the wiring BL, and the other of the source and the drain is electrically connected to the gate of the transistor Tr24. In the transistor Tr26, one of the source and the drain is electrically connected to the gate of the transistor Tr24, and the other of the source and the drain is electrically connected to a wiring to which a predetermined potential is supplied. In the capacitor C12, the first electrode is electrically connected to the gate of the transistor Tr24, and the second electrode is electrically connected to a wiring to which a predetermined potential is supplied.

The gate of the transistor Tr25 is electrically connected to the wiring OSP, and the gate of the transistor Tr26 is electrically connected to the wiring ORP.

Note that FIG. 18 illustrates the case where the transistors Tr24 to Tr26 are n-channel type.

The current source circuit 15 includes a transistor Tr30 corresponding to the wiring BL and a transistor Tr31 corresponding to the wiring BLREF. Specifically, the current source circuit 15 illustrated in FIG. 18 includes, as the transistor Tr30, a transistor Tr30 [j] corresponding to the wiring BL [j] and a transistor Tr30 [j + 1] corresponding to the wiring BL [j + 1]. Is illustrated.

The gate of the transistor Tr30 is electrically connected to the gate of the transistor Tr31. In the transistor Tr30, one of the source and the drain is electrically connected to the corresponding wiring BL, and the other of the source and the drain is electrically connected to a wiring to which a predetermined potential is supplied. In the transistor Tr31, one of a source and a drain is electrically connected to the wiring BLREF, and the other of the source and the drain is electrically connected to a wiring to which a predetermined potential is supplied.

The transistor Tr30 and the transistor Tr31 have the same polarity. FIG. 18 illustrates a case where both the transistor Tr30 and the transistor Tr31 have a p-channel type.

The drain current of the transistor Tr31 corresponds to the current IREF. Since the transistor Tr30 and the transistor Tr31 have a function as a current mirror circuit, the drain current of the transistor Tr30 has almost the same value as the drain current of the transistor Tr31 or a value corresponding to the drain current of the transistor Tr31.

Note that a switch may be provided between the circuit 13 [j] and the circuit 14 [j] illustrated in FIG. Further, a switch may be provided between the circuit 13 [j + 1] and the circuit 14 [j + 1]. Alternatively, a switch may be provided between the transistor Tr31 included in the current source circuit 15 and the reference memory circuit 12.

Next, an example of a specific operation of the semiconductor device 107 according to one embodiment of the present invention will be described with reference to FIGS.

FIG. 19 corresponds to an example of a timing chart showing operations of the memory cell MC and the memory cell MCR shown in FIG. 17 and the circuits 13, 14 and current source circuit 15 shown in FIG. In FIG. 19, the operation of storing the first analog data in the memory cell MC and the memory cell MCR is performed from time T01 to time T04. From time T05 to time T10, an operation of setting an offset current Ioffset in the circuit 13 and the circuit 14 is performed. From time T11 to time T16, an operation of acquiring data corresponding to the product-sum value of the first analog data and the second analog data is performed.

Note that a low-level potential is supplied to the wiring VR [j] and the wiring VR [j + 1]. In addition, all the wirings having a predetermined potential that are electrically connected to the circuit 13 are supplied with the high-level potential VDD. In addition, all wirings having a predetermined potential electrically connected to the circuit 14 are supplied with the low-level potential VSS. In addition, all the wirings having a predetermined potential that are electrically connected to the current source circuit 15 are supplied with the high-level potential VDD.

The transistors Tr21, Tr24, Tr27, Tr30 [j], Tr30 [j + 1], and Tr31 are assumed to operate in the saturation region.

First, from time T01 to time T02, a high-level potential is applied to the wiring WW [i], and a low-level potential is applied to the wiring WW [i + 1]. Through the above operation, the transistor Tr22 is turned on in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i] illustrated in FIG. In addition, the transistor Tr22 is kept off in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1].

From time T01 to time T02, a potential obtained by subtracting the first analog potential from the first reference potential VPR is applied to the wiring WD [j] and the wiring WD [j + 1] illustrated in FIG. Specifically, the potential VPR-Vx [i, j] is applied to the wiring WD [j], and the potential VPR-Vx [i, j + 1] is applied to the wiring WD [j + 1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD + VSS) / 2. Given.

Therefore, the node N [i, j] of the memory cell MC [i, j] illustrated in FIG. 17 is supplied with the potential VPR−Vx [i, j] through the transistor Tr22, and the memory cell MC [i, j + 1]. Node N [i, j + 1] is supplied with the potential VPR-Vx [i, j + 1] through the transistor Tr22, and the node NREF [i] of the memory cell MCR [i] is supplied with the potential VPR through the transistor Tr22. Given.

When the time T02 ends, the potential applied to the wiring WW [i] illustrated in FIG. 17 changes from the high level to the low level, and the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR. In [i], the transistor Tr22 is turned off. Through the above operation, the node N [i, j] holds the potential VPR−Vx [i, j], the node N [i, j + 1] holds the potential VPR−Vx [i, j + 1], and the node NREF [I] holds the potential VPR.

Next, at time T03 to time T04, the potential of the wiring WW [i] illustrated in FIG. 17 is maintained at a low level, and a high-level potential is applied to the wiring WW [i + 1]. Through the above operation, the transistor Tr22 is turned on in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] illustrated in FIG. Further, the transistor Tr22 is kept off in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i].

From time T03 to time T04, a potential obtained by subtracting the first analog potential from the first reference potential VPR is supplied to the wiring WD [j] and the wiring WD [j + 1] illustrated in FIG. Specifically, the potential VPR−Vx [i + 1, j] is applied to the wiring WD [j], and the potential VPR−Vx [i + 1, j + 1] is applied to the wiring WD [j + 1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD + VSS) / 2. Given.

Therefore, the node N [i + 1, j] of the memory cell MC [i + 1, j] illustrated in FIG. 17 is supplied with the potential VPR−Vx [i + 1, j] through the transistor Tr22, and the memory cell MC [i + 1, j + 1]. Node N [i + 1, j + 1] is supplied with the potential VPR-Vx [i + 1, j + 1] via the transistor Tr22, and the node NREF [i + 1] of the memory cell MCR [i + 1] is supplied with the potential VPR via the transistor Tr22. Given.

When the time T04 ends, the potential applied to the wiring WW [i + 1] illustrated in FIG. 17 changes from a high level to a low level, and the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR. At [i + 1], the transistor Tr22 is turned off. Through the above operation, the node N [i + 1, j] holds the potential VPR−Vx [i + 1, j], the node N [i + 1, j + 1] holds the potential VPR−Vx [i + 1, j + 1], and the node NREF [I + 1] holds the potential VPR.

Next, at time T05 to time T06, a high-level potential is applied to the wiring ORP and the wiring ORM illustrated in FIG. In the circuit 13 [j] and the circuit 13 [j + 1] illustrated in FIG. 18, the transistor Tr29 is turned on when a high-level potential is applied to the wiring ORM, and the gate of the transistor Tr27 is reset when the potential VDD is applied. Is done. In the circuit 14 [j] and the circuit 14 [j + 1] illustrated in FIG. 18, the transistor Tr26 is turned on when a high-level potential is applied to the wiring ORP, and the potential VSS is applied to the gate of the transistor Tr24. To reset.

When the time T06 ends, the potentials applied to the wiring ORP and the wiring ORM illustrated in FIG. 18 change from a high level to a low level, the transistor Tr29 is turned off in the circuit 13 [j] and the circuit 13 [j + 1], and the circuit 14 In [j] and the circuit 14 [j + 1], the transistor Tr26 is turned off. With the above operation, the potential VDD is held at the gate of the transistor Tr27 in the circuits 13 [j] and 13 [j + 1], and the potential VSS is held at the gate of the transistor Tr24 in the circuits 14 [j] and 14 [j + 1]. .

Next, at time T07 to time T08, a high-level potential is applied to the wiring OSP illustrated in FIG. In addition, a potential between the potential VSS and the potential VDD, for example, a potential (VDD + VSS) / 2 is supplied as a reference potential to the wiring RW [i] and the wiring RW [i + 1] illustrated in FIG. When the high-level potential is applied to the wiring OSP, the transistor Tr25 is turned on in the circuit 14 [j] and the circuit 14 [j + 1].

When I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, the transistor Tr21 of the memory cell MC [i, j] illustrated in FIG. This means that the sum of the current that can be drawn and the current that can be drawn by the transistor Tr21 of the memory cell MC [i + 1, j] is smaller than the drain current of the transistor Tr30 [j]. Therefore, when the current ΔI [j] is positive and the transistor Tr25 is turned on in the circuit 14 [j], part of the drain current of the transistor Tr30 [j] flows into the gate of the transistor Tr24, and the potential of the gate increases. Begin to. When the drain current of the transistor Tr24 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr24 converges to a predetermined value. The potential of the gate of the transistor Tr24 at this time corresponds to a potential at which the drain current of the transistor Tr24 becomes the current ΔI [j], that is, Ioffset [j] (= ICP [j]). That is, it can be said that the transistor Tr24 of the circuit 14 [j] is set to a current source that can flow the current ICP [j].

Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is positive, the transistor Tr25 is turned on in the circuit 14 [j + 1]. Part of the drain current of the transistor Tr30 [j + 1] flows into the gate of the transistor Tr24, and the potential of the gate starts to rise. When the drain current of the transistor Tr24 becomes substantially equal to the current ΔI [j + 1], the gate potential of the transistor Tr24 converges to a predetermined value. The potential of the gate of the transistor Tr24 at this time corresponds to a potential at which the drain current of the transistor Tr24 becomes the current ΔI [j + 1], that is, Ioffset [j + 1] (= ICP [j + 1]). That is, it can be said that the transistor Tr24 of the circuit 14 [j + 1] is set to a current source that can flow the current ICP [j + 1].

When the time T08 ends, the potential applied to the wiring OSP illustrated in FIG. 18 changes from a high level to a low level, and the transistor Tr25 is turned off in the circuit 14 [j] and the circuit 14 [j + 1]. With the above operation, the potential of the gate of the transistor Tr24 is maintained. Therefore, the circuit 14 [j] maintains a state set as a current source capable of flowing the current ICP [j], and the circuit 14 [j + 1] maintains a state set as a current source capable of flowing the current ICP [j + 1]. To do.

Next, at time T09 to time T10, a high-level potential is applied to the wiring OSM illustrated in FIG. In addition, a potential between the potential VSS and the potential VDD, for example, a potential (VDD + VSS) / 2 is supplied as a reference potential to the wiring RW [i] and the wiring RW [i + 1] illustrated in FIG. When the high-level potential is applied to the wiring OSM, the transistor Tr28 is turned on in the circuit 13 [j] and the circuit 13 [j + 1].

When I [j] flowing through the wiring BL [j] is larger than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is negative, the transistor Tr21 of the memory cell MC [i, j] illustrated in FIG. This means that the sum of the current that can be drawn and the current that can be drawn by the transistor Tr21 of the memory cell MC [i + 1, j] is larger than the drain current of the transistor Tr30 [j]. Therefore, when the current ΔI [j] is negative, when the transistor Tr28 is turned on in the circuit 13 [j], current flows from the gate of the transistor Tr27 to the wiring BL [j], and the potential of the gate starts to decrease. When the drain current of the transistor Tr27 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr27 converges to a predetermined value. At this time, the gate potential of the transistor Tr27 corresponds to a potential at which the drain current of the transistor Tr27 becomes the current ΔI [j], that is, Ioffset [j] (= ICM [j]). That is, it can be said that the transistor Tr27 of the circuit 13 [j] is set to a current source that can flow the current ICM [j].

Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is larger than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is negative, the transistor Tr28 is turned on in the circuit 13 [j + 1]. A current flows from the gate of the transistor Tr27 to the wiring BL [j + 1], and the potential of the gate starts to decrease. When the drain current of the transistor Tr27 becomes substantially equal to the absolute value of the current ΔI [j + 1], the potential of the gate of the transistor Tr27 converges to a predetermined value. The potential of the gate of the transistor Tr27 at this time corresponds to a potential at which the drain current of the transistor Tr27 is equal to the current ΔI [j + 1], that is, the absolute value of Ioffset [j + 1] (= ICM [j + 1]). That is, it can be said that the transistor Tr27 of the circuit 13 [j + 1] is set to a current source that can flow the current ICM [j + 1].

When the time T10 ends, the potential applied to the wiring OSM illustrated in FIG. 18 changes from a high level to a low level, and the transistor Tr28 is turned off in the circuit 13 [j] and the circuit 13 [j + 1]. Through the above operation, the potential of the gate of the transistor Tr27 is maintained. Therefore, the circuit 13 [j] maintains a state set as a current source capable of flowing the current ICM [j], and the circuit 13 [j + 1] maintains a state set as a current source capable of flowing the current ICM [j + 1]. To do.

Note that in the circuit 14 [j] and the circuit 14 [j + 1], the transistor Tr24 has a function of drawing current. Therefore, when the current I [j] flowing through the wiring BL [j] is larger than the current IREF flowing through the wiring BLREF from time T07 to time T08 and ΔI [j] is negative, or the current I flowing through the wiring BL [j + 1] When [j + 1] is larger than the current IREF flowing through the wiring BLREF and ΔI [j + 1] is negative, the current flows from the circuit 14 [j] or the circuit 14 [j + 1] to the wiring BL [j] or the wiring BL [j + 1] without excess or deficiency. May be difficult to supply. In this case, in order to balance the current flowing through the wiring BL [j] or the wiring BL [j + 1] and the current flowing through the wiring BLREF, the transistor Tr21 of the memory cell MC, the circuit 14 [j], or the circuit 14 [j + 1]. ] Transistor Tr24 and transistor Tr30 [j] or Tr30 [j + 1] may be difficult to operate in the saturation region.

Even when ΔI [j] is negative from time T07 to time T08, in order to ensure the operation in the saturation region of the transistor Tr21, Tr24, Tr30 [j], or Tr30 [j + 1], the transistor from time T05 to time T06 Instead of resetting the gate of Tr27 to the potential VDD, the gate potential of the transistor Tr27 may be set to such a level that a predetermined drain current can be obtained. With the above structure, since current is supplied from the transistor Tr27 in addition to the drain current of the transistor Tr30 [j] or Tr30 [j + 1], a current that cannot be drawn in the transistor Tr21 can be drawn to some extent in the transistor Tr24. The operation in the saturation region of the transistors Tr21, Tr24, Tr30 [j] or Tr30 [j + 1] can be ensured.

Note that in the period from time T09 to time T10, when I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, the circuit 14 is processed from time T07 to time T08. Since [j] has already been set as a current source that can flow the current ICP [j], the potential of the gate of the transistor Tr27 in the circuit 13 [j] remains substantially at the potential VDD. Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j + 1] is positive, the circuit 14 [j + 1] is switched to the current ICP from time T07 to time T08. Since the current source that can flow [j + 1] has already been set, the potential of the gate of the transistor Tr27 in the circuit 13 [j + 1] remains substantially at the potential VDD.

Next, at time T11 to time T12, the second analog potential Vw [i] is applied to the wiring RW [i] illustrated in FIG. The wiring RW [i + 1] is still supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as the reference potential. Specifically, the potential of the wiring RW [i] is higher by a potential difference Vw [i] than the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. For easy understanding, it is assumed that the potential of the wiring RW [i] is the potential Vw [i].

When it is assumed that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitor C11 is substantially reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i, j] is VPR−Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR−Vx [i, j + 1] + Vw. [I]. The product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j] is the current obtained by subtracting Ioffset [j] from the current ΔI [j]. In other words, it is reflected in the current Iout [j] flowing out from the wiring BL [j]. The product sum of the first analog data and the second analog data corresponding to the memory cell MC [i, j + 1] is a current obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, the wiring BL [ It can be seen that the current Iout [j + 1] flowing out from j + 1] is reflected.

When the time T12 ends, the wiring RW [i] is again supplied with a potential between the potential VSS and the potential VDD which is the reference potential, for example, the potential (VDD + VSS) / 2.

Next, at time T13 to time T14, the second analog potential Vw [i + 1] is applied to the wiring RW [i + 1] illustrated in FIG. The wiring RW [i] is still supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as the reference potential. Specifically, the potential of the wiring RW [i + 1] is higher by a potential difference Vw [i + 1] than the potential between the reference potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. For ease of explanation, it is assumed that the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

When it is assumed that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitor C11 is reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i + 1, j] is VPR−Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR−Vx [i + 1, j + 1] + Vw. [I + 1]. The product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i + 1, j] is the current obtained by subtracting Ioffset [j] from the current ΔI [j]. That is, it can be seen that it is reflected in Iout [j]. The product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i + 1, j + 1] is a current obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, Iout [j + 1]. ] Is reflected in the

When the time T14 ends, the wiring RW [i + 1] is again supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2.

Next, at time T15 to time T16, the second analog potential Vw [i] is supplied to the wiring RW [i] illustrated in FIG. 17, and the second analog potential Vw [i + 1] is supplied to the wiring RW [i + 1]. . Specifically, the potential of the wiring RW [i] is higher by a potential difference Vw [i] than a potential between the reference potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, and the wiring RW [i] The potential of (i + 1) is higher than the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 by a potential difference Vw [i + 1]. Further, it is assumed that the potential of the wiring RW [i] is the potential Vw [i] and the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

When it is assumed that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitor C11 is substantially reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i, j] is VPR−Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR−Vx [i, j + 1] + Vw. [I]. Further, when it is assumed that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitor C11 is substantially reflected in the amount of change in the potential of the node N, FIG. The potential of the node N in the memory cell MC [i + 1, j] shown is VPR−Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR−Vx [i + 1, j + 1. ] + Vw [i + 1].

From the above equation a14, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j] and the memory cell MC [i + 1, j] is the current ΔI [j ] Is subtracted from Ioffset [j], that is, the current Iout [j] is reflected. Further, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] is obtained from the current ΔI [j + 1] to Ioffset [j + 1]. It can be seen that the current is subtracted from the current Iout [j + 1].

When the time T16 ends, the wiring RW [i] and the wiring RW [i + 1] are again supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2.

With the above configuration, the product-sum operation can be performed with a small circuit scale. In addition, with the above configuration, the product-sum operation can be performed at high speed. In addition, with the above configuration, the product-sum operation can be performed with low power consumption.

Note that transistors Tr22, Tr25, Tr26, Tr28, and Tr29 are preferably transistors with extremely low off-state current. By using a transistor with extremely low off-state current as the transistor Tr22, the potential of the node N can be held for a long time. Further, by using transistors with extremely low off-state current for the transistors Tr25 and Tr26, the potential of the gate of the transistor Tr24 can be held for a long time. Further, by using transistors with extremely low off-state current for the transistors Tr28 and Tr29, the potential of the gate of the transistor Tr27 can be held for a long time.

In order to reduce the off-state current of the transistor, for example, a channel formation region may be formed using a semiconductor with a wide band gap. As described above, a semiconductor having a large band gap may refer to a semiconductor having a band gap of 2.2 eV or more. As such a semiconductor material, an oxide semiconductor can be given. OS transistors may be used as the transistors Tr22, Tr25, Tr26, Tr28, and Tr29.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 5)
In this embodiment, a more specific structure example of the display unit 110 described in Embodiment 1 will be described. Note that in this embodiment, a display device (also referred to as an active organic EL display) in which an organic EL element is used as a light-emitting element and a transistor is included in each pixel is described.

<< Example of pixel circuit >>
FIG. 20A is a circuit example of the pixel 10 that can be used for a display device including an organic EL element. FIG. 20B is a timing chart illustrating an operation example of the pixel 10 illustrated in FIG.

The pixel 10 is electrically connected to the scanning line GL, the signal line SL, the wiring ML, the wiring CTL, and the wiring ANL. In addition, the pixel 10 includes transistors 221 to 223, a capacitor 224, and an organic EL element 227.

The organic EL element 227 is a light-emitting element (also referred to as an “EL element”) that uses electroluminescence. The organic EL element 227 has a pair of electrodes (anode and cathode), and the luminance can be controlled by current or voltage. An organic EL element has a layer containing a light-emitting organic compound (also referred to as an “EL layer”) between a pair of electrodes. When a potential difference larger than the threshold voltage of the organic EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the light-emitting substance contained in the EL layer emits light.

In FIG. 20A, the transistors 221 to 223 are n-type transistors, but some or all of them may be p-type transistors. In addition, the transistors 221 to 223 each include a back gate that is electrically connected to the gate. With such a device structure, the current driving capability of the transistors 221 to 223 can be improved. A part or all of the transistors 221 to 223 may have no back gate.

The transistor 221 is a pass transistor that connects between the gate (node 225) of the transistor 222 and the signal line SL. The transistor 223 is a pass transistor that connects between the wiring ML and the anode of the organic EL element 227. The transistor 222 is a drive transistor and functions as a current source that supplies current to the organic EL element 227. The luminance of the organic EL element 227 is adjusted by the magnitude of the drain current of the transistor 222. The capacitor 224 is a storage capacitor that holds a voltage between the node 226 and the node 225.

When the driving capability of the transistor 222 varies, the luminance of the organic EL element 227 varies for each pixel 10 and the display quality is deteriorated. A pixel 10 illustrated in FIG. 20A has a function of correcting luminance variation of the organic EL element 227 by monitoring the drain current of the transistor 222.

FIG. 20B illustrates a timing chart of the potential of the scanning line GL illustrated in FIG. 20A and the image signal supplied to the signal line SL. Note that the timing chart illustrated in FIG. 20B illustrates the case where all the transistors included in the pixel 10 are n-channel transistors.

The period P1 is a writing operation period, and the organic EL element 227 does not emit light. A high-level potential is applied to the scan line GL, so that the transistors 221 and 223 are turned on. The signal line SL is supplied with the potential Vdata as an image signal. The potential Vdata is supplied to the node 225 through the transistor 221.

When the transistor 222 is an n-channel transistor, in the period P1, the potential of the wiring ML is lower than a potential obtained by adding the threshold voltage Vthe of the organic EL element 227 to the potential of the wiring CTL, and the potential of the wiring ANL is lower than that of the wiring ML. Desirably higher than the potential. With the above structure, the drain current of the transistor 222 can flow preferentially through the wiring ML instead of the organic EL element 227.

The period P2 is a light emission period, and the organic EL element 227 emits light. A low-level potential is applied to the scan line GL, so that the transistors 221 and 223 are turned off. When the transistor 221 is turned off, the potential Vdata is maintained at the node 225. A potential Vano is applied to the wiring ANL, and a potential Vcat is applied to the wiring CTL. The potential Vano is desirably higher than the potential obtained by adding the threshold voltage Vthe of the organic EL element 227 to the potential Vcat. By providing the potential difference between the wiring ANL and the wiring CTL, the drain current of the transistor 222 is supplied to the organic EL element 227, and the organic EL element 227 emits light.

Next, the period P <b> 3 is a monitoring period for acquiring the drain current of the transistor 222. A high-level potential is applied to the scan line GL, so that the transistors 221 and 223 are turned on. A potential is applied to the signal line SL such that the gate voltage of the transistor 222 is higher than the threshold voltage Vth. The potential of the wiring ML is preferably lower than the potential obtained by adding the threshold voltage Vthe of the organic EL element 227 to the potential of the wiring CTL, and the potential of the wiring ANL is preferably higher than the potential of the wiring ML. With the above structure, the drain current of the transistor 222 can flow preferentially through the wiring ML instead of the organic EL element 227.

A current I _MON output from the pixel 10 to the wiring ML in the period P3 corresponds to a drain current flowing in the transistor 222 during the light emission period. The current I _MON is supplied to the monitor circuit. The monitor circuit analyzes the current I _MON and generates a correction signal based on the analysis result. Through the above operation, the pixel 10 can correct the luminance shift.

It is not always necessary to perform the above monitor operation after the light emission operation. For example, in the pixel 10, the monitoring operation can be performed after the cycle of data writing operation and light emitting operation is repeated a plurality of times. Alternatively, the organic EL element 227 may be brought into a non-light emitting state by writing a data signal corresponding to the minimum gradation value [0] to the pixel 10 after the monitor operation.

A pixel 10 illustrated in FIG. 20A may be connected to a plurality of scan lines. A circuit diagram in that case is shown in FIG. In the pixel 10 illustrated in FIG. 21A, the gate of the transistor 221 is electrically connected to the scan line GL1, and the gate of the transistor 223 is electrically connected to the scan line GL2. In this manner, the timing of the monitoring operation can be controlled more freely by individually controlling on / off of the transistor 221 and the transistor 223.

In the pixel 10 illustrated in FIG. 20A, the transistors 221 to 223 are not necessarily provided with a back gate. A circuit diagram in that case is shown in FIG. With the structure shown in FIG. 21B, the manufacturing process of the pixel 10 can be facilitated.

<< Configuration Example of Display Device >>
FIG. 22A is a cross-sectional configuration example illustrating part of the portion indicated by the chain line N1-N2 in FIG.

The pixel 10 and the gate driver 113 provided over the first substrate 4001 illustrated in FIG. 22A each include a plurality of transistors. In FIG. 22A, the transistor 4010 included in the pixel 10 and the gates are included. A transistor 4011 included in the driver 113 is illustrated. An insulating layer 4112 is provided over the transistors 4010 and 4011, and a partition wall 4510 is formed over the insulating layer 4112.

In addition, the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. In addition, the transistor 4010 and the transistor 4011 each include an electrode 517 formed over the insulating layer 4102, and the insulating layer 4103 is formed over the electrode 517. A semiconductor layer 512 is formed over the insulating layer 4103. An electrode 510 and an electrode 511 are formed over the semiconductor layer 512, an insulating layer 4110 and an insulating layer 4111 are formed over the electrode 510 and the electrode 511, and an electrode 516 is formed over the insulating layer 4110 and the insulating layer 4111.

In the transistor 4010 and the transistor 4011, the semiconductor layer 512 functions as a channel formation region, the electrode 517 functions as a gate electrode, the electrode 510 functions as one of a source electrode and a drain electrode, The electrode 511 functions as the other of the source electrode and the drain electrode, and the electrode 516 functions as a back gate electrode. The transistor 4010 and the transistor 4011 each have a bottom gate and a back gate, so that on-state current can be increased. In addition, the threshold value of the transistor can be controlled.

In the case where an OS transistor is used as the transistor 4010, the OS transistor can reduce a current value in an off state (off-state current value). Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

In addition, the display device illustrated in FIG. 22A includes a capacitor 4020. The capacitor 4020 has a region where the electrode 511 and the electrode 4021 overlap with each other with the insulating layer 4103 interposed therebetween. The electrode 4021 is formed using the same conductive layer as the electrode 517.

In the display device, a black matrix (light-shielding layer), an optical member (optical substrate) such as a polarizing member, a retardation member, and an antireflection member, and the like may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used.

FIG. 22A illustrates an example in which an organic EL element is used as the light-emitting element 4513. In the organic EL element, by applying a voltage, electrons from one electrode and holes from the other electrode are injected into the EL layer. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element. Note that in addition to the light-emitting compound, the EL layer includes a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, Material (a material having a high electron transporting property and a high hole transporting property) may be included. The EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.

In FIG. 22A, the light-emitting element 4513 is electrically connected to a transistor 4010 provided in the pixel 10. Note that the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4030, the EL layer 4511, and the second electrode layer 4031; however, the structure is not limited to this structure. The structure of the light-emitting element 4513 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4513, or the like. In addition, the EL layer 4511 may be formed of a single layer or a stack of a plurality of layers.

A partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material and form an opening on the first electrode layer 4030 so that the side surface of the opening is an inclined surface formed with a continuous curvature.

A protective layer may be formed over the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 4513. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed. In addition, a filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and sealed. As described above, it is preferable to package (enclose) the protective film with a protective film (bonded film, ultraviolet curable resin film, or the like) or a cover material that has high hermeticity and little degassing so as not to be exposed to the outside air.

As the filler 4514, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon. PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB ( Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Further, the filler 4514 may contain a desiccant.

As the sealant 4005, a glass material such as glass frit, or a resin material such as a two-component mixed resin, a curable resin that cures at normal temperature, a photocurable resin, or a thermosetting resin can be used. Further, the sealing material 4005 may contain a desiccant.

If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the light emitting element exit surface. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

In addition, when the light-emitting element has a microcavity structure, light with high color purity can be extracted. Further, by combining the microcavity structure and the color filter, the reflection can be reduced and the visibility of the display image can be improved.

The first electrode layer 4030 and the second electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide. A light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

The first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). , Chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) and other metals, or alloys thereof, or One or more metal nitrides can be used.

Alternatively, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

In order for the light-emitting element 4513 to extract light to the outside, at least one of the first electrode layer 4030 and the second electrode layer 4031 only needs to be transparent. Display devices are classified into a top emission (top emission) structure, a bottom emission (bottom emission) structure, and a double emission (dual emission) structure depending on how light is extracted. The top emission structure refers to a case where light is extracted from a surface (upper surface) opposite to a substrate over which a transistor and a light-emitting element are formed. The bottom emission structure refers to a case where light is extracted from a surface (lower surface) of a substrate over which a transistor and a light emitting element are formed. The double emission structure refers to a case where light is extracted from both the upper surface and the lower surface. For example, in the case of a top emission structure, the second electrode layer 4031 may be transparent. For example, in the case of a bottom emission structure, the first electrode layer 4030 may be transparent. For example, in the case of a dual emission structure, the first electrode layer 4030 and the second electrode layer 4031 may be transparent.

FIG. 22B is a cross-sectional view in the case where a top-gate transistor is provided for the transistors 4011 and 4010 illustrated in FIG. In the transistors 4010 and 4011 in FIG. 22B, the electrode 517 functions as a gate electrode, the electrode 510 functions as one of a source electrode and a drain electrode, and the electrode 511 functions as a source electrode or a drain electrode. It functions as the other. The description of FIG. 22A may be referred to for the other components in FIG.

FIG. 22C illustrates a cross-sectional view in the case where the transistor 4011 and the transistor 4010 illustrated in FIG. 22B are provided with the electrode 516 functioning as a back gate. The transistor 4010 and the transistor 4011 each have a top gate and a back gate, so that on-state current can be increased. In addition, the threshold value of the transistor can be controlled. The description of FIG. 22A may be referred to for the other components in FIG.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 6)
In this embodiment, a structure example of a display device in which a reflective element and a light-emitting element are combined is described as a display device applicable to the display unit 110 described in Embodiment 1. It is a hybrid display device in which a reflective element and a light emitting element are provided in one pixel, and a reflective element is used in a bright environment and a light emitting element is used in a dark environment. It is possible to provide a display device that has excellent display quality and low power consumption. Note that liquid crystal, electronic paper, or the like can be applied as the reflective element. Hereinafter, the reflective element will be described as the reflective element 30a, and the light emitting element will be described as the light emitting element 30b.

<Display unit>
A display unit 310 illustrated in FIG. 23 includes a pixel array 311, a gate driver 313, a gate driver 314, and a controller IC 119.

The pixel array 311 includes a plurality of pixels 30, and each pixel 30 is an active element that is driven using a transistor. The pixel 30 includes a reflective element 30a and a light emitting element 30b.

The gate driver 313 has a function of driving a gate line for selecting the reflective element 30a, and the gate driver 314 has a function of driving a gate line for selecting the light emitting element 30b. A source driver that drives a source line that supplies a data signal to the reflective element 30a and a source driver that drives a source line that supplies a data signal to the light emitting element 30b are provided in the controller IC 119, respectively. The number of controller ICs 119 is determined according to the number of pixels in the pixel array.

In the example of FIG. 23, the gate driver 313 and 314 are integrated on the same substrate together with the pixel array 311, but the gate driver 313 and 314 may be a dedicated IC. Alternatively, the gate driver 313 or the gate driver 314 may be incorporated in the controller IC 119.

<Controller IC>
FIG. 24 is a block diagram illustrating a configuration example of the controller IC 119. The controller IC 119 includes an interface 150, a frame memory 151, a decoder 152, a sensor controller 153, a controller 154, a clock generation circuit 155, an image processing unit 160, a memory 170, a timing controller 173, a register 175, a source driver 180, and a touch sensor controller 184. Have Note that the touch sensor unit 120 may be combined with the display unit 310 as in the first embodiment.

The source driver 180 includes source drivers 181 and 182. The source driver 181 is a driver for driving the reflective element 30a, and the source driver 182 is a driver for driving the light emitting element 30b. Here, a controller IC in the case where the reflective element 30a is a liquid crystal (LC) element and the light emitting element 30b is an organic EL element will be described.

When the reflective element 30a and the light emitting element 30b display the same image data, the image processing unit 160 has a function of separately creating image data displayed by the reflective element 30a and image data displayed by the light emitting element 30b. . In this case, the reflection intensity of the reflection element 30a and the emission intensity of the light emitting element 30b can be adjusted according to the brightness of the light 145 measured using the optical sensor 143 and the sensor controller 153. Here, the adjustment is referred to as dimming or dimming processing. A circuit that executes the processing is called a dimming circuit.

For example, when the display unit 310 is used outside on a sunny day, it is not necessary to light up the light emitting element 30b when sufficient luminance can be obtained only by the reflecting element 30a. Further, when the display unit 310 is used at night or in a dark place, the light emitting element 30b is illuminated to perform display.

Depending on the brightness of external light, the image processing unit 160 creates image data to be displayed only by the reflective element 30a, or creates image data to be displayed only by the light emitting element 30b, or the reflective element 30a and the light emitting element 30b. It is possible to create image data to be displayed in combination. The display unit 310 can perform good display both in an environment with bright external light and in an environment with dark external light.

In an environment where the outside light is bright, the power consumption can be reduced by not making the light emitting element 30b shine or by reducing the luminance of the light emitting element 30b. Alternatively, even in an environment with bright external light, color reproducibility and visibility can be improved by causing the light emitting element 30b to shine in addition to the display by the reflective element 30a.

In addition, the color tone can be corrected by combining the display of the light emitting element 30b with the display of the reflective element 30a. For such color tone correction, a function for measuring the color tone of the light 145 may be added to the optical sensor 143 and the sensor controller 153. For example, when the display unit 310 is used in a reddish environment at dusk, only the display by the reflective element 30a is insufficient for the B (blue) component. Therefore, the color tone is obtained by emitting light from the B (blue) pixel of the light emitting element 30b. Can be corrected. Here, the correction is referred to as toning or toning processing. A circuit that executes the processing is called a toning circuit.

Further, the reflective element 30a and the light emitting element 30b can display different image data. In general, liquid crystal, electronic paper, and the like that can be applied as a reflective element often have a slow operation speed (it takes time to display a picture). Therefore, a still image as a background can be displayed on the reflective element 30a, and a moving mouse pointer or the like can be displayed on the light emitting element 30b. The IDS drive described above is performed for a still image, and the light emitting element 30b is illuminated for a moving image, whereby the display unit 310 can achieve both smooth moving image display and low power consumption. In this case, the frame memory 151 may be provided with an area for storing image data to be displayed on each of the reflective element 30a and the light emitting element 30b.

<< Configuration example of display unit >>
FIG. 25 is a block diagram illustrating a configuration example of the display unit 310.

The display unit 310 has a pixel array 311. The display unit 310 can include a gate driver GD or a source driver SD.

<Pixel array 311>
The pixel array 311 scans with a group of a plurality of pixels 702 (i, 1) to 702 (i, n) and another group of a plurality of pixels 702 (1, j) to 702 (m, j). Line G1 (i). In addition, the scanning line G2 (i), the wiring CSCOM, the wiring ANO, and the signal line S2 (j) are included. Note that i is an integer of 1 to m, j is an integer of 1 to n, and m and n are integers of 1 or more.

A group of the plurality of pixels 702 (i, 1) to 702 (i, n) includes a pixel 702 (i, j), and a group of the plurality of pixels 702 (i, 1) to 702 (i, n) includes Arranged in the row direction (direction indicated by arrow R1 in the figure).

The other group of the plurality of pixels 702 (1, j) to 702 (m, j) includes the pixel 702 (i, j), and the other group of the plurality of pixels 702 (1, j) to 702 ( m, j) are arranged in a column direction (direction indicated by an arrow C1 in the drawing) intersecting the row direction.

The scan line G1 (i) and the scan line G2 (i) are electrically connected to a group of the plurality of pixels 702 (i, 1) to 702 (i, n) arranged in the row direction.

Another group of the plurality of pixels 702 (1, j) to 702 (m, j) arranged in the column direction is electrically connected to the signal line S1 (j) and the signal line S2 (j). .

<Gate driver GD>
The gate driver GD has a function of supplying a selection signal based on the control information.

For example, a function of supplying a selection signal to one scanning line at a frequency of 30 Hz or higher, preferably 60 Hz or higher is provided based on the control information. Thereby, a moving image can be displayed smoothly.

For example, a function of supplying a selection signal to one scanning line at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute based on the control information is provided. Thereby, a still image can be displayed in a state where flicker is suppressed.

<Source Driver SD, Source Driver SD1, Source Driver SD2>
The source driver SD includes a source driver SD1 and a source driver SD2. The source driver SD1 and the source driver SD2 have a function of supplying a data signal based on a signal from the controller IC 119.

The source driver SD1 has a function of generating a data signal to be supplied to a pixel circuit that is electrically connected to one display element. Specifically, it has a function of generating a signal whose polarity is inverted. Thereby, for example, a liquid crystal display element can be driven.

The source driver SD2 generates a data signal to be supplied to a pixel circuit electrically connected to another display element (hereinafter also referred to as a second display element) that displays using a method different from that of the one display element. It has a function to do. For example, an organic EL element can be driven.

For example, various sequential circuits such as a shift register can be used for the source driver SD.

For example, an integrated circuit in which the source driver SD1 and the source driver SD2 are integrated can be used for the source driver SD. Specifically, an integrated circuit formed on a silicon substrate can be used for the source driver SD.

The source driver SD may be included in the same integrated circuit as the controller IC 119. Specifically, an integrated circuit formed on a silicon substrate can be used for the controller IC 119 and the source driver SD.

For example, the integrated circuit can be mounted using a COG (Chip on glass) method or a COF (Chip on Film) method. Specifically, an integrated circuit can be mounted on a terminal using an anisotropic conductive film.

<Pixel circuit>
FIG. 26 is a circuit diagram illustrating a configuration example of the pixel 702. The pixel 702 (i, j) has a function of driving the reflective element 30a (i, j) and the light emitting element 30b (i, j). Thus, for example, the reflective element 30a and the light emitting element 30b that performs display using a method different from the reflective element 30a can be driven using a pixel circuit that can be formed using the same process. . By performing display using the reflective display element, the reflective element 30a, power consumption can be reduced. Alternatively, an image can be favorably displayed with high contrast in an environment where the outside light is bright. By performing display using the display element that emits light and the light-emitting element 30b, an image can be favorably displayed in a dark environment.

The pixel 702 (i, j) is electrically connected to the signal line S1 (j), the signal line S2 (j), the scanning line G1 (i), the scanning line G2 (i), the wiring CSCOM, and the wiring ANO.

The pixel 702 (i, j) includes a switch SW1, a capacitor C21, a switch SW2, a transistor M, and a capacitor C22.

A transistor including a gate electrode electrically connected to the scan line G1 (i) and a first electrode electrically connected to the signal line S1 (j) can be used for the switch SW1.

The capacitor C21 includes a first electrode that is electrically connected to the second electrode of the transistor used for the switch SW1, and a second electrode that is electrically connected to the wiring CSCOM.

A transistor including a gate electrode electrically connected to the scan line G2 (i) and a first electrode electrically connected to the signal line S2 (j) can be used for the switch SW2.

The transistor M includes a gate electrode that is electrically connected to the second electrode of the transistor used for the switch SW2, and a first electrode that is electrically connected to the wiring ANO.

Note that the transistor M may include a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode may be electrically connected. The first gate electrode and the second gate electrode preferably have regions overlapping each other with a semiconductor film interposed therebetween.

The capacitor C22 includes a first electrode electrically connected to the second electrode of the transistor used for the switch SW2, and a second electrode electrically connected to the first electrode of the transistor M. .

The first electrode of the reflective element 30a (i, j) is electrically connected to the second electrode of the transistor used for the switch SW1. In addition, the second electrode of the reflective element 30a (i, j) is electrically connected to the wiring VCOM1. Thereby, the reflective element 30a (i, j) can be driven.

The first electrode of the light emitting element 30b (i, j) is electrically connected to the second electrode of the transistor M, and the second electrode of the light emitting element 30b (i, j) is electrically connected to the wiring VCOM2. . Thereby, the light emitting element 30b (i, j) can be driven.

<Top view of display unit>
FIG. 27 is a diagram for explaining the configuration of the display unit 310. 27A is a top view of the display unit 310, and FIG. 27B is a top view illustrating part of the pixels of the display unit 310 illustrated in FIG. 27A. FIG. 27C is a schematic diagram illustrating a structure of the pixel shown in FIG.

In FIG. 27A, the source driver SD and the terminal 519B are arranged on the flexible printed circuit board FPC1.

In FIG. 27C, a pixel 702 (i, j) includes a reflective element 30a (i, j) and a light-emitting element 30b (i, j).

<Cross section of display unit>
28 and 29 are cross-sectional views illustrating the configuration of the display unit 310. FIG. 28A is a cross-sectional view taken along the cutting line X1-X2, the cutting line X3-X4, and the cutting line X5-X6 of FIG. 27A and B, and FIG. 28B is a cross-sectional view of FIG. It is a figure explaining a part of.

FIG. 29A is a cross-sectional view taken along section line X7-X8 and section line X9-X10 of FIG. 27A and FIG. 27B, and FIG. 29B illustrates part of FIG. FIG.

Hereinafter, each component of the display unit 310 will be described with reference to FIGS. 28 and 29.

<Substrate 570>
A material having heat resistance high enough to withstand heat treatment in the manufacturing process can be used for the substrate 570 or the like. For example, a material having a thickness of 0.7 mm or less and a thickness of 0.1 mm or more can be used for the substrate 570. Specifically, a material polished to a thickness of about 0.1 mm can be used.

For example, the areas of the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation (2950 mm × 3400 mm), etc. A large glass substrate can be used for the substrate 570 or the like. Thus, a large display device can be manufactured.

An organic material, an inorganic material, a composite material of an organic material and an inorganic material, or the like can be used for the substrate 570 or the like. For example, an inorganic material such as glass, ceramics, or metal can be used for the substrate 570 or the like.

Specifically, alkali-free glass, soda-lime glass, potash glass, crystal glass, aluminosilicate glass, tempered glass, chemically tempered glass, quartz, sapphire, or the like can be used for the substrate 570 or the like. Specifically, an inorganic oxide film, an inorganic nitride film, an inorganic oxynitride film, or the like can be used for the substrate 570 or the like. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, or the like can be used for the substrate 570 or the like. Stainless steel, aluminum, or the like can be used for the substrate 570 or the like.

For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used for the substrate 570 or the like. Thereby, a semiconductor element can be formed on the substrate 570 or the like.

For example, an organic material such as a resin, a resin film, or plastic can be used for the substrate 570 or the like. Specifically, a resin film or a resin plate such as polyester, polyolefin, polyamide, polyimide, polycarbonate, or an acrylic resin can be used for the substrate 570 or the like.

For example, a composite material in which a film such as a metal plate, a thin glass plate, or an inorganic material is bonded to a resin film or the like can be used for the substrate 570 or the like. For example, a composite material in which a fibrous or particulate metal, glass, inorganic material, or the like is dispersed in a resin film can be used for the substrate 570 or the like. For example, a composite material in which a fibrous or particulate resin, an organic material, or the like is dispersed in an inorganic material can be used for the substrate 570 or the like.

In addition, a single layer material or a material in which a plurality of layers are stacked can be used for the substrate 570 or the like. For example, a material in which a base material and an insulating film that prevents diffusion of impurities contained in the base material are stacked can be used for the substrate 570 or the like. Specifically, a material in which one or a plurality of films selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like that prevents diffusion of impurities contained in glass is used for the substrate 570 or the like. be able to. Alternatively, a material in which a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like, which prevents resin and diffusion of impurities that permeate the resin from being stacked, can be used for the substrate 570 or the like.

Specifically, a resin film such as polyester, polyolefin, polyamide, polyimide, polycarbonate, or an acrylic resin, a resin plate, a laminated material, or the like can be used for the substrate 570 or the like.

Specifically, a material including a resin having a siloxane bond such as polyester, polyolefin, polyamide (nylon, aramid, or the like), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, or silicone can be used for the substrate 570 or the like.

Specifically, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic resin, or the like can be used for the substrate 570 or the like. Alternatively, a cycloolefin polymer (COP), a cycloolefin copolymer (COC), or the like can be used.

Further, paper, wood, or the like can be used for the substrate 570 or the like.

For example, a flexible substrate can be used for the substrate 570 or the like.

Note that a method of directly forming a transistor, a capacitor, or the like over a substrate can be used. Alternatively, for example, a method can be used in which a transistor, a capacitor, or the like is formed over a substrate for a process that has heat resistance to heat applied during the manufacturing process, and the formed transistor, capacitor, or the like is transferred to the substrate 570 or the like. Thus, for example, a transistor or a capacitor can be formed over a flexible substrate.

<Substrate 770>
For example, a material having a light-transmitting property can be used for the substrate 770. Specifically, a material selected from materials that can be used for the substrate 570 can be used for the substrate 770.

For example, aluminosilicate glass, tempered glass, chemically tempered glass, sapphire, or the like can be suitably used for the substrate 770 disposed on the side close to the user of the display unit. Thereby, it is possible to prevent the display unit from being damaged or damaged due to use.

For example, a material having a thickness of 0.7 mm or less and a thickness of 0.1 mm or more can be used for the substrate 770. Specifically, a polished substrate can be used to reduce the thickness. Accordingly, the functional film 770D can be disposed close to the reflective element 30a (i, j). As a result, blurring of the image can be reduced and the image can be clearly displayed.

<Structure KB1>
For example, an organic material, an inorganic material, or a composite material of an organic material and an inorganic material can be used for the structure KB1 or the like. Thereby, a predetermined space | interval can be provided between the structures which pinch | interpose structure KB1 grade | etc.,.

Specifically, polyester, polyolefin, polyamide, polyimide, polycarbonate, polysiloxane, acrylic resin, or a composite material of a plurality of resins selected from these can be used for the structure KB1. Alternatively, a material having photosensitivity may be used.

<Sealing material 705>
An inorganic material, an organic material, a composite material of an inorganic material and an organic material, or the like can be used for the sealing material 705 or the like.

For example, an organic material such as a heat-meltable resin or a curable resin can be used for the sealing material 705 or the like.

For example, an organic material such as a reactive curable adhesive, a photocurable adhesive, a thermosetting adhesive, and / or an anaerobic adhesive can be used for the sealing material 705 or the like.

Specifically, an adhesive including epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin, and the like. Can be used for the sealing material 705 or the like.

<Junction layer 505>
For example, a material that can be used for the sealing material 705 can be used for the bonding layer 505.

<Insulating Film 521, Insulating Film 518>
For example, an insulating inorganic material, an insulating organic material, or an insulating composite material including an inorganic material and an organic material can be used for the insulating films 521 and 518 and the like.

Specifically, an inorganic oxide film, an inorganic nitride film, an inorganic oxynitride film, or the like, or a stacked material in which a plurality selected from these films is stacked can be used for the insulating films 521, 518, and the like. For example, a film including a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, or a stacked material in which a plurality of layers selected from these films is stacked can be used for the insulating films 521 and 518 and the like.

Specifically, polyester, polyolefin, polyamide, polyimide, polycarbonate, polysiloxane, acrylic resin, or the like, or a laminated material or a composite material of a plurality of resins selected from these is used for the insulating films 521, 518, and the like. it can. Alternatively, a material having photosensitivity may be used.

Accordingly, for example, steps originating from various structures overlapping with the insulating films 521 and 518 can be planarized.

<Insulating film 528>
For example, a material that can be used for the insulating film 521 can be used for the insulating film 528 or the like. Specifically, a film containing polyimide with a thickness of 1 μm can be used for the insulating film 528.

<Insulating film 501A>
For example, a material that can be used for the insulating film 521 can be used for the insulating film 501A. For example, a material having a function of supplying hydrogen can be used for the insulating film 501A.

Specifically, a material in which a material containing silicon and oxygen and a material containing silicon and nitrogen are stacked can be used for the insulating film 501A. For example, a material having a function of releasing hydrogen by heating or the like and supplying the released hydrogen to another structure can be used for the insulating film 501A. Specifically, a material having a function of releasing hydrogen taken in during the manufacturing process by heating or the like and supplying the hydrogen to another structure can be used for the insulating film 501A.

For example, a film containing silicon and oxygen formed by a chemical vapor deposition method using silane or the like as a source gas can be used for the insulating film 501A.

Specifically, a material in which a material including silicon and oxygen having a thickness of 200 nm to 600 nm and a material including silicon and nitrogen and having a thickness of about 200 nm can be used for the insulating film 501A.

<Insulating film 501C>
For example, a material that can be used for the insulating film 521 can be used for the insulating film 501C. Specifically, a material containing silicon and oxygen can be used for the insulating film 501C. Thereby, the diffusion of impurities into the pixel circuit or the second display element can be suppressed.

For example, a 200-nm-thick film containing silicon, oxygen, and nitrogen can be used for the insulating film 501C.

<Intermediate film 754A, intermediate film 754B, intermediate film 754C>
For example, a film having a thickness of 10 nm to 500 nm, preferably 10 nm to 100 nm can be used for the intermediate film 754A, the intermediate film 754B, or the intermediate film 754C. Note that in this specification, the intermediate film 754A, the intermediate film 754B, or the intermediate film 754C is referred to as an intermediate film.

For example, a material having a function of permeating or supplying hydrogen can be used for the intermediate film.

For example, a material having conductivity can be used for the intermediate film.

For example, a material having a light-transmitting property can be used for the intermediate film.

Specifically, a material containing indium and oxygen, a material containing indium, gallium, zinc and oxygen, a material containing indium, tin and oxygen, or the like can be used for the intermediate film. Note that these materials have a function of permeating hydrogen.

Specifically, a 50 nm-thick film or a 100 nm-thick film containing indium, gallium, zinc, and oxygen can be used as the intermediate film.

Note that a material in which a film functioning as an etching stopper is stacked can be used for the intermediate film. Specifically, a laminated material obtained by laminating a film having a thickness of 50 nm containing indium, gallium, zinc, and oxygen and a film having a thickness of 20 nm containing indium, tin, and oxygen in this order is used for the intermediate film. it can.

<Wiring, terminal, conductive film>
A conductive material can be used for the wiring or the like. Specifically, a material having conductivity is a signal line S1 (j), a signal line S2 (j), a scanning line G1 (i), a scanning line G2 (i), a wiring CSCOM, a wiring ANO, a conductive film 511B, or The conductive film 511C can be used.

For example, an inorganic conductive material, an organic conductive material, a metal, a conductive ceramic, or the like can be used for the wiring.

Specifically, a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, or manganese is used for wiring or the like. it can. Alternatively, an alloy containing the above metal element can be used for the wiring or the like. In particular, an alloy of copper and manganese is suitable for fine processing using a wet etching method.

Specifically, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a tantalum nitride film or A two-layer structure in which a tungsten film is stacked on a tungsten nitride film, a titanium film, and a three-layer structure in which an aluminum film is stacked on the titanium film and a titanium film is further formed thereon can be used for wiring or the like. .

Specifically, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or zinc oxide to which gallium is added can be used for the wiring or the like.

Specifically, a film containing graphene or graphite can be used for the wiring or the like.

For example, by forming a film containing graphene oxide and reducing the film containing graphene oxide, the film containing graphene can be formed. Examples of the reduction method include a method of applying heat and a method of using a reducing agent.

For example, a film containing metal nanowires can be used for wiring or the like. Specifically, a nanowire containing silver can be used.

Specifically, a conductive polymer can be used for wiring or the like.

Note that, for example, the conductive material ACF1 can be used to electrically connect the terminal 519B and the flexible printed circuit board FPC1.

<Reflection element 30a (i, j)>
The reflective element 30a (i, j) is a display element having a function of controlling the reflection of light. For example, a liquid crystal element, an electrophoretic element, a MEMS display element, or the like can be used. Specifically, a reflective liquid crystal display element can be used for the reflective element 30a (i, j). By using a reflective display element, power consumption of the display unit can be suppressed.

For example, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, FFS (Fringe Field Switching), ASM (Axial Symmetrically Aligned Micro-cell) mode, OCB (OpticBridge) A liquid crystal element that can be driven by a driving method such as a Crystal) mode or an AFLC (Antiferroelectric Liquid Crystal) mode can be used.

In addition, for example, vertical alignment (VA) mode, specifically, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ECB (Electrically Controlled Birefringence) mode, CPB mode A liquid crystal element that can be driven by a driving method such as an (Advanced Super-View) mode can be used.

The reflective element 30a (i, j) includes an electrode 751 (i, j), an electrode 752, and a layer 753 containing a liquid crystal material. The layer 753 includes a liquid crystal material whose alignment can be controlled using a voltage between the electrode 751 (i, j) and the electrode 752. For example, an electric field in the thickness direction (also referred to as a vertical direction) of the layer 753 and a direction intersecting with the vertical direction (also referred to as a horizontal direction or an oblique direction) can be used as an electric field for controlling the alignment of the liquid crystal material.

For example, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used for the layer 753. Alternatively, a liquid crystal material exhibiting a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like can be used. Alternatively, a liquid crystal material exhibiting a blue phase can be used.

For example, a material used for wiring or the like can be used for the electrode 751 (i, j). Specifically, a reflective film can be used for the electrode 751 (i, j). For example, a material in which a conductive film having a light-transmitting property and a reflective film having an opening are stacked can be used for the electrode 751 (i, j).

For example, a material having conductivity can be used for the electrode 752. A material having a light-transmitting property with respect to visible light can be used for the electrode 752.

For example, a conductive oxide, a metal film that is thin enough to transmit light, or a metal nanowire can be used for the electrode 752.

Specifically, a conductive oxide containing indium can be used for the electrode 752. Alternatively, a metal thin film with a thickness of 1 nm to 10 nm can be used for the electrode 752. In addition, a metal nanowire containing silver can be used for the electrode 752.

Specifically, indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide to which gallium is added, zinc oxide to which aluminum is added, or the like can be used for the electrode 752.

<Reflective film>
For example, a material that reflects visible light can be used for the reflective film. Specifically, a material containing silver can be used for the reflective film. For example, a material containing silver and palladium or a material containing silver and copper can be used for the reflective film.

The reflective film reflects, for example, light transmitted through the layer 753. Thereby, the reflective element 30a (i, j) can be made a reflective display element. Further, for example, a material having irregularities on the surface can be used for the reflective film. Thereby, incident light can be reflected in various directions to display white.

For example, the electrode 751 (i, j) or the like can be used for the reflective film.

For example, a film including a region sandwiched between the layer 753 and the electrode 751 (i, j) can be used for the reflective film. Alternatively, when the electrode 751 (i, j) has a light-transmitting property, a film having a region overlapping with the layer 753 with the electrode 751 (i, j) interposed therebetween can be used as the reflective film.

The reflective film preferably has a region that does not block the light emitted from the light emitting element 30b (i, j), for example. For example, it is preferable to use a shape including one or a plurality of openings 751H for the reflective film.

A shape such as a polygon, a rectangle, an ellipse, a circle, or a cross can be used for the opening. In addition, an elongated stripe shape, a slit shape, or a checkered shape can be used for the opening 751H.

If the value of the ratio of the total area of the opening 751H to the total area of the non-opening is too large, the display using the reflective element 30a (i, j) will be dark.

In addition, if the ratio of the total area of the opening 751H to the total area of the non-opening is too small, the display using the light emitting element 30b (i, j) becomes dark.

FIG. 30 is a schematic diagram illustrating the shape of a reflective film that can be used for the pixel of the display unit 310.

For example, the opening 751H of the pixel 702 (i, j + 1) adjacent to the pixel 702 (i, j) passes through the opening 751H of the pixel 702 (i, j) (the direction indicated by the arrow R1 in the drawing). (See FIG. 30A). Alternatively, for example, the opening 751H of the pixel 702 (i + 1, j) adjacent to the pixel 702 (i, j) passes through the opening 751H of the pixel 702 (i, j) in the column direction (in FIG. They are not arranged on a straight line extending in the direction shown (see FIG. 30B).

For example, the opening 751H of the pixel 702 (i, j + 2) is disposed on a straight line that extends in the row direction and passes through the opening 751H of the pixel 702 (i, j) (see FIG. 30A). In addition, the opening 751H of the pixel 702 (i, j + 1) is arranged on a straight line orthogonal to the straight line between the opening 751H of the pixel 702 (i, j) and the opening 751H of the pixel 702 (i, j + 2). Established.

Alternatively, for example, the opening 751H of the pixel 702 (i + 2, j) is disposed on a straight line extending in the column direction passing through the opening 751H of the pixel 702 (i, j) (see FIG. 30B). . For example, the opening 751H of the pixel 702 (i + 1, j) is a straight line orthogonal to the straight line between the opening 751H of the pixel 702 (i, j) and the opening 751H of the pixel 702 (i + 2, j). Arranged above.

Accordingly, the second display element including a region overlapping with the opening of another pixel adjacent to one pixel can be separated from the second display element including a region overlapping with the opening of one pixel. Alternatively, a display element that displays a color different from the color displayed by the second display element of one pixel can be provided in the second display element of another pixel adjacent to the one pixel. Alternatively, the difficulty of arranging a plurality of display elements that display different colors adjacent to each other can be reduced.

Note that, for example, a material having a shape in which an end portion is cut out so that the region 751E that does not block the light emitted from the light emitting element 30b (i, j) can be used for the reflective film ( (See FIG. 30C). Specifically, an electrode 751 (i, j) whose end is cut so that the column direction (the direction indicated by the arrow C1 in the drawing) is shortened can be used for the reflective film.

<Alignment film AF1 and alignment film AF2>
For example, a material containing polyimide or the like can be used for the alignment film AF1 or the alignment film AF2. Specifically, a material formed using a rubbing process or a photo-alignment technique so that the liquid crystal material is aligned in a predetermined direction can be used.

For example, a film containing soluble polyimide can be used for the alignment film AF1 or the alignment film AF2. Thereby, the temperature required for forming the alignment film AF1 or the alignment film AF2 can be lowered. As a result, damage to other components when forming the alignment film AF1 or the alignment film AF2 can be reduced.

<Colored film CF1, colored film CF2>
A material that transmits light of a predetermined color can be used for the colored film CF1 or the colored film CF2. Thereby, the colored film CF1 or the colored film CF2 can be used for a color filter, for example. For example, a material that transmits blue, green, or red light can be used for the colored film CF1 or the colored film CF2. Further, a material that transmits yellow light, white light, or the like can be used for the colored film CF1 or the colored film CF2.

Note that a material having a function of converting irradiated light into light of a predetermined color can be used for the colored film CF2. Specifically, quantum dots can be used for the colored film CF2. Thereby, display with high color purity can be performed.

<Light shielding film BM>
A material that prevents light transmission can be used for the light-shielding film BM. Thereby, the light shielding film BM can be used for, for example, a black matrix.

<Insulating film 771>
For example, polyimide, epoxy resin, acrylic resin, or the like can be used for the insulating film 771.

<Functional film 770P, Functional film 770D>
For example, an antireflection film, a polarizing film, a retardation film, a light diffusion film, a light collecting film, or the like can be used for the functional film 770P or the functional film 770D.

Specifically, a film containing a dichroic dye can be used for the functional film 770P or the functional film 770D. Alternatively, a material having a columnar structure including an axis along a direction intersecting the surface of the base material can be used for the functional film 770P or the functional film 770D. Thereby, light can be easily transmitted in a direction along the axis and can be easily scattered in other directions.

In addition, an antistatic film that suppresses adhesion of dust, a water-repellent film that makes it difficult to adhere dirt, a hard coat film that suppresses generation of scratches due to use, and the like can be used for the functional film 770P.

Specifically, a circularly polarizing film can be used for the functional film 770P. In addition, a light diffusion film can be used for the functional film 770D.

<Light emitting element 30b (i, j)>
For example, a self-luminous light-emitting element such as an organic EL element, an inorganic EL element, a QLED, or a light-emitting diode can be used for the light-emitting element 30b (i, j).

The light-emitting element 30b (i, j) includes an electrode 551 (i, j), an electrode 552, and a layer 553 (j) containing a light-emitting material.

For example, a light-emitting organic compound can be used for the layer 553 (j).

For example, quantum dots can be used for the layer 553 (j). Thereby, the half value width is narrow and it is possible to emit brightly colored light.

For example, a layered material stacked so as to emit blue light, a layered material stacked so as to emit green light, a layered material stacked so as to emit red light, the layer 553 ( j).

For example, a strip-shaped stacked material that is long in the column direction along the signal line S2 (j) can be used for the layer 553 (j).

For example, a stacked material stacked so as to emit white light can be used for the layer 553 (j). Specifically, a layer containing a luminescent material including a fluorescent material that emits blue light, a layer containing a material other than a fluorescent material that emits green and red light, or a fluorescent material that emits yellow light A layered material in which a layer containing any of the above materials is stacked can be used for the layer 553 (j).

For example, a material that can be used for wiring or the like can be used for the electrode 551 (i, j).

For example, a material having a property of transmitting visible light and selected from materials that can be used for wirings or the like can be used for the electrode 551 (i, j).

Specifically, a conductive oxide or a conductive oxide containing indium, indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide to which gallium is added, or the like is used as the electrode 551 (i, j). Can be used. Alternatively, a metal film that is thin enough to transmit light can be used for the electrode 551 (i, j). Alternatively, a metal film that transmits part of light and reflects another part of light can be used for the electrode 551 (i, j). Thereby, the microresonator structure can be provided in the light emitting element 30b (i, j). As a result, light of a predetermined wavelength can be extracted more efficiently than light of other wavelengths.

For example, a material that can be used for wiring or the like can be used for the electrode 552. Specifically, a material having reflectivity with respect to visible light can be used for the electrode 552.

<Gate driver GD>
Various sequential circuits such as a shift register can be used for the gate driver GD. For example, a transistor MD, a capacitor element, or the like can be used for the gate driver GD. Specifically, a transistor that can be used for the switch SW1 or a transistor including a semiconductor film that can be formed in the same process as the transistor M can be used.

For example, a different structure from the transistor that can be used for the switch SW1 can be used for the transistor MD. Specifically, a transistor including the conductive film 524 can be used for the transistor MD.

Note that the same structure as the transistor M can be used for the transistor MD.

<Transistor>
For example, a semiconductor film that can be formed in the same step can be used for a gate driver, a source driver, and a transistor in a pixel circuit.

For example, a bottom-gate transistor, a top-gate transistor, or the like can be used as a gate driver, a source driver transistor, or a pixel circuit transistor.

For example, the OS transistor described in Embodiment 1 can be used. This makes it possible to perform the idling stop described above.

For example, a transistor including the metal oxide 508, the conductive film 504, the conductive film 512A, and the conductive film 512B can be used for the switch SW1 (see FIG. 29B). Note that the insulating film 506 includes a region sandwiched between the metal oxide 508 and the conductive film 504.

The conductive film 504 includes a region overlapping with the metal oxide 508. The conductive film 504 has a function of a gate electrode. The insulating film 506 has a function of a gate insulating film.

The conductive films 512A and 512B are electrically connected to the metal oxide 508. The conductive film 512A has one of the function of the source electrode and the function of the drain electrode, and the conductive film 512B has the other of the function of the source electrode and the function of the drain electrode.

A transistor including the conductive film 524 can be used as a gate driver, a source driver, or a transistor in a pixel circuit. The conductive film 524 includes a region in which the metal oxide 508 is sandwiched between the conductive film 504 and the conductive film 504. Note that the insulating film 514 includes a region sandwiched between the conductive film 524 and the metal oxide 508. For example, the conductive film 524 is electrically connected to a wiring that supplies the same potential as the conductive film 504.

For example, a conductive film in which a 10-nm-thick film containing tantalum and nitrogen and a 300-nm-thick film containing copper are stacked can be used for the conductive film 504. Note that the film containing copper includes a region between which the film containing tantalum and nitrogen is sandwiched between the film containing copper.

For example, a material in which a 400-nm-thick film containing silicon and nitrogen and a 200-nm-thick film containing silicon, oxygen, and nitrogen are stacked can be used for the insulating film 506. Note that the film containing silicon and nitrogen includes a region between the metal oxide 508 and the film containing silicon, oxygen, and nitrogen.

For example, a 25-nm-thick film containing indium, gallium, and zinc can be used for the metal oxide 508.

For example, a conductive film in which a 50-nm-thick film containing tungsten, a 400-nm-thick film containing aluminum, and a 100-nm-thick film containing titanium are stacked in this order as the conductive film 512A or the conductive film 512B. Can be used. Note that the film containing tungsten includes a region in contact with the metal oxide 508.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 7)
In this embodiment, an electronic device including the display device of one embodiment of the present invention will be described.

In this display device, the controller IC monitors the signal from the optical sensor, and can perform display with improved visibility in an environment where there is external light such as outdoors on a sunny day. Further, it has an effect of suppressing the change in the appearance of the display device due to the color tone of the external light. Therefore, this display device is suitable for a display unit of a portable electronic device used in various places. Of course, the present display device can be applied not only to the portable electronic device but also to display portions of various electronic devices. Here, with reference to FIG. 31, some examples of an electronic device including a display unit will be described.

FIG. 31A to FIG. 31G illustrate electronic devices. These electronic devices include a housing 5000, a display portion 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or operation switch), a connection terminal 5006, a sensor 5007 (force, displacement, position, speed, Measure acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared A microphone 5008, and the like.

FIG. 31A illustrates a mobile computer which can include a switch 5009, an infrared port 5010, and the like in addition to the above components. FIG. 31B illustrates a portable image reproducing device (eg, a DVD reproducing device) provided with a recording medium, which includes a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above components. it can. FIG. 31C illustrates a goggle type display which can include a second display portion 5002, a support portion 5012, an earphone 5013, and the like in addition to the above components. FIG. 31D illustrates a portable game machine that can include the memory medium reading portion 5011 and the like in addition to the above objects. FIG. 31E illustrates a digital camera with a television receiving function, which can include an antenna 5014, a shutter button 5015, an image receiving portion 5016, and the like in addition to the above objects. FIG. 31F illustrates a portable game machine that can include the second display portion 5002, the recording medium reading portion 5011, and the like in addition to the above objects. FIG. 31G illustrates a portable television receiver that can include a charger 5017 that can transmit and receive signals in addition to the above components.

The electronic devices illustrated in FIGS. 31A to 31G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, etc., a function for controlling processing by various software (programs) , Wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, read program or data recorded in recording medium A function of displaying on the display portion can be provided. Further, in an electronic device having a plurality of display units, one display unit mainly displays image information and another one display unit mainly displays character information, or the plurality of display units consider parallax. It is possible to have a function of displaying a three-dimensional image, etc. by displaying the obtained image. Furthermore, in an electronic device having an image receiving unit, a function for capturing a still image, a function for capturing a moving image, a function for correcting a captured image automatically or manually, and a captured image on a recording medium (externally or incorporated in a camera) A function of saving, a function of displaying a photographed image on a display portion, and the like can be provided. Note that the functions which the electronic devices illustrated in FIGS. 31A to 31G can have are not limited to these, and can have various functions.

FIG. 31H illustrates a smart watch, which includes a housing 7302, a display panel 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like. Here, the “display panel” can perform display by the same mechanism as the “display unit” described in the other embodiments.

A display panel 7304 mounted on a housing 7302 also serving as a bezel portion has a non-rectangular display region. Note that the display panel 7304 may have a rectangular display region. The display panel 7304 can display an icon 7305 indicating time, another icon 7306, and the like.

Note that the smart watch illustrated in FIG. 31H can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, etc., a function for controlling processing by various software (programs) , Wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, read program or data recorded in recording medium A function of displaying on the display portion can be provided.

In addition, a speaker, a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current are included in the housing 7302. Voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or function of measuring infrared rays), a microphone, or the like. Note that a smart watch can be manufactured by using a light-emitting element for the display panel 7304.

(Embodiment 8)
<Configuration of CAC-OS>
In this embodiment, a structure of a CAC (Cloud-Aligned Composite) -OS that can be used for an OS transistor is described.

The CAC-OS is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.

Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind selected from the above or a plurality of kinds may be included.

For example, a CAC-OS in an In—Ga—Zn oxide (an In—Ga—Zn oxide among CAC-OSs, in particular, may be referred to as a CAC-IGZO) is an indium oxide (hereinafter, InO _X1 and (X1 large real number than 0)), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 are real numbers greater than 0) and to), gallium oxide ( Hereinafter, GaO _X3 (X3 is a real number greater than 0), or gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers greater than 0)), etc. , the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter, cloud And it is also referred to).

That, CAC-OS includes a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is the main component region is a composite oxide semiconductor having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystalline) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, CAC-OS relates to a material structure of an oxide semiconductor. CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component region, in some cases clear boundary can not be observed.

In place of gallium, aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are selected. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

The CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .

The CAC-OS is characterized in that no clear peak is observed when it is measured using a θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

In addition, a CAC-OS includes a ring-shaped region having high luminance and a plurality of bright spots in the ring region in an electron beam diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam). Is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

Further, for example, in a CAC-OS in an In—Ga—Zn oxide, a region in which GaO _X3 is a main component is obtained by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and each region is mainly composed of each element. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2} or _{InO X1,} is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.

On the other hand, areas such as _{GaO X3} is the main _component, as compared to the In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component area, it is highly regions insulating. That is, a region containing GaO _X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act in a complementary manner, resulting in high An on-current (I _on ) and high field effect mobility (μ) can be realized.

In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is optimal for various semiconductor devices including a display.

ACF1 Conductive material AF1 Alignment film AF2 Alignment film C1 Arrow C4 Capacitor C6 Capacitor C7 Capacitor C11 Capacitor C12 Capacitor C13 Capacitor C21 Capacitor C22 Capacitor CF1 Colored film CF2 Colored film CK1 Clock signal CK2 Clock signal CK3 Clock signal CK4 clock signal CS1 capacitive element FPC1 flexible printed circuit board G1 scanning line G2 scanning line GL1 scanning line GL2 scanning line INV1 inverter INV2 inverter KB1 structure LOAD1 signal LOAD2 signal N1 node NW1 transistor P1 period P2 period P3 period R1 arrow S1 signal line S2 Line SAVE1 Signal SAVE2 Signal SD Source driver SD1 Source driver SD2 Source driver SW1 Switch SW2 Switch T01 Time T1 Transistor T02 time T2 transistor T03 time T04 time T05 time T06 time T6 transistor T07 time T08 time T09 time T10 time T11 time T12 time T13 time T14 time T15 time T16 time T17 time T18 time T19 time T20 time Tr21 transistor Tr22 transistor Tr24 transistor Tr24 Tr26 transistor Tr27 transistor Tr28 transistor Tr29 transistor Tr30 transistor Tr31 transistor TR1 transistor TR6 transistor TR7 transistor TR11 transistor VCOM1 wiring VCOM2 wiring 10 pixel 11 memory circuit 12 reference memory circuit 13 circuit 14 circuit 15 current source circuit 17 holding circuit 18 selector 19 flip-flop Circuit 20 Inverter 21 Region 25 Inverter 27 Analog switch 28 Analog switch 30 Pixel 30a Reflective element 30b Light emitting element 31 Inverter 33 Inverter 34 Clocked inverter 35 Analog switch 36 Buffer 100 Display device 107 Semiconductor device 110 Display unit 111 Pixel array 113 Gate driver 115 Controller IC
117 Controller IC
118 Controller IC
119 Controller IC
120 Touch sensor unit 121 Sensor array 125 Peripheral circuit 126 TS driver 127 Sense circuit 140 Host 143 Optical sensor 144 Open / close sensor 145 Optical 150 Interface 151 Frame memory 152 Decoder 153 Sensor controller 154 Controller 155 Clock generation circuit 156 AI controller 160 Image processing unit 161 Gamma correction circuit 162 Dimming circuit 163 Toning circuit 164 EL correction circuit 170 Memory 173 Timing controller 175 Register 175A Scan chain register unit 175B Register unit 175C Scan chain register unit 175D Register unit 180 Source driver 181 Source driver 182 Source driver 184 Touch sensor Controller 186 Source driver IC
190 region 191 region 202 control unit 203 cell array 204 sense amplifier circuit 205 driver 206 main amplifier 207 input / output circuit 208 peripheral circuit 209 memory cell 221 transistor 222 transistor 223 transistor 224 capacitor element 225 node 226 node 227 organic EL element 230 register 231 register 232 Register 233 register 270 circuit 271 circuit 272 circuit 273 circuit 274 circuit 310 display unit 311 pixel array 313 gate driver 314 gate driver 501A insulating film 501C insulating film 504 conductive film 505 bonding layer 506 insulating film 508 metal oxide 510 electrode 511 electrode 511B conductive Film 511C Conductive film 512 Semiconductor layer 512A Conductive film 512B Conductive film 514 Insulating film 516 Electrode 517 Electrode 518 Insulating film 519B Terminal 519C Terminal 521 Insulating film 524 Conductive film 528 Insulating film 551 Electrode 552 Electrode 553 Layer 570 Substrate 702 Pixel 705 Sealant 751 Electrode 751E Region 751H Opening 752 Electrode 753 Layer 754A Intermediate film 754C Intermediate film 754C Intermediate Film 770 Substrate 770D Functional film 770P Functional film 771 Insulating film 4001 Substrate 4005 Sealant 4006 Substrate 4010 Transistor 4011 Transistor 4020 Capacitor element 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4102 Insulating layer 4103 Insulating layer 4110 Insulating layer 4111 Insulating layer 4112 Insulating layer 4510 Partition wall 4511 EL layer 4513 Light emitting element 4514 Filler 5000 Housing 5001 Display portion 5002 Display portion 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support unit 5013 Earphone 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 Charger 7302 Case 7304 Display panel 7305 Icon 7306 Icon 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Clasp

Claims (9)

A display unit;
A first controller;
A second controller;
Frame memory,
Registers,
An image processing unit;
A sensor, and
The frame memory has a function of storing image data;
The image processing unit has a function of processing the image data;
The register has a function of storing parameters for the image processing unit to perform processing,
The frame memory has a function of holding the image data in a state where power supply to the frame memory is interrupted,
The register has a function of holding the parameter in a state where power supply to the register is interrupted,
The first controller has a function of controlling power supply to the frame memory, the register, and the image processing unit,
The second controller has a function of receiving a first signal from the sensor, and a function of generating a second signal for the image processing unit to perform processing based on the first signal.
The second signal has a predetermined threshold;
When the second signal does not exceed the threshold value, the image processing unit has a function of displaying the display unit at a first luminance,
When the second signal exceeds the threshold value, the image processing unit has a function of displaying the display unit with a second luminance. In claim 1,
The semiconductor device, wherein the sensor is an optical sensor. In claim 1 or claim 2,
The first brightness can be selected by a user from a predetermined range,
The semiconductor device, wherein the second luminance cannot be selected by a user. In any one of Claims 1 thru | or 3,
When the second signal exceeds the threshold value, a function of displaying the display unit at the second luminance is disabled when a predetermined time limit elapses. In any one of Claims 1 thru | or 4,
Have a source driver,
The source driver has a function of generating a data signal based on the image data processed by the image processing unit,
The display unit has a light emitting element,
The semiconductor device, wherein the data signal has a function of driving the light emitting element. In claim 5,
The semiconductor device according to claim 1, wherein the light emitting element is an organic EL element. In any one of Claims 1 thru | or 4,
Have a source driver,
The source driver has a function of generating a first data signal and a second data signal based on the image data processed by the image processing unit,
The display unit includes a reflective element and a light emitting element,
The first data signal has a function of driving the reflective element;
The semiconductor device, wherein the second data signal has a function of driving the light emitting element. In claim 7,
The reflective element is a liquid crystal element,
The semiconductor device according to claim 1, wherein the light emitting element is an organic EL element. In any one of Claims 1 thru | or 8,
The frame memory and the register each include a transistor including a metal oxide in a channel formation region.

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