JP2018007033A - Pulse generation device and method - Google Patents

Abstract

Even if a target specification such as a cycle of a pulse signal to be generated is changed, highly accurate control of the pulse signal is easily realized. A clock generator generates first to fourth clock signals having periods T1 to T4. The periodic signal generator 56 generates a periodic signal that generates a pulse with the period of the PWM pulse signal from the first to fourth clock signals. In each period, the period of the first detector 72 is corrected by the first corrector 70. The second detection unit 80 detects the timing at which the number of pulses of the first clock signal reaches the first command value, and the second detection unit 80 sets the number of pulses of the second clock signal whose cycle is corrected by the second correction unit 78 to the second command value. Detecting the arrival timing, the pulse generator 86 generates a PWM pulse signal whose signal level changes at each detected timing. [Selection] Figure 2

Description

  The present invention relates to a pulse generation device and a pulse generation method.

  Patent Document 1 discloses a digital pulse width modulation device having the following configuration. That is, the synchronization detection means detects the synchronization timing of the two clocks A and B with the frequency ratio (N + 1): N and generates two synchronization signals C and D, and the first counter means generates the synchronization signal C The count signal E by the clock A is generated. The second counter means has a function of initializing with the synchronizing signal D and generates a count signal F based on the clock B, and the leading edge control signal generating means uses the clock A to generate the count signal E and the digital signal. A leading edge control signal for specifying the position of the leading edge of the pulse width modulation signal according to the signal is generated. Then, the trailing edge control signal generating means generates a trailing edge control signal for specifying the position of the trailing edge of the pulse width modulation signal using the clock B in accordance with the count signal F and the digital signal. The generation unit generates a pulse width modulation signal by combining the leading edge control signal and the trailing edge control signal.

  Patent Document 2 discloses a PWM control device having the following configuration. The first counter counts the reference clock signal and outputs a first count value, and the first counter control unit detects that the first count value has reached the first set value and detects the first count value. 1 counter is reset. The leading edge control signal generation unit detects that the first count value has reached the second set value, and outputs a leading edge control signal that specifies the leading edge position of the pulse width modulation signal for adjustment. The clock generation unit generates an adjustment clock signal having a period different from that of the reference clock signal. The second counter control unit detects that the first count value has reached the third set value, and instructs the adjustment clock generation unit to start output. The second counter controls the adjustment clock. The signal is counted and a second count value is output. Then, the trailing edge control signal generation unit detects that the second count value has reached the fourth set value, and outputs a trailing edge control signal that designates the trailing edge position of the pulse width modulation signal. The generation unit generates a rising edge of the pulse width modulation signal based on the leading edge control signal, and generates a falling edge of the pulse width modulation signal based on the trailing edge control signal.

JP 2008-193436 A JP 2009-290473 A

  The technique described in Patent Document 1 can generate a pulse width modulation signal that can control the pulse width with a resolution of (one period of clock A / N). However, in the technique described in Patent Document 1, the lower 7 bits of the digital signal are assigned to pulse trailing edge data that defines the position of the trailing edge of the pulse with reference to the clock B, and the upper 9 bits of the digital signal are assigned to the clock A. As a reference, it is assigned to pulse leading edge data defining the position of the pulse leading edge. Then, the level of the trailing edge control signal is changed at the timing when the count signal F is changed by the pulse trailing edge data from the synchronizing timing of the clocks A and B, and the counting signal E is changed from the synchronizing timing of the clocks A and B to the pulse trailing edge data. The level of the leading edge control signal is changed at a timing at which the difference from the pulse leading edge data has changed.

  As described above, the technique described in Patent Document 1 uses the difference between the pulse trailing edge data and the pulse leading edge data having different reference clocks, and calculates the pulse leading edge from the count signal E of one clock (clock A). The position is determined. For this reason, in the technique described in Patent Document 1, the timing at which the level of the leading edge control signal changes varies with the magnitude of the value of the pulse trailing edge data with respect to the original timing, and the generated pulse width An error corresponding to the value of the pulse trailing edge data is also added to the duty ratio of the modulation signal.

  In the technique described in Patent Document 2, when the first count value of the reference clock signal reaches the second set value, the leading edge control signal is output, and the first count value of the reference clock signal is the third count value. After reaching the set value and starting output of the adjustment clock signal, the trailing edge control signal is output when the second count value of the adjustment clock signal reaches the fourth set value. Therefore, the technique described in Patent Document 2 can accurately control the timing of the pulse leading edge and the timing of the pulse trailing edge independently of each other.

  However, in the technique described in Patent Document 2, the reference clock generation unit (30a) of the clock controller (30) receives the first reset signal RST1 input from the first counter control unit (10) as a delay circuit ( The reference clock signal REFC is generated by delaying at 31a) and (32a). For this reason, the time accuracy of the cycle of the reference clock signal REFC depends on the accuracy of the delay times of the delay circuits (31a) and (32a). In the technique described in Patent Document 2, the adjustment clock generator (30b) of the clock controller (30) uses the second reset signal RST2 input from the second counter controller (20) as a delay circuit. The adjustment clock signal ADJC is generated by being delayed by (31b), (32b) and the resolution setting delay circuit (33b). Therefore, the time accuracy of the difference between the cycle of the adjustment clock signal ADJC and the cycle from the reference clock signal REFC depends on the accuracy of the delay times of the delay circuits (31b), (32b) and the resolution setting delay circuit (33b).

  For this reason, in the technique described in Patent Document 2, in order to accurately control the pulse signal to be generated, the delay times of the delay circuits (31a) and (32a) and the delay times of the delay circuits (31b) and (32b) It is indispensable to make a circuit such that the delay time of the resolution setting delay circuit (33b) accurately matches the time corresponding to the resolution. Therefore, the technique described in Patent Document 2 has a problem that it takes cost and time to cope with a change in target specifications such as a change in the period and resolution of a pulse signal to be generated.

  In one aspect, an object of the present invention is to easily realize high-precision control of a pulse signal even when a target specification such as a period of a generated pulse signal is changed.

The pulse generator according to the first aspect of the present invention provides a first clock signal having a period T ₁ = Ts / ((M + 1) · p) from the original clock signal (where Ts is the period of the target pulse signal and M and p are Natural number), a second clock signal with period T ₂ = Ts / (M · q) (where q is a natural number), a third clock signal with period T ₃ = Ts / a, and a second clock signal with period T ₄ = Ts / b A clock generator that generates four clock signals (where a and b are natural numbers and the greatest common divisor = 1), one of the first clock signal and the second clock signal, the third clock signal, and the second clock signal. A periodic signal generator that generates a periodic signal that generates a pulse at a timing synchronized with the four clock signals, and a first timing at which the number of pulses of the first clock signal from the pulse generation timing of the periodic signal is input. Reaching the first command value A first detector for detecting a timing, and a second timing at which the number of pulses of the second clock signal from the pulse generation timing of the periodic signal reaches a second command value that defines the input second timing; A second detection unit; and a pulse generation unit that generates a target pulse signal whose signal level changes at each of the first timing detected by the first detection unit and the second timing detected by the second detection unit; The clock generation unit is configured so that each of the periods T ₁ and T ₂ is obtained by dividing each period from the pulse generation timing of the periodic signal to the next pulse generation timing for each period T ₃ . It is said that it is smaller than the minimum value tmin of the absolute value of the difference between the boundary time t ₁ of the partial period and the boundary time t ₂ of each second partial period when the period is divided every period T ₄ The first to fourth clock signals are generated so as to satisfy the condition.

According to the first aspect of the present invention, the clock generator generates a _first clock signal having a period T ₁ = Ts / ((M + 1) · p) from the original clock signal (where Ts is the period of the target pulse signal and M, p are Natural number), a second clock signal with period T ₂ = Ts / (M · q) (where q is a natural number), a third clock signal with period T ₃ = Ts / a, and a second clock signal with period T ₄ = Ts / b Four clock signals (where a and b are natural numbers and the greatest common divisor = 1) are generated. In the first aspect of the present invention, the target pulse signal is generated using the first to fourth clock signals generated from the original clock signal, respectively. The periods T _{1 to} T ₄ of the _{first to} fourth clock signals are Both are n / m times (n and m are natural numbers) the period Ts of the target pulse signal. For this reason, by setting the cycle of the original clock signal to, for example, a natural number of the cycle Ts of the target pulse signal, the clock generator can perform the first to second operations by at least one of dividing and multiplying the original clock signal. It is also possible to easily change the periods T _{1 to} T ₄ to generate a 4-clock signal, and to easily cope with changes in target specifications such as the period of the pulse signal to be generated.

  According to the first aspect of the present invention, the periodic signal generator generates a pulse at a timing when one of the first clock signal and the second clock signal, the third clock signal, and the fourth clock signal are synchronized. Generate a periodic signal. The first detector detects a first timing at which the number of pulses of the first clock signal from the pulse generation timing of the periodic signal reaches a first command value that defines the input first timing, and performs a second detection. The unit detects a second timing at which the number of pulses of the second clock signal from the pulse generation timing of the periodic signal reaches a second command value that defines the input second timing. The pulse generation unit generates a target pulse signal whose signal level changes at each of the first timing detected by the first detection unit and the second timing detected by the second detection unit.

  Thus, in the first aspect of the invention, the first timing detected by the first detector is determined according to the first command value, and the second timing detected by the second detector is determined according to the second command value. Therefore, the first timing and the second timing, that is, the timing at which the signal level of the target pulse signal changes according to the first command value and the timing at which the signal level of the target pulse signal changes according to the second command value, It can be controlled accurately independently of each other.

  However, in the first aspect of the present invention, since one of the first clock signal and the second clock signal, the third clock signal, and the fourth clock signal are synchronized with each other, a periodic signal pulse is generated. When a period in which three types of clock signals are synchronized with a cycle shorter than the cycle Ts of the target pulse signal (for example, all three types of clock signals are at a high level) occurs, the first from the pulse generation timing of the periodic signal. The number of pulses of the clock signal and the second clock signal deviates from the original values, and the control of the target pulse signal is distorted.

Therefore, according to the first aspect of the present invention, when the clock generation unit divides the period from the pulse generation timing of the periodic signal to the next pulse generation timing for each period T _{3 in} each of the periods T ₁ and T ₂ the boundary time t ₁ of each of the first partial periods, the boundary time t ₂ of the individual second partial periods of time obtained by dividing the period in each cycle T _4, than the minimum value tmin absolute value of the difference between the The first to fourth clock signals are generated so as to satisfy the condition of being small. By generating the first to fourth clock signals so as to satisfy the above conditions, it is possible to suppress the occurrence of a period in which the above-described three types of clock signals are synchronized with a cycle shorter than the cycle Ts of the target pulse signal. It is possible to suppress a deviation in the control of the pulse signal. Therefore, the invention according to claim 1 can easily realize high-precision control of the pulse signal even if the target specification such as the cycle of the generated pulse signal is changed.

In the first aspect of the present invention, when p, q = 1 does not satisfy the above condition, for example, as described in claim 2, the clock generation unit sets p, q ≧ 2 and changes the cycle. processing in association with the period of the clock signal by performing a process comprising the 1 / p times to generate a first clock signal having a period T _1, to the period of the clock signal to change the cycle to 1 / q times the generating the second clock signal with a period T ₂ performed, the correction unit includes a first and a period of the second clock signal to the q times with a period of the first clock signal input to the first detection portion in the p times Preferably, the first command value is multiplied by p and input to the first detection unit, and the second command value is multiplied by q and input to the second detection unit.

As described above, p, q ≧ 2 is generated, and processing including multiplying the cycle of the clock signal whose cycle is changed to 1 / p is performed to generate the first clock signal of cycle T ₁ and the cycle is changed. the period of the clock signal to generate a second clock signal with a period T ₂ processes performed that involves the 1 / q times, described above, each of the minimum value of the period T _1, T ₂ tmin It is possible to satisfy the above-mentioned condition of being smaller than the above. In this case, the number of pulses of the first clock signal is p times and the number of pulses of the second clock signal is q times. As described above, the period of the first clock signal is p times, If the signal cycle is multiplied by q, or the first command value is multiplied by p and the second command value is multiplied by q and input to the first detection unit and the second detection unit, the control of the target pulse signal is distorted. Occurrence is suppressed. Therefore, according to the second aspect of the present invention, even when the condition that each of the periods T ₁ and T ₂ is smaller than the minimum value tmin is not satisfied at p and q = 1, the high accuracy of the generated pulse signal is achieved. Can be realized.

  In the first or second aspect of the invention, for example, in the case of controlling the pulse width (duty ratio) of the target pulse signal, for example, as described in claim 3, the first detector is configured to transmit the periodic signal. The counting of the number of pulses of the first clock signal from the pulse generation timing is repeated alternately with the addition count and the subtraction count at each pulse generation timing of the periodic signal, or the addition count or the subtraction count is randomly performed. 2 The detection unit repeatedly counts the number of pulses of the second clock signal from the pulse generation timing of the periodic signal, repeats the addition count and the subtraction count every time the pulse generation timing of the periodic signal, or adds or subtracts It is preferable to perform the counting at random.

  Thereby, at least one of the first command value and the second command value is compared with the case where the first detection unit and the second detection unit repeat only the addition count or the subtraction count at each pulse generation timing of the periodic signal. Even if the value continues at a constant value, the first timing detected by the first detection unit and the second timing detected by the second detection unit change at every pulse generation timing of the periodic signal (every period of the periodic signal). Will do. Therefore, according to the third aspect of the present invention, it is possible to suppress the generation of electromagnetic noise caused by the timing at which the signal level of the target pulse signal changes periodically.

  Moreover, in the invention according to any one of claims 1 to 3, for example, when controlling the pulse width of the target pulse signal, the input of the first command value to the first detector and the input to the second detector For example, as described in claim 4, the second command value is input by calculating the first command value and the second command value based on the pulse width command value that defines the pulse width of the target pulse signal. This can be realized by providing a command value calculation unit that outputs a value to the first detection unit and outputs a second command value to the second detection unit. Thereby, the timing at which the signal level of the target pulse signal changes can be changed according to the pulse width of the target pulse signal defined by the pulse width command value.

  Further, in the invention according to any one of claims 1 to 4, for example, when controlling the pulse width (duty ratio) of the target pulse signal, the pulse of the target pulse signal as described in claim 5, for example. Based on the pulse width command value that defines the width, a pulse pattern signal generation unit that generates a pulse pattern signal whose signal level changes according to the number of generated pulses in one cycle of the target pulse signal is provided. By synthesizing the first timing detection signal output from the first detection unit, the second timing detection signal output from the second detection unit, and the pulse pattern signal output from the pulse pattern signal generation unit, the target pulse signal Is preferably generated. Thereby, the number of generated pulses in one cycle of the target pulse signal can be changed according to the pulse width of the target pulse signal.

The pulse generation method according to the sixth aspect of the present invention is the first clock signal having a period T ₁ = Ts / ((M + 1) · p) from the original clock signal (where Ts is the period of the target pulse signal, and M and p are Natural number), a second clock signal with period T ₂ = Ts / (M · q) (where q is a natural number), a third clock signal with period T ₃ = Ts / a, and a second clock signal with period T ₄ = Ts / b A clock generator that generates four clock signals (where a and b are natural numbers and the greatest common divisor = 1), one of the first clock signal and the second clock signal, the third clock signal, and the second clock signal. A periodic signal generator that generates a periodic signal that generates a pulse at a timing synchronized with the four clock signals, and a first timing at which the number of pulses of the first clock signal from the pulse generation timing of the periodic signal is input. Reaching the first command value A first detector for detecting a timing, and a second timing at which the number of pulses of the second clock signal from the pulse generation timing of the periodic signal reaches a second command value that defines the input second timing; A second detection unit; and a pulse generation unit that generates a target pulse signal whose signal level changes at each of the first timing detected by the first detection unit and the second timing detected by the second detection unit; , A pulse generation method for generating the target pulse signal by the clock generation unit, wherein each of the periods T ₁ and T ₂ is changed from the pulse generation timing of the periodic signal to the next pulse generation timing by the clock generation unit. a boundary time t ₁ of each of the first partial periods of time obtained by dividing the period until every period T _3, pieces of time obtained by dividing the period in each cycle T ₄ A boundary time t ₂ of the second partial periods of less than the minimum value tmin absolute value of the difference of, so as to satisfy the condition that, since each to generate the first to fourth clock signals, according to claim 1, wherein Similar to the invention, even if there is a change in the target specification such as the period of the pulse signal to be generated, the highly accurate control of the pulse signal can be easily realized.

  As one aspect, even if there is a change in the target specification such as the cycle of the pulse signal to be generated, there is an effect that the highly accurate control of the pulse signal can be easily realized.

It is a schematic block diagram of a power supply device. It is a block diagram which shows an example of a structure of a pulse generation apparatus. It is a diagram for explaining the basic principle of pulse width generation. It is a timing chart which shows each signal generated by a clock generation part, a periodic signal generation part, the 1st amendment part, and the 2nd amendment part. It is a timing chart which shows each signal generated by a pulse pattern signal generation part, a rising pulse edge signal formation part, a falling pulse edge signal formation part, and a pulse generation part. To 4, a timing chart, assuming that the period T ₁ of the first clock signal p times the period T ₂ of the second clock signal and the q times. It is a timing chart for demonstrating the conditions which suppress that a pulse generate | occur | produces in a period signal with a period shorter than the period Tsw of a PWM pulse signal. It is a block diagram which shows the other example of a structure of a pulse generation apparatus. FIG. 9 is a timing chart showing a rising pulse edge signal, a falling pulse edge signal, and a PWM pulse signal when the number of generated pulses in one cycle = 1. FIG. 9 is a timing chart showing a rising pulse edge signal, a falling pulse edge signal, and a PWM pulse signal when the number of generated pulses in one cycle = 2. It is a block diagram which shows the other example of a structure of a pulse generation apparatus. It is a timing chart which shows operation | movement of the set priority RS flip-flop applicable to the pulse generation part of the pulse generator shown in FIG. 11 is a timing chart showing the operation of an AND gate applicable to the pulse generation unit of the pulse generation device shown in FIG.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a power supply device 10. The power supply device 10 includes a DC power supply 12. One end of a capacitor 14 and a collector of a transistor 16 are connected to a plus terminal of the DC power supply 12, and the other end of the capacitor 14 is connected to a minus terminal of the DC power supply 12. ing.

  The cathode of the diode 18 and one end of the choke coil 20 are connected to the emitter of the transistor 16, and the anode of the diode 18 is connected to the other end of the capacitor 14. One end of a capacitor 22 is connected to the other end of the choke coil 20, and the other end of the capacitor 22 is connected to the anode of the diode 18. The load 24 of the power supply device 10 is connected in parallel with the capacitor 22.

  A plus-side connection line between the capacitor 22 and the load 24 is connected to an input end of an A / D (analog / digital) converter 28 via a signal line 26, and an output end of the A / D converter 28 is a digital operation. The input terminal of the unit 29 is connected. The A / D converter 28 converts the output voltage of the power supply device 10 (DC voltage supplied to the load 24) into a digital value (output voltage data) indicating the magnitude of the output voltage, and outputs the digital value to the digital calculation unit 29. To do.

The digital arithmetic unit 29 is based on the deviation between the output voltage of the power supply device 10 represented by the output voltage data input from the A / D converter 28 and a preset target voltage (for example, 5 [V]). By a predetermined control, a command value of the duty ratio of a PWM (Pulse Width Modulation) pulse signal for making the output voltage of the power supply device 10 coincide with the target voltage is calculated. Examples of the predetermined control include known PI control (Proportional-Integral Controller) and PID control (Proportional-Integral-Differential Controller), but are not limited thereto.

  The output terminal of the digital calculation unit 29 is connected to the input terminal of the pulse generator 30, and the duty ratio command value of the PWM pulse signal calculated by the digital calculator 29 is input to the pulse generator 30. The pulse generation device 30 generates a PWM pulse signal controlled to the duty ratio represented by the command value input from the digital calculation unit 29. The PWM pulse signal is an example of the target pulse signal in the present invention.

  The output terminal of the pulse generator 30 is connected to the base of the transistor 16, and the pulse generator 30 supplies the generated PWM pulse signal to the base of the transistor 16. As a result, the transistor 16 is turned on and off at a duty ratio corresponding to the PWM pulse signal supplied to the base, and the output voltage of the power supply device 10 is controlled to match the target voltage. Note that the pulse generation device 30 can be configured by, for example, an FPGA (Field-Programmable Gate Array).

  Next, the details of the pulse generator 30 will be described with reference to FIG. 2A includes a command value calculation unit 32, a clock generation unit 44, a periodic signal generation unit 56, a first correction unit 70, a first detection unit 72, a second correction unit 78, and a second detection unit 80. And a pulse generator 86.

  The command value calculation unit 32 calculates various command values based on the command value of the duty ratio of the PWM pulse signal input from the digital calculation unit 29. The command value calculator 32 includes a pulse width command value calculator 34, a rise timing command value calculator 36, a fall timing command value calculator 38, a control circuit 40, and a pulse pattern signal generator 42.

Based on the input duty ratio command value, the pulse width command value calculation unit 34 determines an on time Ton during which the signal is at a high level in one cycle of the PWM pulse signal. Then, the pulse width command value calculation unit 34 calculates the pulse width command value k by dividing the determined on-time Ton by the time resolution Δ of the pulse width of the preset PWM pulse signal (next ( (See 1).)
k = Ton / Δ (1)

  The pulse width command value calculator 34 is connected to a rising timing command value calculator 36, a falling timing command value calculator 38, and a pulse pattern signal generator 42. The pulse width command value k is a rising timing command value. The values are input to the calculation unit 36, the fall timing command value calculation unit 38, and the pulse pattern signal generation unit 42, respectively.

Here, the basic principle of pulse generation in the pulse generation device 30 according to the present embodiment will be described. In the present embodiment, by using two clocks having different periods such as clocks A and B shown in FIG. 3 as an example, a pulse having a pulse width with time resolution Δ is generated. Note that a natural number M, the period T _A of the clock A in (2), the period T _B of clock B is (3), the time resolution Δ pulse width (4), PWM pulse signal The period Tsw is expressed by equation (5).
T _A = M · Δ (2)
T _B = (M + 1) · Δ (3)
Δ = T _B −T _A = (M + 1) · Δ−M · Δ (4)
Tsw = M · (M + 1) · Δ (5)

FIG. 3 shows a case where M = 3 as an example, and the period T _A = 3 · Δ of the clock A, the period T _B = 4 · Δ of the clock B, and the time resolution Δ = Tsw / 12. . Then, by selectively combining the change timings of the signal levels of the clocks A and B within the period Tsw of the PWM pulse signal, as shown as pulse patterns 1 to 12 in FIG. 3, the on time Ton (= k · Δ) 12 types of pulse patterns that differ in increments of Δ in time resolution can be generated.

When the start of the period Tsw of the PWM pulse signal is set at time t = 0, in each pulse pattern, the pulse rising timing t _rise is expressed by equation (6), and the pulse falling timing t _fall is expressed by equation (7). Is done.
t _rise = {kmod (M + 1)} · TA = {k mod (M + 1)} · M · Δ (6)
t _fall = {kmod M} · TB = {k mod M} · (M + 1) · Δ (7)
Note that “A mod B” in the expressions (6) and (7) represents that the remainder of A / B is calculated.

Based on the pulse width command value k input from the pulse width command value calculation unit 34, the rise timing command value calculation unit 36 calculates the pulse rise timing command value _trie by the above equation (6). The fall timing command value calculation unit 38 calculates the command value t _fall of the pulse fall timing based on the pulse width command value k input from the pulse width command value calculation unit 34 according to the above equation (7). To do. The rising timing command value t _rise is an example of the first command value in the present invention, and the falling timing command value t _fall is an example of the second command value in the present invention.

The rising timing command value calculator 36 and the falling timing command value calculator 38 are connected to the control circuit 40. The rising timing command value t _rise of the pulse calculated by the rising timing command value calculation unit 36 is input to the first detection unit 72 at a predetermined timing via the control circuit 40 and is calculated by the falling timing command value calculation unit 38. The pulse falling timing command value t _fall is input to the second detection unit 80 via the control circuit 40 at a predetermined timing.

  Based on the pulse width command value k input from the pulse width command value calculation unit 34, the pulse pattern signal generation unit 42 generates a pulse pattern signal whose signal level switches according to the number of generated pulses in one cycle of the PWM pulse signal. Generate. As an example, in the 12 types of pulse patterns shown in FIG. 3, the number of generated pulses of pulse patterns 1 to 6, 8, 9, and 12 = 1, and the number of generated pulses of pulse patterns 7, 10, and 11 = 2. In this example, the pulse pattern signal generation unit 42 switches the signal level of the pulse pattern signal between the case where the pulse width command value k = 10 or 11 and the other case.

  In this embodiment, more specifically, the pulse pattern signal generation unit 42 inverts the logic of the signal level of the pulse pattern signal for each cycle of the PWM pulse signal. For example, in the odd-numbered cycle of the PWM pulse signal, the pulse pattern signal generation unit 42 sets the pulse pattern signal to low level when the number of generated pulses = 1, and sets the pulse pattern signal to high level when the number of generated pulses = 2. In the even-numbered cycle of the PWM pulse signal, the pulse pattern signal is set to high level when the number of generated pulses = 1, and the pulse pattern signal is set to low level when the number of generated pulses = 2. An example of the pulse pattern signal is shown in FIG.

The clock generator 44 includes an original clock signal generator 46, a first multiplier / divider 48, a second multiplier / divider 50, a third multiplier / divider 52, and a fourth multiplier / divider 54. It is out. The original clock signal generation unit 46 generates an original clock signal having a cycle of T ₀ and outputs the original clock signal to the first multiplication / division unit 48 to the fourth multiplication / division unit 54, respectively.

The first multiplier / divider 48 generates a first clock signal obtained by multiplying the period T ₀ of the original clock signal input from the original clock signal generator 46 by 1 / (D ₁ · p) times. In the present embodiment, p ≧ 2 and the period of the first clock signal T ₁ = T ₀ / (D ₁ · p). FIG. 4 shows an example of a signal obtained by multiplying the period T ₀ of the original clock signal by 1 / D ₁ times as “original signal of the first clock”, and further increasing the period of this signal to 1 / p times. An example of the signal is shown as a first clock signal. Incidentally, the first multiplier / divider unit 48 in FIG. 2, a functional block that the period of the input clock signal to 1 / D ₁ ×, functional blocks of the period of the input clock signal to 1 / p times The first multiplier / divider 48 can also be realized by a single circuit.

The second multiplying / dividing unit 50 generates a second clock signal obtained by multiplying the period T ₀ of the original clock signal input from the original clock signal generating unit 46 by 1 / (D ₂ · q). In the present embodiment, q ≧ 2 and the cycle of the second clock signal is T ₂ = T ₀ / (D ₂ · q). Figure 4, an example of the signal cycle T ₀ of the original clock signal to 1 / D ₂ times shown denoted as "original signal of the second clock", the period of this signal further 1 / q times An example of the signal is shown as the second clock signal. Incidentally, the second multiplier / divider unit 50 in FIG. 2, a functional block that the period of the input clock signal to 1 / D _2-fold, functional blocks of the period of the input clock signal to 1 / q times However, the second multiplying / dividing unit 50 can be realized by a single circuit.

When the first and second clock signals are used as the clocks A and B shown in FIG. 3, the period T ₁ of the first pulse signal is replaced by the following equation (8) instead of the previous equation (2). The period T ₂ of the second pulse signal is represented by the following expression (9) instead of the previous expression (3), and the period Tsw of the PWM pulse signal is replaced by the following ( It is expressed by equation (10).
T ₁ = M · Δ / p (8)
T ₂ = (M + 1) · Δ / q (9)
Tsw = M · (M + 1) · Δ / (p · q) (10)

The third multiplying / dividing unit 52 generates a third clock signal obtained by multiplying the period T ₀ of the original clock signal input from the original clock signal generating unit 46 by 1 / D ₃ times. The period of the third clock signal is T ₃ = T ₀ / D ₃ = Tsw / a. The fourth multiplying / dividing unit 54 generates a fourth clock signal obtained by multiplying the period T ₀ of the original clock signal input from the original clock signal generating unit 46 by 1 / D ₄ times. The cycle of the fourth clock signal is T ₄ = T ₀ / D ₄ = Tsw / b, where a and b are natural numbers and the greatest common divisor = 1. FIG. 4 shows an example of the third clock signal and the fourth clock signal, respectively.

  The periodic signal generator 56 includes a first rising edge detection one-pulse circuit 58, a second rising edge detection one-pulse circuit 60, a first AND circuit 62, a first falling edge detection one-pulse circuit 64, and a second falling edge detection one-pulse. A circuit 66 and a second AND circuit 68 are included.

  The first rising edge detection one-pulse circuit 58 receives the first clock signal and the third clock signal from the clock generation unit 44, and the first clock signal is at the high level during the period when the third clock signal is at the high level. Then, while the first clock signal is at a high level, a first / third clock synchronization signal (an example is shown in FIG. 4) that is at a high level is generated, and the generated first / third clock synchronization signal is a first AND circuit. To 62. The first rising edge detection one-pulse circuit 58 is a first / third clock synchronization signal that is at a high level for a predetermined period when the first clock signal is at a high level during a period in which the third clock signal is at a high level. May be generated and output.

  The second rising edge detection one-pulse circuit 60 receives the first clock signal and the fourth clock signal from the clock generation unit 44, and when the first clock signal becomes high level during the period when the fourth clock signal is high level. The first / fourth clock synchronization signal (an example is shown in FIG. 4) that becomes high while the first clock signal is at the high level is generated, and the generated first / fourth clock synchronization signal is used as the first AND circuit 62. Output to. Note that the second rising edge detection one-pulse circuit 60 is configured such that the first / fourth clock synchronization signal that is at the high level for a predetermined period when the first clock signal is at the high level during the period in which the fourth clock signal is at the high level. May be generated and output.

  The first AND circuit 62 receives the first / third clock synchronization signal input from the first rising edge detection one-pulse circuit 58 and the first / fourth clock synchronization signal input from the second rising edge detection one-pulse circuit 60. And a signal corresponding to the logical product of the two, that is, a periodic signal in which a pulse is generated at a period Tsw of the PWM pulse signal, and the generated periodic signal is output to the first detection unit 72. FIG. 4 shows an example of a periodic signal output from the first AND circuit 62 as “periodic signal (combination of first / third clock synchronization signal and first / fourth clock synchronization signal)”.

  The first falling edge detection one-pulse circuit 64 receives the second clock signal and the third clock signal from the clock generation unit 44, and the second clock signal is at the high level during the period when the third clock signal is at the high level. Then, while the second clock signal is at the high level, the second / third clock synchronization signal (an example is shown in FIG. 4) which becomes the high level is generated, and the generated second / third clock synchronization signal is generated as the second AND. Output to the circuit 68. Note that the first falling edge detection one-pulse circuit 64 is synchronized with the second / third clock that becomes high level for a predetermined period when the second clock signal becomes high level while the third clock signal is high level. A signal may be generated and output.

  The second falling edge detection one-pulse circuit 66 receives the second clock signal and the fourth clock signal from the clock generation unit 44, and the second clock signal is set to the high level during the period when the fourth clock signal is at the high level. Then, the second / fourth clock synchronization signal (an example is shown in FIG. 4) that is high while the second clock signal is at the high level is generated, and the generated second / fourth clock synchronization signal is generated as the second AND circuit. Output to 68. Note that the second falling edge detection one-pulse circuit 66 is synchronized with the second / fourth clock synchronization which is set to the high level for a predetermined period when the second clock signal is set to the high level during the period in which the fourth clock signal is set to the high level. A signal may be generated and output.

  The second AND circuit 68 receives the second / third clock synchronization signal input from the first falling edge detection one-pulse circuit 64 and the second / fourth clock input from the second falling edge detection one-pulse circuit 66. A signal corresponding to the logical product of the synchronization signal and the periodic signal in which a pulse is generated at the period Tsw of the PWM pulse signal is generated, and the generated periodic signal is output to the second detection unit 80. FIG. 4 shows an example of a periodic signal output from the second AND circuit 68 as “periodic signal (combination of second / third clock synchronization signal and second / fourth clock synchronization signal)”.

  As shown in FIG. 4, in this embodiment, the periodic signal output from the first AND circuit 62 and the periodic signal output from the second AND circuit 68 are the same signal. Therefore, a set of the first rising edge detection one-pulse circuit 58, the second rising edge detection one-pulse circuit 60, and the first AND circuit 62, the first falling edge detection one-pulse circuit 64, and the second falling edge detection one-pulse One of the pair of the circuit 66 and the second AND circuit 68 is omitted, and the periodic signals generated by the remaining pair are output to the first detector 72 and the second detector 80, respectively. Also good.

The first correction unit 70, is inputted from the clock generation unit 44 first clock signal, the period T ₁ of the first clock signal input to produce a corrected first clock signal to p times, generated correction first The clock signal is output to the first detection unit 72. In FIG. 4, an example of the corrected first clock signal output from the first correction unit 70 (example of p = 2) is represented as “divided signal of the first clock divided by two”.

  The first detection unit 72 includes a first clock counting unit 74 and a rising pulse edge signal forming unit 76A. The first clock counting unit 74 receives the first clock signal from the clock generation unit 44 and receives the periodic signal from the first AND circuit 62 of the periodic signal generation unit 56 as the clear signal CLR. The corrected first clock signal is input as the clock enable signal CE.

  The first clock counting unit 74 resets the count value every time a pulse is input as the clear signal CLR (periodic signal) and starts the addition count or the subtraction count alternately (the initial value of the count value in the case of the addition count). The value is 0, and the initial value of the count value in the case of subtraction count is M). Then, the first clock counting unit 74 increments the count value by one each time the pulse of the first clock signal is input while the clock enable signal CE (corrected first clock signal) is at the high level ( Decrement the count value by 1 (in the case of subtraction count). FIG. 5 shows an example of the transition of the count value output from the first clock counter 74 when “M = 3” and Δ = Tsw / 12, expressed as “first clock counter output”.

The rising pulse edge signal forming unit 76A receives the count value from the first clock counting unit 74, the rising timing command value _trie from the command value calculation unit 32, and the period from the first AND circuit 62 of the periodic signal generation unit 56. A signal is input. The rising pulse edge signal forming unit 76A switches the output signal (rising pulse edge signal) to a high level every time the input periodic signal becomes a high level, and the rising timing command value t _rise to which the input count value is input. Is reached (at a timing corresponding to the first timing in the present invention), the rising pulse edge signal to be output is switched to a low level. The rising pulse edge signal is an example of the first timing detection signal in the present invention.

5 shows, the rising timing command value of the first period of the periodic signal _{t rise} = 2, the rising timing command value of the second period of the periodic signal _{t rise} = 1, 3 cycle of rising timing command value _{t rise} of the periodic signal An example of the rising pulse edge signal output from the rising pulse edge signal forming unit 76A when = 3 and the rising timing command value t _rise = 2 of the fourth period of the periodic signal is shown.

Second corrector 78 is inputted from the clock generator 44 and the second clock signal, the period T ₂ of the second clock signal to generate a corrected second clock signal to the q times entered, generated correction second The clock signal is output to the second detection unit 80. In FIG. 4, an example of the corrected second clock signal output from the second correction unit 78 (example of q = 2) is indicated as “second divided signal of the second clock”.

  The second detector 80 includes a second clock counter 82 and a falling pulse edge signal generator 84A. The second clock counting unit 82 receives the second clock signal from the clock generation unit 44 and also receives the periodic signal from the second AND circuit 68 of the periodic signal generation unit 56 as the clear signal CLR. The corrected second clock signal is input as the clock enable signal CE.

  Each time a pulse is input as the clear signal CLR (periodic signal), the second clock counting unit 82 resets the count value and alternately starts the addition count or the subtraction count (the initial count value in the case of the addition count). The value is 0, and the initial value of the count value in the case of subtraction count is M + 1). Then, the second clock counter 82 increments the count value by one each time the pulse of the second clock signal is input while the clock enable signal CE (corrected second clock signal) is at the high level ( Decrement the count value by 1 (in the case of subtraction count). FIG. 5 shows an example of the transition of the count value output from the second clock counter 82 when M = 3 and Δ = Tsw / 12, expressed as “second clock counter output”.

The falling pulse edge signal forming unit 84A receives the count value from the second clock counting unit 82, receives the falling timing command value _tfall from the command value calculation unit 32, and receives the second AND circuit 68 of the periodic signal generation unit 56. A periodic signal is input from. The falling pulse edge signal forming unit 84A switches the output signal (falling pulse edge signal) to high level every time the inputted periodic signal becomes high level, and the falling timing command to which the inputted count value is inputted. When the value t _fall is reached (at a timing corresponding to the second timing in the present invention), the output falling pulse edge signal is switched to a low level. The falling pulse edge signal is an example of the second timing detection signal in the present invention.

FIG. 5 shows the falling timing command value t _fall = 2 of the first cycle of the periodic signal, the falling timing command value t _fall = 0 of the second cycle of the periodic signal, and the falling timing command of the third cycle of the periodic signal. An example of the falling pulse edge signal output from the falling pulse edge signal forming unit 84A when the value t _fall = 1 and the falling timing command value t _fall = 2 of the fourth period of the periodic signal is shown.

  The pulse generating unit 86 is connected to the rising pulse edge signal forming unit 76A, the falling pulse edge signal forming unit 84A, and the pulse pattern signal generating unit 42, and the rising pulse edge signal is input from the rising pulse edge signal forming unit 76A. The falling pulse edge signal is input from the falling pulse edge signal forming unit 84A, and the pulse pattern signal is input from the pulse pattern signal generating unit 42.

  FIG. 2 shows a mode in which the pulse generation unit 86 is configured by a three-input XOR (exclusive OR) circuit 88. The pulse generation unit 86 includes a rising pulse edge signal, a falling pulse edge signal, and a pulse pattern signal. Is output as a PWM pulse signal. With the above-described configuration, the pulse width for each period of the PWM pulse signal is selected from a plurality of types of pulse patterns in which the on-time Ton (= k · Δ) differs in increments of Δ in time resolution as shown in FIG. A pulse pattern corresponding to the command value k is selectively output as a PWM pulse signal. FIG. 5 shows an example of the PWM pulse signal output from the pulse generation unit 86.

  Next, the operation of this embodiment will be described. The pulse generation device 30A according to the present embodiment is configured to prevent the electromagnetic wave noise generated by the pulse generation device 30A from interfering with the reception of AM radio waves when the power supply device 10 is mounted on a vehicle or the like. It is desirable that the period Tsw (also referred to as a switching period) of the pulse signal is out of the range corresponding to the frequency band (approximately 500 to 1600 [kHz]) of the radio waves of AM radio. This can be achieved by setting the frequency fsw (= 1 / Tsw) of the PWM pulse signal to, for example, 2 [MHz].

  However, if the pulse width of the PWM pulse signal having the frequency fsw = 2 [MHz] is to be controlled with a resolution of, for example, 4096 or more, the time resolution of the pulse width is 100 [ps] (= 1/2 [MHz] × 4096). It is necessary to reduce it to the following. When this time resolution is realized simply by increasing the frequency of the clock signal, the frequency of the required clock signal is 10 [GHz], which is more than 20 times the frequency of a general clock signal, which is not realistic. For this reason, the pulse generation device 30A according to the present embodiment uses two clocks having different periods by the time resolution Δ as described above with reference to FIG. 3 to reduce the pulse width of the pulse signal. A technology that controls the time resolution in increments of Δ is used.

  However, even in this technique, if the time resolution of the pulse width is reduced, the count start timing of the two counters that count the number of pulses of clocks with different periods must be matched with the two clocks, the count value of the counter Due to the deviation, an error occurs in the pulse width of the PWM pulse signal with respect to the command value. To solve this problem, the technique described in Patent Document 2 described above realizes the above timing alignment by inputting a reset signal to the reference clock generation unit and the adjustment clock generation unit for each period. Yes. However, the technique described in Patent Document 2 requires accuracy in the creation of the circuit of the clock generation unit, etc., and it is costly to cope with a change in target specifications such as a change in the period and resolution of a pulse signal to be generated. I have another problem that takes time.

For this reason, in the present embodiment, the clock generation unit 44 includes a first clock signal with a cycle T ₁ = Ts / ((M + 1) · p), which is a target of counting the number of pulses, respectively, from the original clock signal, and a cycle T ₂ = Ts / (M · q), respectively, and a third clock signal with period T ₃ = Ts / a and a fourth clock with period T ₄ = Ts / b Clock signals (where a and b are natural numbers and the greatest common divisor = 1) are also generated.

  In addition, the periodic signal generation unit 56 generates a periodic signal in which a pulse is generated at the timing when the first clock signal, the third clock signal, and the fourth clock signal are synchronized (see “first / third clock synchronization” in FIG. 4). Signal and a periodic signal expressed as “combination of the first and fourth clock synchronization signals” and a pulse is generated at the timing when the second clock signal, the third clock signal, and the fourth clock signal are synchronized. To generate a periodic signal (periodic signal expressed as “combination of second / third clock synchronization signal and second / fourth clock synchronization signal” in FIG. 4).

Then, the first detector 72 detects the timing at which the number of pulses of the first clock signal from the pulse generation timing of the periodic signal reaches the input rising timing command value t _rise to form a rising pulse edge signal. The second detection unit 80 detects the timing at which the number of pulses of the second clock signal from the pulse generation timing of the periodic signal reaches the input falling timing command value t _fall to form a falling pulse edge signal. To do.

  As described above, in this embodiment, the clock generation unit 44 generates the third clock signal and the fourth clock signal from the original clock signal, and the periodic signal generation unit 56 includes the first clock signal or the second clock signal, A periodic signal is generated from the third clock signal and the fourth clock signal, and the first detection unit 72 and the second detection unit 80 detect the first clock signal or the second clock signal from the pulse generation timing of the periodic signal. Since the number of pulses is counted, the counting start timing of the number of pulses of the first detection unit 72 and the second detection unit 80 matches the timing of the first and second clock signals.

Further, in the present embodiment, the clock generator 44 generates the PWM pulse signal using the first to fourth clock signals generated from the original clock signal, respectively, but the period T _{1 to} T of the _first to fourth clock signals. ₄ is n / m times (n and m are natural numbers) of the period Tsw of the PWM pulse signal, so that the clock generator 44 causes the first to fourth clocks to be divided by at least one of dividing and multiplying the original clock signal. The configuration is such that the signal generation is simple and the period T _{1 to} T ₄ can be easily changed. Thereby, it is possible to easily cope with a change in the target specification such as the period of the PWM pulse signal.

Further, in the present embodiment, the timing of the rising pulse edge detected by the first detector 72 is determined according to the rising timing command value _trie, and the timing of the falling pulse edge detected by the second detector 80 is the falling timing. Since it is determined according to the command value t _fall , the timing of the rising pulse edge and the falling pulse edge, that is, the timing when the signal level of the PWM pulse signal rises according to the rising timing command value t _rise , and the signal level of the PWM pulse signal Needless to say, the timing of falling according to the _fall timing command value t _fall can be accurately controlled independently of each other in increments of Δ.

  By the way, in this embodiment, since one of the first clock signal and the second clock signal, the third clock signal, and the fourth clock signal are synchronized with each other, a periodic signal pulse is generated. When a period in which the three types of clock signals used in the period synchronize with a period shorter than the period Ts of the PWM pulse signal (for example, all the three types of clock signals are at a high level) occurs, The number of pulses of the clock signal and the second clock signal deviates from the original values, and the PWM pulse signal is distorted.

As an example, FIG. 6 shows a timing chart when it is assumed that the period T ₁ of the first clock signal is multiplied by p and the period T ₂ of the second clock signal is multiplied by q with respect to the timing chart of FIG.

  In FIG. 6, in the period indicated as the switching cycle, the period in which the third clock signal is at the high level for the second time and the period in which the fourth clock signal is at the high level for the second time partially overlap. During this overlapping period, the first clock signal also changes to the high level. As a result, during the synchronization, the first / third clock synchronization signal and the first / fourth clock synchronization signal are each at a high level, and accordingly, the first / third clock synchronization signal and the first / third clock synchronization signal are A pulse generated with a cycle shorter than the cycle Tsw of the PWM pulse signal (= the switching cycle shown in FIG. 6) is generated in the periodic signal obtained by synthesizing the fourth clock synchronization signal with “×” in FIG. doing.

  Further, in the period shown as the switching cycle in FIG. 6, the period when the third clock signal is at the high level for the third time and the period when the fourth clock signal is at the high level for the third time are one. The second clock signal is also changed to a high level within the overlapping period. As a result, during the synchronization, the second / third clock synchronization signal and the second / fourth clock synchronization signal are each at a high level, and accordingly, the second / third clock synchronization signal and the second / second clock synchronization signal are A pulse generated with a cycle shorter than the cycle Tsw of the PWM pulse signal (= the switching cycle shown in FIG. 6) is generated in the periodic signal obtained by synthesizing the fourth clock synchronization signal with “×” in FIG. doing.

  As described above, whenever a pulse occurs in the periodic signal with a period shorter than the period Tsw of the PWM pulse signal, the count value of the first clock counter 74 and the count value of the second clock counter 82 are cleared each time. As a result, the PWM pulse signal is distorted.

Therefore, in the present embodiment, in order to prevent the pulse is generated in the periodic signal with a period shorter than the period Tsw of the PWM pulse signal, as shown in FIG. 7, the period T ₁ and second first clock signal Each period T ₂ of the clock signal includes a boundary time t ₁ of each first partial period when the period from the pulse generation timing of the periodic signal to the next pulse generation timing is divided for each period T ₃ , and the period the boundary time t ₂ of the individual second partial periods of time obtained by dividing every period T _4, smaller than the minimum value tmin of the absolute value of the difference, provided the condition that, configured so as to satisfy the condition Yes.

Specifically, in order to satisfy the above condition, p, q ≧ 2 is set, and the first multiplication / frequency division unit 48 of the clock generation unit 44 sets the cycle T ₀ of the original clock signal to 1 / (D ₁ · p). The first clock signal multiplied by two is generated, and the second multiplication / dividing unit 50 generates the second clock signal by multiplying the period T ₀ of the original clock signal by 1 / (D ₂ · q) times. second clock signal and the period T ₂ of the are the difference between the period T ₁ of the first clock signal and at least twice the time resolution of the pulse width delta. The first correction portion 70 generates and outputs the corrected first clock signal in which the period T ₁ of the first clock signal to p times the first detection unit 72, the second correction portion 78 of the second clock signal A corrected second clock signal in which the period T ₂ is multiplied by q is generated and output to the second detection unit 80.

  When the above condition is satisfied, as shown in FIG. 4, a periodic signal obtained by synthesizing the first / third clock synchronization signal and the first / fourth clock synchronization signal, and the second / second Generation of a pulse with a cycle shorter than the cycle Tsw of the PWM pulse signal is prevented from occurring in the cycle signal obtained by synthesizing the 3-clock synchronization signal and the second / fourth clock synchronization signal.

  Therefore, according to the present embodiment, the third clock signal and the fourth clock signal are generated from the original clock signal, and the first clock signal or the second clock signal, the third clock signal, and the fourth clock signal are used. When generating a periodic signal and counting the number of pulses of the first clock signal or the second clock signal from the pulse generation timing of the periodic signal, it is possible to obtain a periodic signal that generates a pulse at the period Tsw of the PWM pulse signal. The pulse width of the PWM pulse signal can be accurately controlled.

  Further, in the present embodiment, the first clock counting unit 74 of the first detection unit 72 counts the number of pulses of the first clock signal from the pulse generation timing of the periodic signal at every pulse generation timing of the periodic signal. The addition count and the subtraction count are alternately repeated, and the second clock counting unit 82 of the second detection unit 80 counts the number of pulses of the second clock signal from the pulse generation timing of the periodic signal, and the pulse generation timing of the periodic signal. Each time, the addition count and the subtraction count are alternately repeated.

As a result, the first clock counting unit 74 and the second clock counting unit 82 compare the rising timing command value _trie and the rising timing command value with respect to the case where only the addition count or the subtraction count is repeated at each pulse generation timing of the periodic signal. Even if at least one of the falling timing command values t _fall continues with a constant value, the timing of the rising pulse edge detected by the first detector 72 and the timing of the falling pulse edge detected by the second detector 80 are periodic signals. It changes at every pulse generation timing (every period of the periodic signal). Therefore, it is possible to suppress the generation of electromagnetic noise from the power supply apparatus 10 due to the timing at which the signal level of the PWM pulse signal changes periodically.

  The configuration of the pulse generator 30 is not limited to the pulse generator 30A shown in FIG. FIG. 8 shows a pulse generator 30B. Compared with the pulse generation device 30A, the pulse generation device 30B includes a rising pulse edge signal formation unit 76B instead of the rising pulse edge signal formation unit 76A, and a falling pulse instead of the falling pulse edge signal formation unit 84A. The difference is that an edge signal forming unit 84B is provided and a two-input XOR circuit 90 is provided instead of the three-input XOR circuit 88.

  The rising pulse edge signal forming unit 76B and the falling pulse edge signal forming unit 84B are also connected to the pulse pattern signal generating unit 42, and a pulse pattern signal is input from the pulse pattern signal generating unit 42. As shown in FIGS. 9A and 9B, the rising pulse edge signal forming unit 76B has a signal level of the pulse pattern signal input from the pulse pattern signal generating unit 42, that is, the number of generated pulses in one cycle of the PWM pulse signal is 1 or 2. Accordingly, the logic of the rising pulse edge signal to be output is inverted.

Specifically, when the input pulse pattern signal has a signal level representing the number of generated pulses = 1, the rising pulse edge signal forming unit 76B, as shown in FIG. 9A, when the input periodic signal becomes a high level. When the rising pulse edge signal to be output is set to a high level and the input _count value reaches the input rising timing command value _trie , the output rising pulse edge signal is switched to a low level.

On the other hand, when the input pulse pattern signal has a signal level indicating the number of generated pulses = 2, the rising pulse edge signal forming unit 76B outputs a rising edge that is output when the input periodic signal becomes high level as shown in FIG. 9B. When the pulse edge signal is set to the low level and the input _count value reaches the input rising timing command value _trie , the output rising pulse edge signal is switched to the high level.

  Thereby, the output signal of the XOR circuit 90 corresponding to the XOR of the rising pulse edge signal from the rising pulse edge signal forming unit 76B and the falling pulse edge signal from the falling pulse edge signal forming unit 84B, that is, the PWM pulse When the number of generated pulses = 1, one pulse is output in one cycle of the PWM pulse signal as shown in FIG. 9A, and when the number of generated pulses = 2, the PWM pulse is output as shown in FIG. 9B. Two pulses are output in one cycle of the signal.

  Next, the pulse generation device 30C illustrated in FIG. 10 will be described. Compared with the pulse generator 30B, the pulse generator 30C is provided with a set priority RS flip-flop 92 in place of the 2-input XOR circuit 90, and the rising pulse edge signal from the rising pulse edge signal forming unit 76B is received. The difference is that the falling pulse edge signal input to the set terminal S of the set priority RS flip-flop 92 is input to the reset terminal R of the set priority RS flip-flop 92. .

  The set priority RS flip-flop 92 sets the output signal to a high level regardless of the level of the input signal at the reset terminal when the input signal at the set terminal S is at a high level, and sets the output signal at the low level when the input signal at the set terminal S is at a low level. If the input signal at the reset terminal is at a high level, the output signal is set at a low level. If the input signal at the reset terminal is also at a low level, the output signal is maintained at the current level.

  Therefore, when the pulse generation unit 86 is configured by the set priority RS flip-flop 92, as shown in FIG. 11A, a PWM pulse signal having a pulse width smaller than the rising pulse edge signal input to the set terminal S can be generated. Can not. However, for example, in driving a switching element, it is not necessary to generate a PWM pulse signal having a small pulse width due to a problem of responsiveness of the switching element.

  In addition to the XOR circuits 88 and 90 and the set priority RS flip-flop 92 described above, a gate circuit can be applied as the pulse generator 86. FIG. 11B shows the operation of an AND gate as an example of a gate circuit. The gate circuit including the AND gate is not limited in the pulse width of the PWM pulse signal like the set priority RS flip-flop 92, and can be applied to various applications.

  Further, in the above description, the first clock counting unit 74 and the second clock counting unit 82 have described an aspect in which an addition count and a subtraction count are alternately repeated at every pulse generation timing of a periodic signal. However, the present invention is not limited to this. Instead, the addition count or the subtraction count may be randomly performed at each pulse generation timing of the periodic signal. Also in this case, generation of electromagnetic noise from the power supply device 10 can be suppressed. In addition, when the 1st clock counting part 74 and the 2nd clock counting part 82 repeat only an addition count or only a subtraction count, the electromagnetic noise which generate | occur | produces from the power supply device 10 increases, but this invention is such Aspects are also included in the scope of rights.

Further, in the above outputs to the first detection unit 72 is the first correction unit 70 generates the corrected first clock signal in which the period T ₁ of the first clock signal to p times, the second correction portion 78 is a second clock The aspect in which the corrected second clock signal in which the signal cycle T ₂ is multiplied by q is generated and output to the second detection unit 80 has been described. However, the present invention is not limited to this. For example, the first correction unit 70 multiplies the rising timing command value _trie and outputs it to the first detection unit 72, and the second correction unit 78 sets the falling timing command The value t _fall may be multiplied by q and output to the second detection unit 80.

Furthermore, in the above, in order to satisfy the condition that each of the periods T ₁ and T ₂ is smaller than the minimum value tmin of the absolute value of the difference between the boundary time t ₁ and the boundary time t ₂ , p, q ≧ 2 The aspect made was explained. That is, the first multiplier / divider 48 of the clock generator 44 generates a first clock signal in which the period T ₀ of the original clock signal is 1 / (D ₁ · p) times, and the second multiplier / divider 50 generates the second clock signal by multiplying the period T ₀ of the original clock signal by 1 / (D ₂ · q), so that the period T ₂ of the _second clock signal and the period T ₁ of the first clock signal are The mode in which the difference is set to be twice or more the time resolution Δ of the pulse width has been described. However, the present invention is not limited to this, and the period T ₀ of the original clock signal is set to 1 / p or 1 / q times depending on the relationship of parameters such as the period Tsw of the PWM pulse signal and the time resolution Δ of the pulse width. It is also possible to generate the first clock signal and the second clock signal that satisfy the above-described conditions. In this case, since at least the first correction unit 70 and the second correction unit 78 can be omitted, the configuration is simplified.

  Moreover, although the aspect which applied this invention to the production | generation of the PWM pulse signal used for the PWM control of the output voltage of the power supply device 10 was demonstrated above, the pulse generation device which concerns on this invention is limited to mounting in a power supply device. However, the present invention is not limited to using the pulse signal generated by the pulse generator for PWM control. The pulse generator according to the present invention can be used for other purposes such as a clock generator.

DESCRIPTION OF SYMBOLS 10 ... Power supply device 30,30A, 30B, 30C ... Pulse generator, 32 ... Command value calculating part, 34 ... Pulse width command value calculating part, 36 ... Rising timing command value calculating part, 38 ... Falling timing command value calculation , 42... Pulse pattern signal generation unit, 44... Clock generation unit, 46... Original clock signal generation unit, 48... First multiplication / frequency division unit, 50. Frequency dividing unit 54... 4th frequency division / frequency dividing unit 56... Period signal generation unit 58... First rising edge detection one pulse circuit 60. First falling edge detection one-pulse circuit 66 Second falling edge detection one-pulse circuit 68 Second AND circuit 70 First correction unit 72 First detection unit 74 1 clock counter, 76A, 76B ... rising pulse edge signal generator, 78 ... second corrector, 80 ... second detector, 82 ... second clock counter, 84A, 84B ... falling pulse edge signal generator, 86: Pulse generation unit, 88 ... XOR circuit, 90 ... XOR circuit, 92 ... Set priority RS flip-flop

Claims (6)

From the original clock signal, a _first clock signal having a period T ₁ = Ts / ((M + 1) · p) (where Ts is a period of a target pulse signal, M and p are natural numbers), and a period T ₂ = Ts / (M · q ) Second clock signal (where q is a natural number), a third clock signal having a period T ₃ = Ts / a, and a fourth clock signal having a period T ₄ = Ts / b (where a and b are natural numbers and the greatest promise) A clock generator for generating (number = 1) each;
A periodic signal generator that generates a periodic signal in which a pulse is generated at a timing in which one of the first clock signal and the second clock signal, the third clock signal, and the fourth clock signal are synchronized;
A first detector that detects a first timing at which a pulse number of the first clock signal from a pulse generation timing of the periodic signal reaches a first command value that defines an input first timing;
A second detector for detecting a second timing at which the number of pulses of the second clock signal from the pulse generation timing of the periodic signal reaches a second command value that defines the input second timing;
A pulse generator for generating a target pulse signal whose signal level changes at each of the first timing detected by the first detector and the second timing detected by the second detector;
Including
The clock generation unit is configured such that each of the periods T ₁ and T ₂ is a boundary between individual first partial periods when the period from the pulse generation timing of the periodic signal to the next pulse generation timing is divided every period T _3. the time t _1, so as to satisfy the minimum is smaller than tmin, the condition that the absolute value of the difference between the boundary time t ₂ of the individual second partial periods of time obtained by dividing the period in each cycle T _4, A pulse generator for generating each of the first to fourth clock signals. When p, q = 1 does not satisfy the above condition, the clock generation unit performs a process including setting p, q ≧ 2 and setting the period of the clock signal to change the period to 1 / p times. Generating the first clock signal of T ₁ and performing the processing including multiplying the period of the clock signal whose period is changed by 1 / q times to generate the second clock signal of period T ₂ ;
The cycle of the first clock signal is multiplied by p and input to the first detection unit and the cycle of the second clock signal is multiplied by q and input to the second detection unit, or the first command value 2. The pulse generation device according to claim 1, further comprising a correction unit that multiplies p and inputs the second command value to the first detection unit and inputs the second command value to the second detection unit. Whether the first detection unit alternately counts the number of pulses of the first clock signal from the pulse generation timing of the periodic signal, and alternately repeats the addition count and the subtraction count at each pulse generation timing of the periodic signal. , Randomly adding or subtracting,
Whether the second detector repeats counting the number of pulses of the second clock signal from the pulse generation timing of the periodic signal alternately between the addition count and the subtraction count at each pulse generation timing of the periodic signal. The pulse generation device according to claim 1, wherein the addition count or the subtraction count is randomly performed.   The first command value and the second command value are calculated based on a pulse width command value that defines a pulse width of the target pulse signal, the first command value is output to the first detector, and the second command value is output. The pulse generation device according to any one of claims 1 to 3, further comprising a command value calculation unit that outputs a command value to the second detection unit. A pulse pattern signal generator that generates a pulse pattern signal whose signal level changes according to the number of generated pulses in one cycle of the target pulse signal based on a pulse width command value that defines a pulse width of the target pulse signal; In addition,
The pulse generation unit includes a first timing detection signal output from the first detection unit, a second timing detection signal output from the second detection unit, and a pulse pattern output from the pulse pattern signal generation unit. The pulse generation device according to any one of claims 1 to 4, wherein the target pulse signal is generated by combining signals. From the original clock signal, a _first clock signal having a period T ₁ = Ts / ((M + 1) · p) (where Ts is a period of a target pulse signal, M and p are natural numbers), and a period T ₂ = Ts / (M · q ) Second clock signal (where q is a natural number), a third clock signal having a period T ₃ = Ts / a, and a fourth clock signal having a period T ₄ = Ts / b (where a and b are natural numbers and the greatest promise) A clock generator for generating (number = 1) each;
A periodic signal generator that generates a periodic signal in which a pulse is generated at a timing in which one of the first clock signal and the second clock signal, the third clock signal, and the fourth clock signal are synchronized;
A first detector that detects a first timing at which a pulse number of the first clock signal from a pulse generation timing of the periodic signal reaches a first command value that defines an input first timing;
A second detector for detecting a second timing at which the number of pulses of the second clock signal from the pulse generation timing of the periodic signal reaches a second command value that defines the input second timing;
A pulse generator for generating a target pulse signal whose signal level changes at each of the first timing detected by the first detector and the second timing detected by the second detector;
A pulse generation method for generating the target pulse signal by a pulse generation device including:
Each of the periods T ₁ and T ₂ is a boundary between each first partial period when the period from the pulse generation timing of the periodic signal to the next pulse generation timing is divided every period T ₃ by the clock generation unit. the time t _1, so as to satisfy the minimum is smaller than tmin, the condition that the absolute value of the difference between the boundary time t ₂ of the individual second partial periods of time obtained by dividing the period in each cycle T _4, A pulse generation method for generating the first to fourth clock signals, respectively.