JP2017038006A - Nitride semiconductor light emitting diode and nitride semiconductor light emitting diode manufacturing method - Google Patents

Abstract

A nitride semiconductor light emitting diode with high quality, low cost, and high light extraction efficiency is provided.
A heterogeneous substrate, a first group III nitride semiconductor layer, a mask made of an oxide or nitride and having a periodic pattern, and a first group over the mask. A second group III nitride semiconductor layer 4 epitaxially grown on the nitride semiconductor layer 2, a first conductivity type nitride semiconductor layer 11, a second conductivity type nitride semiconductor layer 13, and electrodes 14 and 15 are provided. And the light emission wavelength of the light emitting structure 10 is λ, the pattern period of the mask 3 is 0.85λ or more and 1.15λ or less, and the width of the mask 3 in the direction in which the pattern has periodicity. Is a nitride semiconductor light emitting diode 100 in which the thickness of the mask 3 is 0.15λ or more and 0.70λ or less, or 1.25λ or more and 1.80λ or less.
[Selection] Figure 1

Description

  The present invention relates to a nitride semiconductor light emitting diode and a method for manufacturing a nitride semiconductor light emitting diode.

Patent Document 1 discloses a nitride semiconductor light emitting diode. In the nitride semiconductor light emitting diode, a first undoped GaN layer, a mask made of SiO ₂ , a second undoped GaN layer, an n-type layer, an active layer, and a p-type layer are laminated in this order on a sapphire substrate. . According to the disclosure of the example, the thickness of the first undoped GaN layer is 5 μm, the thickness of the mask is 0.1 μm, the width of the mask stripe is 15 μm, the interval between the stripes of the mask (window) is 5 μm, The thickness of the undoped layer is 10 μm.

  Patent Document 2 discloses a nitride semiconductor light emitting diode. In the nitride semiconductor light emitting diode, a first conductivity type nitride semiconductor layer, an active layer, and a second conductivity type nitride semiconductor layer are stacked on a substrate made of a nitride semiconductor. That is, a sapphire substrate is not used. For this reason, the fall of the light extraction efficiency by reflection of the light in the interface of a sapphire substrate and a nitride semiconductor layer is suppressed. The nitride semiconductor light-emitting diode improves light extraction efficiency by forming irregularities that change the traveling direction of light on the lower surface of a substrate made of a nitride semiconductor.

  Patent Documents 3 to 6 disclose a method for manufacturing a template substrate having a nitride semiconductor layer. In these manufacturing methods, a nitride semiconductor layer is formed on a heterogeneous substrate such as a sapphire substrate, and then a mask having a pattern period and a mask width in nanometer units is formed thereon. A nitride semiconductor is epitaxially grown on the nitride semiconductor layer through a mask. In any of Patent Documents 3 to 6, it is disclosed that a mask may be formed directly on a heterogeneous substrate.

JP 2002-33512 A International Publication No. 2010/150809 JP 2014-76928 A JP 2014-76929 A JP 2014-78652 A JP 2014-78653 A

  There is a need for nitride semiconductor light emitting diodes that are high quality, low cost, and high in light extraction efficiency.

  The arrangement position, shape, and size of the opening of the mask for laterally growing the group III nitride semiconductor can affect the quality of the group III nitride semiconductor layer. For example, the dislocation density generated in the group III nitride semiconductor layer can be controlled by the size, arrangement position, shape, etc. of the opening. In the case of the technique described in Patent Document 1 in which the mask period and width are in units of micrometers, the degree of freedom of the mask pattern is small, and there is a situation in which the size, arrangement position, shape, etc. of the opening cannot be set to a desired state. obtain. As a result, the quality of the group III nitride semiconductor layer becomes insufficient, which may affect the quality of the nitride semiconductor light emitting diode.

  In the case of the technique described in Patent Document 2, since a substrate made of a nitride semiconductor is used instead of the sapphire substrate, the cost becomes high. Further, in order to change the traveling direction of light, irregularities having only the function are formed on the lower surface of the substrate made of a nitride semiconductor. For this reason, the manufacturing cost increases accordingly.

  Patent Documents 3 to 6 do not disclose a technical idea related to light extraction efficiency of a nitride semiconductor light emitting diode.

  An object of the present invention is to provide a nitride semiconductor light emitting diode having high quality, low cost, and high light extraction efficiency.

According to the present invention,
A heterogeneous substrate made of a different material from the group III nitride semiconductor;
A first group III nitride semiconductor layer located on the heterogeneous substrate;
A mask located on the first group III nitride semiconductor layer, made of oxide or nitride, and having a periodic pattern;
A second group III nitride semiconductor layer epitaxially grown on the first group III nitride semiconductor layer over the mask;
A light emitting structure located on the second group III nitride semiconductor layer and having an n-type group III nitride semiconductor layer, a p-type group III nitride semiconductor layer, and an electrode;
Have
When the emission wavelength of the light emitting structure is λ,
The period of the pattern of the mask is 0.85λ or more and 1.15λ or less,
The width of the mask in the direction in which the pattern has periodicity is 0.25λ to 0.60λ,
A nitride semiconductor light emitting diode having a mask thickness of 0.15λ to 0.70λ or 1.25λ to 1.80λ is provided.

Moreover, according to the present invention,
A first step of forming a first group III nitride semiconductor layer on a heterogeneous substrate;
A second step of forming a mask formed of an oxide or nitride and having a periodic pattern formed on the first group III nitride semiconductor layer;
A third step of epitaxially growing a group III nitride semiconductor on the first group III nitride semiconductor layer over the mask to form a second group III nitride semiconductor layer;
A fourth step of forming a light emitting structure having an n-type group III nitride semiconductor layer, a p-type group III nitride semiconductor layer, and an electrode on the second group III nitride semiconductor layer;
Have
In the second step,
When the emission wavelength of the light emitting structure is λ,
The period of the pattern of the mask is 0.85λ or more and 1.15λ or less,
The width of the mask in the direction in which the pattern has periodicity is 0.25λ to 0.60λ,
A method of manufacturing a nitride semiconductor light emitting diode for forming the mask having a thickness of the mask of 0.15λ to 0.70λ or 1.25λ to 1.80λ is provided.

  According to the present invention, a nitride semiconductor light emitting diode with high quality, low cost, and high light extraction efficiency is realized.

It is an example of the side surface schematic diagram of the nitride semiconductor light-emitting diode of this embodiment. It is an example of the plane schematic diagram of the mask of this embodiment. It is an example of the plane schematic diagram of the mask of this embodiment. It is an example of the plane schematic diagram of the mask of this embodiment. It is a manufacturing process figure which shows an example of the manufacturing method of the board | substrate part of this embodiment. It is a manufacturing process figure which shows an example of the manufacturing method of the board | substrate part of this embodiment. It is a manufacturing process figure which shows an example of the manufacturing method of the board | substrate part of this embodiment. It is an example of the schematic diagram of an HVPE apparatus. It is a figure for demonstrating the content of simulation. It is a figure which shows a simulation result. It is a figure which shows a simulation result. It is a figure which shows a simulation result. It is a figure which shows a simulation result. It is a figure which shows a simulation result. It is an example of the side surface schematic diagram of the board | substrate part of this embodiment. It is an example of the side surface schematic diagram of the board | substrate part of this embodiment. It is a figure for demonstrating the effect of this embodiment. It is an example of the side surface schematic diagram of the board | substrate part of this embodiment.

  Hereinafter, embodiments of a nitride semiconductor light-emitting diode and a method for manufacturing a nitride semiconductor light-emitting diode according to the present invention will be described with reference to the drawings. The drawings are only schematic diagrams for explaining the configuration of the invention in an easy-to-understand manner.The size, shape, and number of each member, the size and thickness ratio of different members, etc. are shown unless otherwise specified. It is not limited to what you do.

<First Embodiment>
First, an outline of the nitride semiconductor light emitting diode of the present embodiment will be described. In the present embodiment, after the first nitride semiconductor layer is formed on a heterogeneous substrate such as a sapphire substrate, a mask having a pattern period and a mask width in nanometer units is obtained using the techniques described in Patent Documents 3 to 6. Form. Then, a nitride semiconductor is epitaxially grown on the first nitride semiconductor layer through a mask, and a light emitting structure is formed thereon.

  In the present embodiment, by optimizing the thickness of the first nitride semiconductor layer, the pattern period of the mask, the width and the thickness, etc., the quality of the group III nitride semiconductor grown over the mask is improved, The light extraction efficiency of light of a predetermined wavelength (efficiency of extracting light in the nitride semiconductor light emitting diode to the outside) is improved. Details will be described below.

  First, the configuration of the nitride semiconductor light emitting diode of this embodiment will be described. FIG. 1 shows an example of a schematic side view of a nitride semiconductor light emitting diode 100 of the present embodiment. As shown in the drawing, the nitride semiconductor light emitting diode 100 has a substrate portion 6 and a light emitting structure 10. The substrate unit 6 includes a heterogeneous substrate 1, a first group III nitride semiconductor layer 2, a mask 3, and a second group III nitride semiconductor layer 4. The light emitting structure 10 includes a first conductivity type nitride semiconductor layer 11, an active layer 12, a second conductivity type nitride semiconductor layer 13, a second electrode 14, and a first electrode 15. Hereinafter, each component will be described.

  The heterogeneous substrate 1 is a substrate made of a material different from that of the group III nitride semiconductor. The heterogeneous substrate 1 is preferably, for example, one of a sapphire substrate, a silicon substrate, a SiC substrate, a GaAs substrate, a GaP substrate, and a ZnO substrate. Of these, a sapphire substrate or a silicon substrate is preferable from the viewpoint of manufacturing cost, ease of handling, and the like.

  The first group III nitride semiconductor layer 2 is located on the heterogeneous substrate 1. The first group III nitride semiconductor layer 2 includes, for example, a low temperature growth buffer layer and an epitaxial layer formed thereon. The thickness of the first group III nitride semiconductor layer 2 is not less than 0.1 μm and not more than 2 μm. By setting the lower limit in this way, the light extraction efficiency of the light emitted from the light emitting structure 10 is improved. Details thereof will be described below. In addition, by setting the upper limit in this way and not increasing the thickness of the first group III nitride semiconductor layer 2 unnecessarily, it is possible to reduce costs, improve manufacturing efficiency, and reduce the thickness of the device.

The first group III nitride semiconductor layer 2 is In _x Al _y Ga _z N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1), for example, a GaN layer is there. The surface of the first group III nitride semiconductor layer 2 opposite to the heterogeneous substrate 1 is a crystal plane, for example, a (0001) plane (c plane).

The mask 3 is located on the first group III nitride semiconductor layer 2. The mask 3 is made of oxide or nitride, and for example, SiO ₂ is exemplified. The mask 3 forms a periodic repeating pattern. The region where the mask 3 does not exist is an opening, and the first group III nitride semiconductor layer 2 underneath is exposed in this portion. Although not shown, as disclosed in Patent Documents 3 to 6, a recess (a recess formed in the first group III nitride semiconductor layer 2) may be formed in a region immediately below the opening. .

  An example of the pattern of the mask 3 is shown in FIGS. 2 to 4 are examples of schematic plan views of the mask 3. In the example shown in FIG. 2, the line-shaped masks 3 are repeatedly arranged in a one-dimensional direction to form a stripe pattern. In the example shown in FIG. 3, the dot-shaped masks 3 are repeatedly arranged in the vertical direction and the horizontal direction. In the example shown in FIG. 4, todd-shaped masks 3 are repeatedly arranged in a lattice pattern. Note that the examples shown in FIGS. 2 to 4 are merely examples, and the present invention is not limited to these. For example, the dots may be other shapes instead of squares. The masks 3 may be arranged according to other regularity.

  The pattern period, mask width, and thickness of the mask 3 of this embodiment are optimized according to the emission wavelength λ of the light emitting structure 10. The pattern period (P in FIG. 2) of the mask 3 is 0.85λ or more and 1.15λ or less, preferably 0.90λ or more and 1.10λ or less. The width (W in FIG. 2) of the mask 3 in the direction in which the pattern has periodicity (lateral direction in FIG. 2) is 0.25λ to 0.60λ, preferably 0.30λ to 0.55λ. The thickness of the mask 3 (D in FIG. 1) is 0.15λ to 0.70λ or 1.25λ to 1.80λ, preferably 0.20λ to 0.65λ or 1.30λ to 1.75λ. It is.

  In addition, as shown in FIGS. 3 and 4, when there are a plurality of directions in which the pattern has periodicity (both FIGS. 3 and 4 are three directions of vertical, horizontal, and diagonal), all directions are as described above. Although optimized, it is sufficient that at least one of them is optimized as described above. Especially, it is preferable that the direction with the smallest period P is optimized as mentioned above.

  As will be described below, the light extraction efficiency of the light emitted from the light emitting structure 10 is improved by optimizing the pattern period, mask width, and thickness of the mask 3 in this manner. Further, by making the width of the opening of the mask 3 (= (pattern period) − (mask width)) sufficiently small as described above (for example, 300 nm or less), dislocations are disclosed as disclosed in Patent Document 6. It can be reduced sufficiently. As a result, a high-quality second group III nitride semiconductor layer 4 is obtained.

Returning to FIG. 1, the second group III nitride semiconductor layer 4 is a layer epitaxially grown on the first group III nitride semiconductor layer 2 through the mask 3. That is, the second group III nitride semiconductor layer 4 is composed of a group III nitride semiconductor epitaxially grown from the first group III nitride semiconductor layer 2 exposed at the opening of the mask 3. The second group III nitride semiconductor layer 4 is In _x Al _y Ga _z N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1), for example, a GaN layer. is there. The second group III nitride semiconductor layer 4 preferably has the same composition as the first group III nitride semiconductor layer 2.

The second group III nitride semiconductor layer 4 has a group III nitride semiconductor facet structure and a group III nitride semiconductor film provided so as to cover the facet structure. Is also one facet structure and film _{In x Al y Ga z N (} x + y + z = 1,0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1), the same composition. For example, GaN.

  The thickness of the second group III nitride semiconductor layer 4 is, for example, 10 μm to 35 μm, preferably 10 μm to 30 μm, and more preferably 10 μm to 20 μm. Since the second group III nitride semiconductor layer 4 grows over the mask 3 whose pattern period and mask width are in nanometer units, even if the upper limit of the thickness is set in this way, the first group III nitride is sufficiently formed. The physical semiconductor layer 2 and the mask 3 can be filled and planarized. As a result of being able to reduce the thickness in this way, it is possible to reduce costs, improve manufacturing efficiency, and reduce the thickness of the device.

  The structure of the second group III nitride semiconductor layer 4 of the present embodiment is disclosed in, for example, Patent Documents 3 to 6, “Group III nitride semiconductor obtained by epitaxially growing a group III nitride semiconductor from an opening of a mask” The configuration can be the same as that of the “layer”.

  In the light emitting structure 10, a first conductivity type nitride semiconductor layer 11, an active layer 12, and a second conductivity type nitride semiconductor layer 13 are stacked in this order. A first electrode 15 is located on the first conductivity type nitride semiconductor layer 11. A second electrode 14 is located on the second conductivity type nitride semiconductor layer 13.

  When the first conductivity type nitride semiconductor layer 11 is an n-type group III nitride semiconductor layer, the second conductivity type nitride semiconductor layer 13 becomes a p-type group III nitride semiconductor layer. When the first conductivity type nitride semiconductor layer 11 is a p-type group III nitride semiconductor layer, the second conductivity type nitride semiconductor layer 13 becomes an n-type group III nitride semiconductor layer.

  In addition, the light emitting structure 10 of this embodiment can employ | adopt all the structures according to a prior art. For example, the configuration of the active layer 12 is not particularly limited, and any configuration according to the conventional technology can be adopted. Further, the light emitting structure 10 may be configured without the active layer 12.

  The light emitting structure 10 may be configured to emit blue light (wavelength: about 380 nm to about 495 nm). Alternatively, the light emitting structure 10 may be configured to emit green light (wavelength: about 495 nm to about 570 nm). Alternatively, the light emitting structure 10 may be configured to emit red light (wavelength: about 610 nm to about 780 nm). The light emitted from the light emitting structure 10 can be adjusted by adjusting the compound constituting the light emitting structure 10.

Next, a method for manufacturing the nitride semiconductor light emitting diode 100 of this embodiment will be described. The manufacturing method of the nitride semiconductor light emitting diode 100 of this embodiment is as follows.
A first step of forming a first group III nitride semiconductor layer on a heterogeneous substrate;
A second step of forming a mask formed of an oxide or nitride and having a periodic pattern formed on the first group III nitride semiconductor layer;
A third step of epitaxially growing a group III nitride semiconductor over the first group III nitride semiconductor layer over a mask to form a second group III nitride semiconductor layer;
A fourth step of forming a light emitting structure having an n-type group III nitride semiconductor layer, a p-type group III nitride semiconductor layer, and an electrode on the second group III nitride semiconductor layer;
Have

  In the second step, when the emission wavelength of the light emitting structure is λ, the pattern period is 0.85λ or more and 1.15λ or less, preferably 0.90λ or more and 1.10λ or less, and the pattern has periodicity. The width in the direction is 0.25λ to 0.60λ, preferably 0.30λ to 0.55λ, and the thickness is 0.15λ to 0.70λ or 1.25λ to 1.80λ, preferably 0 A mask that is 20λ to 0.65λ or 1.30λ to 1.75λ is formed.

  Hereinafter, with reference to FIGS. 5 to 8, an example of a manufacturing method (first to third steps) of the substrate unit 6 which is a characteristic part of the nitride semiconductor light emitting diode 100 of the present embodiment will be described. In addition, since the method (4th process) which manufactures the light emission structure 10 on the board | substrate part 6 is realizable using all the prior arts, description here is abbreviate | omitted.

The manufacturing method of the substrate unit 6 of this embodiment is as follows:
Preparing a transfer body having an uneven pattern formed on the surface;
A step of first growing a group III nitride semiconductor on the heterogeneous substrate 1 to obtain a first group III nitride semiconductor layer 2 (first step);
A step of providing a coating film covering the first group III nitride semiconductor layer 2 (second step);
A step of providing a transfer layer for covering the coating film (second step);
A step (second step) of bringing the uneven pattern of the transfer body into contact with the transferred layer and transferring the uneven pattern to the transferred layer;
The transfer layer has an opening by removing the portion located at the bottom of the recess formed in the transfer layer by the transferring process and the portion of the coating film located below the bottom of the recess. A step of forming the mask 3 (second step);
A step of obtaining a second group III nitride semiconductor layer 4 by epitaxially growing a group III nitride semiconductor from the opening of the mask 3 (third step);
including.

  In such a manufacturing method, by forming the concave / convex pattern of the transfer body into a desired shape, the mask 3 having a desired pattern, that is, the mask 3 satisfying the above-described conditions (pattern period, mask 3 width, etc.) is obtained. Can be obtained. In the case of such a manufacturing method, a fine pattern can be formed by setting the pattern period and the width of the mask 3 to the nanometer unit. For this reason, the degree of freedom in designing the mask 3 is increased, and a desired mask 3 can be formed. Hereinafter, each of the above steps will be described in detail.

"Process of preparing a transfer body"
As shown in FIG. 5A, a master mold 30 having a concavo-convex pattern corresponding to the pattern of the mask 3 is prepared. The master mold 30 is made of, for example, silicon or quartz. The master mold 30 is manufactured as follows, for example.

  A metal film, for example, a Cr film is formed on a quartz or silicon substrate by sputtering to have a thickness of 10 to 20 nm. An electron beam resist film is applied onto the metal film, and the resist is irradiated with an electron beam (EB) from a drawing apparatus, and then developed with a developing device. Thereafter, the metal film exposed from the opening of the resist is etched by a dry etching apparatus to form an opening in the metal film. Further, the substrate exposed from the opening of the metal film is etched by a dry etching apparatus. Thereafter, the resist film and the metal film are all peeled off. Thereby, the master mold 30 can be obtained.

  On the other hand, the laminated body which apply | coated the resin layer 22 on the film 21 is prepared. The application method is not particularly limited, but a spin coating method can be employed.

  Next, as shown in FIG. 5 (B), the master mold 30 on which the concavo-convex pattern is formed is pressed on the resin layer 22 so that the resin layer 22 enters the recess of the master mold 30. Transfer uneven pattern.

  At this time, either a thermal imprint method in which transfer is performed by heating the resin layer 22 or an optical imprint method in which transfer is performed by irradiating the resin layer 22 with light may be employed. It is preferable to adopt an optical imprinting method (for example, UV (ultraviolet) imprinting method) capable of

  In the thermal imprint method, the resin layer 22 containing a thermoplastic resin is heated to a glass transition temperature or higher to be softened, and the concave / convex pattern of the master mold 30 is transferred to the resin layer 22. Thereafter, the resin layer 22 is cooled and solidified.

  On the other hand, in the photoimprint method, the resin layer 22 is made of a photocurable resin composition, and the uncured resin layer 22 is brought into contact with the concavo-convex pattern of the master mold 30 to perform transfer. Then, the resin layer 22 is photocured by irradiating light such as UV (ultraviolet) light.

  The photocurable resin composition constituting the resin layer 22 is, for example, a radical polymerizable compound containing a photo radical generator and a radical polymerizable compound, or a cationic curable composition containing a photo acid generator and a cationic polymerizable compound. Things are given.

  As a radically polymerizable compound, the composition which has a (meth) acrylate compound as a main component is mentioned, for example. As a cationic curable composition, what has any 1 or more types of an epoxy compound, an oxetane compound, and a vinyl ether compound as a main component is mentioned, for example.

  Thereafter, as shown in FIG. 5C, the resin layer 22 and the master mold 30 are separated from each other to obtain a transfer body 20 composed of the resin layer 22 on which a predetermined uneven pattern is formed and the film 21. . The transfer body 20 can be prepared by the above process.

“Step of obtaining first group III nitride semiconductor layer 2”
A heterogeneous substrate 1 is prepared, and a group III nitride semiconductor is epitaxially grown on the heterogeneous substrate 1 to obtain a first group III nitride semiconductor layer 2. For example, a sapphire substrate is prepared as the heterogeneous substrate 1, and a group III nitride semiconductor is epitaxially grown on the (0001) plane of the sapphire substrate.

  For example, the first group III nitride semiconductor layer 2 is obtained under the following conditions. A low temperature growth buffer layer is formed at 400 to 700 ° C. by metal organic chemical vapor deposition (MOCVD), and then a group III nitride semiconductor layer is formed at 1000 to 1200 ° C. by MOCVD. A first group III nitride semiconductor layer 2 of ˜2 μm is obtained.

"Process of providing coating film"
This step is performed after the step of obtaining the first group III nitride semiconductor layer 2. As shown in FIG. 6A, a coating film 3 A is provided on the first group III nitride semiconductor layer 2. The coating film 3A becomes the mask 3 through subsequent processing. For example, a disilane (SiH ₄ ) gas and an oxygen gas are reacted to form a SiO ₂ coating film 3 A that covers the entire surface of one surface of the first group III nitride semiconductor layer 2. The thickness of the coating film 3A satisfies, for example, 0.25λ to 0.40λ, or 1.55λ to 1.65λ.

"Process for providing the transferred layer"
The said process is performed after the process of providing a coating film. As shown in FIG. 6A, a transferred layer 5A that covers the coating film 3A is provided. Specifically, the resin composition constituting the transfer layer 5A is applied on the coating film 3A. The application method is not particularly limited, but a spin coating method can be employed. As the transferred layer 5A, the same layer as the resin layer 22 described above can be adopted.

"Process to transfer uneven pattern to transfer layer"
This step is performed after the step of preparing the transfer body and the step of providing the transfer layer. As shown in FIGS. 6B and 6C, the concavo-convex pattern of the transfer body 20 is transferred by pressing the concavo-convex pattern of the transfer body 20 onto the transfer layer 5A. As this transfer method, a method similar to the transfer method to the resin layer 22 described above can be adopted. Specifically, either a thermal imprint method in which transfer is performed by heating the transfer target layer 5A or a photoimprint method in which transfer is performed by irradiating the transfer target layer 5A with light may be employed. It is preferable to employ an optical imprint method (for example, a UV imprint method) that can be carried out in (1).

  Thereafter, as shown in FIG. 6D, the transferred layer 5A and the transfer body 20 are separated to obtain a transferred layer 5A on which a predetermined uneven pattern is formed. As shown in FIG. 7A, the thickness of the portion 42 where the concave portion 41 of the transferred layer 5A exists is much smaller than the thickness of the portion where the concave portion 41 does not exist.

“Process for forming mask 3”
This step is performed after the step of transferring the concavo-convex pattern to the transfer layer. First, from the state of FIG. 7A, the transferred layer 5A is etched, and the portion 42 where the recessed portion 41 of the transferred layer 5A exists is removed, so that as shown in FIG. The coating film 3A is exposed at the bottom. As an etching method, dry etching is exemplified. By appropriately adjusting the etching rate of the transferred layer 5A and maintaining the arrangement pattern of the protrusions formed on the transferred layer 5A, the opening 42 is formed by removing the portion 42. As a result, the concave portion 41 of the concave / convex pattern formed in the transferred layer 5A before etching becomes the opening 43, and the mask 5 in which the convex portion becomes the covering portion 44 is formed.

  In dry etching, reactive ion etching and etching are performed in which high-frequency power is applied to the electrode on which the object is to be etched, and the ions generated from the plasma are accelerated and impacted on the object to be etched by the negative self-bias voltage generated. Although plasma etching is generally divided into etching an object to be etched by radicals generated from plasma without applying a bias to the object, any method may be adopted.

Examples of the etching gas include those containing a fluorine-based gas. As the fluorine-based gas, one or more of C _x F _y (for example, CF ₄ , C ₂ F ₆ , C ₃ F ₈ ) gas, SF ₆ gas, and CHF ₃ gas can be used. An oxygen-containing gas may be used as the etching gas. Further, an oxygen-containing gas may be mixed with the fluorine-based gas. As the oxygen-containing gas, any one or more of O ₂ gas, CO gas, and O ₃ gas can be used.

  Next, the coating film 3A (see FIG. 7B) exposed from the opening 43 of the mask 5 is selectively removed to obtain the state of FIG. 7C.

  As the etching gas, the gas described above can be used. While selecting an etching gas suitably, the selection ratio which is a ratio of the etching rate of 3 A of coating films, and the etching rate of the mask 5 is adjusted appropriately. Thereby, selective etching of the coating film 3 </ b> A exposed at the bottom of the opening 43 is realized. Here, it is preferable to perform reactive ion etching.

  Thereafter, as shown in FIG. 7D, the mask 5 is removed. For example, the mask 5 is removed by ashing. Specifically, oxygen gas may be turned into plasma by high frequency or the like, and the mask 5 may be carbonized by the plasma.

“Step of obtaining second group III nitride semiconductor layer 4”
This step is performed after the step of forming the mask 3. In this step, a group III nitride semiconductor is epitaxially grown from the first group III nitride semiconductor layer 2 exposed in the opening of the mask 3 to form the second group III nitride semiconductor layer 4. This step includes the following two steps.

(1) First growth step (2) for growing a facet structure of a group III nitride semiconductor having a facet surface inclined with respect to the growth surface of the first group III nitride semiconductor layer 2 from the opening of the mask 3 Further, a group III nitride semiconductor is grown, and a group III nitride semiconductor crystal grown from the facet structure is united to obtain a second group III nitride semiconductor layer 4.

  In the first growth step and the second growth step, the same type of vapor phase growth method is used. The partial pressure of the group III source gas in the first growth step is higher than the partial pressure of the group III source gas in the second growth step. Below, each growth process is demonstrated in detail.

"First growth process"
In the first growth step, a group III nitride semiconductor is epitaxially grown from the opening of the mask 3 to form a facet structure.

First, as shown in FIG. 8, the structure 60 (see FIG. 7D) obtained in the above-described process is set in the folder 51 in the reaction tube 50 of the HVPE (Hydride Vapor Phase Epitaxy) apparatus 500. Then, nitrogen (N ₂ ) gas is supplied through the gas introduction pipes 53 and 54 to purge the inside of the reaction pipe 50. The gas supplied into the reaction tube 50 is discharged from the discharge port 58. After sufficiently purging the inside of the reaction tube 50, the reaction tube 50 is heated by the heater 55 by switching to hydrogen (H ₂ ) gas. When the temperature of the growth region 56 reaches around 500 ° C., the temperature is increased by adding a group V source gas (a nitrogen-containing gas such as ammonia (NH ₃ )) gas from the gas introduction pipe 54. Further, the temperature increase is continued until the temperature of the Ga source (group III source) 57 region reaches 850 ° C. and the temperature of the growth region 56 reaches 950 ° C. to 1100 ° C.

  After the temperature of the Ga source 57 region and the temperature of the growth region 56 are stabilized, a gas containing a halogen element (for example, HCl gas) is added and supplied from the gas introduction tube 53 to react with gallium (Ga) in the source boat 59. Thus, the group III element is halogenated to generate gallium chloride (GaCl) as a group III source gas and transport it to the growth region 56. Then, in the growth region 56, gallium chloride reacts with the nitrogen-containing gas to form a group III nitride semiconductor.

  As described above, a plurality of facet structures grown from each of the plurality of openings can be obtained. The process ends before the plurality of facet structures grown from each of the plurality of openings are fully united and integrated. Note that the process may end after a part of adjacent facet structures are combined.

The partial pressure of the group III source gas (here, GaCl) is higher than the partial pressure of the group III source gas (here, GaCl) in the second growth step described below. For example, the partial pressure of the group III source gas in this step is preferably 2 × 10 ⁻³ MPa or more and 6 × 10 ⁻³ MPa or less. In particular, it is preferably 3 × 10 ⁻³ MPa or more.

Furthermore, the ratio of the flow rate (molar supply amount) of the group V source gas (nitrogen-containing gas (NH ₃ gas)) and the flow rate (molar supply amount) of the group III source gas (GaCl gas) in the first growth step A certain V / III ratio is preferably lower than the V / III ratio in the second growth step. For example, the V / III ratio in this step is preferably 5 or more and 15 or less. In addition, it is preferable that the flow rate of the group III source gas is 100 cc / min to 300 cc / min, and the flow rate of the group V source gas is 500 cc / min to 4500 cc / min.

  In the first growth step, the growth time of the facet structure immediately after the supply of the gas containing a halogen element is started is, for example, 10 to 60 seconds.

  In this specification, the V / III ratio refers to a value based on the molar ratio. However, HVPE growth is performed at normal pressure. In addition, since the Group III source gas and the Group V source gas are supplied at the same pressure and temperature, the flow rate ratio thereof shows the same value regardless of the flow rate ratio standard or the molar ratio standard.

"Second growth process"
After the first growth step, the second growth step is performed by changing the flow rate of the group III source gas and changing the V / III ratio.

  In the second growth step, a facet structure made of a group III nitride semiconductor crystal is grown in the lateral direction, and adjacent facet structures are combined. The second group III nitride semiconductor layer 4 is formed by advancing the process and integrating a plurality of facet structures.

The HVPE method is also employed in the second growth step, but the partial pressure of the source gas containing the group III element in the second growth step is the partial pressure of the source gas containing the group III element in the first growth step. Smaller than. For example, it is set to 0.1 × 10 ⁻³ MPa or more and 2 × 10 ⁻³ MPa or less. In addition to this, the V / III ratio in the second growth step is preferably larger than the V / III ratio in the first growth step. The partial pressure of the source gas containing the group III element in the second growth step is made smaller than the partial pressure of the source gas containing the group III element in the first growth step, and V / III in the second growth step By making the ratio larger than the V / III ratio in the first growth step, the growth rate of the group III nitride semiconductor in the second growth step can be lowered.

  Especially, it is preferable that V / III ratio in a 2nd growth process is 18-30. For example, the flow rate of the group III source gas is made larger than that in the first growth step, for example, 50 cc / min to 200 cc / min, and the flow rate of the group V source gas is set to 900 cc / min to 6000 cc / min.

  In the second growth step, the flow rate of the group V source gas may be different from the flow rate of the group V source gas in the first growth step. It is preferable that only the flow rate of the source gas is different from that of the first growth step.

  From the viewpoint of manufacturing efficiency, the growth temperature of the group III nitride semiconductor in the second growth step is preferably the same as that in the first growth step, but is lower than the growth temperature in the first growth step. May be. For example, the growth temperature of the second growth process is set lower than that of the first growth process, the growth rate of the group III nitride semiconductor is reduced, and the group III nitride semiconductor crystals grown from the facet structure are gradually grown. You may combine at speed. By doing so, dislocations in the vertical direction of the base substrate (the c-axis direction of the group III nitride semiconductor) that are likely to occur when the group III nitride semiconductor crystals grown from the facet structure are united, that is, threading dislocations are performed. Can be reduced.

  The second growth step is stopped when the thickness of the second group III nitride semiconductor layer 4 reaches a predetermined thickness.

  Next, the effect of this embodiment is demonstrated.

  In this embodiment, a heterogeneous substrate 1 such as a sapphire substrate is used instead of a substrate composed of a group III nitride semiconductor. For this reason, the increase in cost by using the board | substrate comprised by the group III nitride semiconductor can be avoided.

  In the present embodiment, the second group III nitride semiconductor layer 4 is formed over the mask 3 whose pattern period and mask width are in nanometer units. Then, the width of the opening of the mask 3 (= (pattern period) − (mask width)) is made sufficiently small (eg, 300 nm or less). For this reason, dislocations can be sufficiently reduced as disclosed in Patent Document 6. As a result, the high-quality second group III nitride semiconductor layer 4 and the high-quality nitride semiconductor light emitting diode 100 are obtained.

  In the present embodiment, the thickness of the first group III nitride semiconductor layer 2, the pattern period of the mask 3, the width of the mask 3, and the thickness of the mask 3 are set according to the emission wavelength of the light emitting structure 10. The light extraction efficiency of the light of the wavelength (the efficiency of extracting the light in the nitride semiconductor light emitting diode 100 to the outside) is optimized. For this reason, the light extraction efficiency of the light emitted from the light emitting structure 10 is improved.

  In this embodiment, the mask 3 having a characteristic configuration achieves both high quality and improved light extraction efficiency. For this reason, it is not necessary to have the structure etc. which have only the function which improves light extraction efficiency. As a result, reduction of cost, improvement of manufacturing efficiency, etc. are realized.

  Here, by optimizing the thickness of the first group III nitride semiconductor layer 2, the pattern period of the mask 3, the width of the mask 3, and the thickness of the mask 3 as described above, The improvement of the light extraction efficiency will be described.

  As shown in the upper diagram of FIG. 9, the light emitted from the light emitting structure 10 moves in the nitride semiconductor light emitting diode 100. For example, when the incident angle with respect to the interface between the different substrate 1 and the first group III nitride semiconductor layer 2 or the interface between the different substrate 1 and air does not satisfy a predetermined condition, the light is totally reflected. The nitride semiconductor light emitting diode 100 cannot be taken out.

  In the case of the nitride semiconductor light emitting diode 100 of the present embodiment, the traveling direction of the light can be changed (varied) by the first group III nitride semiconductor layer 2 and the mask 3.

  When light passes through the layer on which the mask 3 is located (the layer made up of the mask 3 and the group III nitride semiconductor filling the opening), part of the light passes through the opening (that is, the group III nitride semiconductor filling the opening). However, the other part passes through the mask 3 (that is, oxide or nitride). For this reason, while passing through the layer where the mask 3 is located, the traveling speed of the light is partially different. As a result, when light exits from the layer where the mask 3 is located and enters the first group III nitride semiconductor layer 2, a phase shift occurs between the light passing through the opening and the light passing through the mask 3. Will occur. Due to such a phase shift, the traveling direction of the light traveling in the first group III nitride semiconductor layer 2 changes from the traveling direction so far.

  In the present embodiment, the thickness of the first group III nitride semiconductor layer 2 is 0.1 μm or more. For this reason, after the light passes through the layer on which the mask 3 is located, the light travels due to the phase shift before reaching the interface between the first group III nitride semiconductor layer 2 and the heterogeneous substrate 1. The change of fully occurs.

  Next, details and results of the simulation analyzing the relationship between the thickness of the first group III nitride semiconductor layer 2, the pattern period of the mask 3, the width of the mask 3, and the thickness of the mask 3 and the light extraction efficiency Indicates.

  In the simulation, it is ideal that the light extraction efficiency is obtained by tracing all the light emitted from the active layer 12. For this purpose, it is necessary to construct the entire structure of the nitride semiconductor light emitting diode 100 on simulation software. However, in that case, calculation time and memory size become enormous, and calculation becomes difficult. Therefore, here, the effect of this embodiment is simulated by paying attention to a partial structure including the mask 3 and the like, and performing calculation using a model that applies a plane wave.

9A and 9B show model structures for performing simulation. FIG. 9A shows a model without the mask 3 (SiO ₂ mask), and FIG. 9B shows a model with the mask 3 (SiO ₂ mask). The distance from the air / GaN interface to the mask 3 was 100 nm.

  FIG. 9A shows a model in which a plane wave having a wavelength of 450 nm traveling in GaN is incident on the interface between GaN and air at 45 °. Since the critical angle of total reflection at the interface between GaN and air is 23.6 °, in this model, plane waves are totally reflected and do not come out into the air.

  FIG. 9B shows a model in which a plane wave having a wavelength of 450 nm traveling in GaN is incident at 45 ° on a layer where the mask 3 is located (a layer made of GaN filling the mask 3 and the opening). . In this model, plane waves are diffracted and reflected by the presence of the layer on which the mask 3 is located.

  FIG. 10 shows a simulation result with the above model. For the simulation, commercially available software “Electromagnetic field analysis software-KeyFDTD” of Science and Technology Research Institute, Inc. was used.

  FIG. 10A shows the result of the model of FIG. 9A, and FIG. 10B shows the result of the model of FIG. 9B. As shown in FIG. 10A, in the case of the model of FIG. 9A, the plane wave hardly appears on the air side. On the other hand, as shown in FIG. 10B, in the case of the model of FIG. 9B, the plane waves appearing on the air side are clearly increased as compared with the model of FIG. 9A.

  Next, simulation results of the relationship between the period, width, and thickness of the mask 3 and the light extraction efficiency in the model of FIG. 9B are shown in FIGS. The electric field strength on the vertical axis indicates the average electric field strength in the air in the model of FIG. The larger the value, the more improved the light extraction efficiency.

  From the results of FIGS. 11 to 14, it can be seen that the average electric field strength in the air, that is, the light extraction efficiency varies depending on the period, width, and thickness of the mask 3. And it turns out that the light extraction efficiency of the nitride semiconductor light emitting diode 100 can be improved by optimizing these.

  In addition, from the results of FIGS. 11, 13, and 14, when the light emitting structure 10 emits blue light (λ = 450 nm), the preferable pattern period of the mask 3 is 382.5 nm or more from the viewpoint of improving the light extraction efficiency. It is 517.5 nm, More preferably, it is 405.0 nm or more and 495.0 nm or less. Similarly, the preferable width of the mask 3 in the direction in which the pattern has periodicity is 112.5 nm or more and 270.0 nm or less, and more preferably 135.0 nm or more and 247.5 nm or less. Similarly, the preferable thickness of the mask 3 is 67.5 nm or more and 315.0 nm or less or 562.5 nm or more and 810.0 nm or less, and more preferably 90.0 nm or more and 292.5 nm or less or 585.0 nm or more and 787.5 nm or less. It is.

  That is, assuming that the light emission wavelength of the light emitting structure 10 is λ, the mask 3 preferably has a pattern period of 0.85λ or more and 1.15λ or less, more preferably 0.90λ or more and 1.10λ or less from the viewpoint of improving light extraction efficiency. is there. Similarly, the preferable width of the mask 3 in the direction in which the pattern has periodicity is 0.25λ to 0.60λ, and more preferably 0.30λ to 0.55λ. Similarly, the thickness of the mask 3 is preferably 0.15λ or more and 0.70λ or less or 1.25λ or more and 1.80λ or less, more preferably 0.20λ or more and 0.65λ or less, or 1.30λ or more and 1.75λ or less. . As shown in FIG. 12, it can be seen that the same relationship holds when λ takes a value different from 450 nm.

<Second Embodiment>
The nitride semiconductor light emitting diode 100 of the present embodiment is different from the first embodiment in that the side surface of the mask 3 has a characteristic structure. Other configurations are the same as those of the first embodiment.

  FIGS. 15 and 16 are schematic side views of only the substrate portion 6 extracted from the nitride semiconductor light emitting diode 100 of the present embodiment.

  As illustrated, the mask side surface 3-2 and the mask side surface 3-3 are not perpendicular to the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2 (non-vertical). The mask side surface 3-1 and the mask side surface 3-3 do not have to be flat surfaces. For example, the mask side surface 3-1 and the mask side surface 3-3 may be curved or uneven. In the present embodiment, from the viewpoint of increasing the area of the mask side surface 3-2 and the mask side surface 3-3, the thickness of the mask 3 is preferably set to 1.25λ or more and 1.80λ or less. More preferably, it is 30λ or more and 1.75λ or less.

  For example, after the state of FIG. 7D is obtained, the mask 3 having the mask side surface 3-2 as shown in FIG. 15 can be obtained by dry etching from above in the drawing. The dry etching here can use the same etching gas as used when etching the coating film 3A in the “step of forming the mask 3” described in the first embodiment. The mask side surface 3-2 can be obtained by appropriately adjusting the etching time of dry etching with relatively low selectivity, the etching rate (depending on acceleration voltage, etching gas concentration, etc.), and the like.

  In addition, when obtaining the process of obtaining such a mask side surface 3-2, the thickness of the mask 3 becomes thin by the amount of dry etching in the process. For this reason, it is preferable to make the thickness of the coating film 3 </ b> A thicker than the desired thickness of the mask 3.

In addition, after the state shown in FIG. 7C is obtained, the mask 3 having the mask side surface 3-3 as shown in FIG. 16 can be obtained by performing wet etching before removing the mask 5. . The wet etching conditions here are, for example, temperature: room temperature, etching solution: buffered hydrofluoric acid (NH ₄ F (40%) + HF (49%), 6: 1), etching rate: several tens of m / min (note that , Increasing the ratio of HF increases the etching rate). The mask side surface 3-3 can be obtained by appropriately adjusting these etching conditions, etching time, and the like.

  Next, the function and effect of the nitride semiconductor light emitting diode 100 of this embodiment will be described.

  As shown in FIG. 17, when the mask side surface 3-1 is a surface that is perpendicular and flat to the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2, theoretically, the mask side surface 3-1. The incident angle of light with respect to the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2 cannot be changed by the reflection at.

That is, in the figure, the light traveling as indicated by the arrow A is not reflected by the mask side surface 3-1, but proceeds as it is and reaches the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2. The incident angle with respect to the interface is α ₀ . Further, the light traveling as indicated by the arrow A is reflected by the mask side surface 3-1, proceeds as indicated by the arrow B, and reaches the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2. The incident angle with respect to the interface is α ₁ . In the case where the mask side surface 3-1 is a plane that is perpendicular and flat with respect to the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2, α ₀ and α ₁ are theoretically equal.

  Thus, when the mask side surface 3-1 is a surface that is perpendicular and flat with respect to the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2, the reflection on the mask side surface 3-1. Therefore, the incident angle of light with respect to the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2 cannot be changed. For this reason, the light extraction efficiency cannot be increased by the reflection at the mask side surface 3-1.

  On the other hand, when the mask side surface 3-2 and the mask side surface 3-3 are provided as in the present embodiment, the reflection from the mask side surface 3-2 and the mask side surface 3-3 causes the heterogeneous substrate 1 and the first group III. The incident angle of light with respect to the interface of the nitride semiconductor layer 2 can be changed. Further, when the mask side surface 3-2 and the mask side surface 3-3 are not flat, the reflection angle of light can be varied, so that the light with respect to the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2 can be dispersed. Incident angles can be varied. As a result, the light extraction efficiency can be increased by such reflection on the mask side surface 3-2 and the mask side surface 3-3.

  According to the present embodiment, in addition to the improvement of the light extraction efficiency due to the operation described in the first embodiment, the improvement of the light extraction efficiency due to reflection at the mask side surface 3-2 and the mask side surface 3-3 can also be realized. . As a result, the light extraction efficiency can be further increased.

  As a modification, as shown in FIG. 18, the mask side surface 3-1 may be perpendicular to the interface between the heterogeneous substrate 1 and the first group III nitride semiconductor layer 2. In this case, the thickness of the mask 3 is preferably 0.15λ or more and 0.70λ or less, and more preferably 0.20λ or more and 0.65λ or less. In the case of this example, improvement in light extraction efficiency due to reflection at the mask side surface 3-1 cannot be expected. For this reason, the area of the mask side surface 3-1 may be small. By reducing the thickness of the mask 3 as described above, it is possible to reduce costs, improve manufacturing efficiency, and reduce the thickness of the device.

Hereinafter, examples of the reference form will be added.
1. A heterogeneous substrate made of a different material from the group III nitride semiconductor;
A first group III nitride semiconductor layer located on the heterogeneous substrate;
A mask located on the first group III nitride semiconductor layer, made of oxide or nitride, and having a periodic pattern;
A second group III nitride semiconductor layer epitaxially grown on the first group III nitride semiconductor layer over the mask;
A light emitting structure located on the second group III nitride semiconductor layer and having an n-type group III nitride semiconductor layer, a p-type group III nitride semiconductor layer, and an electrode;
Have
When the emission wavelength of the light emitting structure is λ,
The period of the pattern of the mask is 0.85λ or more and 1.15λ or less,
The width of the mask in the direction in which the pattern has periodicity is 0.25λ to 0.60λ,
The nitride semiconductor light emitting diode, wherein the mask has a thickness of 0.15λ to 0.70λ, or 1.25λ to 1.80λ.
2. The nitride semiconductor light emitting diode according to 1, wherein
A nitride semiconductor light emitting diode in which a side surface of the mask is not perpendicular to an interface between the heterogeneous substrate and the first group III nitride semiconductor layer.
3. In the nitride semiconductor light emitting diode according to 2,
The nitride semiconductor light emitting diode, wherein the mask has a thickness of 1.25λ or more and 1.80λ or less.
4). The nitride semiconductor light emitting diode according to 1, wherein
A side surface of the mask is perpendicular to an interface between the heterogeneous substrate and the first group III nitride semiconductor layer;
The nitride semiconductor light emitting diode, wherein the mask has a thickness of 0.15λ or more and 0.70λ or less.
5). In the nitride semiconductor light emitting diode according to any one of 1 to 4,
The nitride semiconductor light emitting diode wherein the thickness of the first group III nitride semiconductor layer is 0.1 μm or more and 2 μm or less.
6). In the nitride semiconductor light-emitting diode according to any one of 1 to 5,
The light emitting structure emits blue light,
The period of the pattern of the mask is 382.5 nm or more and 517.5 nm or less,
The width of the mask in the direction in which the pattern has periodicity is 112.5 nm or more and 270.0 nm or less,
The nitride semiconductor light emitting diode, wherein the mask has a thickness of 67.5 nm to 315.0 nm or 562.5 nm to 810.0 nm.
7). A first step of forming a first group III nitride semiconductor layer on a heterogeneous substrate;
A second step of forming a mask formed of an oxide or nitride and having a periodic pattern formed on the first group III nitride semiconductor layer;
A third step of epitaxially growing a group III nitride semiconductor on the first group III nitride semiconductor layer over the mask to form a second group III nitride semiconductor layer;
A fourth step of forming a light emitting structure having an n-type group III nitride semiconductor layer, a p-type group III nitride semiconductor layer, and an electrode on the second group III nitride semiconductor layer;
Have
In the second step,
When the emission wavelength of the light emitting structure is λ,
The period of the pattern is 0.85λ or more and 1.15λ or less,
The width in the direction in which the pattern has periodicity is 0.25λ or more and 0.60λ or less,
A method of manufacturing a nitride semiconductor light-emitting diode for forming the mask having a thickness of 0.15λ to 0.70λ, or 1.25λ to 1.80λ.

DESCRIPTION OF SYMBOLS 1 Dissimilar board | substrate 2 1st group III nitride semiconductor layer 3 Mask 3A Cover film 3-1 Mask side surface 3-2 Mask side surface 3-3 Mask side surface 4 2nd group III nitride semiconductor layer 5A Transferred layer 6 Substrate Part 10 Light emitting structure 11 First conductivity type nitride semiconductor layer 12 Active layer 13 Second conductivity type nitride semiconductor layer 14 Second electrode 15 First electrode 20 Transfer body 21 Film 22 Resin layer 30 Master mold 41 Recess 42 Portion 43 Opening 44 Covering portion 50 Reaction tube 51 Folder 53 Gas introduction tube 54 Gas introduction tube 55 Heater 56 Growth region 57 Source 58 Discharge port 59 Source boat 60 Structure 100 Nitride semiconductor light emitting diode 500 HVPE apparatus

Claims (7)

A heterogeneous substrate made of a different material from the group III nitride semiconductor;
A first group III nitride semiconductor layer located on the heterogeneous substrate;
A mask located on the first group III nitride semiconductor layer, made of oxide or nitride, and having a periodic pattern;
A second group III nitride semiconductor layer epitaxially grown on the first group III nitride semiconductor layer over the mask;
A light emitting structure located on the second group III nitride semiconductor layer and having an n-type group III nitride semiconductor layer, a p-type group III nitride semiconductor layer, and an electrode;
Have
When the emission wavelength of the light emitting structure is λ,
The period of the pattern of the mask is 0.85λ or more and 1.15λ or less,
The width of the mask in the direction in which the pattern has periodicity is 0.25λ to 0.60λ,
The nitride semiconductor light emitting diode, wherein the mask has a thickness of 0.15λ to 0.70λ, or 1.25λ to 1.80λ. The nitride semiconductor light-emitting diode according to claim 1,
A nitride semiconductor light emitting diode in which a side surface of the mask is not perpendicular to an interface between the heterogeneous substrate and the first group III nitride semiconductor layer. The nitride semiconductor light-emitting diode according to claim 2,
The nitride semiconductor light emitting diode, wherein the mask has a thickness of 1.25λ or more and 1.80λ or less. The nitride semiconductor light-emitting diode according to claim 1,
A side surface of the mask is perpendicular to an interface between the heterogeneous substrate and the first group III nitride semiconductor layer;
The nitride semiconductor light emitting diode, wherein the mask has a thickness of 0.15λ or more and 0.70λ or less. The nitride semiconductor light-emitting diode according to any one of claims 1 to 4,
The nitride semiconductor light emitting diode wherein the thickness of the first group III nitride semiconductor layer is 0.1 μm or more and 2 μm or less. The nitride semiconductor light emitting diode according to any one of claims 1 to 5,
The light emitting structure emits blue light,
The period of the pattern of the mask is 382.5 nm or more and 517.5 nm or less,
The width of the mask in the direction in which the pattern has periodicity is 112.5 nm or more and 270.0 nm or less,
The nitride semiconductor light emitting diode, wherein the mask has a thickness of 67.5 nm to 315.0 nm or 562.5 nm to 810.0 nm. A first step of forming a first group III nitride semiconductor layer on a heterogeneous substrate;
A second step of forming a mask formed of an oxide or nitride and having a periodic pattern formed on the first group III nitride semiconductor layer;
A third step of epitaxially growing a group III nitride semiconductor on the first group III nitride semiconductor layer over the mask to form a second group III nitride semiconductor layer;
A fourth step of forming a light emitting structure having an n-type group III nitride semiconductor layer, a p-type group III nitride semiconductor layer, and an electrode on the second group III nitride semiconductor layer;
Have
In the second step,
When the emission wavelength of the light emitting structure is λ,
The period of the pattern is 0.85λ or more and 1.15λ or less,
The width in the direction in which the pattern has periodicity is 0.25λ or more and 0.60λ or less,
A method of manufacturing a nitride semiconductor light-emitting diode for forming the mask having a thickness of 0.15λ to 0.70λ, or 1.25λ to 1.80λ.