JP2017028513A - Imaging apparatus, imaging system and signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase of circuit scale while reducing influences due to darkening phenomenon.SOLUTION: The imaging apparatus compares a threshold value and a digital signal value which is at least one of a digital reference signal and a digital image signal. As the comparison result, when the digital signal value is smaller than the threshold value, a differential value between the digital reference signal and the digital image signal is output; and when the digital signal value is larger than the threshold value, a correction value which has a value different from the differential value is output.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an imaging apparatus, an imaging system, and a signal processing method.

  When high-luminance light is incident on the photoelectric conversion unit of the imaging device, the charge generated by the photoelectric conversion unit may overflow to the floating diffusion (FD), and the value of the reference signal corresponding to the dark state may increase. For this reason, the value of the signal obtained from the difference between the image signal and the reference signal may be smaller than the value corresponding to the actual luminance. In such a case, a black sun phenomenon may occur in which an image in which a high-brightness portion is actually low-brightness is output.

  Patent Document 1 discloses a technique in which a comparison circuit that detects saturation of a photoelectric conversion unit based on the level of an analog signal read from a pixel is provided in each column circuit in order to suppress the above-described black sun phenomenon. Has been.

US Pat. No. 6,873,363

  In the technique described in Patent Document 1, a comparison circuit that detects saturation is provided in the column circuit of each column. Therefore, the circuit scale can be increased.

  The present invention has been made in view of the above-described problems, and an object thereof is to suppress an increase in circuit scale while reducing the influence of the black sun phenomenon.

  An imaging apparatus according to an aspect of the present invention includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, and each of the plurality of pixels generates an analog reference signal and an analog image signal; A plurality of column circuit units each provided corresponding to the columns of the pixel units, each of which converts the analog reference signal into a digital reference signal, and converts the analog image signal into a digital image signal. A reference signal output line to which the digital reference signal of each of the plurality of column circuit units is input; an image signal output line to which the digital image signal of each of the plurality of column circuit units is input; and the reference signal A digital signal value that is at least one of the digital reference signal input from the output line and the digital image signal input from the image signal output line, and a threshold value When the comparison result of the threshold comparison unit that performs comparison and the threshold comparison unit indicates that the digital signal value is smaller than the threshold, the difference value between the digital reference signal and the digital image signal is calculated. A difference processing unit that outputs a correction value having a value different from the difference value when the comparison result of the threshold value comparison unit indicates that the digital signal value is larger than the threshold value. It is characterized by having.

  Provided is an imaging apparatus that suppresses an increase in circuit scale while reducing the influence of a black sun phenomenon.

It is a figure which shows the structure of the imaging device which concerns on 1st Embodiment. It is a figure which shows the structure of the pixel which concerns on 1st Embodiment, a read-out part, and DSP. It is a figure which shows the timing of AD conversion of the imaging device which concerns on 1st Embodiment. It is a figure which shows the structure of the pixel which concerns on 2nd Embodiment, a read-out part, and DSP. It is a figure which shows the timing of AD conversion of the imaging device which concerns on 3rd Embodiment. (A) is a figure which shows the structure of DSP which concerns on 4th Embodiment, (b) is a figure which shows the structure of DSP which concerns on 5th Embodiment. It is a figure which shows the structure of the amplification part which concerns on 6th Embodiment. It is a figure which shows the circuit structure of the pixel and comparator which concern on 7th Embodiment. It is a figure which shows the structure of the imaging system which concerns on 8th Embodiment.

  Embodiments of the present invention will be described with reference to the drawings. In the drawings of each embodiment, elements having similar functions are denoted by the same reference numerals, and redundant description may be omitted.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration of an imaging apparatus 100 according to the first embodiment. The imaging apparatus 100 includes a pixel unit 10, a vertical scanning circuit 20, a reading unit 30, a reference signal generation circuit 40, a counter 50, a horizontal scanning circuit 60, a digital signal processor (DSP) 70, and a timing generation circuit (TG) 80. The reading unit 30 includes a comparison unit 34 and a memory unit 36. The comparison unit 34 includes a comparator 34 a provided corresponding to each column of the pixel unit 10.

  The pixel unit 10 includes a plurality of pixels 10a arranged in a matrix of m rows and n columns over a plurality of rows (m rows) and a plurality of columns (n columns). The vertical scanning circuit 20 supplies a control signal for each row to the pixel 10a via row control signal lines (X1,... Xm) provided corresponding to each row of the pixel unit 10. By these control signals, the pixels 10a in each row of the pixel unit 10 are sequentially selected, and a pixel signal Vpix that is an analog signal is output from each pixel 10a. The pixel signal Vpix includes two types of signals: a reference signal Vn (analog reference signal) and an image signal Vs (analog image signal). The reference signal Vn is a signal indicating a reference level when the pixel 10a is reset, and the image signal Vs is a signal obtained by superimposing the reference signal Vn on a signal corresponding to light incident on the pixel 10a.

  The pixel signal Vpix output from the pixel 10 a is transmitted to the reading unit 30 via vertical signal lines (Y 1,... Yn) provided corresponding to each column of the pixel unit 10.

  The reading unit 30 includes a comparison unit 34 and a memory unit 36. The comparison unit 34 includes a comparator 34 a provided corresponding to each column of the pixel unit 10. The memory unit 36 includes a memory 36 </ b> S and a memory 36 </ b> N provided corresponding to each column of the pixel unit 10. The reading unit 30 mainly has a function of performing analog-digital conversion (AD conversion) on the pixel signal Vpix output from the pixel unit 10. The reading unit 30 has a plurality of column circuit units. Each of the plurality of column circuit units includes one comparator 34a, one memory 36S, and one memory 36N. One column circuit portion is provided corresponding to one column of the pixels 10a.

  The reference signal generation circuit 40 outputs a reference signal to each comparator 34 a provided in the comparison unit 34. The reference signal is a ramp signal whose potential changes linearly with respect to time, for example. In the following description, the reference signal is the ramp signal Vramp. The counter 50 outputs a counter signal Φcot to each of the memories 36N and 36S provided in the memory unit 36.

  The comparison unit 34 compares the pixel signal Vpix output from the pixel 10a in each column with the ramp signal Vramp. At this time, the processing in the comparison unit 34 of each column is performed in parallel. A counter value indicating the time until the comparison result is inverted is temporarily held in each of the memories 36N and 36S in the memory unit 36 as digital data (for example, 12-bit binary digital data). In this way, AD conversion is performed for each column. Each memory 36N holds a reference signal Vn (digital reference signal) after AD conversion, and each memory 36S holds an image signal Vs (digital image signal) after AD conversion.

  The horizontal scanning circuit 60 outputs control signals (H1,... Hn) to the memories 36N and 36S. Each of the memories 36N and 36S sequentially outputs the digital data held therein to the reference signal output line 38N and the image signal output line 38S in accordance with the control signal (H1,... Hn). That is, the digital data held in the memory 36N of each column is input in common to the reference signal output line 38N, and the digital data held in the memory 36S of each column is input in common to the image signal output line 38S. The reference signal output line 38N and the image signal output line 38S are connected to the DSP 70.

  The DSP 70 performs signal processing such as saturation detection of the pixel 10a and noise reduction based on the digital data input via the reference signal output line 38N and the image signal output line 38S, and outputs the image data to the outside of the imaging apparatus 100. It is a signal processing device.

  The TG 80 outputs control signals to the vertical scanning circuit 20, the reference signal generation circuit 40, the counter 50, the horizontal scanning circuit 60, and the DSP 70 based on a predetermined processing flow to control them. The TG 80 performs these operations based on external control. For example, the TG 80 is controlled by a system control unit of an imaging system in which the imaging apparatus 100 is mounted.

  FIG. 2 is a diagram illustrating a configuration of the pixel 10a, the readout unit 30, and the DSP 70 according to the first embodiment. The pixel 10a shown in the figure is assumed to be a pixel arranged in the i-th column, and the circuit shown in the reading unit 30 is shown by extracting only a portion corresponding to the pixel 10a in the i-th column.

  The pixel 10 a includes a photodiode PD, a transfer transistor 11, a reset transistor 12, an amplification transistor 13, and a selection transistor 14. Control signals ΦTx, ΦRes, and ΦSel are input from the vertical scanning circuit 20 to the gates of the transfer transistor 11, the reset transistor 12, and the selection transistor 14, respectively. These transistors are N-type MOS transistors, but may be other transistors. For example, each transistor may be P-type.

  The photodiode PD is a photoelectric conversion unit that generates a charge corresponding to incident light. The cathode of the photodiode PD is connected to the source of the transfer transistor 11. The drain of the transfer transistor 11 and the source of the reset transistor 12 are connected to a floating diffusion (FD) that is the gate of the amplification transistor. The power supply voltage Vd is input to the drain of the reset transistor 12 and the drain of the amplification transistor 13. The source of the amplification transistor 13 is connected to the drain of the selection transistor 14, and the source of the selection transistor 14 is connected to the vertical signal line Yi.

  When the control signal ΦTx input to the gate of the transfer transistor 11 becomes High, the photocharge generated in the photodiode PD is transferred to the FD, and charge-voltage conversion is performed by the parasitic capacitance generated in the FD. When the control signal ΦRes input to the gate of the reset transistor 12 becomes High, the residual charge held in the FD is removed and reset. The amplification transistor 13, the selection transistor 14, and the current source IR constitute a source follower circuit.

  The selection transistor 14 controls the operation of the source follower circuit by controlling the connection between the source of the amplification transistor 13 and the current source IR by the control signal ΦSel. The pixel signal Vpix is output from the pixel 10a to the vertical signal line Yi by the operation of the source follower circuit.

  As described above, the pixel signal Vpix includes two types of signals: the reference signal Vn and the image signal Vs. The reference signal Vn is a signal output to the vertical signal line Yi when the reset transistor 12 is turned on to reset the FD. The image signal Vs is a signal output to the vertical signal line Yi when the transfer transistor 11 is turned on and the photoelectric charge accumulated in the photodiode PD is transferred to the FD. That is, the image signal Vs is a signal in which the reference signal Vn is superimposed on a signal corresponding to incident light.

  The comparator 34a has a first input terminal and a second input terminal to which two voltages to be compared are input, and an output terminal for outputting a comparison result. The reset switch SW0 and the clamp capacitors Ci1 and Ci2 are connected to the comparator 34a. The pixel signal Vpix is input to the first input terminal of the comparator 34a via the clamp capacitor Ci1. The ramp signal Vramp output from the reference signal generation circuit 40 is input to the second input terminal of the comparator 34a via the clamp capacitor Ci2.

  One ends of the two reset switches SW0 are connected to the first input terminal and second input terminal signals of the comparator 34a, respectively. The reset switch SW0 is controlled by a control signal ΦAz. When the control signal ΦAz becomes High, the voltage clamped in the clamp capacitors Ci1 and Ci2 is reset.

  The comparator 34a outputs the latch signal ΦLt when the magnitude relationship between the signal levels of the pixel signal Vpix and the ramp signal Vramp is inverted. A counter signal Φcot corresponding to 12 bits is supplied from the counter 50 to the memories 36S and 36N. The memories 36S and 36N hold the counter value of the counter signal Φcot at the time when the latch signal ΦLt is input as a digital signal. .

  The memory 36N outputs a digital signal DN (digital reference signal) corresponding to the reference signal Vn to the reference signal output line 38N. The memory 36S outputs a digital signal DS (digital image signal) corresponding to the image signal Vs to the image signal output line 38S. Digital signals DN and DS are input to the DSP 70.

  The DSP 70 includes a difference processing unit 72, a signal processing unit 74, a determination data output unit 76, and a determination unit 78.

  The difference processing unit 72 performs difference processing for subtracting the digital signal DN from the digital signal DS, thereby removing the influence of the voltage of the reference signal of the pixel 10a, the offset voltage of the comparator 34a, and the like, and corresponding to the digital charge. The signal DS2 is output.

  The signal processing unit 74 adds the black offset signal as a dark signal shading countermeasure to the digital signal DS2, performs data level shift as the digital gain processing of the effective signal, adjusts the number of data bits, and acquires the digital signal DS3. Output to the outside.

  The determination unit 78 determines whether or not the signal level of the digital signal DS is saturated. The saturation of the signal level of the digital signal DS can be caused by charge saturation in the photodiode PD. Further, the saturation of the signal level of the digital signal DS may also occur when the image signal Vs exceeds the convertible range of AD conversion and the AD conversion processing is saturated.

  The determination data output unit 76 includes a storage unit such as a register that stores a predetermined determination value used for determination by the determination unit 78. The predetermined determination value is a threshold value to be compared with a digital signal value of at least one of the digital reference signal and the digital image signal. In the determination data output unit 76, the determination data DS_H (digital image signal determination) falls within a value smaller than a value corresponding to an output value when the charge is saturated in the photodiode PD in advance, that is, within a range where the charge is not saturated in the photodiode PD. Value). The determination data DS_H is set within a range in which the AD conversion processing of the image signal Vs is not saturated so that the signal level saturation of the digital signal DS can be detected correctly.

  The determination unit 78 compares the digital signal DS with the determination data DS_H. As a result of the comparison, when the signal level of the digital signal DS is equal to or higher than the determination data DS_H, the determination unit 78 outputs a determination signal ΦCT indicating the determination result as High. When the signal level of the digital signal DS is less than the determination data DS_H, the determination unit 78 outputs a determination signal ΦCT indicating the determination result as Low. The determination unit 78 is a threshold value comparison unit that compares at least one digital signal value of the digital reference signal and the digital image signal with a predetermined determination value that is a threshold value.

  The difference processing unit 72 outputs one of the two types of signals as the digital signal DS2 based on the level of the determination signal ΦCT. Specifically, when the determination signal ΦCT is Low, a difference value obtained by subtracting the digital signal DN from the digital signal DS as described above is output as the digital signal DS2. Thereby, the influence of the voltage of the reference signal Vn of the pixel 10a, the offset voltage of the comparator 34a, etc. is removed, and the digital signal DS2 corresponding to the photocharge is obtained. In contrast, when the determination signal ΦCT is High, the difference processing unit 72 outputs a digital signal having a correction value corresponding to a white level different from the difference value obtained by subtracting the digital signal DN from the digital signal DS as the digital signal DS2. To do. The digital signal corresponding to the white level can be, for example, the maximum value that can be taken by the digital signal.

  When the charge is saturated in the photodiode PD, a false signal generated by the charge overflowed from the photodiode PD is superimposed on the digital signal DN. In such a case, the digital signal DS2 can be at a signal level lower than the white level by the difference processing between the digital signal DS and the digital signal DN. At this time, in the photographed image, there may occur a black sun phenomenon in which the luminance of a portion that should originally be white decreases. In the present embodiment, it is possible to reduce the influence of the black sun phenomenon by detecting that the charge in the photodiode PD is saturated and setting the output signal to a signal level corresponding to the white level.

  The signal corresponding to the white level output as the digital signal DS2 may be a high-resolution 12-bit signal or a low-resolution 6-bit signal.

  Similarly, since the determination data DS_H is data for determining saturation, the determination data DS_H may have low resolution, for example, 6 bits. However, the present invention is not limited to this, and may be 12 bits, for example.

  The determination unit 78, the determination data output unit 76, and the like according to the first embodiment are circuits that are provided in common for each column of the reading unit 30. Therefore, the circuit scale can be reduced in the first embodiment as compared with the case where the determination unit 78, the determination data output unit 76, and the like are provided for each column. Therefore, according to the first embodiment, it is possible to suppress an increase in circuit scale while reducing the influence of the black sun phenomenon. In addition, according to the configuration of the first embodiment, since the circuit scale is small, power consumption can be reduced.

  As described above, the determination signal ΦCT indicating the determination result is a signal supplied to the difference processing unit 72. However, the determination signal ΦCT can be output to the outside as a flag signal. In the signal processing unit outside the imaging apparatus 100, for example, the data corresponding to the case where the determination signal ΦCT is High is not used for the interpolation processing between the image data, thereby optimizing the interpolation signal level. Is possible.

  FIG. 3 is a diagram illustrating AD conversion timing of the pixel signal Vpix in the imaging apparatus 100 according to the first embodiment. In FIG. 3, the horizontal direction indicates time, and the vertical direction indicates a schematic waveform of the potential of each signal.

  The waveforms of the ramp signal Vramp and the pixel signal Vpix in FIG. 3 indicate changes in potential that are input to the two input terminals of the comparator 34a and compared by the comparator 34a.

  Also, FIG. 3 shows signals in normal light that are incident light amounts in a range where the photodiode PD of the pixel 10a is not saturated and signals in excessive light that is incident light amount that the photodiode PD of the pixel 10a is saturated. It is shown. In the figure, “Vn” and “Vs” indicate reference signals and image signals during normal light, and “Vn ′” and “Vs ′” indicate reference signals and image signals during excessive light. .

  A period from time t31 to t33 is a period during which AD conversion of the reference signal Vn is performed (N-AD conversion period), and a period from time t51 to t53 is a period during which AD conversion of the image signal Vs is performed (S-AD conversion). Period). In the N-AD period, the comparator 34a performs a comparison process between the reference signal Vn (or Vn ′) and the ramp signal Vramp_N. In the S-AD period, the comparator 34a performs a comparison process between the image signal Vs (or Vs') and the ramp signal Vramp_S. In each AD conversion period, the counter 50 supplies the counter signal Φcot to the memories 36S and 36N. When the magnitude relationship between the potentials of the pixel signal Vpix and the ramp signal Vramp is inverted, the comparator 34a generates the latch signal ΦLt based on the comparison result. In response to this, the counter value at that time is held in the memories 36S and 36N.

  First, AD conversion during normal light and processing operation in the DSP 70 will be described.

  At time t1, the control signal ΦSel becomes High, and the pixel source follower circuit is operated. At time t1, the control signals ΦRes and ΦAz become High, and the FD and the comparator 34a are reset to the initial state.

  At time t2, the control signal ΦRes becomes Low, and the reference signal Vn is output to the vertical signal line Yi.

  At time t3, the control signal ΦAz becomes Low, and the potential of the input side terminal of the clamp capacitor Ci1 becomes the level of the reference signal Vn. Thereby, the output side terminal of the capacitor Ci1, that is, the input potential of the comparator 34a is clamped to Vn. Further, the potential of the input side terminal of the capacitor Ci2 is clamped to the reference potential of the ramp signal Vramp, and the output side of the capacitor Ci2 is clamped to the same potential as Vn.

  At time t31, N-AD conversion is started, and the potential of the ramp signal Vramp_N starts to decrease. At time t32, the potential of the ramp signal Vramp_N falls below the potential of the reference signal Vn. At this time, a pulse of the latch signal ΦLt is generated, and the count value N1 is held in the memory 36N.

  At time t4, the control signal ΦTx becomes High, and the photocharge accumulated in the photodiode PD is transferred. At time t5, the control signal ΦTx becomes Low, and the input potential of the comparator 34a becomes the potential of the image signal Vs. Become.

  At time t51, S-AD conversion is started, and the potential of the ramp signal Vramp_S starts to decrease. At time t52, the potential of the ramp signal Vramp_S falls below the potential of the image signal Vs. Thereby, a pulse of the latch signal ΦLt is generated, and the count value S1 is held in the memory 36S.

  The count values N1 and S1 are transmitted to the difference processing unit 72 as digital signals DN and DS, respectively. The level of the digital signal DS is compared with the determination data DS_H by the determination unit 78. However, since the digital signal DS is smaller than the determination data DS_H, the determination signal ΦCT remains Low. Therefore, the difference processing unit 72 outputs a digital signal DS2 having a difference between DS and DN.

  Next, A / D conversion at excessive light and processing operations in the DSP 70 will be described. The description of the same operation as in normal light may be simplified or omitted.

  At time t3, the control signal ΦAz becomes Low, and the potential of the input side terminal of the clamp capacitor Ci1 becomes the level of the reference signal Vn ′. As a result, the output side terminal of the capacitor Ci1, that is, the input potential of the comparator 34a is clamped to Vn '. However, after time t3, the charge saturated in the photodiode PD overflows to the FD, and the level of the reference signal Vn ′ gradually decreases with time. At this time, the potential of the input side terminal of the capacitor Ci2 is clamped to the reference potential of the ramp signal Vramp, and the output side of the capacitor Ci2 is clamped to the same potential as Vn ′.

  Unlike the normal light described above, since the potential of the reference signal Vn ′ decreases with time, the comparison process between the reference signal Vn ′ and the ramp signal Vramp_N may not end within the N-AD period. At this time, the memory 36N holds a value indicating that AD conversion has not been completed within the N-AD period. Specifically, at time t34, the count value N2 is held in the memory 36N by surplus bits for overflow or carry. As another example, predetermined data may be stored in the memory 36N before AD conversion and held.

  At time t4, the control signal ΦTx becomes High, and the pixel signal Vpix changes to the image signal Vs ′ by superimposing a signal based on the photocharge on the reference signal Vn ′. Similar to the N-AD period, the comparison process between the image signal Vs ′ and the ramp signal Vramp_S may not be completed within the S-AD period. Accordingly, at time t54, the memory 36S holds the count value S2 by the surplus bit for overflow or carry. As another example, data corresponding to the determination data DS_H may be stored in the memory 36S before AD conversion and held.

  The count values N2 and S2 are transmitted to the difference processing unit 72 as digital signals DN and DS, respectively. The digital signal DS is compared with the determination data DS_H by the determination unit 78. Since the digital signal DS is larger than the determination data DS_H, the determination signal ΦCT changes from Low to High. In response to the change of the determination signal ΦCT to High, the difference processing unit 72 outputs a signal corresponding to the white level as the digital signal DS2, not the difference between the digital signal DS and the digital signal DN.

  As described above, by performing the saturation determination of the photodiode PD based on the signal level of the digital signal DS, the digital signal DS2 can be set to the white level regardless of the value of the digital signal DN. Can be reduced. In the present embodiment, one column circuit unit is provided for one column of pixels 10a. As another example, one column circuit unit may be provided for a plurality of columns of pixels 10a. In addition, a plurality of column circuit units may be provided for one column of pixels 10a. Such an example is also included in a form in which each of the plurality of column circuit units is arranged corresponding to the column in which the pixels 10a are arranged. In the present embodiment, the ramp signal Vramp has an example in which the potential changes in a slope shape. The present invention is not limited to this example. For example, a signal whose potential changes stepwise is also included in the category of the ramp signal.

(Second Embodiment)
In the first embodiment, the saturation of the photodiode PD is determined by comparing the digital signal DS and the determination data DS_H. On the other hand, in the second embodiment, the configuration of the DSP 70 is changed, and the saturation of the photodiode PD is performed by comparing the digital signal DN with the determination data DN_H (digital reference signal determination value) for the digital signal DN. Is determined. Since the other configuration is the same as that of the first embodiment, the description is simplified or omitted.

  FIG. 4 is a diagram illustrating the configuration of the pixel 10a, the readout unit 30, and the DSP 70 according to the second embodiment.

  In the determination data output unit 76, the determination data DN_H is set in advance to a value smaller than a value corresponding to the output value when the charge is saturated in the photodiode PD, that is, within a range where the charge is not saturated in the photodiode PD. . The determination data DN_H is set within a range in which the AD conversion processing of the reference signal Vn is not saturated so that the saturation of the signal level of the digital signal DN can be detected correctly.

  The determination unit 78 compares the digital signal DN with the determination data DN_H. As a result of the comparison, when the signal level of the digital signal DN is equal to or higher than the determination data DN_H, the determination unit 78 outputs a determination signal ΦCT indicating the determination result as High. When the signal level of the digital signal DN is less than the determination data DN_H, the determination unit 78 outputs a determination signal ΦCT indicating the determination result as Low. When the determination signal ΦCT is High, the difference processing unit 72 outputs a digital signal corresponding to a white level different from the difference obtained by subtracting the digital signal DN from the digital signal DS.

  Also in the second embodiment, similarly to the first embodiment, it is possible to suppress an increase in circuit scale while reducing the influence of the black sun phenomenon. Further, since the circuit scale is small, power consumption can be reduced.

  Note that both the digital signals DS and DN are determined by combining the configuration for comparing the digital signal DS and the determination data DS_H of the first embodiment with the configuration for comparing the digital signal DN and the determination data DN_H of the second embodiment. It may be configured as possible.

(Third embodiment)
FIG. 5 is a diagram illustrating AD conversion timing of the imaging apparatus according to the third embodiment. In the third embodiment, a function of making the amplitude of the ramp signal Vramp output from the reference signal generation circuit variable is added to the configuration of the first embodiment or the second embodiment. By making the amplitude of the ramp signal Vramp signal variable, the resolution of AD conversion can be made variable. That is, the gain of the pixel signal at the time of AD conversion can be changed. In the third embodiment, description will be made assuming that the gain is variable to two values of 1 or 2. Since other configurations are the same as those of the first embodiment or the second embodiment, description thereof is omitted or simplified. In the third embodiment, the determination may be made by the digital signal DS as in the first embodiment, the determination may be made by the digital signal DN as in the second embodiment, or both may be performed. Good.

  The change in signal level with respect to the time of the ramp signal Vramp differs by two times when the gain is 1 time and when the gain is 2 times. The N-AD ramp signal Vramp_N1 and the S-AD ramp signal Vramp_S1 shown in FIG. 5 correspond to a gain of one. The ramp signal Vramp_N2 for N-AD and the ramp signal Vramp_S2 for S-AD correspond to a double gain.

  First, determination data used when determining the saturation (or the maximum value of AD conversion) of the photodiode PD from the digital signal DS will be described. When the gain is 1, the determination data DS_H1 having a value smaller than the digital value corresponding to the maximum value of the ramp signal Vramp_S1 is used. When the gain is twice, determination data DS_H2 having a value smaller than the digital value corresponding to the maximum value of the ramp signal Vramp_S2 is used. In this way, determination data serving as a determination reference can be determined according to the resolution of AD conversion.

  When the gain is double, even if the photodiode PD is saturated, the signal level after AD conversion is hardly saturated. However, the maximum value of AD conversion greater than the determination data DS_H2 corresponds to the white level. Therefore, when the value obtained by AD converting the image signal Vs ′ with the double gain is equal to or greater than the determination data DS_H2, the difference processing unit 72 is not a difference between the digital signal DS and the digital signal DN but a signal corresponding to the white level. Is output as a digital signal DS2.

  Next, determination data for determining saturation of the photodiode PD (or AD conversion maximum value) from the digital signal DN will be described. The comparator 34a generates an offset voltage between two input terminals after the initial setting. Therefore, it is necessary to acquire and remove the offset voltage. A period during which AD conversion of the reference signal Vn including the offset voltage is performed is an N-AD period. The amplitude of the ramp signal Vramp_N2 is set to a voltage larger than the range of the offset voltage variation ΔVoff between the columns. In addition, it is necessary to consider the level of the false signal that is generated when the charge overflowed by the saturation of the photodiode PD is superimposed on the reference signal. The determination signal DN_H1 is the maximum value of the ramp signal Vramp_N2 when the gain determined in consideration of these is twice. This determination data DN_H1 is used both when the gain is 1 and when the gain is 2 times. As described above, the determination data serving as a reference for determining the digital signal DN can be determined in consideration of the offset voltage variation between the columns and the level of the false signal, and is the same even when the resolution of AD conversion is changed. Sometimes.

  The reason why the determination data DN_H1 should be used even when the gain is 1 will be described. Let us consider a case where the determination data DN_H corresponding to the maximum value of AD conversion is set when the gain is one. The reference signal Vn ′ is superimposed with the charge overflowed by the saturation of the photodiode PD. Here, in AD conversion in which the gain for comparing the ramp signal Vramp_N and the reference signal Vn ′ is 1, the output of the comparator 34a is inverted within the N-AD period, and the count value N at that time is held in the memory 36N. Is done. The determination unit 78 compares the digital signal DN corresponding to the count value N with the determination data DN_H. As a result, since the value of the digital signal DN is smaller than the value of the determination data DN_H, the determination signal ΦCT remains Low. Therefore, the difference processing unit 72 outputs the difference between the digital signal DS and the digital signal DN even though the photodiode PD is saturated. As a result, the signal level of the digital signal DS2 is reduced by the level of the false signal, and a black sun phenomenon may occur in the image. The determination data DN_H1 is set in consideration of the influence of a false signal due to saturation of the photodiode PD. Therefore, if the determination data DN_H1 is used even when the gain is 1 as in the third embodiment, the influence of the black sun phenomenon due to such factors can be reduced.

  As described above, according to the third embodiment, in addition to obtaining the same effects as those of the first and second embodiments, a function of changing the gain at the time of AD conversion is added.

(Fourth embodiment)
FIG. 6A is a diagram illustrating a configuration of a DSP 70 according to the fourth embodiment. The difference processing unit 72 included in the DSP 70 illustrated in FIG. 6A includes a difference circuit 72A, a white data output unit 72B, and a switch SW1. Since the other configuration is the same as that of the first embodiment described above, the description thereof is omitted or simplified.

  The difference circuit 72A outputs the difference between the digital signal DS and the digital signal DN. The white data output unit 72B outputs a digital signal corresponding to the white level as white data. The switch SW1 connects the signal processing unit 74 to the difference circuit 72A or the white data output unit 72B based on the determination signal ΦCT from the determination unit 78. When the determination signal ΦCT from the determination unit 78 is High, the output signal of the white data output unit 72B is input to the signal processing unit 74, and when the determination signal ΦCT from the determination unit 78 is Low, the output signal of the difference circuit 72A is The signal is input to the signal processing unit 74.

  In the fourth embodiment, the same effect as in the first embodiment can be obtained. In addition to this, in the fourth embodiment, white data can be set to an arbitrary value, and there is an effect that the degree of freedom of operation is improved.

(Fifth embodiment)
FIG. 6B is a diagram showing the configuration of the DSP 70 according to the fifth embodiment. The difference processing unit 72 included in the DSP 70 illustrated in FIG. 6B includes a difference circuit 72A and a switch SW1. Since the other configuration is the same as that of the first embodiment described above, the description thereof is omitted or simplified.

  The switch SW1 switches whether to input the digital signal DN to the difference circuit 72A based on the determination signal ΦCT from the determination unit 78. The difference circuit 72A outputs the difference between the digital signal DS and the digital signal DN. When the determination signal ΦCT from the determination unit 78 is High, the switch SW1 is not connected, and the digital signal DN is not input to the difference circuit 72A. That is, the difference circuit 72A outputs a signal corresponding to the input digital signal DS as the digital signal DS2. When the determination signal ΦCT from the determination unit 78 is Low, the switch SW1 is in a connected state, and the difference circuit 72A outputs a digital signal DS2 that is a difference between the digital signal DS and the digital signal DN.

  In the fifth embodiment, the same effect as in the first embodiment can be obtained. Further, since the circuit for generating white data can be omitted, the circuit scale can be further reduced.

  As a modified embodiment of FIG. 6B, the switch SW1 may be replaced with a circuit that replaces the digital signal DS with black level data when the determination signal ΦCT is High. Also in this modified embodiment, the same effect as the first embodiment can be obtained. Furthermore, since the switch SW1 can be omitted in this modified embodiment, the circuit scale can be further reduced.

(Sixth embodiment)
FIG. 7 is a diagram illustrating a circuit configuration of the amplifying unit 32 according to the sixth embodiment. In the present embodiment, an amplifying unit 32 is added between the pixel unit 10 of the first embodiment and the comparator 34a. In FIG. 7, only the circuit in the i-th column is extracted and shown.

  The amplifying unit 32 includes an amplifier 32a, an input capacitor Co, a variable capacitor Cf, and a switch SWC. The input capacitor Co is connected between the vertical signal line Yi and the inverting input terminal of the amplifier 32a. The variable capacitor Cf is connected between the inverting input terminal of the amplifier 32a and the output terminal of the amplifier 32a. The switch SWC is also connected between the inverting input terminal of the amplifier 32a and the output terminal of the amplifier 32a, and is in a parallel connection relationship with the variable capacitor Cf. The voltage Vref is input to the non-inverting input terminal of the amplifier 32a.

  The amplifying unit 32 can change the gain (Co / Cf) by changing the capacitance value of the variable capacitor Cf. As a result, the imaging apparatus 100 can switch the photographing sensitivity.

  The operation of the amplifying unit 32 will be described. When the pixel 10a is reset, the switch SWC is controlled to be in a connected state. Thereby, the amplification unit 32 is reset. Thereafter, the switch SWC is disconnected and an image signal is input.

  In the sixth embodiment, the same effect as in the first embodiment can be obtained. In the sixth embodiment, by providing the amplifying unit 32, it is possible to amplify the image signal while suppressing a decrease in the SN ratio of the image signal at the time of photographing under low illuminance.

  Note that the amplification unit 32 of the sixth embodiment and the gain setting based on the amplitude of the ramp signal amplitude of the third embodiment may be combined.

(Seventh embodiment)
FIG. 8 is a diagram illustrating a circuit configuration of the pixel 10a and the comparator 34a according to the seventh embodiment of the present invention. In the seventh embodiment, a part of the circuit of the pixel 10a and the comparator 34a included in the readout unit 30 share a part of elements to constitute a differential circuit. The comparator 34a of the seventh embodiment includes transistors 15 and 16, a capacitor Cp, and a switch SW3. In the seventh embodiment, the transistor 15 is assumed to be N-type and the transistor 16 is assumed to be P-type. However, the present invention is not limited to this. Since the configuration of the pixel 10a is the same as that of the first embodiment, the description thereof is omitted or simplified.

  The ramp signal Vramp is applied to the gate of the transistor 15 via the capacitor Cp. The source of the transistor 15 is connected to the vertical signal line Yi. That is, the source of the transistor 15 and the source of the selection transistor 14 are shared by the vertical signal line Yi and connected to the current source IR. The drain of the transistor 15 is connected to the drain of the transistor 16. A switch SW3 is connected between the gate and drain of the transistor 15. The switch SW3 is controlled by a control signal ΦAz.

  The transistor 16 is a load transistor of the transistor 15. A bias voltage Vb is connected to the gate of the transistor 16. A power supply voltage Vd is input to the source of the transistor 16.

  A voltage indicating the comparison result between the potential of FD and the ramp signal Vramp is generated at the drain node of the transistor 15. That is, the drain node of the transistor 15 serves as an output terminal of a differential circuit constituted by the pixel 10a and the comparator 34a. The output voltage Vo of the differential circuit is input to a subsequent circuit (not shown), and a latch signal ΦLt is generated. Subsequent circuits can be configured in the same manner as in the first embodiment.

  Even when the circuits of the pixel 10a and the comparator 34a share a part to form a differential circuit as in the seventh embodiment, the same effect as in the first embodiment can be obtained. In the present embodiment, in addition to this, since the configuration of the comparator 34a is simplified, AD conversion processing can be performed at high speed.

(Eighth embodiment)
FIG. 9 is a diagram illustrating a configuration of an imaging system 200 according to the eighth embodiment. The imaging system 200 includes, for example, an optical unit 210, an imaging device 100, a video signal processing unit 230, a recording / communication unit 240, a system control unit 260, and a playback / display unit 270. In addition, this structure is an example, The part which has another function may be added, and one part may be abbreviate | omitted. As the imaging apparatus 100 provided in the imaging system 200 of the eighth embodiment, the imaging apparatus 100 of any of the first to seventh embodiments can be used.

  An optical unit 210 that is an optical system such as a lens forms an image of a subject by forming light from the subject on the pixel unit 10 in which a plurality of pixels 10a are arranged in a matrix in the imaging apparatus 100.

  The imaging device 100 outputs a signal corresponding to the light imaged on the pixel unit 10 at a timing based on the signal from the TG 80. A signal output from the imaging apparatus 100 is input to the video signal processing unit 230. The video signal processing unit 230 performs signal processing according to a method determined by a program or the like. The DSP 70 described in the first to seventh embodiments may be provided in the video signal processing unit 230 instead of the imaging device 100, and separate signal processing is performed between the imaging device 100 and the video signal processing unit 230. It may be provided as a device. The signal obtained by the processing in the video signal processing unit 230 is sent to the recording / communication unit 240 as image data. The recording / communication unit 240 sends a signal for forming an image to the reproduction / display unit 270 to cause the reproduction / display unit 270 to reproduce / display a moving image / still image. The recording / communication unit 240 receives a signal from the video signal processing unit 230 and communicates with the system control unit 260, and also performs an operation of recording a signal for forming an image on a recording medium (not shown). Do.

  The system control unit 260 comprehensively controls the operation of the imaging system, and controls driving of the optical unit 210, the TG 80, the recording / communication unit 240, and the reproduction / display unit 270. In addition, the system control unit 260 includes a storage device (not shown) that is a recording medium, for example, and a program necessary for controlling the operation of the imaging system is recorded therein. Further, the system control unit 260 supplies, for example, a signal for switching the driving mode in accordance with a user operation into the imaging system 200.

(Other embodiments)
The embodiment to which the present invention is applied is merely an example of some aspects to which the present invention can be applied, and does not prevent appropriate modifications and variations from being made without departing from the spirit of the present invention.

  For example, a part or all of the configurations shown in the above embodiments may be arbitrarily selected and combined.

  The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a recording medium, and one or more processors in the computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

10 pixel unit 10a pixel 30 readout unit (column circuit unit)
38N Reference signal output line 38S Image signal output line 72 Difference processing unit 78 Determination unit (threshold value comparison unit)

Claims (16)

A pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the plurality of pixels generating an analog reference signal and an analog image signal;
A plurality of column circuit units each provided corresponding to the columns of the pixel units, each of which converts the analog reference signal into a digital reference signal, and converts the analog image signal into a digital image signal. ,
A reference signal output line to which the digital reference signal of each of the plurality of column circuit units is input;
An image signal output line to which the digital image signal of each of the plurality of column circuit units is input;
A threshold comparison unit that compares a digital signal value that is at least one of the digital reference signal input from the reference signal output line and the digital image signal input from the image signal output line with a threshold;
When the comparison result of the threshold comparison unit indicates that the digital signal value is smaller than the threshold, a difference value between the digital reference signal and the digital image signal is output, and the threshold comparison unit And a difference processing unit that outputs a correction value having a value different from the difference value when the result of the comparison indicates that the digital signal value is greater than the threshold value. .   The imaging apparatus according to claim 1, wherein the threshold value comparison unit compares the value of the digital image signal as the digital signal value and a predetermined digital image signal determination value as the threshold value as the comparison. .   The imaging apparatus according to claim 2, wherein the digital image signal determination value is set to a value within a range in which analog-digital conversion processing of the analog image signal is not saturated.   The imaging apparatus according to claim 2, wherein the digital image signal determination value is set to a value within a range in which charge is not saturated in a photoelectric conversion unit included in each of the plurality of pixels.   The imaging apparatus according to claim 1, wherein the threshold value comparison unit compares the value of the digital reference signal as the digital signal value and a predetermined digital reference signal determination value as the threshold value as the comparison. .   The imaging apparatus according to claim 5, wherein the digital reference signal determination value is set to a value within a range in which analog-to-digital conversion processing of the analog reference signal is not saturated.   The imaging apparatus according to claim 5, wherein the digital reference signal determination value is set to a value within a range where charge is not saturated in a photoelectric conversion unit included in each of the plurality of pixels.   The imaging apparatus according to claim 1, wherein resolution of analog-digital conversion performed in each of the plurality of column circuit units is variable.   The imaging apparatus according to claim 1, wherein the correction value corresponds to a white level.   The imaging apparatus according to claim 1, wherein the correction value corresponds to an input value of the digital image signal.   The imaging apparatus according to claim 1, wherein the correction value corresponds to a difference between the digital image signal and a black level.   The imaging device according to any one of claims 1 to 11, wherein the threshold value comparison unit outputs a signal indicating a determination result as a flag signal used for signal processing outside the imaging device. .   The imaging apparatus according to claim 1, further comprising an amplifying unit having a variable gain that amplifies the analog reference signal and the analog image signal for each column of the pixel units. . Each of the plurality of column circuit units constitutes a differential circuit with each of the pixels,
The imaging apparatus according to claim 1, wherein analog-digital conversion is performed by the differential circuit. The imaging device according to any one of claims 1 to 14,
An imaging system comprising: a video signal processing unit that processes a signal output from the imaging device. A pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the plurality of pixels generating an analog reference signal and an analog image signal;
A plurality of column circuit units each provided corresponding to the columns of the pixel units, each of which converts the analog reference signal into a digital reference signal, and converts the analog image signal into a digital image signal. ,
A reference signal output line to which the digital reference signal of each of the plurality of column circuit units is input;
An image signal output line to which the digital image signal of each of the plurality of column circuit units is input;
A signal processing method for the digital reference signal and the digital image signal output from an imaging device having:
A digital signal value that is at least one of the digital reference signal input from the reference signal output line and the digital image signal input from the image signal output line is compared with a threshold value,
When the comparison result indicates that the digital signal value is smaller than the threshold value, a difference value between the digital reference signal and the digital image signal is output, and the comparison result is the digital signal value. When the signal value is larger than the threshold value, a correction value having a value different from the difference value is output.

Images