JP2017079324A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltage and large current. There are multiple types of power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to the application. It has been.

  For example, a bipolar transistor or IGBT has a higher current density than a MOSFET and can increase the current, but cannot be switched at high speed. Specifically, the bipolar transistor is limited in use at a switching frequency of about several kHz, and the IGBT is limited in use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or IGBT and is difficult to increase in current, but can perform a high-speed switching operation up to several MHz.

  In the market, there is a strong demand for power semiconductor devices having both high current and high speed, and IGBTs and power MOSFETs have been focused on improving them, and are currently being developed to almost the material limit. For this reason, a semiconductor material that replaces silicon has been studied from the viewpoint of a power semiconductor device, and silicon carbide as a semiconductor material capable of producing (manufacturing) a next-generation power semiconductor device excellent in low on-voltage, high-speed characteristics, and high-temperature characteristics. (SiC) is attracting attention (for example, see Non-Patent Document 1 below).

  Silicon carbide is a chemically stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Silicon carbide is also expected as a semiconductor material that can sufficiently reduce the on-resistance because the maximum electric field strength is one digit or more larger than that of silicon. Such a feature of silicon carbide similarly applies to other semiconductors having a wider band gap than silicon (hereinafter referred to as a wide band gap semiconductor) such as gallium nitride (GaN). For this reason, by using a wide band gap semiconductor, it is possible to increase the breakdown voltage of the semiconductor device (see, for example, Non-Patent Document 2 below).

  In such a high breakdown voltage semiconductor device using silicon carbide, since the loss generated in the high breakdown voltage semiconductor device is reduced, for example, when used in an inverter, the carrier frequency is one digit higher than that of a conventional semiconductor device using silicon. Applied. When a high voltage semiconductor device is applied at a high carrier frequency, the heat generation temperature of a semiconductor chip constituting the high voltage semiconductor device is increased, which adversely affects device reliability. In particular, a bonding wire (bonder) is bonded to the front surface electrode provided on the front surface of the semiconductor chip by a bonding device (bonder). As a result, the reliability of the semiconductor device is adversely affected.

  As another wiring structure, a structure in which a flat wiring member serving as an external connection terminal for taking out the potential of the front surface electrode to the outside instead of the bonding wire is bonded to the front surface electrode has been proposed ( For example, see the following Patent Document 1 (paragraphs 0032 to 0034). In Patent Document 1 below, the heat dissipation efficiency is improved by making the heat capacity of the wiring member itself larger than the heat capacity of the bonding wire itself and increasing the contact area with the semiconductor chip.

  As another wiring structure, a pin-shaped wiring member (hereinafter referred to as a terminal pin) serving as an external connection terminal is joined to the front surface electrode in a state of being substantially perpendicular to the chip front surface. A structure has been proposed. A structure of a conventional semiconductor device having a wiring structure using terminal pins will be described by taking an n-channel MOSFET having a planar gate structure, which is a switching device manufactured using silicon carbide, as an example. FIG. 10 is a cross-sectional view showing the structure of a conventional semiconductor device. The conventional semiconductor device shown in FIG. 10 has a main surface (surface on the p-type silicon carbide layer 104 side) side of a semiconductor substrate (hereinafter referred to as a silicon carbide substrate (semiconductor chip)) 200 made of silicon carbide. The semiconductor element 210 has a general MOS gate (metal-oxide film-insulated gate made of semiconductor) structure.

The silicon carbide substrate 200 has an n ⁻ type semiconductor layer (hereinafter referred to as n ⁻ ) made of silicon carbide on the front surface of an n ⁺ type support substrate (hereinafter referred to as n ⁺ type silicon carbide substrate) 201 made of silicon carbide. Type silicon carbide layer) 202 and a p-type semiconductor layer (hereinafter referred to as p-type silicon carbide layer) 204 made of silicon carbide. A source electrode (source pad) 212 and a gate pad (not shown) are provided apart from each other on the front surface of the silicon carbide substrate 200. Source electrode 212 is in contact with n ⁺ -type source region 205 and p ⁺ -type contact region 206 and is electrically insulated from gate electrode 209 by interlayer insulating film 211. The gate pad is electrically connected to the gate electrode 209 at a portion not shown.

Different terminal pins 215 are joined to the source electrode 212 and the gate pad via a plating film 213 and a solder layer 214, respectively. Portions other than the plating film 213 on the surface of the source electrode 212 and the gate pad are covered with a first protective film 216. The second protective film 217 covers the boundary between the plating film 213 and the first protective film 216. Drain electrode 218 is in contact with the back surface of silicon carbide substrate 200 (the back surface of n ⁺ -type silicon carbide substrate 201). Reference numerals 203 and 204a denote p-type base regions. P type base region 204 a is a portion of p type silicon carbide layer 204 other than n ⁺ type source region 205 and p ⁺ type contact region 206. Reference numerals 207 and 208 denote an n-type JFET region and a gate insulating film, respectively.

In the MOSFET having the configuration shown in FIG. 10, when a positive voltage is applied to the drain electrode 218 with respect to the source electrode 212, and a voltage lower than the threshold voltage is applied to the gate electrode 209, the p-type base region Since the pn junction between 204a and the n-type JFET region 207 is reverse-biased, the reverse breakdown voltage of the active region is secured and no current flows. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 209, an n-type inversion layer (channel) is formed in the surface layer of the p-type base region 204a immediately below the gate electrode 209 (drain side). The Thereby, a current flows through the path of n ⁺ type silicon carbide substrate 201, n ⁻ type silicon carbide layer 202, n type JFET region 207, surface inversion layer of p type base region 204 a and n ⁺ type source region 205. As described above, the known MOSFET switching operation can be performed by controlling the gate voltage.

JP 2014-099444 A

K. Shenai, two others, Optim Semiconductors for High-Power Electronics, I Triple E Transactions on Electron Devices (IEEEs TransD) September, Vol. 36, No. 9, p. 1811-1823 By B. Jayant Baliga, Silicon Carbide Power Devices (USA), World Scientific Publishing Co. (World Science Publishing Co.), 30th March, 200 p. . 61

  However, in the conventional semiconductor device, the terminal pin 215 is bonded only to the source electrode (source pad) 212 and the gate pad of the main semiconductor element 210 via the plating film 213 and the solder layer 214. On the other hand, bonding wires are bonded to electrode pads of circuit portions (not shown) such as a protection circuit, a control circuit, and an arithmetic circuit arranged on the same semiconductor chip (silicon carbide substrate 200). For this reason, under high temperature conditions, there is a problem that the adhesion between the electrode pad of the circuit portion and the bonding wire is lowered, and the reliability of the semiconductor device is inferior.

  An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing a semiconductor device even under a high temperature condition in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A plurality of semiconductor elements are arranged on the same semiconductor substrate made of a semiconductor having a wider band gap than silicon. The plurality of electrode pads electrically connected to the plurality of semiconductor elements are arranged in a predetermined plane layout on the front surface of the semiconductor substrate. Terminal pins for taking out the potential of the electrode pads to the outside are solder-bonded to all the electrode pads via plating films, respectively.

  In the semiconductor device according to the present invention, in the above-described invention, the plurality of semiconductor elements include a first semiconductor element that performs a main operation, and one or more second semiconductor elements that protect or control the first semiconductor element. It is characterized by comprising.

  In the semiconductor device according to the present invention, the planar layout in which the electrode pad electrically connected to each of the plurality of second semiconductor elements is arranged in the central portion of the active region through which the main current flows is the above-described invention. It is characterized by having.

  In the semiconductor device according to the present invention, in the above-described invention, two or more second semiconductor elements are disposed, and the electrode pads electrically connected to each of the two or more second semiconductor elements are provided. It has a planar layout arranged in a line in a straight line.

  In the semiconductor device according to the present invention, in the above-described invention, two or more second semiconductor elements are disposed, and the electrode pads electrically connected to each of the two or more second semiconductor elements are provided. The semiconductor device has a planar layout in which the electrode pad electrically connected to the first semiconductor element is arranged in two portions with the electrode pad interposed therebetween.

  In the semiconductor device according to the present invention, in the above-described invention, the second semiconductor element includes a first overvoltage protection unit that protects the first semiconductor element from an overvoltage, and a current that detects a current flowing through the first semiconductor element. It is a sense part, a temperature sense part for detecting the temperature of the first semiconductor element, or an arithmetic circuit part for controlling the first semiconductor element.

  The semiconductor device according to the present invention includes the second conductive type first semiconductor region, the first conductive type second semiconductor region, the gate insulating film, the gate electrode, and the first and second electrodes. A first semiconductor element is provided. The first semiconductor region is provided on a front surface side of the first conductivity type semiconductor substrate. The second semiconductor region is selectively provided inside the first semiconductor region. The gate insulating film is provided in contact with a region of the first semiconductor region between the second semiconductor region and the semiconductor substrate. The gate electrode is provided on the opposite side of the first semiconductor region with the gate insulating film interposed therebetween. The first electrode is in contact with the first semiconductor region and the second semiconductor region. The second electrode is in contact with the back surface of the semiconductor substrate. The first electrode is the electrode pad electrically connected to the first semiconductor element.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the semiconductor having a wider band gap than silicon is silicon carbide.

  In the semiconductor device according to the present invention, in the above-described invention, the element structure of the first semiconductor element and the element structure of the second semiconductor element to be the current sensing portion are arranged at a predetermined pitch. It is characterized by.

  In the semiconductor device according to the present invention as set forth in the invention described above, the element structure of the second semiconductor element serving as the current sensing portion is configured by a part of the element structure of the first semiconductor element. And

  In the semiconductor device according to the present invention, in the above-described invention, the element structure of the first semiconductor element is an insulated gate structure, and the element structure of the second semiconductor element serving as the current sensing portion is an insulated gate structure. . The channel length of the element structure of the second semiconductor element serving as the current sensing portion is equal to the gate threshold voltage of the element structure of the second semiconductor element serving as the current sensing portion and the element structure of the first semiconductor element. It is set to become.

  In the semiconductor device according to the present invention, the first semiconductor element includes a second conductivity type first semiconductor region, a first conductivity type second semiconductor region, a gate insulating film, a gate electrode, and a first electrode. It has 1 and 2 electrodes. The first semiconductor region is provided on a front surface side of the first conductivity type semiconductor substrate. The second semiconductor region is selectively provided inside the first semiconductor region. The gate insulating film is provided in contact with a region of the first semiconductor region between the second semiconductor region and the semiconductor substrate. The gate electrode is provided on the opposite side of the first semiconductor region with the gate insulating film interposed therebetween. The first electrode is in contact with the first semiconductor region and the second semiconductor region. The second electrode is in contact with the back surface of the semiconductor substrate. The first electrode is the electrode pad electrically connected to the first semiconductor element.

  The semiconductor device according to the present invention is the above-described invention, wherein the first semiconductor region and the second semiconductor region are electrically connected to the first semiconductor element, and a plurality of the first semiconductor regions. The two semiconductor elements are arranged in a predetermined layout facing the electrode pads electrically connected to each of the two semiconductor elements in the depth direction.

In the semiconductor device according to the present invention, the electrode pad electrically connected to the second semiconductor element serving as the current sensing portion in the first semiconductor region and the second semiconductor region in the invention described above. The current sensing portion is configured by a portion facing in the depth direction.

  In the semiconductor device according to the present invention, the first semiconductor element further includes a third semiconductor region in the above-described invention. The third semiconductor region is selectively provided at a position deeper than the first semiconductor region from the front surface of the semiconductor substrate, and is in contact with the first semiconductor region. The third semiconductor region is disposed so as to be adjacent to a portion of the first semiconductor region serving as the current sensing portion.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, a fourth semiconductor region having a conductivity type different from that of the third semiconductor region is selectively provided in the third semiconductor region. To do.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention includes a plurality of semiconductors arranged on the same semiconductor substrate made of a semiconductor having a wider band gap than silicon. A method for manufacturing a semiconductor device comprising an element and a plurality of electrode pads electrically connected to the plurality of semiconductor elements, respectively, and has the following characteristics. First, a step of forming element structures of the plurality of semiconductor elements on the front surface side of the semiconductor substrate is performed. Next, a step of forming a metal film in contact with a plurality of contact regions of the element structure on the front surface of the semiconductor substrate is performed. Next, the step of selectively removing the metal film and disposing a plurality of the electrode pads respectively electrically connected to the plurality of semiconductor elements on a front surface of the semiconductor substrate in a predetermined planar layout I do. Next, a step of solder-joining terminal pins for taking out the potential of the electrode pads to the outside via the plating films on all the electrode pads is performed.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, the semiconductor device can be manufactured (manufactured) without using a bonding wire having low adhesion to the electrode pad under high temperature conditions. There is an effect that a highly reliable semiconductor device can be provided even under conditions.

1 is a cross-sectional view showing an example of the structure of a semiconductor device according to a first embodiment; 1 is a cross-sectional view showing a wiring structure of a semiconductor device according to a first embodiment; 3 is a plan view showing an example of a planar layout of electrode pads of the semiconductor device according to the first exemplary embodiment; FIG. 3 is a plan view showing an example of a planar layout of electrode pads of the semiconductor device according to the first exemplary embodiment; FIG. 3 is a plan view showing an example of a planar layout of electrode pads of the semiconductor device according to the first exemplary embodiment; FIG. 6 is a plan view showing an example of a planar layout of electrode pads of a semiconductor device according to a second exemplary embodiment; FIG. 6 is a plan view showing an example of a planar layout of electrode pads of a semiconductor device according to a second exemplary embodiment; FIG. 6 is a plan view showing an example of a planar layout of electrode pads of a semiconductor device according to a second exemplary embodiment; FIG. 6 is a plan view showing an example of a planar layout of electrode pads of a semiconductor device according to a second exemplary embodiment; FIG. It is sectional drawing which shows the structure of the conventional semiconductor device. 7 is a plan view showing an example of a planar layout of a semiconductor device according to a third embodiment; FIG. FIG. 12 is a cross-sectional view showing a cross-sectional structure taken along a cutting line Y1-Y1 ′ in FIG. 11. FIG. 12 is a cross-sectional view showing a cross-sectional structure taken along a cutting line X1-X1 ′ in FIG. 11. FIG. 12 is a cross-sectional view showing another example of the cross-sectional structure taken along the cutting line Y1-Y1 ′ of FIG. 11. FIG. 6 is a plan view showing a planar layout of a main part of a semiconductor device according to a fourth embodiment; FIG. 6 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment. FIG. 6 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment. FIG. 10 is a cross-sectional view showing another example of the structure of the semiconductor device according to the fourth embodiment.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. In the present specification, in the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

(Embodiment 1)
The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the first embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described. FIG. 1 is a cross-sectional view illustrating an example of the structure of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view illustrating a wiring structure of the semiconductor device according to the first embodiment. FIG. 1 illustrates an active region of a semiconductor substrate 100 (hereinafter referred to as a silicon carbide substrate (semiconductor substrate (semiconductor chip))) made of silicon carbide, and an edge termination region surrounding the active region is not illustrated. The active region is a region through which current flows in the on state. The edge termination region is a region that relaxes the electric field on the front surface side of the substrate in the drift region and maintains a withstand voltage.

  As shown in FIG. 1, the semiconductor device according to the first embodiment protects and controls the main semiconductor element (first semiconductor element) 10 and the main semiconductor element 10 in the active region of the same silicon carbide substrate 100. A plurality of circuit portions (second semiconductor elements). Examples of the circuit unit for protecting and controlling the main semiconductor element 10 include an overvoltage protection unit (first overvoltage protection unit) 30, a current sensing unit 40, a temperature sensing unit 50, and an arithmetic circuit unit 60. The main semiconductor element 10 and the circuit portion that protects and controls the main semiconductor element 10 have a wiring structure with the same configuration using pin-shaped wiring members (terminal pins 15 described later). The wiring structure of the semiconductor device according to the first embodiment will be described with reference to FIGS. 1 and 2 by taking as an example the case where the main semiconductor element 10 is a vertical MOSFET having a planar gate structure.

Main semiconductor element 10 has first and second p-type base regions (first semiconductor regions) 3, 4 a, n on the front surface (surface on the side of p-type silicon carbide layer 4 described later) 4 of silicon carbide substrate 100. ^A MOS gate structure including a ⁺ type source region (second semiconductor region) 5, a p ⁺ type contact region 6, an n type JFET region 7, a gate insulating film 8 and a gate electrode 9 is provided. One unit cell (functional unit of element) is formed by one MOS gate structure. Although not shown, the plurality of MOS gate structures are arranged in a striped planar layout extending in a direction parallel to the base surface, for example. That is, a plurality of unit cells are arranged adjacent to each other. The main semiconductor element 10 is composed of a plurality of unit cells (for example, about several hundred to several tens of thousands) arranged adjacent to each other.

Specifically, the silicon carbide substrate 100 includes, for example, an n ⁻ type semiconductor layer (n) made of silicon carbide on the front surface of an n ⁺ type support substrate (n ⁺ type silicon carbide substrate) 1 made of silicon carbide. ^- -type silicon carbide layer) 2, a p-type semiconductor layer (p-type silicon carbide layer) 4 made of silicon carbide, formed by stacking in sequence. N ⁺ type silicon carbide substrate 1 functions as a drain region of main semiconductor element 10. A first p-type base region 3 is selectively provided on the surface layer of the n ⁻ -type silicon carbide layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side (base surface side). . A portion of n ⁻ type silicon carbide layer 2 other than first p type base region 3 is a drift region.

A p-type silicon carbide layer 4 is provided on the surface of n ⁻ -type silicon carbide layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 so as to cover first p-type base region 3. The impurity concentration of p-type silicon carbide layer 4 may be lower than the impurity concentration of first p-type base region 3. Inside the p-type silicon carbide layer 4, an n ⁺ -type source region 5 and a p ⁺ -type contact region 6 are selectively provided in a portion facing the first p-type base region 3 in the depth direction. Inside p-type silicon carbide layer 4, an n-type semiconductor region 7 that penetrates p-type silicon carbide layer 4 in the depth direction and reaches n ⁻ -type silicon carbide layer 2 is provided.

n-type semiconductor region 7 is disposed apart from the n ⁺ -type source region 5 with respect to the n ⁺ -type source region 5 to the opposite side of the p ⁺ -type contact region 6. A portion of the p-type silicon carbide layer 4 other than the n ⁺ -type source region 5, the p ⁺ -type contact region 6 and the n-type semiconductor region 7 (hereinafter referred to as a second p-type base region) 4 a And function as a base area. An n-type semiconductor region (hereinafter referred to as an n-type JFET region) 7 is a JFET (Junction FET) region sandwiched between adjacent base regions, and functions as a drift region together with the n ⁻ -type silicon carbide layer 2.

On the surface of the second p-type base region 4 a sandwiched between the n ⁺ -type source region 5 and the n-type JFET region 7, a gate electrode 9 is provided via a gate insulating film 8. A gate insulating film 8 extends on the surface of the n-type JFET region 7 constituting the same unit cell, and the gate electrode 9 is formed so as to face the n-type JFET region 7 in the depth direction with the gate insulating film 8 interposed therebetween. It may be provided. Interlayer insulating film 11 is provided on the entire front surface of silicon carbide substrate 100 so as to cover gate electrode 9. In the contact hole opened in the interlayer insulating film 11, the n ⁺ type source region 5 and the p ⁺ type contact region 6 are exposed.

Source electrode (first electrode) 12 is in contact with n ⁺ -type source region 5 and p ⁺ -type contact region 6 through a contact hole, and is electrically insulated from gate electrode 9 by interlayer insulating film 11. The source electrode 12 may have a stacked structure in which a plurality of metal films are stacked. In FIG. 2, for example, a titanium nitride (TiN) film 21, a titanium (Ti) film 22, a titanium nitride film 23, a titanium film 24, and an aluminum (Al) film 25 are stacked in this order from the substrate front surface side. A source electrode 12 having a layer structure is shown. The titanium nitride film 21 covers the interlayer insulating film 11. Titanium nitride film 21 extends over the interlayer insulating film 11 to the on n ⁺ -type source region 5 of the contact hole, may be in contact with the n ⁺ -type source regions 5.

Titanium film 22 is provided along the surface of titanium nitride film 21 and the inner wall of the contact hole, and is in contact with n ⁺ -type source region 5 and p ⁺ -type contact region 6 of the contact hole. The titanium nitride film 23 is provided on the titanium film 22. The titanium film 24 is provided on the titanium nitride film 23. The titanium nitride film 21, the titanium film 22, the titanium nitride film 23, and the titanium film 24 function as a barrier metal. The barrier metal has a function of preventing diffusion of metal atoms from the source electrode 12 to the silicon carbide substrate 100 and the interlayer insulating film 11 side. In addition, the barrier metal has a function of preventing a mutual reaction between metal films constituting the barrier metal or between regions facing each other with the barrier metal interposed therebetween.

  The aluminum film 25 is provided on the titanium film 24. Instead of the aluminum film 25, for example, an aluminum-silicon (Al-Si) film, an aluminum-silicon-copper (Al-Si-Cu) film, or an aluminum-copper (Al-Cu) film may be provided. The source electrode 12 becomes a source pad (electrode pad) of the main semiconductor element 10. A terminal pin 15 is bonded onto the source electrode 12 via a plating film 13 and a solder film 14. The terminal pin 15 is a round bar-shaped (columnar) wiring member having a predetermined diameter, and serves as an external connection terminal (for example, an implant pin) that extracts the potential of the source electrode 12 to the outside. That is, one end of terminal pin 15 is exposed to the outside of a case (not shown) on which a semiconductor chip (silicon carbide substrate 100) is mounted, and is electrically connected to an external device (not shown). The terminal pin 15 has high adhesion to the source electrode 12 even under high temperature conditions (for example, 200 ° C. to 300 ° C.), and is less likely to be peeled than wire bonding.

  The other end of the terminal pin 15 is solder-bonded to the plating film 13 in a state in which the terminal pin 15 stands substantially perpendicular to the base surface. In FIG. 2, the terminal pins 15 are illustrated in a simplified manner, but actually, the rod-like terminal pins 15 are vertically and vertically joined on the solder film 14. A plurality of terminal pins 15 may be joined to the source electrode 12. The diameter and number of the terminal pins 15 joined to the source electrode 12 are determined based on the current capability of the main semiconductor element 10. The current capability of the main semiconductor element 10 increases as the diameter of the terminal pin 15 increases and the number of the terminal pins 15 bonded to the source electrode 12 increases. The surface area of the plating film 13 is approximately the same as the surface area of the end portion (bottom surface) of the terminal pin 15 when one terminal pin 15 is bonded to the source electrode 12, and a plurality (n, n When the terminal pins 15 of> 1) are joined, the size is such that all the terminal pins 15 can be joined (= the area of the end of the terminal pin 15 × n).

  A portion of the surface of the source electrode 12 other than the portion covered with the plating film 13 is covered with the first protective film 16. The first protective film 16 functions as a mask for preventing the plating film 13 from spreading when the plating film 13 is formed. A second protective film 17 is provided on the boundary between the plating film 13 and the first protective film 16 so as to cover the end portions of the plating film 13 and the first protective film 16. The second protective film 17 functions as a mask for preventing the solder film 14 from spreading when the terminal pins 15 are soldered. The second protective film 17 may cover the entire surface of the first protective film 16. By providing the second protective film 17, the source electrode 12 is not exposed even when a gap is generated between the plating film 13 and the first protective film 16.

Gate electrodes 9 of all unit cells constituting the main semiconductor element 10 are electrically connected to gate pads (electrode pads) at portions not shown. The configuration of the gate pad is the same as that of the source electrode 12. On the gate pad, similarly to the source electrode 12, terminal pins 15 are joined via a plating film 13 and a solder film 14. The diameter and number of terminal pins 15 bonded to the gate pad may be determined based on the current capability of the main semiconductor element 10. A back electrode (second electrode) 18 is provided on the entire back surface of silicon carbide substrate 100 (the back surface of n ⁺ -type silicon carbide substrate 1). The back electrode 18 functions as a drain electrode of the main semiconductor element 10.

Next, a circuit unit for protecting and controlling the main semiconductor element 10 will be described with reference to FIG. 1 taking the overvoltage protection unit 30, the current sensing unit 40, the temperature sensing unit 50, and the arithmetic circuit unit 60 as an example. . The overvoltage protection unit 30 is a diode formed by a pn junction 33 between the p-type anode region 31 and the n ⁻ -type silicon carbide layer 2, and for example, from the overvoltage (OV: Over Voltage) such as a surge to the main semiconductor element 10. Protect. In FIG. 1, the case where the overvoltage protection part 30 is arrange | positioned in two places is shown. The p-type anode region 31 is selectively provided on the surface layer of the n ⁻ -type silicon carbide layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side (base surface side), and n ⁻ -type A pn junction 33 is formed between silicon carbide layer 2 and silicon carbide layer 2.

The anode electrode 32 is in contact with the p-type anode region 31 through a contact hole (not shown). The anode electrode 32 is electrically connected to the source electrode 12 of the main semiconductor element 10. The configuration of the anode electrode 32 is the same as that of the source electrode 12 of the main semiconductor element 10. The anode electrode 32 serves as an electrode pad (hereinafter referred to as an OV pad) of the overvoltage protection unit 30. Although not shown, terminal pins 15 are joined on the anode electrode 32 via the plating film 13 and the solder film 14 in the same manner as the source electrode 12 of the main semiconductor element 10 (see FIG. 2). The diameter and number of the terminal pins 15 joined to the anode electrode 32 may be determined based on the current capability of the overvoltage protection unit 30. N ⁺ type silicon carbide substrate 1 and back electrode 18 function as a cathode region and a cathode electrode of overvoltage protection unit 30, respectively.

The current sensing unit 40 has a function of detecting an overcurrent (OC: Over Current) flowing through the main semiconductor element 10. The current sense unit 40 is a vertical MOSFET including several unit cells having the same configuration as the main semiconductor element 10. That is, the current sense unit 40 includes a first and second p-type base regions 41 and 42, an n ⁺ -type source region 43, a p ⁺ -type contact region 44, an n-type JFET region 45, a gate insulating film 46, and a gate electrode 47. A gate structure and a source electrode 48; Each part constituting the MOS gate structure part of the current sense part 40 has the same structure as each corresponding part of the MOS gate structure part of the main semiconductor element 10.

  The configuration of the source electrode 48 is the same as that of the source electrode 12 of the main semiconductor element 10. The source electrode 48 serves as an electrode pad (hereinafter referred to as an OC pad) of the current sensing unit 40. Although not shown, the terminal pin 15 is joined to the source electrode 48 via the plating film 13 and the solder film 14, similarly to the source electrode 12 of the main semiconductor element 10. The diameter and number of the terminal pins 15 joined to the source electrode 48 may be determined based on the current capability of the current sensing unit 40. The source electrode 48 is electrically connected to the source electrode 12 of the main semiconductor element 10 via the sense resistor 49.

  The current sensing unit 40 detects and divides a part of the drain current flowing when the main semiconductor element 10 is turned on and off as a minute current via the sense resistor 49. The thickness of a part of the gate insulating film 46 may be increased so that a part 47a of the gate electrode 47 protrudes in a convex shape toward the interlayer insulating film (not shown). The gate electrodes 47 of all the unit cells constituting the current sensing unit 40 are electrically connected to the gate pad of the main semiconductor element 10. The back electrode 18 functions as a drain electrode of the current sense unit 40. In other words, the gate pad and drain electrode of the current sense unit 40 are common to the gate pad and drain electrode of the main semiconductor element 10, respectively.

The temperature sensing unit 50 is a diode formed by a pn junction 53 between the p-type anode region 51 and the n-type cathode region 52, and detects the temperature of the main semiconductor element 10 using the temperature characteristics of the diode. It has a function. P type anode region 51 is selectively provided on the surface layer of n ⁻ type silicon carbide layer 2 opposite to the n ⁺ type silicon carbide substrate 1 side. The n-type cathode region 52 is selectively provided inside the p-type anode region 51, and forms a pn junction 53 with the p-type anode region 51. The anode electrode 54 is in contact with the p-type anode region 51 through a contact hole (not shown). The cathode electrode 55 is in contact with the n-type cathode region 52 through a contact hole (not shown). The cathode electrode 55 is electrically connected to the source electrode 12 of the main semiconductor element 10.

  The configurations of the anode electrode 54 and the cathode electrode 55 are the same as those of the source electrode 12 of the main semiconductor element 10. The anode electrode 54 serves as an anode pad of the temperature sensing unit 50. The cathode electrode 55 serves as a cathode pad of the temperature sensing unit 50. Although not shown, terminal pins 15 are joined to the anode electrode 54 and the cathode electrode 55 through the plating film 13 and the solder film 14, respectively, similarly to the source electrode 12 of the main semiconductor element 10 (FIG. 2). The diameter and number of the terminal pins 15 joined to the anode electrode 54 and the cathode electrode 55 may be determined based on the current capability of the temperature sensing unit 50.

  Temperature sensing unit 50 may be a diode formed by a pn junction between a p-type polysilicon (Poly-Si) layer deposited on the front surface of silicon carbide substrate 100 and an n-type polysilicon layer. Good. In this case, the p-type polysilicon layer and the n-type polysilicon layer constituting the temperature sensing unit 50 are deposited on the front surface of the silicon carbide substrate 100 when, for example, the gate electrode 9 of the main semiconductor element 10 is formed. What is necessary is just to form using a part of polysilicon layer. By forming the temperature sensing unit 50 with a polysilicon layer, the temperature sensing unit 50 is less likely to be adversely affected by the current flowing through the main semiconductor element 10.

  The arithmetic circuit unit 60 controls the overvoltage protection unit 30, the current sensing unit 40, and the temperature sensing unit 50. The arithmetic circuit unit 60 controls the main semiconductor element 10 based on output signals from the overvoltage protection unit 30, the current sensing unit 40, the temperature sensing unit 50, and the like. Specifically, for example, when the temperature of the main semiconductor element 10 rises excessively, the arithmetic circuit unit 60 reduces the gate voltage applied to the main semiconductor element 10 to limit the current flowing through the main semiconductor element 10. Thus, the main semiconductor element 10 is protected. The arithmetic circuit unit 60 is composed of a plurality of semiconductor elements such as a CMOS (Complementary MOS) circuit, for example, and FIG. 1 shows an n-channel MOSFET constituting the CMOS circuit.

The n-channel MOSFET constituting the CMOS circuit of the arithmetic circuit unit 60 may be, for example, a vertical MOSFET having the same configuration as that of the main semiconductor element 10. That is, the n-channel MOSFET constituting the CMOS circuit of the arithmetic circuit unit 60 includes the first and second p-type base regions 61 and 62, the n ⁺ -type source region 63, the p ⁺ -type contact region 64, the n-type JFET region 65, the gate insulation. A MOS gate structure composed of a film 66 and a gate electrode 67 and a source electrode 68 are provided. Each part constituting the MOS gate structure part of the n-channel MOSFET constituting the CMOS circuit of the arithmetic circuit part 60 has the same structure as the corresponding part of the MOS gate structure part of the main semiconductor element 10.

  Source electrodes 68 and front surface electrodes (not shown) of other semiconductor elements constituting the arithmetic circuit unit 60 are electrode pads of the arithmetic circuit unit 60 (hereinafter referred to as arithmetic unit pads (not shown)). Is electrically connected. The configuration of the calculation unit pad is the same as that of the source electrode 12 of the main semiconductor element 10, for example. Although not shown in the figure, terminal pins 15 are joined to the arithmetic unit pads via a plating film 13 and a solder film 14 in the same manner as the source electrode 12 of the main semiconductor element 10. The diameter and number of the terminal pins 15 to be joined to the calculation unit pad may be determined based on the current capability of the calculation circuit unit 60.

  The source electrode 12 (hereinafter referred to as the source pad 12), the gate pad, the anode electrode 32 (hereinafter referred to as the OV pad 32), the source electrode 48 (hereinafter referred to as the OC pad 48), the anode electrode 54 (hereinafter referred to as the following). The electrode pads such as the anode pad 54, the cathode electrode 55 (hereinafter referred to as the cathode pad 55), and the calculation unit pad are separated from the front surface of the silicon carbide substrate 100 at a predetermined interval, and have a predetermined planar layout. Placed in. That is, almost the entire front surface of silicon carbide substrate 100 is covered with a plurality of plating films 13 arranged at predetermined intervals. Each electrode pad is electrically insulated. The plating film 13 on each electrode pad is electrically insulated by the first protective film 16.

  Next, the planar layout of each electrode pad will be described. 3 to 5 are plan views illustrating an example of a planar layout of electrode pads of the semiconductor device according to the first embodiment. 3 and 4 show a planar layout of the source pad 12, the gate pad 19, the OV pad 32, the OC pad 48, the anode pad 54, and the cathode pad 55. FIG. 3 and 4, the source pad 12, gate pad 19, OV pad 32, OC pad 48, anode pad 54 and cathode pad 55 are denoted as S, G, OV, OC, A and K, respectively (FIG. 3). The same applies to 5-9. FIG. 5 shows a planar layout of the source pad 12, the gate pad 19, the OV pad 32, the OC pad 48, the anode pad 54, the cathode pad 55, and the arithmetic unit pad 69. FIG. 5 shows the calculation unit pad 69 as a calculation unit (the same applies to FIG. 8).

  The main semiconductor element 10 has a larger current capability than other circuit units. For this reason, as shown in FIGS. 3 and 4, the source pad 12 is substantially the entire surface of the active region 101 (the region used as the active region 101) excluding the region where the electrode pads other than the source pad 12 are disposed. Placed in. The planar layout of the source pad 12 can be variously changed according to required specifications, and is determined by, for example, the current capacity of the main semiconductor element 10. Specifically, for example, when electrode pads other than the source pad 12 are arranged in a straight line in the center of the active region 101, the two source pads 12 are sandwiched between all the electrode pads other than the source pad 12. May be arranged (FIG. 3).

  Further, depending on the size of the chip (silicon carbide substrate 100), four source pads 12 facing each vertex of the substantially rectangular planar semiconductor chip (silicon carbide substrate 100) may be arranged (FIG. 4). . In this case, a gate runner (not shown) can be disposed in the portion 103 of the active region 101 sandwiched between the source pads 12 disposed adjacent to each other without sandwiching another electrode pad. The gate runner is electrically connected to the gate electrodes 9 of all the unit cells constituting the main semiconductor element 10. For example, when the gate electrodes 9 of the main semiconductor element 10 are arranged in a striped planar layout, the gate resistance is increased, and there is a possibility that an operation timing shift (unbalance operation) occurs in each unit cell of the main semiconductor element 10. By arranging a gate runner, the operation timing of each unit cell can be made substantially the same.

  The current sensing unit 40 is configured using, for example, some unit cells of the main semiconductor element 10 in order to operate under the same conditions as the main semiconductor element 10. That is, the OC pad 48 is disposed in the effective area in the active area 101. The electrode pads other than the source pad 12 and the OC pad 48 may be arranged in an ineffective region (region not used as the active region 101) in the active region 101. Further, the gate pad 19 may be arranged in the edge termination region 102 (for example, about 100 μm in width). The OV pad 32, the anode pad 54, and the cathode pad 55 may be disposed in the edge termination region 102 together with the element structures of the overvoltage protection unit 30 and the temperature sensing unit 50. Preferably, the anode pad 54 and the cathode pad 55 are arranged in the vicinity of a region where the amount of current of the main semiconductor element 10 is large (for example, the central portion of the active region 101).

When electrode pads other than the source pad 12 are arranged in parallel, the arrangement order can be variously changed. For example, another electrode pad may be disposed between the anode pad 54 and the cathode pad 55. In FIG. 3, the anode pad 54 and the cathode pad 55 are shown adjacent to each other, but actually, the anode pad 54 and the cathode pad 55 are electrically insulated (the same applies to FIGS. 4 to 9). The distance x1 between adjacent electrode pads can be as narrow as about 500 μm or less, for example. The chip size increases as the current capability of the main semiconductor element 10 increases. When the chip size is 5 mm ² , five electrode pads can be arranged in a straight line when the distance x1 between adjacent electrode pads is about 500 μm. The surface area of the active region 101 decreases as the chip size decreases. For this reason, each electrode pad may be arranged in two rows.

  The arithmetic circuit unit 60 is composed of a plurality of semiconductor elements such as CMOS circuits as described above. For this reason, the arithmetic circuit unit 60 includes an arithmetic unit pad 69 in addition to the front surface electrodes (source electrode 68 and the like) of the plurality of semiconductor elements constituting the arithmetic circuit unit 60. When the arithmetic circuit unit 60 is arranged on the same silicon carbide substrate 100 as the main semiconductor element 10, the element structure (including the front surface electrode) of a plurality of semiconductor elements constituting the arithmetic circuit unit 60 is effective for the active region 101. What is necessary is just to arrange | position to the area | region. The calculation unit pad 69 may be disposed in either the effective region or the invalid region of the active region 101 (FIG. 5) or may be disposed in the edge termination region 102. When the arithmetic unit pad 69 is disposed in the active region 101, it is preferable to dispose it as close to the edge termination region 102 as possible. FIG. 5 shows a state in which a calculation unit pad 69 is added near the boundary between the active region 101 and the edge termination region 102 in the planar layout of the electrode pad shown in FIG.

Next, the method for manufacturing the semiconductor device according to the first embodiment will be described by taking as an example the case where the main semiconductor element 10 having a withstand voltage class of 1200 V, for example, is manufactured. First, a silicon carbide single crystal n ⁺ -type silicon carbide substrate (semiconductor wafer) 1 doped with an n-type impurity (dopant) such as nitrogen (N) so as to have an impurity concentration of 2.0 × 10 ¹⁹ / cm ³ , for example. Prepare. The front surface of n ⁺ -type silicon carbide substrate 1 may be, for example, a (000-1) plane having an off angle of about 4 degrees in the <11-20> direction. Next, on the front surface of the n ⁺ type silicon carbide substrate 1, an n ⁻ type silicon carbide layer 2 doped with an n type impurity such as nitrogen so as to have an impurity concentration of 1.0 × 10 ¹⁶ / cm ³ , for example. Is epitaxially grown to a thickness of 10 μm, for example.

Next, the first p-type base region 3 of the main semiconductor element 10 is selectively formed on the surface layer of the n ⁻ -type silicon carbide layer 2 by photolithography and ion implantation. At this time, together with the first p-type base region 3 of the main semiconductor element 10, a p-type region having the same configuration of the circuit portion disposed on the same silicon carbide substrate 100 as the main semiconductor element 10 is formed. Specifically, the p-type region of the circuit unit disposed on the same silicon carbide substrate 100 as the main semiconductor element 10 is, for example, the p-type anode region 31 of the overvoltage protection unit 30 and the first p-type of the current sense unit 40. The base region 41, the p-type anode region 51 of the temperature sensing unit 50, the first p-type base region 61 of the arithmetic circuit unit 60, and the like. When the depth and impurity concentration are different from those of the first p-type base region 3 (for example, the p-type anode region 31 of the overvoltage protection unit 30), the process of photolithography and ion implantation as one set may be repeated.

Next, the p-type silicon carbide layer 4 doped with p-type impurities such as aluminum on the surface of the n ⁻ -type silicon carbide layer 2 to have an impurity concentration of 2.0 × 10 ¹⁶ / cm ³ , for example, Epitaxial growth is performed with a thickness of 5 μm. Through the steps up to here, silicon carbide substrate 100 is fabricated by sequentially stacking n ⁻ type silicon carbide layer 2 and p type silicon carbide layer 4 on the front surface of n ⁺ type silicon carbide substrate 1. Next, the n ⁺ -type source region 5, the p ⁺ -type contact region 6 and the n-type JFET region 7 are formed by repeatedly performing a process of combining photolithography and ion implantation under different ion implantation conditions. The order of forming the n ⁺ -type source region 5, the p ⁺ -type contact region 6 and the n-type JFET region 7 can be variously changed. At this time, an n ⁺ -type region, a p ⁺ -type region, and an n-type region having the same configuration of the circuit portion disposed on the same silicon carbide substrate 100 as the main semiconductor element 10 are formed together with each of these regions.

Specifically, the n ⁺ type region of the circuit unit disposed on the same silicon carbide substrate 100 as the main semiconductor element 10 is, for example, the n ⁺ type source region 43 of the current sense unit 40 and the n ⁺ type of the arithmetic circuit unit 60. ⁺ Type source region 63 and the like. The p ⁺ type region of the circuit portion arranged on the same silicon carbide substrate 100 as the main semiconductor element 10 is, for example, the p ⁺ type contact region 44 of the current sense unit 40 and the p ⁺ type contact region 64 of the arithmetic circuit unit 60. Etc. The n-type region of the circuit unit arranged on the same silicon carbide substrate 100 as the main semiconductor element 10 is, for example, the n-type JFET region 45 of the current sensing unit 40, the n-type cathode region 52 of the temperature sensing unit 50, and the arithmetic circuit. For example, the n-type JFET region 65 of the portion 60. The portions of the p-type silicon carbide layer 4 facing the first p-type base regions 41 and 61 in the depth direction are respectively the second p-type base region 42 of the current sensing unit 40 and the second p-type base region 62 of the arithmetic circuit unit 60. Become.

Next, heat treatment (annealing) for activating a plurality of regions formed in the silicon carbide substrate 100 by ion implantation is performed at a temperature of, for example, about 1620 ° C. for about 2 minutes. Next, for example, the front surface of the silicon carbide substrate 100 is thermally oxidized by heat treatment at a temperature of about 1000 ° C. in a mixed gas atmosphere of oxygen (O ₂ ) gas and hydrogen (H ₂ ) gas, for example, about 100 nm. A gate insulating film is formed with a thickness of Thereby, the entire front surface of silicon carbide substrate 100 is covered with the insulating film. This insulating film becomes the gate insulating film 8 of the main semiconductor element 10, the gate insulating film 46 of the current sensing unit 40, the gate insulating film 66 of the arithmetic circuit unit 60, and the like. Next, a polysilicon layer doped with, for example, phosphorus (P) is formed on the insulating film. Next, this polysilicon layer is selectively removed by patterning, leaving the gate electrode 9 of the main semiconductor element 10, the gate electrode 47 of the current sensing unit 40, and the gate electrode 67 of the arithmetic circuit unit 60.

  Next, an interlayer insulating film 11 made of, for example, phosphorous glass (PSG) is formed to have a thickness of, for example, 1.0 μm so as to cover the gate electrodes 9, 47, 67 on the entire front surface of the silicon carbide substrate 100. A film is formed (formed). Next, the interlayer insulating film 11 and the gate insulating films 8, 46, 66 are patterned by photolithography and etching to form the main semiconductor element 10 and contact holes for each circuit portion. Next, the interlayer insulating film 11 is planarized by heat treatment (reflow). Next, a titanium nitride film 21 is formed (deposited) so as to cover the interlayer insulating film 11 by, for example, sputtering. Next, a titanium film 22 is formed along the surface of the titanium nitride film 21, the side wall of the contact hole, and the surface of the silicon carbide semiconductor portion exposed in the contact hole, for example, by sputtering.

Next, for example, a nickel (Ni) film to be the back electrode 18 is formed on the back surface of the silicon carbide substrate 100 (the back surface of the n ⁺ -type silicon carbide substrate 1) by, for example, sputtering. Then, for example, by heat treatment at a temperature of 970 ° C., the titanium film 22 forms an ohmic junction with the silicon carbide semiconductor portion and an ohmic junction between the back electrode 18 and the silicon carbide substrate 100. Next, a titanium nitride film 23 is formed on the titanium film 22 by, eg, sputtering. Next, a titanium film 24 is formed on the titanium nitride film 23 by sputtering, for example. Next, a metal film mainly made of aluminum such as an aluminum film 25 is formed on the titanium film 24 by, for example, sputtering. By laminating the titanium nitride film 21, the titanium film 22, the titanium nitride film 23, the titanium film 24, and the aluminum film 25, a metal laminated film serving as a front electrode is formed.

  Next, the metal laminated film to be the front electrode is patterned by photolithography and etching. By this patterning, the front electrode of each semiconductor element constituting the source pad 12, the gate pad 19, the OV pad 32, the OC pad 48, the anode pad 54, the cathode pad 55, and the arithmetic circuit unit 60 of the metal laminated film A portion to be the calculation unit pad 69 or the like is left in a predetermined plane layout. Next, for example, a titanium film, a nickel film, and a gold (Au) film to be the back electrode 18 are sequentially formed on the surface of the nickel film formed as the back electrode 18. Next, a portion of each electrode pad other than the formation region of the plating film 13 is covered with the first protective film 16. At this time, the first protective film 16 is embedded between the electrode pads to electrically insulate the electrode pads from each other. Before the first protective film 16 is formed, another insulating film may be embedded between the electrode pads to electrically insulate the electrode pads from each other.

  Next, the plating film 13 is formed on the surface of each electrode pad using the first protective film 16 as a mask. Thereby, almost the entire front surface of silicon carbide substrate 100 is selectively covered with plating film 13. Next, the boundary between the first protective film 16 and the plating film 13 is covered with a second protective film 17. Next, the terminal pin 15 is soldered (solder film 14) on the plating film 13 of each electrode pad. Thereafter, the silicon carbide substrate 100 is cut (diced) into chips to obtain individual pieces, thereby completing the MOSFETs shown in FIGS.

  As described above, according to the first embodiment, the terminal pins are joined to all the electrode pads provided on the same silicon carbide substrate via the plating film and the solder film, so that the electrode can be used under a high temperature condition. A semiconductor device can be manufactured (manufactured) without using a bonding wire having low adhesion to the pad. For this reason, for example, high reliability even under a high temperature condition of, for example, about 200 ° C. to 300 ° C. (about 150 ° C. for silicon (Si)), which is the operating temperature of a semiconductor device using a wide band gap semiconductor such as silicon carbide. Can be secured. In addition, since no bonding wire is used, adverse effects caused by cutting the bonding wire or drawing the bonding wire can be avoided, and the reliability of the semiconductor device can be improved.

  Further, when bonding wires are used as in the prior art, electrode pads other than the source pads are arranged near the boundary between the active region and the edge termination region so that wire bonding is easy. On the other hand, according to the first embodiment, since the terminal pin is used, the potential can be taken out from the electrode pad even if the electrode pad is arranged at the center of the semiconductor chip. For this reason, the freedom degree of arrangement | positioning of an electrode pad is high (there is no restriction | limiting in the arrangement | positioning of an electrode pad). Further, when bonding wires are used as in the prior art, the size (surface area) of electrode pads and the distance between electrode pads (over 500 μm) are limited and difficult to reduce, so there is a limit to miniaturization of semiconductor devices. On the other hand, according to the first embodiment, the size of the electrode pad can be reduced by reducing the diameter of the terminal pin or by optimizing the process for forming the plating film on the electrode pad. it can. For this reason, the chip size can be made smaller than before, and the semiconductor device can be miniaturized.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. 6 to 9 are plan views illustrating an example of a planar layout of the electrode pads of the semiconductor device according to the second embodiment. In the semiconductor device according to the second embodiment, the planar layout of the source pad 12, the gate pad 19, the OV pad 32, the OC pad 48, the anode pad 54, the cathode pad 55, and the arithmetic unit pad 69 is the same as that of the first embodiment. Different from such a semiconductor device. 6, 7, and 9 show planar layouts of the source pad 12, the gate pad 19, the OV pad 32, the OC pad 48, the anode pad 54, and the cathode pad 55. FIG. 8 shows a planar layout of the source pad 12, the gate pad 19, the OV pad 32, the OC pad 48, the anode pad 54, the cathode pad 55, and the arithmetic unit pad 69.

  As shown in FIGS. 6 to 9, each electrode pad other than the source pad 12 may be arranged near the boundary between the active region 101 and the edge termination region 102. In this case, one source pad 12 may be disposed on almost the entire surface of the active region 101 excluding the region where the electrode pads other than the source pad 12 are disposed (FIG. 6). A pad 12 may be arranged (FIG. 7). Further, it is preferable that the calculation unit pad 69 be arranged as far as possible from other electrode pads other than the source pad 12 and as close to the edge termination region 102 as possible. Specifically, for example, the arithmetic unit pad 69 and the electrode pads other than the source pad 12 may be arranged near the opposite sides (sides that do not share the vertex) 100a and 100b of the semiconductor chip (FIG. 8). ). FIG. 8 shows a state in which a calculation unit pad 69 is added near the boundary between the active region 101 and the edge termination region 102 in the planar layout of the electrode pad shown in FIG.

  Further, as shown in FIG. 9, the source pad 12 may be arranged in the center of the active region 101, and the electrode pads other than the source pad 12 may be arranged in two places so as to sandwich the source pad 12. Specifically, for example, the gate pad 19 and the OC pad 48, the OV pad 32, the anode pad 54, and the cathode pad 55 are disposed near the opposite sides 100c and 100d of the semiconductor chip, respectively. The source pad 12 may be disposed between the gate pad 19 and the OC pad 48 and the OV pad 32, the anode pad 54, and the cathode pad 55. The type and number of electrode pads arranged on the opposite sides 100c and 100d of the semiconductor chip can be variously changed. Similarly to the first embodiment, each electrode pad other than the source pad 12 and the OC pad 48 may be arranged further outside, that is, in the edge termination region 102.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained. Further, in the conventional semiconductor device, electrode pads other than the source pad are arranged near the boundary between the active region and the edge termination region. Therefore, according to the second embodiment, the present invention can be applied to a conventional semiconductor device, and the size can be reduced without changing the arrangement of each circuit portion.

(Embodiment 3)
Next, in the third embodiment, an example of the arrangement and various conditions of the MOS gate structure portions of the main semiconductor element 10 and the current sense portion 40 will be described. FIG. 11 is a plan view illustrating an example of a planar layout of the semiconductor device according to the third embodiment. 12 is a cross-sectional view showing a cross-sectional structure taken along the cutting line Y1-Y1 ′ of FIG. FIG. 13 is a cross-sectional view showing a cross-sectional structure taken along section line X1-X1 ′ of FIG. FIG. 14 is a cross-sectional view showing another example of the cross-sectional structure taken along the cutting line Y1-Y1 ′ of FIG. Here, a case where, for example, a current sense unit 40, a temperature sense unit 50, and a gate pad unit 20 are arranged on the same silicon carbide substrate 100 as that of the main semiconductor element 10 is shown, but the first overvoltage is the same as in the first embodiment. You may arrange | position a protection part and an arithmetic circuit part.

  As shown in FIG. 11, on the front surface of the silicon carbide substrate 100, there are an active region 101, a source pad (source electrode) 12, a gate pad 19, an OC pad (source electrode) 48, and an anode pad (anode electrode). 54 and a cathode pad (cathode electrode) 55 are provided in a predetermined plane layout. The planar layout of the source pad 12 can be variously changed according to required specifications. For example, the source pads 12 are arranged in a plane layout having a substantially rectangular frame shape surrounding all electrode pads other than the source pads 12, and the electrode pads other than the source pads 12 are arranged in a straight line in the center of the active region 101. May be. The planar layout of each electrode pad may be the same as in the first and second embodiments (see FIGS. 3 to 9).

  As shown in FIG. 12, the semiconductor region constituting each MOS gate structure portion of the main semiconductor element 10 has a predetermined pitch x2 over the entire active region 101 regardless of the planar layout of each electrode pad arranged in the active region 101. It is arranged with. The MOS gate structure portion 70 b of the current sensing portion 40 is configured using a part of the MOS gate structure portion arranged as the main semiconductor element 10 on the silicon carbide substrate 100. The MOS gate structure portion 70b of the current sensing portion 40 has a pitch x3 with the MOS gate structure portion 70a of the main semiconductor element 10 adjacent in the second direction Y, which will be described later, between the MOS gate structure portions 70a of the main semiconductor element 10. It can be made equal to the pitch x2 (x2 = x3).

Specifically, the MOS gate structure 70a of the main semiconductor element 10 includes a p-type base region 71, an n ⁺ -type source region 72, a p ⁺ -type contact region 73, an n-type JFET region 74, a gate insulating film 75, and a gate electrode. 76. The p-type base region 71 is selectively provided in the surface layer on the front surface side of the silicon carbide substrate 100. The p-type base region 71 may be composed of first and second p-type base regions as in the first embodiment. An n ⁺ type source region 72 and a p ⁺ type contact region 73 are selectively provided inside the p type base region 71, respectively. An n-type JFET region 74 is provided between adjacent p-type base regions 71.

The p-type base region 71, n ⁺ -type source region 72, p ⁺ -type contact region 73 and n-type JFET region 74 are not only directly under the source pad 12 (parts facing in the depth direction) but also the entire active region 101. It is also arranged in a portion other than directly below the source pad 12. That is, the entire active region 101 becomes an effective region. The p-type base region 71, the n ⁺ -type source region 72, and the p ⁺ -type contact region 73 are, for example, in a direction parallel to the front surface of the base for contact (electrical contact) with the source pad 12 as will be described later. It is preferable to arrange in a striped planar layout extending in the horizontal direction. The p-type base regions 71 may be arranged at regular intervals, for example, at a predetermined pitch x2 over the entire active region 101.

The n ⁺ -type source region 72, the p ⁺ -type contact region 73, and the n-type JFET region 74 have a striped planar layout extending in the same direction (hereinafter referred to as the first direction) X as the striped p-type base region 71. Be placed. The n ⁺ type source region 72 and the p ⁺ type contact region 73 are in contact with the source pad 12 at a portion immediately below the source pad 12. The portions immediately below the gate pad 19, the anode pad 54 and the cathode pad 55 of the n ⁺ type source region 72 and the p ⁺ type contact region 73 are in contact with the source pad 12 at a portion not shown. Of the MOS gate structure portion arranged as the main semiconductor element 10 on the silicon carbide substrate 100, the portion immediately below the OC pad 48 (the portion facing the drain side in the depth direction) is used as the MOS gate structure portion 70b of the current sensing portion 40. The other part becomes the MOS gate structure part 70 a of the main semiconductor element 10.

Specifically, at least one part of the striped p-type base region 71 becomes the p-type base region 71 constituting the MOS gate structure portion 70 b of the current sensing portion 40. For this reason, the MOS gate structure part 70a of the main semiconductor element 10 and the MOS gate structure part 70b of the current sense part 40 are continuous in the first direction X (FIG. 13). In the portion immediately below the OC pad 48, the n ⁺ type source region 72 and the p ⁺ type contact region 73 are in contact with the OC pad 48. The OC pad 48 has a size about one thousandth that of the source pad 12 (for example, about 20 μm square to about 50 μm square). The OC pad 48 is arranged in a width (a width of a direction perpendicular to the first direction X (hereinafter referred to as a second direction) Y) facing the plurality of stripe-shaped p-type base regions 71 in the depth direction. (FIG. 12).

Immediately below the source pad 12 and the OC pad 48, the gate of the p-type base region 71 is sandwiched between the n ⁺ -type source region 72 and the n-type JFET region 74 via the gate insulating film 75. An electrode 76 is provided. Gate electrode 76 is electrically insulated from source pad 12 and OC pad 48 by interlayer insulating film 77. The gate electrode 76 is not disposed in the temperature sensing unit 50 and the gate pad unit 20. Gate pad 19, anode pad 54, cathode pad 55, and diode 80 of temperature sensing unit 50, which will be described later, are electrically connected to silicon carbide substrate 100 by interlayer insulating film 77 and oxide film 78 on the front surface of silicon carbide substrate 100. Is electrically insulated.

  The temperature sensing unit 50 is a diode 80 formed by a pn junction between the p-type polysilicon layer 81 and the n-type polysilicon layer 82. The p-type polysilicon layer 81 and the n-type polysilicon layer 82 are disposed on the oxide film 78 and are in contact with the anode pad 54 and the cathode pad 55, respectively. All gate electrodes 76 of the MOS gate structure portions 70a and 70b are electrically connected to the gate pad 19 at portions not shown. As in the first embodiment, terminal pins (not shown) are joined to each electrode pad via a plating film 13 and a solder film 14, respectively. Each electrode pad is electrically insulated from each other by the first and second protective films 16 and 17 as in the first embodiment.

  The p-type base region 71 constituting the MOS gate structure 70a of the main semiconductor element 10 corresponds to the first and second p-type base regions 3 and 4a of the main semiconductor element 10 of the first embodiment (see FIGS. 1 and 2). The parts (reference numerals 72 to 76) other than the p-type base region 71 correspond to the corresponding parts (reference numerals 5 to 9) of the main semiconductor element 10 of the first embodiment. The p-type base region 71 constituting the MOS gate structure 70 b of the current sense unit 40 corresponds to the first and second p-type base regions 41 and 42 of the current sense unit 40 of the first embodiment, and other than the p-type base region 71. Each part (reference numerals 72 to 76) corresponds to each corresponding part (reference numerals 43 to 47) of the current sensing part 40 of the first embodiment.

  Thus, by arranging the semiconductor regions constituting the MOS gate structures 70a and 70b, the entire active region 101 can be made an effective region. In addition, the MOS gate structure 70b of the current sense unit 40 is configured by a part of the MOS gate structure 70a of the main semiconductor element 10 so that the main semiconductor element 10 and the current sense unit 40 are normally arranged. Ineffective areas (for example, 600 μm to 300 μm wide) disappear. As a result, the semiconductor chips can be reduced, and the yield of the semiconductor chips cut from one semiconductor wafer is improved. For this reason, it is particularly useful when using a silicon carbide wafer having many crystal defects.

  Further, since there is no ineffective region separating the main semiconductor element 10 and the current sensing unit 40, the pitch between the MOS gate structure 70a of the main semiconductor element 10 and the MOS gate structure 70b of the current sensing unit 40 is not changed. Can be arranged. Thereby, since it is possible to suppress the drift current flowing into the current sense unit 40 from being reduced, the overcurrent detection accuracy of the current sense unit 40 is improved. In addition, since there is no invalid region that separates the main semiconductor element 10 and the current sensing unit 40, it is possible to prevent characteristic degradation (for example, the on-resistance RonA is increased) due to the invalid region.

Further, in a silicon carbide semiconductor device, as the chip size increases (for example, 8 mm ² or more), it is difficult to adopt a wiring structure using bonding wires, and a wiring structure using terminal pins is adopted. Also, in the conventional wiring structure using terminal pins, there are many ineffective regions that separate the main semiconductor element and the current sensing portion. For this reason, Embodiment 3 is particularly useful when the chip size is large. Both the main semiconductor element 10 and the current sense unit 40 are MOSFETs, and even if current imbalance occurs, they are not easily broken. For this reason, there is no problem in characteristics even if an ineffective region for separating the main semiconductor element 10 and the current sensing unit 40 is not provided.

  In the present invention, since the terminal pin is soldered to the electrode pad, the MOS gate structure portion 70b of the current sensing portion 40 is set to a design value different from the MOS gate structure portion 70a of the main semiconductor element 10. Is preferred. The reason is as follows. The current sense unit 40 is designed to have the same design value as the main semiconductor element 10 so as to have the same characteristics as the main semiconductor element 10. However, the terminal pin (not shown: reference numeral 15 in FIG. 2) soldered to the OC pad 48 is smaller than the diameter of the terminal pin (not shown) soldered to the source pad 12, so that the terminal pin During the soldering, the OC pad 48 is subjected to a stress larger than the stress applied to the source pad 12.

  It has been confirmed by the inventors that the gate threshold voltage of the current sensing section 40 becomes different from the gate threshold voltage of the main semiconductor element 10 due to the stress applied when soldering the terminal pins. In this case, the main semiconductor element 10 and the current sense unit 40 do not operate at a predetermined current ratio, and a large current tends to flow through the current sense unit 40. As a result, the withstand voltage of the current sense unit 40 is lower than the withstand voltage of the main semiconductor element 10, so that the voltage gain (voltage amplification factor) of the current sense unit 40 must be the same as the voltage gain of the main semiconductor element 10. Because there is. Therefore, for example, the initial design value of the current sense unit 40 is changed so that the gate threshold voltage of the current sense unit 40 is as close as possible to the gate threshold voltage of the main semiconductor element 10.

  Specifically, for example, the channel length L2, which is one of the variables for changing the gate threshold voltage of the current sense unit 40, is changed to a design value different from the initial design value (that is, the channel length L1 of the main semiconductor element 10). do it. The method for changing the design value of the channel length L2 of the current sensing unit 40 is as follows. First, a shift in the gate threshold voltage between the main semiconductor element 10 and the current sensing unit 40 is acquired from a semiconductor device that has been fabricated or simulated in advance based on the initial design value. Based on the shift of the gate threshold voltage between the main semiconductor element 10 and the current sensing unit 40, the channel length L2 of the current sensing unit 40 is recalculated. Then, a semiconductor device that finally becomes a product may be manufactured with a new design value based on the recalculated value.

  In the recalculation of the channel length L2 of the current sense unit 40, the gate threshold voltage of the current sense unit 40, which has changed due to the stress applied to the OC pad 48 when the terminal pin is soldered, approaches the gate threshold voltage of the main semiconductor element 10. What is necessary is just to calculate. The deviation of the gate threshold voltage between the main semiconductor element 10 and the current sense unit 40 caused by the stress at the time of soldering the terminal pins is usually about 1 V, and has reproducibility. For this reason, the gate threshold voltage of the current sense unit 40 is set to a main level with a predetermined tolerance by manufacturing a semiconductor device that will eventually become a product with a new design value based on the channel length L2 of the recalculated current sense unit 40. A semiconductor device close to the gate threshold voltage of the semiconductor element 10 can be easily manufactured.

  Thus, the withstand voltage of the current sensing unit 40 is improved by recalculating and setting the channel length L2 of the current sensing unit 40 based on the shift in the gate threshold voltage between the main semiconductor element 10 and the current sensing unit 40. be able to. An allowable error of the deviation of the gate threshold voltage between the main semiconductor element 10 and the current sense unit 40 is, for example, about ± 0.5V. Even if the gate threshold voltage of the current sense unit 40 changes due to stress applied to the OC pad 48 when soldering the terminal pins, it is assumed that the breakdown voltage of the current sense unit 40 is equal to or higher than the breakdown voltage of the main semiconductor element 10. In this case, a semiconductor device that finally becomes a product may be manufactured with an initial design value without recalculating the channel length L2 of the current sense unit 40.

As shown in FIG. 14, immediately below the gate pad 19, the anode pad 54, and the cathode pad 55, a semiconductor region that constitutes the MOS gate structure 70a may be disposed without being disposed. In this case, the MOS gate structure may be arranged in a stripe-like planar layout extending in the first direction X, or may be arranged in a matrix-like planar layout. When the MOS gate structure is arranged in a striped planar layout, the p-type base region 71, the n ⁺ -type source region 72, the p ⁺ -type contact region 73 and the n-type JFET region 74 are effective regions in the active region 101. Are arranged in a striped planar layout extending in the first direction X.

When the MOS gate structure is arranged in a matrix-like planar layout, the p-type base region 71 is arranged in a matrix-like planar layout in the effective area of the active region 101. The p ⁺ type contact region 73 is arranged near the center of the p type base region 71, and the n ⁺ type source region 72 is arranged in a planar layout surrounding the periphery of the p ⁺ type contact region 73. The n-type JFET region 74 is arranged in a lattice-like planar layout passing between adjacent p-type base regions 71. A p-type base region 71 and a p ⁺ -type contact region 73 constituting the adjacent main semiconductor element 10 or current sensing unit 40 may extend immediately below the gate pad 19, the anode pad 54, and the cathode pad 55. .

  In the third embodiment, a part of the MOS gate structure portion arranged as main semiconductor element 10 on silicon carbide substrate 100 is used as MOS gate structure portion 70b of current sensing portion 40. In addition, the channel length L2 of the current sensing unit 40 is set so that the voltage gain between the main semiconductor element 10 and the current sensing unit 40 is as close as possible. As long as this condition can be satisfied, for example, the MOS gate structure 70a of the main semiconductor element 10 and the MOS gate structure 70b of the current sensing unit 40 may be arranged in different planar layouts.

  As described above, according to the third embodiment, the same effect as in the first and second embodiments can be obtained. Further, according to the third embodiment, the semiconductor region constituting the MOS gate structure portion is arranged over the entire active region, and the current sense portion is constituted by a part of the semiconductor region, thereby reducing the size of the semiconductor chip and It is possible to improve the yield of semiconductor chips cut from the semiconductor wafer, improve the current capability of the main semiconductor element, and the like. Further, according to the third embodiment, the channel length of the current sense unit is set so that the gate threshold voltage of the current sense unit approaches the gate threshold voltage of the main semiconductor element, so that the withstand voltage of the current sense unit is reduced to the main semiconductor element. It is possible to prevent the voltage from falling below the withstand voltage.

(Embodiment 4)
Next, the structure of the semiconductor device according to the fourth embodiment will be described. FIG. 15 is a plan view showing a planar layout of the main part of the semiconductor device according to the fourth embodiment. 16 and 17 are sectional views showing an example of the structure of the semiconductor device according to the fourth embodiment. Here, the planar layout of the semiconductor device according to the fourth embodiment is the same as that of the third embodiment (see FIG. 11), but the first overvoltage protection unit and the arithmetic circuit unit are arranged as in the first embodiment. Also good. FIG. 15 shows a planar layout near the OC pad 48 of FIG. FIG. 16 shows a cross-sectional structure taken along the cutting line Y1-Y1 ′ of FIG. FIG. 17 shows a cross-sectional structure taken along the cutting line X1-X1 ′ in FIG.

  The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the third embodiment in that a part of the main semiconductor element 10 includes a second overvoltage protection unit 90 for protecting the current sense unit 40 from overvoltage. Is a point.

  Specifically, as shown in FIG. 15, the second overvoltage protection unit 90 is arranged in, for example, a substantially rectangular frame shape surrounding the current sensing unit 40. In FIG. 15, the second overvoltage protection unit 90 is a portion surrounded by two thick broken line frames. For example, it is assumed that the p-type base region 71 is arranged in a striped planar layout. The p-type base region 71a closest to the current sense unit 40 in the second direction Y and the p-type base region 71b disposed between the p-type base regions 71a are p-type regions parallel to the second direction Y ( (Hereinafter referred to as a p-type base connecting portion) 71c. The p-type base coupling portion 71 c has, for example, the same depth and impurity concentration as the p-type base region 71 and functions as the p-type base region 71.

  The p-type base connection portion 71 c connects the portions of the p-type base region 71 that become the MOS gate structure portion 70 a of the main semiconductor element 10, and does not face the OC pad 48 in the depth direction Z. In addition, two p-type base coupling portions 71 c are arranged so as to sandwich the current sensing portion 40. That is, the current sense unit 40 is arranged in a rectangular frame formed by the p-type base region 71a closest to the current sense unit 40 in the second direction Y and the p-type base coupling unit 71c. The second overvoltage protection unit 90 is arranged in a substantially rectangular frame-like planar layout along the p-type base region 71a closest to the current sense unit 40 in the second direction Y and the p-type base coupling portion 71c. It faces the mold base region 71a and the p-type base connecting part 71c in the depth direction. In FIG. 15, components other than the p-type base region 71 and the n-type JFET region of the MOS gate structure are not shown.

  Although not shown, the second overvoltage protection unit 90 may be arranged in a substantially concentric circle surrounding the current sensing unit 40. In this case, at least two p-type base coupling portions 71c adjacent to each other with the current sensing portion 40 interposed therebetween are arranged in a striped planar layout extending in the second direction Y. These four or more p-type base connection portions 71c and the p-type base region 71 (including the p-type base region 71a) that becomes the MOS gate structure portion 70a of the main semiconductor element 10 surround the current sensing portion 40. A concentric planar layout is formed. A concentric plane along these four or more p-type base coupling portions 71c and a p-type base region 71 (including the p-type base region 71a) to be the MOS gate structure 70a of the main semiconductor element 10 is provided. The second overvoltage protection unit 90 may be arranged in the layout.

As shown in FIGS. 16 and 17, the second overvoltage protection unit 90 includes an n-type or p-type first semiconductor region (third semiconductor region) 91. First semiconductor region 91 includes n ⁻ type silicon carbide layer 2, n ⁺ type silicon carbide substrate 1, and n ⁻ type silicon carbide layer 2 (drift region) at a portion deeper on the drain side than p type base region 71. It is selectively provided at a depth that does not reach the interface. The first semiconductor region 91 is opposed to the p-type base region 71 closest to the current sensing unit 40 in the depth direction Z among the p-type base regions 71 constituting the MOS gate structure 70a of the main semiconductor element 10, and It contacts the p-type base region 71 (FIG. 16). The first semiconductor region 91 is opposed to the p-type base coupling portion 71c in the depth direction Z and is in contact with the p-type base coupling portion 71c (FIG. 17).

  Further, it is assumed that the second overvoltage protection unit 90 is arranged in a substantially concentric circle surrounding the current sensing unit 40 as described above. Although not shown, in this case, the first semiconductor region 91 is a plurality of p-type base regions adjacent to each other in the second direction Y among the p-type base regions 71 constituting the MOS gate structure 70 a of the main semiconductor element 10. 71 may be disposed at a position facing the depth direction Z.

The size of the current sense unit 40 is significantly smaller than that of the main semiconductor element 10, and normally, the current sense unit 40 is more likely to be overvoltage or surge than the main semiconductor element 10. For this reason, the breakdown voltage of the main semiconductor element 10 is made lower than the breakdown voltage of the current sensing unit 40 in the portion where the first semiconductor region 91 is provided. As a result, the main semiconductor element 10 has a structure that easily absorbs overvoltage at the portion where the first semiconductor region 91 is provided, so that it is possible to suppress the overvoltage from being applied to the current sensing unit 40. The conductivity type (n-type, p-type) of the first semiconductor region 91 can be variously changed based on design conditions. When n-type first semiconductor region 91 is arranged, the impurity concentration of first semiconductor region 91 is made higher than the impurity concentration of the drift region (n ⁻ type silicon carbide layer 2).

  When the n-type first semiconductor region 91 is disposed, the extension of the depletion layer extending from the pn junction between the p-type base region 71 and the first semiconductor region 91 to the drain side is suppressed. For this reason, the breakdown voltage of the main semiconductor element 10 in the portion where the first semiconductor region 91 is provided is lowered. When the p-type first semiconductor region 91 is arranged, the pn junction between the first semiconductor region 91 and the drift region is located deeper on the drain side than the pn junction between the p-type base region 71 and the drift region. Is formed. For this reason, the electric field is easily concentrated on the pn junction between the first semiconductor region 91 and the drift region, and the breakdown voltage of the main semiconductor element 10 in the portion where the first semiconductor region 91 is provided is lowered. In this manner, the breakdown voltage of the main semiconductor element 10 in the portion where the first semiconductor region 91 is provided can be made lower than the breakdown voltage of the current sensing unit 40 regardless of the conductivity type of the first semiconductor region 91.

  Further, the second semiconductor region 92 may be selectively provided in the first semiconductor region 91 so as to be in contact with the p-type base region 71. The conductivity type (n-type, p-type) of the second semiconductor region (third semiconductor region) 92 can be variously changed based on design conditions. For example, the second semiconductor region 92 may be a semiconductor region having the same conductivity type as that of the first semiconductor region 91 and having a different impurity concentration from that of the first semiconductor region 91. The second semiconductor region 92 may have a conductivity type different from that of the first semiconductor region 91. It suffices if the main semiconductor element 10 has a structure that easily absorbs overvoltage at the portion where the first semiconductor region 91 is provided, and the design type depends on the conductivity type of the first semiconductor region 91 and whether or not the second semiconductor region 92 is provided. Various changes can be made based on this. For example, when the second overvoltage protection unit 90 is configured only by the n-type first semiconductor region 91, the structure that absorbs the overvoltage is the easiest.

  In addition, when the second overvoltage protection unit 90 is configured by the first and second semiconductor regions 91 and 92 having different conductivity types, the depletion layer extending in the source side in the first and second semiconductor regions 91 and 92 is accelerated. The speed of absorbing overvoltage is increased. For this reason, breakdown of the main semiconductor element 10 at the portion where the second overvoltage protection unit 90 is provided can be accelerated. When the n-type second semiconductor region 92 is disposed inside the p-type first semiconductor region 91, the speed t2 of absorbing the overvoltage is determined by the thickness t1 of the second semiconductor region 92. When the p-type second semiconductor region 92 is disposed inside the n-type first semiconductor region 91, the overvoltage is absorbed by the portion t <b> 2 sandwiched between the drift region and the second semiconductor region 92 in the first semiconductor region 91. The speed to do is decided.

  The first and second semiconductor regions 91 and 92 can be formed by ion implantation. For this reason, in the manufacturing method of the semiconductor device according to the first embodiment described above, the second overvoltage protection unit 90 can be easily disposed only by adding one ion implantation step. The ion implantation process for forming the first and second semiconductor regions 91 and 92 may be performed at any timing at which the normal ion implantation process can be performed as long as the ion implantation acceleration voltage is appropriately set. For example, the acceleration voltage for ion implantation is set so that the first and second semiconductor regions 91 and 92 are formed only at a predetermined position deeper than the p-type base region 71 from the front surface of the base, thereby forming the p-type base region. Even after 71 is formed, the first and second semiconductor regions 91 and 92 can be formed.

  The first and second semiconductor regions 91 and 92 may be formed simultaneously with other semiconductor regions having the same ion implantation conditions (conductivity type, depth, impurity concentration). The ion implantation process for forming the first and second semiconductor regions 91 and 92 may be multistage ion implantation (multiple ion implantations with different acceleration voltages and doses). Although not shown, the planar shapes of the first and second semiconductor regions 91 and 92 can be variously changed, and may be, for example, a substantially rectangular shape, a triangular shape, or a circular shape.

  FIG. 18 is a cross-sectional view illustrating another example of the structure of the semiconductor device according to the fourth embodiment. As shown in FIG. 18, immediately below the gate pad 19, the anode pad 54, and the cathode pad 55, a semiconductor region that constitutes the MOS gate structure 70a may be disposed as an invalid region. In this case, the MOS gate structure portion 70a of the main semiconductor element 10 is disposed so as to surround the periphery of the MOS gate structure portion 70b of the current sense portion 40. The arrangement of the first semiconductor region 91 is as described above. The source pad 12 is arranged in a planar layout surrounding only the periphery of the OC pad 48. The electrode pad other than the OC pad 48 may be surrounded by the source pad 12 at a portion different from the OC pad 48.

  As described above, according to the fourth embodiment, the same effects as in the first to third embodiments can be obtained. According to the fourth embodiment, since the overvoltage can be absorbed by the first and second semiconductor regions provided in the portion adjacent to the current sensing portion of the main semiconductor element, the current sensing portion is protected from the overvoltage. be able to.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in each of the above-described embodiments, a plurality of electrode pads other than the source pad are arranged, but the reliability of the semiconductor device can be improved even in a configuration in which one electrode pad is arranged in addition to the source pad. Can do. Although the case where the main semiconductor element is a planar gate type MOSFET has been described as an example, semiconductor devices having various element structures such as bipolar transistors, IGBTs, and trench gate type semiconductor devices can be used as the main semiconductor element. The semiconductor element disposed on the same semiconductor chip as the main semiconductor element is not limited to the circuit unit for protecting and controlling the main semiconductor element, and can be variously changed. Various dimensions and impurity concentrations are set in accordance with required specifications. The present invention also has the same effect in a semiconductor device using another wide band gap semiconductor such as gallium nitride (GaN) or a semiconductor device using silicon. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a semiconductor device used as a switching device, and are particularly suitable for a semiconductor device using silicon carbide.

1 n ⁺ type silicon carbide substrate 2 n ⁻ type silicon carbide layer 3, 4a, 41, 42, 61, 62, 71 p type base region 4 p type silicon carbide layer 5, 43, 63, 72 n ⁺ type source region 6 , 44, 64, 73 p ⁺ -type contact region 7, 45, 65, 74 n-type JFET region 8, 46, 66, 75 Gate insulating film 9, 47, 67, 76 Gate electrode 47a Part of gate electrode 10 Main semiconductor Element 11, 77 Interlayer insulating film 12 Source electrode (source pad)
DESCRIPTION OF SYMBOLS 13 Plating film 14 Solder film 15 Terminal pin 16,17 Protective film 18 Back surface electrode 19 Gate pad 20 Gate pad part 21,23 Titanium nitride film 22,24 Titanium film 25 Aluminum film 30,90 Overvoltage protective part 31,51 P-type anode Region 32 Anode electrode (OV pad)
33, 53 pn junction 40 Current sensing part 48 Source electrode (OC pad)
49 Sense resistor 50 Temperature sensing part 52 N-type cathode region 54 Anode electrode (anode pad)
55 Cathode electrode (cathode pad)
60 arithmetic circuit part 68 source electrode 69 arithmetic part pad 70a, 70b MOS gate structure part 70c One p-type base region extending in a stripe shape near the current sense part of the part that becomes the MOS gate structure part of the main semiconductor element 78 oxide film 80 diode 81 p-type polysilicon layer 82 n-type polysilicon layer 91, 92 n-type or p-type semiconductor region constituting an overvoltage protection unit 100 silicon carbide substrate 100a to 100d side of silicon carbide substrate 101 active region 102 Edge termination region 103 Part of active region sandwiched between source pads L1, L2 Channel length t1, t2 Thickness of semiconductor region constituting overvoltage protection unit x1 Distance between adjacent electrode pads x2, x3 MOS gate structure Pitch of

Claims (17)

A plurality of semiconductor elements arranged on the same semiconductor substrate made of a semiconductor having a wider band gap than silicon;
A plurality of electrode pads disposed in a predetermined planar layout on the front surface of the semiconductor substrate and electrically connected to the plurality of semiconductor elements,
With
A semiconductor device, wherein terminal pins for taking out the potential of the electrode pads to the outside are solder-bonded to all of the electrode pads, respectively, through a plating film. The plurality of semiconductor elements;
A first semiconductor element performing a main operation;
The semiconductor device according to claim 1, comprising: one or more second semiconductor elements that protect or control the first semiconductor element.   3. The semiconductor device according to claim 2, wherein the semiconductor device has a planar layout in which the electrode pads electrically connected to each of the plurality of second semiconductor elements are arranged in a central portion of an active region through which a main current flows. Two or more of the second semiconductor elements are arranged,
4. The semiconductor device according to claim 2, wherein the semiconductor device has a planar layout in which the electrode pads electrically connected to each of the two or more second semiconductor elements are arranged in a line in a straight line. 5. Two or more of the second semiconductor elements are arranged,
A planar layout in which the electrode pads electrically connected to each of the two or more second semiconductor elements are arranged in two portions with the electrode pads electrically connected to the first semiconductor elements in between; The semiconductor device according to claim 2, further comprising: The second semiconductor element is:
A first overvoltage protection unit protecting the first semiconductor element from overvoltage;
A current sensing unit for detecting a current flowing in the first semiconductor element;
A temperature sensing unit for detecting a temperature of the first semiconductor element;
The semiconductor device according to claim 2, wherein the semiconductor device is an arithmetic circuit unit that controls the first semiconductor element. The first semiconductor element includes:
A first semiconductor region of a second conductivity type provided on the front surface side of the semiconductor substrate of the first conductivity type;
A second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region;
A gate insulating film provided in contact with a region of the first semiconductor region between the second semiconductor region and the semiconductor substrate;
A gate electrode provided on the opposite side of the first semiconductor region across the gate insulating film;
A first electrode in contact with the first semiconductor region and the second semiconductor region;
A second electrode in contact with the back surface of the semiconductor substrate,
The semiconductor device according to claim 2, wherein the first electrode is the electrode pad that is electrically connected to the first semiconductor element.   The semiconductor device according to claim 1, wherein the semiconductor having a wider band gap than silicon is silicon carbide.   7. The semiconductor device according to claim 6, wherein the element structure of the first semiconductor element and the element structure of the second semiconductor element to be the current sensing portion are arranged at a predetermined pitch.   10. The semiconductor device according to claim 9, wherein an element structure of the second semiconductor element serving as the current sensing portion is configured by a part of the element structure of the first semiconductor element. The element structure of the first semiconductor element is an insulated gate structure,
The element structure of the second semiconductor element serving as the current sensing portion is an insulated gate structure,
The channel length of the element structure of the second semiconductor element serving as the current sensing part is the same gate threshold voltage as the element structure of the second semiconductor element serving as the current sensing part and the element structure of the first semiconductor element. The semiconductor device according to claim 9, wherein the semiconductor device is set as follows. The first semiconductor element includes:
A first semiconductor region of a second conductivity type provided on the front surface side of the semiconductor substrate of the first conductivity type;
A second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region;
A gate insulating film provided in contact with a region of the first semiconductor region between the second semiconductor region and the semiconductor substrate;
A gate electrode provided on the opposite side of the first semiconductor region across the gate insulating film;
A first electrode in contact with the first semiconductor region and the second semiconductor region;
A second electrode in contact with the back surface of the semiconductor substrate,
The semiconductor device according to claim 9, wherein the first electrode is the electrode pad electrically connected to the first semiconductor element.   The first semiconductor region and the second semiconductor region include the electrode pad electrically connected to the first semiconductor element, and the electrode pad electrically connected to each of the plurality of second semiconductor elements, The semiconductor device according to claim 12, wherein the semiconductor device is arranged in a predetermined layout opposite to each other in the depth direction.   The current sensing portion is configured by a portion of the first semiconductor region and the second semiconductor region facing the electrode pad that is electrically connected to the second semiconductor element serving as the current sensing portion in the depth direction. The semiconductor device according to claim 13. The first semiconductor element includes:
A third semiconductor region that is selectively provided at a position deeper than the first semiconductor region from the front surface of the semiconductor substrate and is in contact with the first semiconductor region;
The semiconductor device according to claim 14, wherein the third semiconductor region is disposed adjacent to a portion of the first semiconductor region that becomes the current sensing portion.   16. The semiconductor device according to claim 15, wherein a fourth semiconductor region having a conductivity type different from that of the third semiconductor region is selectively provided inside the third semiconductor region. Manufacturing of a semiconductor device comprising a plurality of semiconductor elements arranged on the same semiconductor substrate made of a semiconductor having a wider bandgap than silicon, and a plurality of electrode pads electrically connected to the plurality of semiconductor elements, respectively. A method,
Forming each of the plurality of semiconductor element element structures on the front surface side of the semiconductor substrate;
Forming a metal film in contact with a plurality of contact regions of the element structure on the front surface of the semiconductor substrate;
Selectively removing the metal film and disposing a plurality of the electrode pads electrically connected to the plurality of semiconductor elements on a front surface of the semiconductor substrate in a predetermined planar layout; and
A step of solder-bonding terminal pins for taking out the potential of the electrode pads to the outside via plating films on all the electrode pads;
A method for manufacturing a semiconductor device, comprising:

Images