JP2015106352A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device capable of outputting a functional block signal and an internal signal by multiplexing the functional block signal with the internal signal even if strict timing restrictions are imposed on a rear stage.SOLUTION: A clock multiplication unit 104 multiplies a clock from a clock source 200. An output switch unit (A) 103-1, an output switch unit (B) 103-2, ..., and an output switch unit (C) 103-3 each switch over between a functional block signal and an internal signal and outputs either the functional block signal or the internal signal. An output control unit 105 controls the output switch unit (A) 103-1, the output switch unit (B) 103-2, ..., and the output switch unit (C) 103-3 to switch over between the functional block signal and the internal signal on the basis of the clock from the clock multiplication unit 104.

Description

  The present invention relates to a semiconductor device that outputs a function block signal, which is an output originally intended for a circuit, and an internal signal indicating a state in the circuit.

  In order to output debug information of a semiconductor device, for example, there is a device described in Patent Document 1 as a configuration for outputting an internal signal without providing an output port dedicated for debugging. This device has an output control unit that switches an output signal from a functional block in the device and an internal signal for collecting debug information, and a plurality of output ports from a single output port by switching control of the output control unit. A signal is output. That is, in this apparatus, the rising edge and falling edge of the clock are used as a method of superimposing the functional block signal and the internal signal. By controlling the function block signal to be output at the rising edge of the clock and to output the internal signal at the falling edge, the function block signal and the internal state signal are superimposed on one output port.

JP 2012-3292 A

  However, in the conventional semiconductor device, the function block signal and the internal signal are superimposed using the rising and falling edges of the clock, and the duty ratio of the clock is generally set to 1: 1. Output time is half of the clock cycle, so if the timing constraints are severe, such as the sum of the setup time and hold time of the subsequent device that processes using the functional block signal is longer than the half cycle of the clock, There was a problem that the block signal output could not be correctly transmitted to the subsequent device.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device that can multiplex and output a function block signal and an internal signal even when timing restrictions at the later stage are severe. .

  A semiconductor device according to the present invention includes an output switching unit that switches and outputs a function block signal that is an output signal of a circuit constituting the semiconductor device and an internal signal that indicates an internal state in the circuit, and a clock from a clock source. A clock multiplying unit that multiplies and an output control unit that performs switching control of the function block signal and the internal signal in the output switching unit using the multiplied clock.

  In the semiconductor device according to the present invention, the clock is multiplied and the switching of the function block signal and the internal signal is performed using the multiplied clock. Multiplexed signals can be output.

1 is a configuration diagram showing a semiconductor device according to a first embodiment of the present invention. It is explanatory drawing which shows the relationship between the clock and signal output of the semiconductor device by Embodiment 1 of this invention. It is a block diagram which shows the semiconductor device by Embodiment 2 of this invention. It is a block diagram which shows the semiconductor device by Embodiment 3 of this invention. It is explanatory drawing which shows the relationship between the clock and signal output of the semiconductor device by Embodiment 3 of this invention. It is explanatory drawing which shows the relationship between the clock and signal output of the other example of the semiconductor device by Embodiment 3 of this invention. It is a block diagram which shows the semiconductor device by Embodiment 4 of this invention. It is explanatory drawing which shows the relationship between the clock and signal output of the semiconductor device by Embodiment 4 of this invention.

Embodiment 1 FIG.
1 is a block diagram showing a semiconductor device according to a first embodiment of the present invention.
The semiconductor device illustrated in FIG. 1 includes a semiconductor circuit 100, a clock source 200, a subsequent device 201, and an internal information acquisition device 202. The semiconductor circuit 100 is a semiconductor integrated circuit such as an FPGA, for example, a functional block (A) 101-1, a functional block (B) 101-2, ..., a functional block (C) 101-3, an internal bus 102, and an output switching unit. (A) 103-1, an output switching unit (B) 103-2, ..., an output switching unit (C) 103-3, a clock multiplication unit 104, an output control unit 105, and output ports 106-1 to 106-3. ing.

  The functional block (A) 101-1, the functional block (B) 101-2,..., The functional block (C) 101-3 perform various processes in synchronization with the clock supplied from the clock source 200, respectively. Are output to the output switching unit (A) 103-1, the output switching unit (B) 103-2,..., And the output switching unit (C) 103-3. The internal bus 102 includes these functional block (A) 101-1, functional block (B) 101-2, ..., functional block (C) 101-3, output switching unit (A) 103-1, output switching unit ( B) 103-2,..., An output switching unit (C) 103-3, and an output control unit 105 are connected to each other. The output switching unit (A) 103-1, the output switching unit (B) 103-2,..., And the output switching unit (C) 103-3 are each functional block (A) 101 in accordance with an instruction from the output control unit 105. −1, the function block (B) 101-2,..., The function block (C) 101-3 are output as they are, or any one of the function blocks (A) 101-1 and the function block via the internal bus 102. (B) 101-2,... Is a switching unit for selecting the output signal of the functional block (C) 101-3 and outputting it to the output ports 106-1 to 106-3.

  The clock multiplication unit 104 is a processing unit that receives a clock from the clock source 200 and multiplies it. The output control unit 105 uses the clock multiplied by the clock multiplication unit 104 to output each output switching unit (A) 103-1, output switching unit (B) 103-2, ..., output switching unit (C) 103-. 3 is a control unit that performs switching control in FIG. The output ports 106-1 to 106-3 output the outputs of the output switching unit (A) 103-1, the output switching unit (B) 103-2, ..., the output switching unit (C) 103-3 to the outside, respectively. This is a port of the semiconductor circuit 100.

  The clock source 200 is a clock generation unit that supplies an operation clock to the semiconductor circuit 100. The latter-stage device 201 is a device that performs processing based on the output signal of the semiconductor circuit 100. The internal information acquisition device 202 is a device that collects internal signals output from the semiconductor circuit 100 in order to perform processing such as debugging.

  The output from the functional block (A) 101-1 is not limited to the connection to the output switching unit (A) 103-1, and the output from the functional block (A) 101-1 is not limited to one. . The same applies to the functional block (B) 101-2 and the functional block (C) 101-3. In FIG. 1, the post-stage device 201 and the internal information acquisition apparatus 202 are described as one, but these may be different devices or apparatuses for each of the output ports 106-1 to 106-3. .

  Next, the operation of the semiconductor device of the first embodiment will be described. The clock multiplication unit 104 multiplies the operation clock from the clock source 110 by a predetermined multiplication number and supplies it to the output control unit 105. The output control unit 105 controls which of the function block signal and the internal signal is output by distributing the cycle of the multiplied clock based on the multiplied clock. The function block signal is an output signal originally intended for the semiconductor circuit 100, and the internal signal is a function block (A) 101-1, a function block (B) 101-2,. C) An output signal of 101-3, which means a signal that is not originally intended for use. The output control unit 105 instructs the result of the output control to the output switching unit (A) 103-1, the output switching unit (B) 103-2, ..., the output switching unit (C) 103-3. The output switching unit (A) 103-1, the output switching unit (B) 103-2,..., The output switching unit (C) 103-3 receive an instruction from the output control unit 105, and receive a function block signal and an internal signal. Are output to the output ports 106-1 to 106-3.

  FIG. 2 shows clocks and outputs used in the first embodiment. FIG. 2 shows an input clock 300, a multiplied clock 301, and an output value 302 from the output port 106-1. In FIG. 2, as an example, the clock multiplication number is set to 5, and among the multiplied five clock cycles, three cycles are assigned to the output of the function block signal, one cycle is assigned to the internal signal 1, and one cycle is assigned to the internal signal 2. The output time ratio of the block signal, the internal signal 1 and the internal signal 2 is 3: 1: 1. For example, the internal signal 1 is an output from the functional block (B) 101-2, and the internal signal 2 is an output from the functional block (C) 101-3. Note that the clock multiplication number and the output time ratio are values set in consideration of the timing constraints of the post-stage device 201, and may be values other than those shown here.

As indicated by the output value 302, the operation when a plurality of internal signals are output from one port is as follows, for example.
The functional block signal is directly output from the functional block (A) 101-1 to the output switching unit (A) 103-1.
The function block (B) 101-2 directly outputs another function block signal B to the output switching unit (B) 103-2, and also outputs the internal signal 1 via the internal bus 102. (A) is output to 103-1.
In addition to outputting another function block signal C directly to the output switching unit (C) 103-3, the function block (C) 101-3 outputs the internal signal 2 via the internal bus 102. The data is output to the switching unit (A) 103-1.
In response to an instruction from the output control unit 105, the output switching unit (A) receives a function block signal from the function block (A) 101-1, an internal signal 1 from the function block (B) 101-2, The internal signal 2 from the functional block (C) 101-3 is output in a time division manner.

  As described above, in the first embodiment, the function block signal and the internal signal can be superimposed even when the timing restrictions of the semiconductor circuit 100 and the subsequent device 201 are severe, and a plurality of internal signals are simultaneously output from one port. Therefore, in addition to miniaturization of the semiconductor circuit 100, debugging of the semiconductor circuit 100 and the substrate / system including the semiconductor circuit 100 can be accelerated.

  Note that although the example in which the clock multiplication unit 104 is provided in the semiconductor circuit 100 is described in Embodiment 1, the clock multiplication unit 104 may be provided outside the semiconductor circuit 100.

  As described above, according to the semiconductor device of the first embodiment, output switching is performed by switching between a function block signal that is an output signal of a circuit that constitutes the semiconductor device and an internal signal that indicates an internal state in the circuit. Unit, a clock multiplying unit that multiplies the clock from the clock source, and an output control unit that performs switching control of the function block signal and the internal signal in the output switching unit using the multiplied clock. Even when the timing constraint is severe, the function block signal and the internal signal can be multiplexed and output, and the output of a plurality of types of internal signals can be supported.

Embodiment 2. FIG.
In the first embodiment, the ratio between the multiplication number in the clock multiplication unit 104 and the clock cycle distribution in the output control unit 105 is set to a predetermined value. However, in addition to the ratio between the clock multiplication number and the clock cycle distribution, an internal signal to be output is output. This type may be set from the outside, which will be described below as a second embodiment.

FIG. 3 is a configuration diagram showing the semiconductor device of the second embodiment.
The semiconductor device illustrated in FIG. 3 includes a semiconductor circuit 100a, a clock source 200, a post-stage device 201, an internal information acquisition device 202, and an output setting unit 203. The semiconductor circuit 100a is configured in the first embodiment shown in FIG. 1 except that the setting of the output setting unit 203 is input via the input port 107 and the output control unit 105a performs control according to the setting input. It is the same. The clock source 200, the subsequent device 201, and the internal information acquisition device 202 are the same as those in the first embodiment. The output setting unit 203 is provided outside the semiconductor circuit 100a, and designates at least one of the clock multiplication number, the clock cycle distribution ratio assigned to the function block signal and the internal signal, and the type of the internal signal to be output. Is performed on the output control unit 105a.

  Next, the operation of the semiconductor device of the second embodiment will be described. The output setting unit 203 sets the clock multiplication number, the clock cycle distribution ratio, and the type of internal signal to be output to the output control unit 105a. In response to this setting, the output control unit 105 a instructs the clock multiplication unit 104 to generate a clock for performing output switching based on the setting. In response to the instruction from the output control unit 105a, the clock multiplication unit 104 multiplies the input clock from the clock source 200 and supplies it to the output control unit 105a. The output control unit 105a controls the signal to be output using the multiplied clock, the clock cycle distribution ratio set by the output setting unit 203, and the type of internal signal to be output, and the output switching unit (A) 103- 1. Instruct the output switching unit (B) 103-2, ..., the output switching unit (C) 103-3. In response to this instruction, the output switching unit (A) 103-1, the output switching unit (B) 103-2,..., The output switching unit (C) 103-3 switch the function block signal and the internal signal to output ports. It outputs to 106-1.

  As described above, in the second embodiment, even when the device that acquires the internal signal changes in the middle and the timing constraint becomes severe, the setting value is changed so as to satisfy the timing constraint. Efficiency reduction can be prevented. Also, since the types of internal signals to be output can be changed each time, the types of internal signals that can be output to the outside are increased compared to the first embodiment, and debugging can be performed efficiently.

  As described above, according to the semiconductor device of the second embodiment, at least one of the clock multiplication number, the clock cycle distribution ratio assigned to the function block signal and the internal signal, and the type of the internal signal to be output is designated. Since the output control unit performs switching control of the output switching unit based on the information specified by the output setting unit, even when the situation of outputting the internal signal changes, the output control unit can easily Can respond.

Embodiment 3 FIG.
In the first embodiment and the second embodiment, the internal signal is simply multiplexed on the output signal. Instead, a signal is generated based on the value of the internal signal for some output ports. May be output, which will be described below as a third embodiment.

FIG. 4 is a configuration diagram showing the semiconductor device of the third embodiment.
The illustrated semiconductor device includes a semiconductor circuit 100b, a clock source 200, a post-stage device 201, and an internal information acquisition device 202. The clock source 200 to the internal information acquisition device 202 are the same as those in the first and second embodiments. A signal generation unit 108 is provided in the semiconductor circuit 100b. The signal generation unit 108 is a processing unit that generates a signal based on the output timing of the internal signal. Further, the output control unit 105b corresponds to the signal generation in the signal generation unit 108, the output switching unit (A) 103-1, the output switching unit (B) 103-2, ..., the output switching unit (C) 103-. 3 switching control is performed.

  Next, the operation of the semiconductor device of the third embodiment will be described with respect to parts different from those of the first and second embodiments. The output control unit 105b instructs the signal generation unit 108 to output a pulse in accordance with the timing of outputting the internal signal. The signal generation unit 108 receives the instruction, generates a pulse, and outputs the pulse to the output switching unit (B) 103-2 and the output switching unit (C) 103-3. The output signal in this case is shown in FIG.

  The output value 302 shown in FIG. 5 is a signal from the output port 106-1, the output value 303 is a signal from the output port 106-2, and the output value 304 is a signal from the output port 106-3. The functional block signal, the internal signal 1 and the internal signal 2 are all multiplexed on the output value 302, and a pulse in accordance with the output timing of the internal signal 1 is output as the output value 303. Further, a pulse that matches the output timing of the internal signal 2 is output as an output value 304. Here, for example, the internal signals 1 and 2 are both signals of the functional block (A) 101-1, and at the timing when each internal signal is input to the signal generation unit 108 via the internal bus 102, the signal generation unit At 108, a pulse is generated and sent to the output switching unit (B) 103-2 and the output switching unit (C) 103-3. The output value 303 is output from the output switching unit (B) 103-2 via the output port 106-2, and the output value 304 is output from the output switching unit (C) 103-3 via the output port 106-3. Is done.

  In the above description, the output value 303 and the output value 304 are pulses matched to the output timings of the internal signal 1 and the internal signal 2, respectively. It is good also as a pulse to show. The output waveform in this case is shown in FIG. A pulse is output to the output value 305 at the timing when the value of the internal signal 1 changes, and a pulse is output to the output value 306 at the timing when the value of the internal signal 2 changes. Note that the pulse output in this case is performed by the signal generator 108 holding the values of the internal signal 1 and the internal signal 2 and determining whether each value is different from the previous value.

  As described above, in the third embodiment, the internal information acquisition device 202 needs to transmit the internal signal output timing or the internal signal change timing to the internal information acquisition device 202 that acquires the internal signal. The internal information acquisition device 202 can acquire internal signals for a long period of time by reducing the number of samplings.

  As described above, according to the semiconductor device of the third embodiment, the signal generation unit that outputs the signal indicating the output timing of the internal signal is provided, and the output control unit outputs the output switching unit according to the output of the signal generation unit Since the switching control is performed, it is possible to reduce the load on the device that acquires the internal signal.

  Further, according to the semiconductor device of the third embodiment, since the signal generation unit outputs a signal indicating the output timing when the internal signal changes, the load on the device that acquires the internal signal is further reduced. be able to.

Embodiment 4 FIG.
In the first to third embodiments, a clock that has been multiplied or changed in phase based on the input clock is used, but without using these, the duty ratio is shifted from 1: 1 as the input clock, and the rising and The output signal may be switched using the lowering, which will be described below as a fourth embodiment.

FIG. 7 is a configuration diagram showing the semiconductor device of the fourth embodiment.
The illustrated semiconductor device includes a semiconductor circuit 100c, a subsequent device 201, an internal information acquisition device 202, and a clock control unit 204. The subsequent device 201 and the internal information acquisition device 202 are the same as those in the first to third embodiments. The clock control unit 204 is a clock supply unit that controls and supplies a duty ratio of an input clock to the semiconductor circuit 100c. The clock control unit 204 supplies a function block (A) 101-1 and a function block (B) 101-2. ,... Are configured to be supplied to the functional block (C) 101-3 and the output control unit 105c. The output control unit 105c adjusts the duty ratio of the clock output from the clock control unit 204 based on input information such as the transmission order and the transmission time ratio of the function block signal and the internal signal set from the outside, and Using the clock adjusted by the clock control unit 204, the output switching unit (A) 103-1, the output switching unit (B) 103-2, ..., the output switching unit (C) 103-3 are controlled to be switched. It is configured. The functional block (A) 101-1, the functional block (B) 101-2,..., The functional block (C) 101-3 and the internal bus 102 in the semiconductor circuit 100c are the same as those in the first to third embodiments. .

Next, the operation of the semiconductor device of the fourth embodiment will be described.
The transmission order and transmission time ratio of the functional block signal and the internal signal are set from the outside to the output control unit 105c. In response to these settings, the output control unit 105 c adjusts the duty ratio of the clock output from the clock control unit 204. Also, using the clock with the adjusted duty ratio, the function block signal is output at the rising edge and the internal signal is output at the falling edge. This duty ratio can be freely adjusted from the outside, and the order of function block signal output and internal signal output may be reversed. FIG. 8 shows the clock and output signal with the duty ratio adjusted with the original clock. In FIG. 8, a clock 401 after the duty ratio adjustment is generated by the clock control unit 204 with respect to the original clock input 400, which is a functional block (A) 101-1, a functional block (B) 101-2,. (C) Used for the operation of 101-3 and the output switching control of the output control unit 105c. The output 402 is a signal from the output ports 106-1 to 106-3.

  In the fourth embodiment, since the output in which the transmission time ratio of the functional block signal and the internal signal is shifted from 1: 1 can be realized with only one clock, the power consumption can be reduced.

  In the configuration shown in FIG. 7, the clock control unit 204 is provided outside the semiconductor circuit 100c, but may be provided inside the semiconductor circuit 100c.

  As described above, according to the semiconductor device of the fourth embodiment, the output switching is performed by switching the function block signal, which is the output signal of the circuit constituting the semiconductor device, and the internal signal indicating the internal state in the circuit. Unit, a clock control unit that changes the duty ratio of the input clock to the circuit, and an output control unit that performs switching control of the function block signal and the internal signal in the output switching unit using the clock with the changed duty ratio Therefore, even when the timing restrictions at the subsequent stage are severe, the function block signal and the internal signal can be multiplexed and output, and the power consumption can be reduced.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  100, 100a, 100b, 100c Semiconductor circuit, 101-1 function block (A), 101-2 function block (B), 101-3 function block (C), 102 internal bus, 103-1 output switching unit (A) , 103-2 output switching unit (B), 103-3 output switching unit (C), 104 clock multiplication unit, 105, 105a, 105b, 105c output control unit, 106-1 to 106-3 output port, 107 input port , 108 signal generation unit, 200 clock source, 201 subsequent device, 202 internal information acquisition device, 203 output setting unit, 204 clock control unit.

Claims (5)

An output switching unit that switches and outputs a function block signal that is an output signal of a circuit constituting the semiconductor device and an internal signal indicating an internal state in the circuit;
A clock multiplier for multiplying the clock from the clock source;
A semiconductor device comprising: an output control unit that performs switching control of the functional block signal and the internal signal in the output switching unit using the multiplied clock. An output setting unit for designating at least one of a clock multiplication number, a clock period distribution ratio assigned to the functional block signal and the internal signal, and a type of the internal signal to be output;
The semiconductor device according to claim 1, wherein the output control unit performs switching control of the output switching unit based on information specified by the output setting unit. A signal generation unit that outputs a signal indicating the output timing of the internal signal;
The semiconductor device according to claim 1, wherein the output control unit performs switching control of the output switching unit in accordance with an output of the signal generation unit.   4. The semiconductor device according to claim 3, wherein the signal generator outputs a signal indicating the output timing when the internal signal changes. An output switching unit that switches and outputs a function block signal that is an output signal of a circuit constituting the semiconductor device and an internal signal indicating an internal state in the circuit;
A clock control unit for changing a duty ratio of an input clock to the circuit;
A semiconductor device comprising: an output control unit that performs switching control of the functional block signal and the internal signal in the output switching unit using a clock whose duty ratio is changed.

Images