JP2014110730A - Power conversion device and control device - Google Patents

Abstract

Loss generated in a plurality of switching elements can be made uniform.
A power conversion device according to an embodiment includes a pair of legs in which two switching elements that are short-circuited to a DC power supply are connected in series, and outputs an AC voltage between the switching elements of the pair of legs. A power conversion unit, and a control unit that performs control to switch a plurality of switching elements of the power conversion unit with a predetermined switching pattern, and the control unit includes a combination of switching elements having a large loss among the plurality of switching elements. A plurality of different switching patterns are periodically switched.
[Selection] Figure 4

Description

  Embodiments described herein relate generally to a power conversion device and a control device.

  2. Description of the Related Art Conventionally, there is a power conversion device that converts electric power supplied from a DC power source into AC by a combination of ON and OFF of a plurality of switching elements. This power conversion device includes a pair of legs connected in series with two switching elements that are short-circuited to a DC power supply, and a single-phase full-bridge inverter that outputs an AC voltage between the switching elements of the pair of legs. There is.

Japanese Patent Laid-Open No. 10-337045

  However, in the above-described conventional technology, there is a case where variations occur in losses generated in a plurality of switching elements in the power conversion device. For example, when an AC voltage is output with a phase difference between the U phase and the V phase between the U phase switching leg and the V phase switching leg, the load characteristics after full-wave rectification are inductive. Depending on whether it is capacitive or capacitive, there is a bias between the loss that occurs in the two switching elements of the leg that switches in the U phase and the loss that occurs in the two switching elements of the leg that switches in the V phase. More specifically, at the time of inductive load, the minimum value of the current ripple is taken at the switching of the leading phase, and the maximum value of the current ripple is taken at the switching of the lagging phase. Loss is biased. On the other hand, at the capacitive load, the maximum value of the current ripple is taken at the switching of the leading phase and the minimum value of the current ripple is taken at the switching of the lagging phase, so the loss is biased to the two switching elements of the leg that switches at the leading phase. .

  In this way, if the loss that occurs in multiple switching elements varies, the capacity of the switching element can be increased by designing a cooler that cools the heat generated by the loss, for example, due to the design restrictions in accordance with the worst case. Since many designs are required, it is difficult to reduce the size, weight, and cost.

  In order to solve the above-described problem, the power conversion device according to the embodiment has a pair of legs in which two switching elements that are short-circuited to a DC power source are connected in series, and between the switching elements of the pair of legs. A power conversion unit that outputs an AC voltage; and a control unit that performs control to switch a plurality of switching elements of the power conversion unit with a predetermined switching pattern, wherein the control unit is a loss among the plurality of switching elements. A plurality of switching patterns having different combinations of switching elements having a large value are periodically switched.

  The control device according to the embodiment includes a plurality of legs that are connected in series with two switching elements that are short-circuited to a DC power supply, and that output an AC voltage between the switching elements of the pair of legs. These switching elements are controlled to switch with a predetermined switching pattern, and among the plurality of switching elements, a plurality of switching patterns having different combinations of switching elements having a large loss are periodically switched.

Drawing 1 is a figure which illustrates the composition of the power converter concerning an embodiment. FIG. 2 is a waveform diagram illustrating the first switching pattern. FIG. 3 is a waveform diagram illustrating the second switching pattern. FIG. 4 is a waveform diagram illustrating a case where the first switching pattern and the second switching pattern are periodically switched. FIG. 5 is a waveform diagram illustrating a third switching pattern. FIG. 6 is a waveform diagram illustrating a fourth switching pattern. FIG. 7 is a waveform diagram illustrating a case where the third switching pattern and the fourth switching pattern are periodically switched.

  Hereinafter, a power conversion device and a control device according to embodiments will be described in detail with reference to the accompanying drawings. This power conversion device converts power supplied from a DC power source into AC by a combination of ON and OFF of a plurality of switching elements. A low-loss device such as SiC (silicon carbide device) may be applied to the elements in the power converter.

  FIG. 1 is a diagram illustrating a configuration of a power conversion device 100 according to the embodiment. As shown in FIG. 1, the power conversion apparatus 100 insulates the power conversion circuit 1 that receives the DC power supply 2 and generates an AC output voltage Vo between the output terminals 121 and 122 from the primary side and the secondary side. Then, the isolation transformer 6 that converts the voltage into a desired voltage, the full-wave rectifier 7 such as a diode bridge, the voltage measuring unit 4 that measures the output voltage Vp output from the full-wave rectifier 7, and the power conversion circuit 1 are driven. A drive circuit 5 is provided. The power conversion apparatus 100 converts DC power supplied from the DC power supply 2 into AC and supplies power to the full-wave rectifier 7 and the subsequent DC load 3 via the insulating transformer 6 connected to the output terminals 121 and 122. To do. In the present embodiment, the full-wave rectifier 7 and the subsequent DC load 3 have inductive load characteristics, but it goes without saying that they may have capacitive load characteristics. . The full-wave rectifier 7 and the subsequent DC load 3 may be an AC load having inductive or capacitive load characteristics.

  The power conversion circuit 1 is a single-phase full-bridge inverter circuit, and a leg 100U (U-phase) in which two switching elements 101 and 102 that are short-circuited to a DC power supply 2 are connected in series, and two switching that are also short-circuited. A leg 100V (V phase) to which the elements 103 and 104 are connected in series is provided in parallel. In addition, the power conversion circuit 1 is connected between the switching elements 101 and 102 of the leg 100U and the output terminal 121, and is connected between the switching elements 103 and 104 of the leg 100V and the output terminal 122, and has a predetermined switching pattern. By switching the switching elements 101, 102, 103, and 104 (details will be described later), an alternating voltage is output.

  The switching elements 101, 102, 103, and 104 have a self-extinguishing capability, and are arbitrarily switched according to gate voltages Su, Sx, Sv, and Sy that apply on / off between the collector and the emitter to the gate. In addition, free-wheeling diodes 111, 112, 113, and 114 are connected to the switching elements 101, 102, 103, and 104 in antiparallel.

  The voltage measuring unit 4 detects the voltage value (output voltage Vp) output from the full-wave rectifier 7. The detected voltage value is output to the drive circuit 5. The drive circuit 5 applies the gate voltages Su, Sx, Sv, Sy in accordance with a predetermined switching pattern (details will be described later), so that the plurality of switching elements (101, 102, 103, 104) of the power conversion circuit 1 are applied. Switch. The drive circuit 5 switches the switching elements (101, 102, 103, 104) with respect to the U-phase and V-phase carrier waveforms output at a predetermined carrier frequency from a pulse generator (not shown). It is obtained by comparing with the modulation rate. In this embodiment, the case of a triangular waveform is illustrated as an example of the carrier waveform, but it goes without saying that the carrier waveform may be a sawtooth waveform.

  The drive circuit 5 holds, in an internal memory or the like, a plurality of switching patterns in which combinations of switching elements having a large loss among the plurality of switching elements (101, 102, 103, 104) are different from each other. The switching pattern is periodically switched. The drive circuit 5 may be incorporated in the power conversion device 100, or the gate voltages Su, Sx, Sv, Sy are applied to the switching elements 101, 102, 103, 104 from the outside of the power conversion device 100. The control apparatus which applies may be sufficient.

  Here, switching in a predetermined switching pattern by the drive circuit 5 will be described in detail. FIG. 2 is a waveform diagram illustrating the first switching pattern. FIG. 3 is a waveform diagram illustrating the second switching pattern. 2 and 3 exemplify the waveforms of the output voltage Vo, the output current Io, the U-phase carrier waveform WU and the V-phase carrier waveform WV, and the gate voltages Su, Sx, Sv, and Sy in order from the top.

  As shown in FIG. 2, in the first switching pattern, the drive circuit 5 switches the switching elements 101, 102, 103, and 104 of the legs 100U and 100V in a switching pattern in which the U phase advances with respect to the V phase. . In the first switching pattern, since the load characteristic of the DC load 3 is inductive, the gate voltages Su and Sx are turned on / off at the rising timing (time t11, t13) of the output voltage Vo with a small output current Io. Then, the switching elements 101 and 102 are turned on / off. Further, the gate voltages Sv and Sy are turned on / off at the falling timing (time t12, t14) of the output voltage Vo with a large output current Io, and the switching elements 103 and 104 are turned on / off. Therefore, the loss generated in the switching elements 103 and 104 that turn on / off in the V phase is larger than that in the U phase.

  As shown in FIG. 3, in the second switching pattern, the drive circuit 5 switches the switching elements 101, 102, 103, and 104 of the legs 100U and 100V in a switching pattern in which the V phase advances with respect to the U phase. . In the second switching pattern, since the load characteristic of the DC load 3 is inductive, the gate voltages Sv and Sy are turned on / off at the rising timing (time t21, t23) of the output voltage Vo with a small output current Io. Thus, the switching elements 103 and 104 are turned on / off. Further, the gate voltages Su and Sx are turned on / off at the falling timing (time t22, t24) of the output voltage Vo with a large output current Io, and the switching elements 101 and 102 are turned on / off. Therefore, the loss generated in the switching elements 101 and 102 that turn on / off in the U phase is larger than that in the V phase.

  As described above, in the first switching pattern and the second switching pattern, of the pair of legs 100U and 100V, the phase for switching the switching element of one leg and the phase for switching the switching element of the other leg Are different from each other. For example, in the first switching pattern, the phase of the leg 100U is advanced with respect to the phase of the leg 100V. For this reason, in the first switching pattern, when the load characteristic of the DC load 3 is inductive, the combination having a large loss is the switching elements 103 and 104. Further, in the second switching pattern, the phase of the leg 100V is advanced with respect to the phase of the leg 100U. For this reason, in the second switching pattern, when the load characteristic of the DC load 3 is inductive, the combination having a large loss is the switching elements 101 and 102.

  FIG. 4 is a waveform diagram illustrating a case where the first switching pattern P1 and the second switching pattern P2 are periodically switched. As shown in FIG. 4, the drive circuit 5 includes a first switching pattern P1 in which a combination with a large loss becomes the switching elements 103 and 104, and a second switching pattern P2 in which a combination with a large loss becomes the switching elements 101 and 102. By switching alternately periodically, the loss generated in the switching elements 101, 102, 103, 104 is made uniform.

  Specifically, based on the voltage value detected by the voltage measurement unit 4, the drive circuit 5 uses the first switching pattern P <b> 1 and the second switching pattern P <b> 1 based on the rising or falling timing of the AC output voltage Vo. Switching of the switching pattern P2 is performed. More specifically, the first switching pattern P1 and the second switching pattern P2 are switched at the rising timing (time t1, t2) of the output voltage Vo with a small output current Io.

  As described above, the power conversion device 100 can uniformize the loss generated in the switching elements 101, 102, 103, and 104 by periodically switching the first switching pattern P1 and the second switching pattern P2 alternately. This eliminates the design restrictions for the worst case. For this reason, the size of the cooler of the switching elements 101, 102, 103, and 104 can be reduced, and the capacity of the switching elements 101, 102, 103, and 104 can be designed to be the same, thereby reducing size, weight, and cost. realizable.

  In the embodiment, the case of an inductive load is illustrated. However, in the case of a capacitive load, only the bias of loss is reversed, and the first switching pattern P1 and the second switching pattern P2 are set to be periodic. By switching automatically, the loss can be made uniform in the same manner. Further, the periodic switching between the first switching pattern P1 and the second switching pattern P2 illustrated in FIG. 4 is merely an example, and the first switching pattern P1 and the second switching pattern P2 are periodically switched. If it is, it will not be limited to the structure which switches the 1st switching pattern P1 and the 2nd switching pattern P2 for every period of AC output voltage Vo. For example, when switching from .fwdarw.P1.fwdarw.P1.fwdarw.P2.fwdarw.P2.fwdarw..fwdarw..fwdarw.P1.fwdarw.P2.fwdarw..fwdarw.P1.fwdarw.P1.fwdarw.P2.fwdarw.P2...

(Modification)
Below, the modification of the switching pattern in the drive circuit 5 is demonstrated. FIG. 5 is a waveform diagram illustrating a third switching pattern. FIG. 6 is a waveform diagram illustrating a fourth switching pattern. 5 and 6 illustrate the waveforms of the output voltage Vo, the output current Io, the U-phase carrier waveform WU and the V-phase carrier waveform WV, and the gate voltages Su, Sx, Sv, and Sy in order from the top.

  As shown in FIG. 5, in the third switching pattern, the drive circuit 5 uses the V-phase carrier waveform WV, the U-phase carrier waveform WU, and the modulation rate to generate the gate voltage Su, at the timings t31, t32, t33, and t34. Sx, Sv, and Sy are turned on / off. Specifically, the drive circuit 5 turns on the zero voltage of the output voltage Vo, turns on the gate voltages Su and Sv of the upper arm switching elements 101 and 103, and turns on the gate voltages Sx and Sy of the lower arm switching elements 102 and 104. Is turned off, and the switching elements 101 and 103 of the upper arm are turned on and the switching elements 102 and 104 of the lower arm are turned off. In this third switching pattern, the conduction period of the switching elements 101 and 103 of the upper arm is long and the conduction period of the switching elements 102 and 104 of the lower arm is short, so that the switching element 101 of the upper arm is shorter than the lower arm. , 103 increases.

  As shown in FIG. 6, in the fourth switching pattern, the drive circuit 5 uses the V-phase carrier waveform WV, the U-phase carrier waveform WU, and the modulation rate to generate the gate voltage Su, at the timings t41, t42, t43, and t44. Sx, Sv, and Sy are turned on / off. Specifically, the drive circuit 5 turns on the zero voltage of the output voltage Vo, turns on the gate voltages Sx and Sy of the lower arm switching elements 102 and 104, and sets the gate voltages Su and Sv of the upper arm switching elements 101 and 103. Is turned off, the switching elements 102 and 104 of the lower arm are turned on, and the switching elements 101 and 103 of the upper arm are turned off. In the fourth switching pattern, the conduction period of the switching elements 102 and 104 of the lower arm is long and the conduction period of the switching elements 101 and 103 of the upper arm is short. Therefore, the switching element 102 of the lower arm is shorter than the upper arm. , 104 is increased.

  FIG. 7 is a waveform diagram illustrating a case where the third switching pattern P3 and the fourth switching pattern P4 are periodically switched. As shown in FIG. 7, the drive circuit 5 includes a third switching pattern P3 in which the combination with large loss becomes the switching elements 101 and 103, and a fourth switching pattern P4 in which the combination with large loss becomes the switching elements 102 and 104. By switching alternately periodically, the loss generated in the switching elements 101, 102, 103, 104 is made uniform.

  Specifically, the drive circuit 5 becomes a peak (maximum) or a valley (minimum) of the V-phase carrier waveform WV and the U-phase carrier waveform WU based on the V-phase carrier waveform WV and the U-phase carrier waveform WU. Switching between the third switching pattern P3 and the fourth switching pattern P4 is performed based on the timing (time t3, t4). In the illustrated example, at the peak of the V-phase carrier waveform WV (time t3, t4), the modulation rate is switched to switch the third switching pattern P3 and the fourth switching pattern P4. Thus, in the case of switching between the third switching pattern P3 and the fourth switching pattern P4, it is not necessary to detect the output voltage Vo, and therefore it is not necessary to include the voltage measuring unit 4.

  As described above, the power conversion device 100 can uniformize the loss generated in the switching elements 101, 102, 103, and 104 by periodically alternately switching the third switching pattern P3 and the fourth switching pattern P4. This eliminates the design restrictions for the worst case. For this reason, the size of the cooler of the switching elements 101, 102, 103, and 104 can be reduced, and the capacity of the switching elements 101, 102, 103, and 104 can be designed to be the same, thereby reducing size, weight, and cost. realizable.

  In the embodiment, the case of an inductive load is illustrated. However, in the case of a capacitive load, only the bias of loss is reversed, and the third switching pattern P3 and the fourth switching pattern P4 are set to be periodic. By switching automatically, the loss can be made uniform in the same manner. In addition, the periodic switching of the third switching pattern P3 and the fourth switching pattern P4 illustrated in FIG. 7 is merely an example, and the third switching pattern P3 and the fourth switching pattern P4 are periodically switched. If it is, it will not be limited to the structure which switches the 1st switching pattern P1 and the 2nd switching pattern P2 for every period of AC output voltage Vo. For example, when switching from .fwdarw.P3.fwdarw.P3.fwdarw.P4.fwdarw.P4.fwdarw..fwdarw..fwdarw.P3.fwdarw.P4.fwdarw..fwdarw.P3.fwdarw.P3.fwdarw.P4.fwdarw.P4.fwdarw., Etc., there may be various laws of the cycle.

  Further, the drive circuit 5 not only switches the first switching pattern P1 and the second switching pattern P2, and switches the third switching pattern P3 and the fourth switching pattern P4, but also the first switching pattern P1, the second switching pattern P4, and the like. Needless to say, the second switching pattern P2, the third switching pattern P3, and the fourth switching pattern P4 may be switched. When switching the first switching pattern P1, the second switching pattern P2, the third switching pattern P3, and the fourth switching pattern P4, the switching of the first switching pattern P1 and the second switching pattern P2 is , Based on the rise or fall timing of the AC output voltage Vo. The switching between the third switching pattern P3 and the fourth switching pattern P4 is performed based on the timing at which the carrier waveform has a peak (maximum) or a valley (minimum). In addition, switching between the first switching pattern P1 and the second switching pattern P2, and the third switching pattern P3 and the fourth switching pattern P4 is changed from the first switching pattern P1 to the fourth switching pattern P4. The second switching pattern P2 is switched to the third switching pattern P3, or vice versa.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined.

  DESCRIPTION OF SYMBOLS 100 ... Power converter device, 1 ... Power converter circuit, 2 ... DC power supply, 3 ... DC load, 4 ... Voltage measurement part, 5 ... Drive circuit, 6 ... Insulation transformer, 7 ... Full wave rectifier, 100U, 100V ... Leg, 101-104 ... switching element, 111-114 ... freewheeling diode, 121, 122 ... output terminal, Io ... output current, P1 ... first switching pattern, P2 ... second switching pattern, P3 ... third switching pattern, P4 ... Fourth switching pattern, Su, Sx, Sv, Sy ... Gate voltage, t1-t44 ... Time, Vo, Vp ... Output voltage, WU ... U-phase carrier waveform, WV ... V-phase carrier waveform

Claims (7)

A power conversion unit that has a pair of legs connected in series with two switching elements connected in series to each other for short-circuiting a DC power supply, and that outputs an AC voltage between the switching elements of the pair of legs;
A control unit that performs control to switch a plurality of switching elements of the power conversion unit with a predetermined switching pattern;
The said control part is a power converter device which switches periodically the several switching pattern from which the combination of a switching element with a big loss among these switching elements differs mutually. The control unit is configured such that a phase for switching a switching element of one leg of the pair of legs is different from a phase for switching a switching element of the other leg, and the phase of the one leg is different from that of the other leg. Periodically switching between a first switching pattern in which the phase of the first leg advances and a second switching pattern in which the phase of the one leg advances with respect to the phase of the other leg,
The power conversion device according to claim 1. The control unit outputs a zero voltage between the switching elements of the pair of legs when the switching element of the upper arm of the pair of legs is turned on and the switching element of the lower arm is turned off; Periodically switching between the fourth switching pattern output when the switching element of the lower arm of the pair of legs is turned on and the switching element of the upper arm is turned off,
The power conversion device according to claim 1. The controller periodically switches the first switching pattern, the second switching pattern, the third switching pattern, and the fourth switching pattern;
The power converter according to claim 2 or 3. A voltage detection unit for detecting a voltage value output by the power conversion unit;
The control unit switches the switching pattern based on the rising or falling timing of the AC voltage based on the detected voltage value.
The power converter device as described in any one of Claims 1 thru | or 4. The control unit performs switching of the switching pattern based on a timing at which a carrier waveform related to a timing at which the switching element is turned on or off is maximized or minimized.
The power converter device as described in any one of Claims 1 thru | or 4.   A pair of legs in which two switching elements for short-circuiting a DC power source are connected in series are provided in parallel, and a plurality of switching elements of a power conversion unit that outputs an AC voltage from between the switching elements of the pair of legs A control device that performs switching control according to a switching pattern and periodically switches a plurality of switching patterns having different combinations of switching elements having a large loss among the plurality of switching elements.

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