JP2014059923A - Flash memory device provided with reference word line - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plurality of flash memory devices for improving efficiency of a sense amplification module of a flash memory.SOLUTION: A flash memory array block includes: N storage columns; n reference word line cell units; and one reference storage column, n being a positive integer here. Each of the reference word line cell units is arranged in each of the storage columns, and further, the reference word line cell units are connected to a reference word line and a dummy word line. The reference storage column includes: a plurality of reference bit-line cells; a reference word line and a dummy word line; and a cell connected to the reference word line among the reference bit line cells is connected to the reference bit lines. The sense amplification module compares current from one of bit lines with current from a corresponding reference bit line to generate at least one detection result.

Description

  The present invention relates to a flash memory device, and more particularly to a flash memory device having a reference word line.

  Referring to FIG. 1, FIG. 1 is a circuit diagram of a conventional flash memory device 100. The flash memory device 100 includes a reference line control circuit 110, an X decoder 120, a plurality of memory cells M11-Mm3, and a plurality of reference cells R11-Rm3. X decoder 120 is coupled to memory cells M11-Mm3 and reference cells R11-Rm3. X decoder 120 generates word line signals W1-Wm and supplies them to memory cells M11-Mm3 and reference cells R11-Rm3, respectively. Memory cells M11-Mm1, M12-Mm2, and M13-Mm3 are coupled to bit lines B1, B2, and B3, respectively, and reference cells R11-Rm1, R12-Rm2, and R13-Rm3 are coupled to reference bit lines R1, R2, and R3, respectively. Combined. The reference line control circuit 110 is coupled to the reference cells R11 to Rm3, and the sources of the reference cells R11 to Rm3 are grounded or floated by the reference control circuit 110. The flash memory device 100 compares the current from one of the bit lines B1-B3 with the current from one of the bit lines R1-R3 to generate a data output of the flash memory device 100.

  The present invention provides a plurality of flash memory devices that improve the efficiency of the sense amplifier module of the flash memory.

  The present invention provides a flash memory device comprising at least one flash memory array block and a sense amplification module. The flash memory array block includes N storage columns, N reference word line cell units, and one reference storage column. Each storage column comprises a plurality of memory cells coupled in series, each memory cell coupled to a word line and a bit line, respectively, where N is a positive integer. Each of the reference word line cell units is disposed in each of the storage columns, each reference word line cell unit is coupled to a memory cell in the corresponding storage column, and the reference word line cell unit further includes a reference word line and a dummy word line. Combined with The reference storage column is disposed adjacent to the storage column, and the reference storage column includes a plurality of reference bit line cells coupled in series, and these reference bit line cells are coupled to a word line, a reference word line, and a dummy word line. One of the reference bit line cells coupled to the reference word line is coupled to the reference bit line. The sense amplifier module compares the current from one of the bit lines with the current from the corresponding reference bit line to generate at least one detection result.

  The present invention provides another flash memory device comprising a plurality of flash memory array blocks and a sense amplification module. Each of the flash memory array blocks includes N storage columns, N reference word line cell units, and first and second reference storage columns. Each storage column comprises a plurality of memory cells coupled in series, each memory cell coupled to a word line and a bit line, respectively, where N is a positive integer. Each reference word line cell unit is disposed in each storage column, each reference word line cell is coupled to a memory cell in the corresponding storage column, and the reference word line cell unit is connected to the first and second reference word lines. Combined. The first and second reference storage columns are arranged adjacent to the storage column, and each of the first and second reference storage columns includes a plurality of reference bit line cells coupled in series, the first reference storage column The reference bit line cells in the column are respectively coupled to the word line and the first reference word line, and the reference bit line cells in the second reference storage column are respectively coupled to the word line and the second reference word line. One of the reference bit line cells of the first and second reference storage columns coupled to the first and second reference word lines is coupled to the first and second reference bit lines, respectively. The sense amplifier module compares the current from one of the bit lines and / or the corresponding first and second reference bit lines to generate at least one detection result.

  Accordingly, the present application provides at least one reference storage column that generates at least one reference current in a reference bit line. The sense amplification module generates at least one detection result by comparing the current from one of the bit lines with the current from the corresponding reference bit line. That is, the current of the reference bit line changes according to the process variation of the flash memory device. Therefore, it is not necessary to set a wide reference current range for the sense amplification module of the flash memory device disclosed in the present application.

  During the read operation of the flash memory, the read bit line current is compared with the reference value. Since the process parameters vary for different wafers, it is difficult to determine a reference value. In other words, the conventional flash memory requires a wide range of reference values.

  A flash memory device having a reference word line is provided. The flash memory device includes at least one reference storage column that generates at least one reference current in a reference bit line. The sense amplification module generates at least one detection result by comparing the current from one of the bit lines with the current from the corresponding reference bit line.

(Effect of the invention)
Since the current of the reference bit line changes according to the process variation of the flash memory device, it is not necessary to set a wide reference current range for the sense amplification module of the flash memory device disclosed in this application, and the performance of the flash memory device is improved. To do.

1 is a circuit diagram of a conventional flash memory device 100. FIG. 1 is a circuit diagram of a flash memory device 200 according to an embodiment of the present invention. FIG. 5 is a circuit diagram of a flash memory device 300 according to another embodiment of the present invention. It is a circuit diagram of a plurality of selection circuits. FIG. 6 is a block diagram of a sense amplification module 500 according to an embodiment of the present invention. 3 is a block diagram of a sense amplifier circuit 510 according to an embodiment of the present invention. FIG. FIG. 5 is a circuit diagram of a sense amplifier circuit 510 according to an embodiment of the present invention. FIG. 6 is another circuit diagram of the sense amplifier circuit 510 according to an embodiment of the present invention.

  Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

  Referring to FIG. 2, FIG. 2 is a circuit diagram of a flash memory device 200 according to an embodiment of the present invention. The flash memory device 200 includes at least one flash memory array block IO1-IOP and a sense amplification module 230. Each of the flash memory array blocks, for example, the flash memory array block IO1, includes N storage columns SC1, N reference word line cell units RWCN, and one reference storage column RSC1, where N is a positive integer ( In FIG. 2, N is equal to 1). Storage column SC1 includes a plurality of memory cells coupled in series. These memory cells are coupled to word lines ZWL0-ZWL127, respectively, and these memory cells are also coupled to bit lines BL0-BL127, respectively. Note that storage column SC1 includes a plurality of transistors M0-M127 and non-volatile memory (NVM) transistors MF0-MF127. Each of the transistors M0 to M127 and each of the NVM transistors MF0 to MF127 are alternately arranged in the storage column SC1, and one of the continuously arranged transistors M0 to M127 and one of the NVM transistors MF0 to MF127 constitute a memory cell. For example, the transistor M127 and the NVM transistor MF127 constitute one of the memory cells of the storage column SC1.

  Transistors M0-M127 have their gates coupled to word lines ZWL0-ZWL127 in the chip in which flash memory device 200 is embedded, respectively. Further, the control ends of the NVM transistors are coupled to control lines ZCL0-ZCL127, respectively. Further, the reference word line cell unit RWCN is arranged in the storage column SC1, the reference word line cell unit RWCN is coupled to the storage cell in the corresponding storage column SC1, and the reference word line cell unit RWCN is further connected to the reference word line REFZWL and Coupled to dummy word line DMZWL.

  For example, in a memory cell comprising transistor M127 and NVM transistor MF127, the first end of transistor M127 is coupled to source line SL127, the control end is coupled to word line ZWL127, and the second end of transistor M127 is the NVM transistor. Coupled to the first end of MF127. The control terminal of NVM transistor MF127 is coupled to control line ZCL127, and the second terminal of NVM transistor MF127 is coupled to bit line BL127 and NVM transistor MF126 of the next memory cell.

  In this embodiment, the reference word line cell unit RWCN includes a reference transistor MA1, a dummy transistor MA2, an NVM transistor MFA1, and a dummy NVM transistor MFA2. The reference cell is composed of a reference transistor MA1 and an NVM transistor MFA1, and the dummy cell is composed of a reference transistor MA2 and an NVM transistor MFA2. The first end of the reference transistor MA1 is coupled to the source line SREF, the control end of the reference transistor MA1 is coupled to the reference word line REFZWL, and the second end of the reference transistor MA1 is connected to the first end of the reference NVM transistor MFA1. Combined. The control end of reference NVM transistor MFA1 is coupled to reference control line REFZCL, and the second end of reference NVM transistor MFA1 is coupled to the first end of dummy NVM transistor MFA2. Further, the control end of dummy NVM transistor MFA2 is coupled to dummy control line DMZCL, and the second end of dummy NVM transistor MFA2 is coupled to the first end of dummy transistor MA2. The control end of dummy transistor MA2 is coupled to dummy word line DMZWL, and the second end of dummy transistor MA2 is coupled to dummy source line SDMY.

  In some embodiments, bit lines BL0-BL127 can also be coupled to the coupling terminals of reference VNM transistor MFA1 and dummy NVM transistor MFA2.

  On the other hand, the reference storage column RSC1 is arranged adjacent to the storage column SC1. Reference storage column RSC1 includes reference bit line cells coupled in series. Reference bit line cells are coupled to word lines ZWL0-ZWL127, reference word line REFZWL, and dummy word line DMZWL. One of the reference bit line cells coupled to the reference word line REFZWL is coupled to the reference bit line RBL1.

  The reference storage column RSC1 includes a plurality of bit line reference transistors MR0 to MR127 and MAR1 to MAR2, and bit line reference NVM transistors MFR0 to MFR127 and MRFA1 to MRFA2. Each of the reference bit line cells in the reference storage column RSC1 includes bit line reference transistors MR0 to MR127 and MAR1 to MAR2 and corresponding bit line reference NVM transistors. For example, in FIG. 2, the bit line reference transistor MR0 and the bit line NVM transistor MRF0 constitute one of the reference bit line cells in the reference storage column RSC1.

  In reference storage column RSC1, reference bit line RBL1 is coupled to a reference bit line cell coupled to reference word line REFZWL. That is, the reference bit line cell including the bit line reference NVM transistor MRFA1 and the bit line reference transistor MAR1 is coupled to the reference bit line RBL1. Reference bit line RBL1 is also coupled to a reference bit line cell including reference bit line NVM transistor MRFA2 and reference bit line transistor MAR2 coupled to dummy control line DMZCL and dummy word line DMZWL, respectively.

  Sense amplifier module 230 is coupled to bit lines BL0-BL127 and reference bit line RBL1. The sense amplification module 230 compares the current from one of the bit lines BL0 to BL127 with the current from the corresponding reference bit line RBL1, and generates at least one detection result DOUT.

  In one embodiment, when the flash memory device operates in the data read mode, the voltage level of the reference control line REFZCL can be set to 2.0V, and the voltage level of the control lines ZCL0-ZCL127 can be set to 2.8V. . As a result, a current is generated in the reference bit line RBL1, and the current level can be 10 μA. Data read from each of the memory cells in the flash memory block IO1 can be determined by comparing each current of the bit lines BL0 to BL127 with a current of the reference bit line RBL1. For example, when the current of the bit line BL0 is larger than the current of the reference bit line RBL1, the data stored in the memory cell including the transistors M127 and MF127 is logic “0”. On the contrary, when the current of the bit line BL0 is smaller than the current of the reference bit line RBL1, the data stored in the memory cell composed of the transistors M127 and MF127 is logic “1”.

  When the flash memory device operates in the program mode, a high voltage is supplied to the memory cell selected for programming. The reference control line REFZCL can be set to 2.0V, and the voltage level of the control line ZCL0 can be set to 4.3V. Whether or not the program mode is completed can be determined by comparing the current of the bit line BL0 and the current of the reference bit line RBL1. That is, when the current of the bit line BL0 is smaller than the current of the reference bit line RBL1, the program mode is continued, and when the current of the bit line BL0 is larger than the current of the reference bit line RBL1, the program mode is completed.

  When the flash memory device operates in the erase mode, a high voltage is supplied to at least one of the flash memory blocks IO1-IOP. The voltage level of the reference control line REFZCL can be set to 2.0V, and the voltage level of the control lines ZCL0 to ZCL127 can be set to 2.0V. Whether or not the erase mode is completed can be determined by comparing each current of the bit lines BL0 to BL127 with the current of the reference bit line RBL1. That is, when each current of the bit lines BL0 to BL127 is larger than the current of the reference bit line RBL1, the erase mode is continued, and when each current of the bit lines BL0 to BL127 is smaller than the current of the reference bit line RBL1, The mode is complete.

  In one embodiment, the dummy cell is maintained in an erased state. That is, the dummy cell including the dummy transistor MA2 and the dummy NVM transistor MFA2 is maintained in the erased state. In one embodiment, both the dummy cell and the reference cell can be turned on by signals on the dummy word line DMZWL and the reference word line REFZWL, respectively. When both the dummy cell and the reference cell are turned on, a higher and more stable erase current is obtained on the reference bit line RBL1. For example, the current level of the reference bit line RBL1 can be doubled. As a result, the detection capability of the sense amplification module 230 can be increased.

  Referring to FIG. 3, FIG. 3 is a circuit diagram of a flash memory device 300 according to another embodiment of the present invention. The flash memory device 300 includes a plurality of flash memory array blocks IO1-IOP. For example, the flash memory array block IO1 includes a storage column SC1, a reference word line cell unit RWCN, first and second reference storage columns RSC1 and RSC2, and A sense amplification module 330 is included. Storage column SC1 includes a plurality of memory cells coupled in series. These memory cells are also coupled to word lines ZWL0-ZWL127 and bit lines BL0-BL127, respectively. The reference word cell unit RWCN is arranged in each storage column SC1, the reference word line cell unit RWCN is coupled to the storage cell in the corresponding storage column SC1, and the reference word line cell unit RWCN is further connected to the first and second reference cells. Coupled to word lines REFZWL1 and REFZWL2. The first and second reference storage columns RSC1 and RSC2 are arranged adjacent to the storage column SC1. Each of the first and second reference storage columns RSC1 and RSC2 includes a plurality of reference bit line cells coupled in series, and the reference bit line cells in the first reference storage column RSC1 include the word lines ZWL0 to ZWL127 and the first reference bit line cells. Are coupled to one reference word line REFZWL1. Reference bit line cells in second reference storage column RSC2 are coupled to word lines ZWL0-ZWL127 and second reference word line REFZWL2, respectively. One of the reference bit line cells of the first and second reference storage columns RSC1 and RSC2 coupled to the first and second reference word lines REFWZL1 and REFZWL2 is connected to the first and second reference bit lines RBLO1 and RBLE1, respectively. Combined.

  The first reference storage column RSC1 includes a plurality of memory cells, and these memory cells include transistors MR01-MR1271 and NVM transistors MFR01-MFR1271. The second reference storage column RSC2 includes a plurality of memory cells, and these memory cells include transistors MR02-MR1272 and NVM transistors MFR02-MFR1272.

  It should be noted here that the first reference storage column RSC1 includes reference transistors MAR11 and MAR12 and reference NVM transistors MRFA11 and MRFA12. The second reference storage column RSC2 includes reference transistors MAR21 and MAR22 and reference NVM transistors MRFA21 and MRFA22. The connection end of the reference NVM transistors MRFA11 and MRFA12 is further coupled to the first reference bit line RBLO1, and the connection end of the reference NVM transistors MRFA21 and MRFA22 is further coupled to the second reference bit line RBLE1. The gates of the reference transistor MAR11 and the reference NVM transistor MRFA11 are coupled to the first reference word line REFZWL1 and the first reference control line REFZCL1, respectively. Second reference word line REFZWL2 and second reference control line REFZCL2 are coupled to the gates of reference transistor MAR12 and reference NVM transistor MRFA12, respectively. Conversely, the gates of the reference transistor MAR22 and the reference NVM transistor MRFA22 are coupled to the second reference word line REFZWL2 and the second reference control line REFZCL2, respectively. First reference word line REFZWL1 and first reference control line REFZCL1 are coupled to the gates of reference transistor MAR21 and reference NVM transistor MRFA21, respectively.

  The sense amplification module 330 compares the current from one of the bit lines with the corresponding current from the first and second reference bit lines RBLO1 and / or RBLE1, and generates at least one detection result DOUT.

  In this embodiment, the bit line cells in one column of the first and second reference storage columns RSC1 and RSC2 are connected to the selected sense amplifier module 330, and the first and second reference storage columns RSC1 and RSC2 are connected. The other columns are isolated from the sense amplification module 330. In this example, the reference bit line cell selected to be connected to the sense amplifier module 330 constitutes a reference cell, and the reference bit line cell insulated from the sense amplifier module 330 constitutes a dummy cell.

  Referring to FIGS. 3 and 4, FIG. 4 is a circuit diagram of a plurality of selection circuits. These selection circuits are constituted by transistor switches SW1-SWR. Select circuits SW1-SWR are coupled between flash memory array block IO1-IOP and sense amplifier module 330. The selection circuits SW1-SWR are controlled by the selection gate control signal RSG [0: 1], and each of the selection circuits SW1-SWR corresponds to the first and / or second corresponding to the selection gate control signal RSG [0: 1]. It is determined whether or not the current of the reference bit lines RBLO 1 -RBLOQ and RBLE 1 -RBLEQ is transported to the sense amplifier module 330. In this embodiment, the selection gate control signal RSG [0: 1] is a 2-bit digital signal. One bit of the selection gate control signal RSG [0: 1] is selected by the selection circuits SW1, SW3,. . . The other bits of the selection gate control signal RSG [0: 1] are used for the selection circuits SW2, SW4,. . . Used to control.

  For example, the selection circuit SW1 is controlled by the selection gate control signal RSG [0], and the selection circuit SW2 is controlled by the selection gate control signal RSG [1]. The turn-on or turn-off states of the selection circuits SW1 and SW2 may be different or the same.

  Referring to FIG. 5A, FIG. 5A is a block diagram of a sense amplification module 500 according to one embodiment of the present invention. The sense amplifier module 500 includes one or more sense amplifier circuits 510-5P0. Each of sense amplifier circuits 510-5P0 is coupled to each of flash memory array blocks IO1-IOP, and receives current from one of the bit lines and the reference bit line of the corresponding flash memory array block. The sense amplifier circuits 510-5P0 receive currents from the selected bit lines BLS1-BLSP and reference bit lines RBL1-RBLP, respectively, and generate detection results DOUT1-DOUTP, respectively.

  Referring to FIG. 5B, FIG. 5B is a block diagram of a sense amplifier circuit 510 according to one embodiment of the present invention. The sense amplifier circuit 510 includes a current-voltage converter 511 and a comparator 512. The current-voltage converter 511 receives the current of the selected bit line BL1 and reference bit line RBL1, and generates first and second comparison voltages VC1 and VC2 according to the selected bit line BL1 and reference bit line RBL1. To do. Comparator 12 is coupled to current-voltage converter 511. The comparator 512 compares the first and second comparison voltages VC1 and VC2 and generates a detection result DOUT1.

  Referring to FIG. 5C, FIG. 5C is a circuit diagram of the sense amplifier circuit 510 according to an embodiment of the present invention. The current-voltage converter 511 includes transmission gates TR1 and TR2, transistor switches SWA1 and SWA2, a transistor MA and a transistor MB. The first end of the transistor MA receives one bit line current from the data line DL, and the second end of the transistor MA is coupled to the reference ground voltage GND. The first end of the transistor MB receives a reference bit line current from the reference data line RDL, the second end of the transistor MB is coupled to the reference ground voltage GND, and the control end of the transistor MB is the control of the first transistor MA. Coupled to the end and the first end of the transistor MB.

  Comparison voltages VC1 and VC2 are generated at the first ends of transistors MA and MB, respectively. The comparison voltages VC1 and VC2 are supplied to the comparator 512. Further, the data line DL is coupled to one of the bit lines of the corresponding flash memory array block, and the reference data line RDL is coupled to the reference bit line of the corresponding flash memory array block. The transistor switch SWA1 is configured to turn on or off the connection between the data line DL and the transistor MA, and the transistor switch SWA2 is configured to turn on or off the connection between the reference data line RDL and the transistor MB. The Transmission gate TR1 is configured to equalize data line DL and reference data line RDL, and transmission gate TR2 is configured to equalize the first ends of transistors MA and MB.

  Referring to FIG. 5D, FIG. 5D is another circuit diagram of the sense amplifier circuit 510 according to one embodiment of the present invention. In this embodiment, the connection relationship between the transistors MA and MB is different from the embodiment of FIG. 5C. In FIG. 5D, transistors MA and MB are each configured as a diode-connected transistor. That is, the first end and the control end of the transistor MA are interconnected, and the first end and the control end of the transistor MB are interconnected. The cathode of the diode constituted by the transistors MA and MB is coupled to the reference ground GND, and the anode of the diode constituted by the transistors MA and MB generates the first and second comparison voltages, respectively.

(Industrial applicability)
The flash memory device according to the disclosed embodiments can be used in place of a conventional flash memory device and does not require a large range of reference values. The reference value of the flash memory device according to the embodiment is given by the reference current generated by the reference word line cell unit, and the process change can be ignored. Therefore, the efficiency of the flash memory device is improved.

100, 200: Flash memory device 110: Reference line control circuit 120: X decoder M11-Mm3: Memory cells R11-Rm3: Reference cells B1-B3: Bit lines R1-R3: Reference bit lines IO1-IOP: Flash memory array block 230: Sense amplification module SC1: Storage column RWCN: Reference word line cell units RSC1, RSC2: Reference storage columns ZWL0-ZWL127: Word lines BL0-BL127: Bit lines MF0-MF127: Non-volatile memory (NVM) transistors M0-M127: Transistors REFZWL, REFAWL1, REFZEL2: Reference word line DMZWL: Dummy word line SL127: Source lines ZCL0 to ZCL127: Control line MA1: Reference line Transistor MA2: Dummy transistor MFA1: NVM transistor MFA2: Dummy NVM transistor REFZCL: Reference control line DMZCL: Dummy control line DMZWL: Dummy word line SDMY: Dummy source lines MR0-MR127, MAR1-MRA2, MR01-MR1271, MR02-MR1272, MAR11-MAR21, MAR12-MRA22: Reference transistors MRF0-MRF127, MRFAI-MRFA2, MFR02-MFF1271, mRFA11, MRFA12, MRFA21, MRFA22: Reference NVM transistor RBL1-RBLP: Reference bit line DOUT: Detection result RBLO1-RBLE1: Reference bit Line SW1-SWR: selection circuit 500: set Amplifier module 510-5P0: sense amplifier circuits BLS1-MLSP: selected bit lines DOUT1-DOUTP: detection result 511: current-voltage converter 512: comparators VC1, VC2: comparison voltages TR1, TR2: transmission gate SWA1, SWA2: Transistor switch MA, MB: Transistor

Claims (19)

Comprising at least one flash memory array block;
The flash memory array block includes N storage columns, N reference word line cell units, a reference storage column, and a sense amplification module.
Each of the N storage columns includes a plurality of memory cells coupled in series, each memory cell coupled to a word line and a bit line, respectively, where N is a positive integer,
Each of the N reference word line cell units is disposed in each of the storage columns, each of the reference word line cell units is coupled to the memory cell in the corresponding storage column, and the reference word line cell The unit is further coupled to a reference word line and a dummy word line,
The reference storage column is disposed adjacent to the storage column, and the reference storage column includes a plurality of reference bit line cells coupled in series, the reference bit line cell including the word line, the reference word line, and the One of the reference bit line cells coupled to a dummy word line and coupled to the reference word line is coupled to a reference bit line;
The sense amplification module compares the current from one of the bit lines with the current from the corresponding reference bit line to generate at least one detection result;
A flash memory device. Each of the reference word line cell units is
A reference cell coupled to one of the memory cells and coupled to the reference word line; and a dummy cell coupled to the reference cell and another one of the memory cell and coupled to a dummy word line.
The flash memory device according to claim 1. The reference cell is
A reference transistor having a first end, a second end, and a control end, wherein the first end is coupled to a reference source line, the control end is coupled to the reference word line, and a first end; A reference non-volatile memory (NVM) transistor having a second end and a control end;
A first end of the reference NVM transistor is coupled to the second end of the reference transistor, a control end of the reference NVM transistor is coupled to a reference control line, and a second end of the reference NVM transistor corresponds to the second end. Coupled to the dummy cell;
The flash memory device according to claim 2. The dummy cell is
A dummy NVM transistor having a first end, a second end, and a control end, wherein the first end of the dummy NVM transistor is coupled to a second end of the reference NVM transistor, and the control end of the dummy NVM transistor; Is coupled to the dummy control line, and includes a dummy transistor having a first end, a second end, and a control end, the first end of the dummy transistor being coupled to the second end of the dummy NVM transistor, A second end of the dummy transistor is coupled to a dummy source line, and a control end of the dummy transistor is coupled to the dummy word line;
The flash memory device according to claim 2.   The flash memory device according to claim 2, wherein the dummy cell is maintained in an erased state. Each of the memory cells
A transistor having a first end, a second end and a control end, wherein the first end of the transistor is coupled to a source line, a control end is coupled to the corresponding word line, and the first end; An NVM transistor having a second end and a control end, wherein a first end of the NVM transistor is coupled to a second end of the transistor, a control end of the NVM transistor is coupled to a control line, and the NVM transistor Are coupled to the corresponding bit lines,
The flash memory device according to claim 1. The sense amplification module includes:
Comprising at least one sense amplifier circuit, the sense amplifier circuit comprising:
A current-voltage converter for receiving a current of one of the bit lines and the reference bit line and generating first and second comparison voltages according to the current of the one of the bit lines and the reference bit line, respectively; And a comparator coupled to the current-voltage converter for comparing the first and second comparison voltages to generate a detection result;
The flash memory device according to claim 1. The current-voltage converter is
A first transistor having a first end, a second end and a control end, wherein the first end of the first transistor receives one current of the bit line, and the second end of the first transistor; And a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor receiving a current of the reference bit line. Receiving, the second end of the first transistor is coupled to a reference ground voltage, and the control end of the second transistor is coupled to the control end of the first transistor and the first end of the second transistor. And
The first and second comparison voltages are generated at first ends of the first and second transistors, respectively;
The flash memory device according to claim 7. The current-voltage converter is
A first diode having an anode receiving one current of the bit line and a cathode coupled to a reference ground voltage; and an anode receiving a current of the reference bit line and a cathode coupled to the reference ground voltage. With a diode
The first and second comparison voltages are generated at the anodes of the first and second diodes, respectively;
The flash memory device according to claim 7.   The floating memory device according to claim 9, wherein the first diode is a first diode-connected transistor, and the second diode is a second diode-connected transistor. With multiple flash memory array blocks,
Each of the flash memory array blocks includes N storage columns, N reference word line cell units, first and second reference storage columns, and a sense amplification module.
Each of the N storage columns includes a plurality of memory cells coupled in series, each memory cell coupled to a word line and a bit line, respectively, where N is a positive integer,
Each of the N reference word line cell units is disposed in each of the storage columns, each of the reference word line cell units is coupled to the memory cell in the corresponding storage column, and the reference word line cell The unit is further coupled to a reference word line and a dummy word line,
The first and second reference storage columns are disposed adjacent to the storage column, and each of the first and second reference storage columns includes a plurality of reference bit line cells coupled in series, The reference bit line cell in one reference storage column is coupled to the word line and the first reference word line, respectively, and the reference bit line cell in the second reference storage cell is the word line and the reference A reference bit line cell of the first and second reference storage columns coupled to a word line and coupled to the first and second reference word lines, respectively, is coupled to the first and second reference bit lines;
The sense amplifier module compares at least one current from one of the bit lines with a corresponding current from the first and / or second reference bit line to generate at least one detection result;
A flash memory device. A plurality of selection circuits coupled between the flash memory array block and the sense amplifier module and controlled by a selection gate connection signal are provided, each of the selection circuits being in response to the selection gate control signal. And / or determining whether to transport the current of the second reference bit line to the sense amplifier module;
The floating memory device according to claim 11. Each of the reference word line cell units is
A reference cell coupled to one of the memory cells and coupled to the reference word line; and a dummy cell coupled to the reference cell and another one of the memory cell and coupled to a dummy word line.
The flash memory device according to claim 11. The reference cell is
A reference transistor having a first end, a second end, and a control end, wherein the first end is coupled to a reference source line, and the control end is coupled to the first reference word line; A reference non-volatile memory (NVM) transistor having a first end, a second end and a control end,
A first end of the reference NVM transistor is coupled to a second end of the reference transistor, a control end of the reference NVM transistor is coupled to a reference control line, and a second end of the reference NVM transistor corresponds to the second end. Coupled to a dummy cell,
The flash memory device according to claim 13. The dummy cell is
A dummy NVM transistor having a first end, a second end, and a control end, wherein the first end of the dummy NVM transistor is coupled to a second end of the reference NVM transistor, and the control end of the dummy NVM transistor; Is coupled to the dummy control line, and includes a dummy transistor having a first end, a second end, and a control end, the first end of the dummy transistor being coupled to the second end of the dummy NVM transistor, A second end of the dummy transistor is coupled to a dummy source line, and a control end of the dummy transistor is coupled to the second reference word line;
The flash memory device according to claim 13. Each of the memory cells
A transistor having a first end, a second end, and a control end, wherein the first end of the transistor is coupled to a source line, the control end is coupled to a corresponding word line, and the first end, the second end An NVM transistor having a second end and a control end, wherein a first end of the NVM transistor is coupled to a second end of the transistor, a control end of the NVM transistor is coupled to a control line, and the NVM transistor includes: The second end is coupled to a corresponding bit line;
The flash memory device according to claim 11. The sense amplification module includes:
Comprising at least one sense amplifier circuit, the sense amplifier circuit comprising:
The current of one of the bit lines and the first and second reference bit lines is received, and the first is responsive to at least one current of the bit lines and at least one current of the first and second reference bit lines. And a current-voltage converter for generating a second comparison voltage, respectively, and a comparator coupled to the current-voltage converter for comparing the first and second comparison voltages and generating a detection result,
The flash memory device according to claim 11. The current-voltage converter is
A first transistor having a first end, a second end and a control end, wherein the first end of the first transistor receives one current of the bit line, and the second end of the first transistor; A second transistor having a first end coupled to a reference ground voltage and having a first end, a second end, and a control end, wherein the first end of the second transistor is the first and second ends. Receiving at least one current of a reference bit line, the second end of the first transistor is coupled to a reference ground voltage, the control end of the second transistor is the control end of the first transistor and the second end of the second transistor; Coupled to the first end of the transistor,
The first and second comparison voltages are generated at first ends of the first and second transistors, respectively;
The flash memory device according to claim 17. The current-voltage converter is
An anode receiving one current of the bit line; a cathode receiving a first diode coupled to a reference ground voltage; and an anode receiving at least one current of the first and second reference bit lines; A first diode coupled to a reference ground voltage;
The first and second comparison voltages are generated at the anodes of the first and second diodes, respectively;
The flash memory device according to claim 17.

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