JP2014041692A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify control of semiconductor memory devices having such types that a time required for writing is different depending on a logical value to be written.SOLUTION: A device includes memory elements MC arranged at cross points of word lines WL and bit lines BL, a write driver WD supplying a writing current to the bit line BL, a writing control circuit WC controlling operation of the write driver WD, and a timing signal generating circuit 13 supplying a timing signal TS to the writing control circuit WC. The timing signal TS has pulses P1 to P3. When a first logical level is written, the timing signal TS activates the write driver WD over P1 to P3 period, and when a second logical level is written, the timing signal TS activates the write driver WD over P1 to P2 period. Thus, control of semiconductor memory devices having such types that a time required for writing is different depending on a logical value to be written can be simplified.

Description

  The present invention relates to a semiconductor memory device and a writing control method thereof, and more particularly to a semiconductor memory device having a writing time difference depending on a logic level of data to be written and a writing control method for such a semiconductor memory device.

  Various storage devices constructed hierarchically are used for personal computers and servers. The lower layer storage device is required to be inexpensive and have a large capacity, and the upper layer storage device is required to be accessed at high speed. As the lowermost storage device, a magnetic storage such as a hard disk drive or a magnetic tape is generally used. Magnetic storage is non-volatile, and can store extremely large amounts of data at a low cost compared to semiconductor memory, etc., but has a slow access speed and often has random accessibility. Absent. For this reason, the magnetic storage stores a program, data to be stored in the long term, and the like, and transfers them to a higher-layer storage device as necessary.

  The main memory is a storage device in an upper layer than the magnetic storage. Generally, a DRAM (Dynamic Random Access Memory) is used as the main memory. DRAM can be accessed at a higher speed than magnetic storage and has random accessibility. In addition, the bit unit price is lower than that of a high-speed semiconductor memory such as SRAM (Static Random Access Memory).

  The uppermost storage device is a built-in cache memory built in an MPU (Micro Processing Unit). Since the built-in cache memory is connected to the core of the MPU via an internal bus, it can be accessed at extremely high speed. However, the recording capacity that can be secured is extremely small. Note that a secondary cache, a tertiary cache, or the like may be used as a storage device that forms a hierarchy between the internal cache and the main memory.

  The reason why the DRAM is selected as the main memory is that the balance between the access speed and the bit unit price is very good. Moreover, a chip having a large capacity among semiconductor memories and having a capacity exceeding 1 gigabit has been developed in recent years. However, the DRAM is a volatile memory, and the stored data is lost when the power is turned off. Therefore, the DRAM is not suitable for storing a program or data to be stored for a long time. In addition, since it is necessary to perform a refresh operation periodically to keep data even when the power is turned on, there is a limit to reducing power consumption, and there is a problem that complicated control by the controller is necessary. Yes.

  A flash memory is known as a large-capacity nonvolatile semiconductor memory. However, the flash memory has a demerit that a large current is required for data writing and data erasing, and the writing time and erasing time are very long. Therefore, it is inappropriate to replace the DRAM as the main memory. In addition, nonvolatile memories such as MRAM (Magnetoresistive Random Access Memory) and FRAM (Ferroelectric Random Access Memory) have been proposed, but it is difficult to obtain a storage capacity equivalent to that of DRAM.

  On the other hand, PRAM (Phase change Random Access Memory) that performs recording using a phase change material has been proposed as a semiconductor memory that replaces DRAM (see Patent Documents 1 and 2). The PRAM stores data according to the phase state of the phase change material included in the recording layer. That is, the phase change material has a large difference in electrical resistance in the crystalline phase and in the amorphous phase, and thus data can be recorded using this.

  The change in phase state is performed by passing a write current through the phase change material, thereby heating the phase change material. Data is read by passing a read current through the phase change material and measuring its resistance value. The read current is set to a value sufficiently smaller than the write current so as not to cause a phase change. Thus, since the phase state of the phase change material does not change unless high heat is applied, data is not lost even when the power is turned off.

  In order to make the phase change material amorphous (reset), it is necessary to heat the phase change material to a temperature equal to or higher than the melting point by applying a write current and then rapidly cool the phase change material. On the other hand, in order to crystallize (set) the phase change material, it is necessary to heat the phase change material to a temperature higher than the crystallization temperature and lower than the melting point by applying a write current, and then gradually cool it. For this reason, the PRAM has a feature that the time required for the set operation is longer than the reset operation.

JP 2006-24355 A JP 2005-158199 A

  As described above, in the PRAM, the time required for the set operation and the time required for the reset operation are greatly different, so that the control at the time of data writing becomes complicated, and it is difficult to ensure compatibility with other general-purpose memories such as DRAM. Met. Such a problem is a problem that occurs not only in the PRAM but also in a semiconductor memory device of a type in which the time required for writing differs depending on the logical value to be written.

  The present invention has been made to solve such problems, and the semiconductor memory device according to the present invention simplifies the control of a semiconductor memory device of a type in which the time required for writing differs depending on the logic value to be written. With the goal.

  A semiconductor memory device according to the present invention includes a word line, a bit line intersecting with the word line, a memory element arranged at an intersection of the word line and the bit line, and a different time required for writing depending on a logical value, A write driver that supplies a write current to the bit line; a write control circuit that controls an operation of the write driver; and a timing signal generation circuit that supplies a timing signal to the write control circuit. In the case of writing a pulse indicating the start of supply of the write current in the case of writing the logic level, a pulse indicating the end of supply of the write current in the case of writing the first logic level, and in writing the second logic level Including a pulse indicating at least one of supply start and supply end of the write current It characterized in that it has the form.

  According to another aspect of the present invention, there is provided a write control method for a semiconductor memory device, wherein a word line, a bit line intersecting the word line, and an intersection of the word line and the bit line are arranged. A write control method for a semiconductor memory device comprising different memory elements and first and second write transistors for supplying a write current to the bit line, wherein a timing signal having first to third pulses is generated. When writing the first logic level, and when writing the second logic level, the first writing transistor is turned on during the period from the first pulse to the third pulse. Conducting the second write transistor over a period from the first pulse to the second pulse. And butterflies.

  As described above, according to the present invention, since the timing signal indicating the writing start time and the writing end time of the first and second logic levels is used and the write current is supplied to the bit line in synchronization therewith, writing is performed. It is possible to simplify the control of a semiconductor memory device of a type in which the time required for writing differs depending on the power value. As a result, data can be written without being aware of the logical value to be written, so that it is easy to provide compatibility with a synchronous DRAM.

1 is a circuit diagram of a semiconductor memory device according to a preferred embodiment of the present invention. 4 is a circuit diagram of a memory cell MC when the semiconductor memory device according to the present invention is a PRAM. FIG. It is a graph for demonstrating the method to control the phase state of the phase change material containing a chalcogenide material. It is a wave form diagram of timing signals TS1-TS5 and timing selection signals SEL1-SEL5. It is a block diagram which shows the structure of the write control circuit WC (WC1-WCn). 3 is a circuit diagram of a write data latch circuit 41. FIG. 3 is a circuit diagram of a selector 42. FIG. 3 is a circuit diagram of a shift register 43. FIG. It is a wave form diagram of various internal signals. 4 is a circuit diagram of a write pulse generator 44. FIG. FIG. 6 is a timing diagram illustrating a write control operation according to a preferred embodiment of the present invention. It is a wave form diagram which shows the other example of timing signal TS. It is a wave form diagram which shows the further another example of timing signal TS. It is a figure which shows the circuit by the modification which produces | generates column selection signal CS1-CSn. FIG. 17 is a timing chart for explaining the operation of the circuit shown in FIG. 16. It is a timing chart showing an example of operation when j = 0.5.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a circuit diagram of a semiconductor memory device according to a preferred embodiment of the present invention.

  The semiconductor memory device shown in FIG. 1 includes word lines WL1 to WLm, bit lines BL1 to BLn intersecting the word lines WL1 to WLm, and memory cells MC (1, 1) arranged at the intersections of the word lines and the bit lines. A memory in the form of a matrix having .about.MC (m, n).

  Selection of the word lines WL1 to WLm is performed by the row selector 11, and any one of the word lines WL1 to WLm is activated. Further, write drivers WD1 to WDn for supplying a write current are connected to the bit lines BL1 to BLn, respectively. The operations of the write drivers WD1 to WDn are controlled by the write control circuits WC1 to WCn, respectively. As shown in FIG. 1, write data Data is commonly supplied to the write control circuits WC1 to WCn.

  The column selector 12 is a circuit that generates column selection signals CS1 to CSn corresponding to the write control circuits WC1 to WCn, respectively, and thereby the write control circuits WC1 to WCn are selected. The column selector 12 is supplied with the clock signal CLK, and the column selector 12 thereby operates in synchronization with the clock signal CLK.

  As shown in FIG. 1, each of the write drivers WD1 to WDn includes a set transistor 21 and a reset transistor 22. Both transistors are P-channel MOS transistors. The source of the setting transistor 21 is connected to the set potential wiring Vset, and the source of the resetting transistor 22 is connected to the reset potential wiring Vreset. The drains of these transistors 21 and 22 are commonly connected to corresponding bit lines BL1 to BLn via Y switches Y1 to Yn. A selection signal Ysel is commonly supplied to the Y switches Y1 to Yn.

  As a result, when the setting transistor 21 is turned on while the selection signal Ysel is activated, a set current is supplied to the corresponding bit lines BL1 to BLn. On the other hand, when the reset transistor 22 is turned on while the selection signal Ysel is activated, a reset current is supplied to the corresponding bit lines BL1 to BLn.

  The set pulse 31 supplied to the gate of the set transistor 21 and the reset pulse 32 supplied to the gate of the reset transistor 22 are generated by the corresponding write control circuits WC1 to WCn.

  As shown in FIG. 1, the write control circuits WC1 to WCn are supplied with the timing signal TS and the timing selection signal SEL generated by the timing signal generation circuit 13, in addition to the write data Data and the column selection signals CS1 to CSn. . Among these signals, the write data Data, the timing signal TS, and the timing selection signal SEL are supplied in common to the write control circuits WC1 to WCn. On the other hand, the column selection signals CS1 to CSn are individually supplied to the write control circuits WC1 to WCn.

  The timing signal TS is composed of five timing signals TS1 to TS5, and the timing selection signal SEL is composed of five timing selection signals SEL1 to SEL5.

  FIG. 2 is a circuit diagram of the memory cell MC when the semiconductor memory device according to the present invention is a PRAM.

  As shown in FIG. 2, when the semiconductor memory device according to the present invention is a PRAM, the memory cell MC is composed of a nonvolatile memory element PC made of a phase change material and a selection transistor Tr, which are a bit line BL and a source potential VSS. Will be connected in series.

The phase change material constituting the nonvolatile memory element PC is not particularly limited as long as it is a material that takes two or more phase states and has different electric resistance depending on the phase state, but it is preferable to select a so-called chalcogenide material. The chalcogenide material refers to an alloy containing at least one element such as germanium (Ge), antimony (Sb), tellurium (Te), indium (In), and selenium (Se). As an example, binary elements such as GaSb, InSb, InSe, Sb ₂ Te ₃ and GeTe, ternary elements such as Ge ₂ Sb ₂ Te ₅ , InSbTe, GaSeTe, SnSb ₂ Te ₄ and InSbGe, AgInSbTe, (GeSn ) Quaternary elements such as SbTe, GeSb (SeTe), Te ₈₁ Ge ₁₅ Sb ₂ S _{2 and the} like.

  Phase change materials including chalcogenide materials can take either an amorphous phase (amorphous phase) or a crystalline phase. The amorphous phase has a relatively high resistance state and the crystalline phase has a relatively low resistance. It becomes a state.

  The selection transistor Tr is composed of an N-channel MOS transistor, and its gate electrode is connected to the corresponding word line WL. Accordingly, when the word line WL is activated, the nonvolatile memory element PC is connected between the bit line BL and the source potential VSS.

  As described above, in order to make the phase change material amorphous (reset), it is necessary to heat the phase change material to a temperature equal to or higher than the melting point by applying a write current and then rapidly cool the phase change material. On the other hand, in order to crystallize (set) the phase change material, it is necessary to heat the phase change material to a temperature higher than the crystallization temperature and lower than the melting point by applying a write current, and then gradually cool it. FIG. 3 is a graph for explaining this. A curve a shows a heating method when the phase change material constituting the nonvolatile memory element PC is amorphized (reset), and a curve b crystallizes the phase change material constituting the nonvolatile memory element PC ( This shows the heating method when setting.

  As shown in FIG. 3, in the PRAM, the time required for the set operation is longer than the reset operation.

  FIG. 4 is a waveform diagram of the timing signals TS1 to TS5 and the timing selection signals SEL1 to SEL5.

  As shown in FIG. 4, the timing signals TS1 to TS5 are all signals synchronized with the clock signal CLK, and are signals having phases different from each other by j clocks. In this embodiment, j = 1, and therefore the phases of the timing signals TS1 to TS5 are shifted from each other by one clock.

  The timing signals TS1 to TS5 have a waveform in which three pulses repeatedly appear. The timing signal TS1 will be specifically described as an example. The pulse group P composed of pulses P1 to P3 synchronized with the active edges # 1, # 2 and # 5 of the clock signal CLK is repeated. Therefore, one pulse group P uses a period of 5 clocks. Therefore, by shifting the phases of the timing signals TS1 to TS5 from each other by one clock, all the active edges of the clock signal CLK become the start timing of one of the pulse groups P. In the example shown in FIG. 4, the active edges # 1 to # 5 of the clock signal CLK are the start timings of the pulse group P of the timing signals TS1 to TS5, respectively. The active edges # 6 to # 10 of the clock signal CLK are also the start timing of the pulse group P of the timing signals TS1 to TS5, respectively.

  A period from the pulse P1 to the pulse P3 corresponds to a period for crystallizing (setting) the phase change material, and is 4 clocks in this embodiment. The period from the pulse P1 to the pulse P2 corresponds to a period for making the phase change material amorphous (reset), and is one clock in this embodiment.

  As shown in FIG. 4, the timing selection signals SEL1 to SEL5 each have a one-shot pulse waveform prior to the start of the pulse group P of the timing signals TS1 to TS5. Accordingly, the phases of the timing selection signals SEL1 to SEL5 are also shifted from each other by one clock, and are activated every five clocks.

  Next, the circuit configuration of the write control circuit WC (WC1 to WCn) will be described.

  FIG. 5 is a block diagram showing a configuration of the write control circuit WC (WC1 to WCn).

  As shown in FIG. 5, the write control circuit WC includes a write data latch circuit 41, a selector 42, a shift register 43, and a write pulse generator 44. Of the signals supplied to the write control circuit WC, the write data Data is supplied to the write data latch circuit 41, and the timing signal TS and the timing selection signal SEL are supplied to the selector 42. The column selection signal CS (CS1 to CSn) is supplied to all the blocks 41 to 44.

  FIG. 6 is a circuit diagram of the write data latch circuit 41.

  As shown in FIG. 6, the write data latch circuit 41 is constituted by a circuit called a so-called transparent latch circuit (or a through latch circuit). The transparent latch circuit has two input terminals D and G, and latches the signal supplied to the input terminal D at the timing when the signal supplied to the input terminal G changes from low level to high level. While the signal supplied to the input terminal G is at a high level, the latched logic level is output from the output terminal Q, but when the signal supplied to the input terminal G becomes low level, it is supplied to the input terminal D. The signal is output from the output terminal Q as it is. That is, when the signal supplied to the input terminal G is at a low level, the input signal is passed through.

  As shown in FIG. 6, the write data Data is supplied to the input terminal D, and the corresponding column selection signals CS (CS1 to CSn) are supplied to the input terminal G. The output terminal Q is supplied as an internal signal 51 to the write pulse generator 44.

  FIG. 7 is a circuit diagram of the selector 42.

  As shown in FIG. 7, the selector 42 includes five transparent latch circuits 61 to 65 and five transfer gates 71 to 75 corresponding to these. The functions of the transparent latch circuits 61 to 65 are as already described.

  Timing selection signals SEL1 to SEL5 are supplied to input terminals D of the transparent latch circuits 61 to 65, respectively. Corresponding column selection signals CS (CS1 to CSn) are commonly supplied to the input terminals G of the transparent latch circuits 61 to 65.

  Timing signals TS1 to TS5 are supplied to input terminals of the transfer gates 71 to 75, respectively. The operations of the transfer gates 71 to 75 are controlled by the output signals of the transparent latch circuits 61 to 65, respectively. When the output terminals Q of the corresponding transparent latch circuits 61 to 65 become high level and the inverted output terminals / Q become low level, Corresponding timing signals TS1 to TS5 are passed. The outputs of the transfer gates 71 to 75 are connected in common and supplied to the shift register 43 as an internal signal 52.

  With such a circuit configuration, when the corresponding column selection signal CS (CS1 to CSn) changes from the low level to the high level, the timing selection signals SEL1 to SEL5 are latched in the transparent latch circuits 61 to 65, respectively. Therefore, the high level is latched in any one of the transparent latch circuits 61 to 65, and the corresponding transfer gates 71 to 75 are turned on. Thereby, the output internal signal 52 has the same waveform as any of the timing signals TS1 to TS5.

  FIG. 8 is a circuit diagram of the shift register 43.

  As shown in FIG. 8, the shift register 43 includes three latch circuits 81 to 83 with a reset function. These latch circuits 81 to 83 with a reset function take in a signal supplied to the input terminal D at a timing when the signal supplied to the clock terminal C changes from low level to high level, and output this from the output terminal Q It is. Further, when the signal supplied to the reset terminal R becomes high level, the latched data is reset to zero.

  These three latch circuits 81 to 83 with reset function are cascade-connected as shown in FIG. 8, and the corresponding column selection signal CS (CS1 to CSn) is supplied to the input terminal D of the latch circuit 81 at the first stage. . An internal signal 52 is commonly supplied to the clock terminal C, and an internal signal 56 described later is commonly supplied to the reset terminal R.

  The signals output from the output terminals Q of the latch circuits with reset function 81 to 83 are supplied to the write pulse generator 44 as internal signals 53 to 55, respectively.

  The waveforms of the internal signals 53 to 55 are shown in FIG.

  As described above, the internal signal 52 supplied to the clock terminal C has the same waveform as any of the timing signals TS1 to TS5. For this reason, as shown in FIG. 9, the internal signal 52 has three pulses P1 to P3. Accordingly, the level of the column selection signal CS (CS1 to CSn) is sequentially taken into the latch circuits 81 to 83 with a reset function in synchronization with the pulses P1 to P3. As a result, the internal signals 53 to 55 sequentially become high level in synchronization with the pulses P1 to P3.

  FIG. 10 is a circuit diagram of the write pulse generator 44.

  As shown in FIG. 10, the write pulse generator 44 receives the one-shot pulses 103 and 105 and the one-shot pulses 103 and 105 that receive the internal signals 53 to 55 and generate the one-shot pulses 103 to 105, respectively. An SR latch 111 and an SR latch 112 that receives the one-shot pulses 103 and 104 are included.

  The one-shot pulse generators 93 to 95 include a delay element that delays the corresponding internal signal 53 to 55, an inverter that inverts the output of the delay element, and a NAND circuit that receives the corresponding internal signal 53 to 55 and the output of the inverter. It is configured. With this configuration, as shown in FIG. 9, the one-shot pulse generators 93 to 95 make the one-shot pulse that becomes low level by the delay at the timing when the corresponding internal signals 53 to 55 change from low level to high level. Pulses 103-105 are generated.

  The write pulse generation unit 44 is further provided with a reset circuit unit 96 that generates an internal signal 56 from the one-shot pulse 105. The reset circuit unit 96 includes a delay element that delays the one-shot pulse 105 and an inverter that inverts the output of the delay element. The waveform of the internal signal 56 thus generated is as shown in FIG. 9, and becomes a one-shot pulse waveform delayed by the delay amount. As shown in FIG. 8, the internal signal 56 is supplied to the reset terminal R of the latch circuits 81 to 83 with a reset function, and resets the latched data to zero.

The SR latch 111 is a circuit that is set when the one-shot pulse 103 is activated and reset when the one-shot pulse 105 is activated. The SR latch 112 is a circuit that is set when the one-shot pulse 103 is activated and reset when the one-shot pulse 104 is activated. Therefore, the waveforms of the internal signals 121 and 122 which are the outputs of the SR latches 111 and 112 are as shown in FIG. That is, the internal signal 121 is the output of the SR latch 111 is the period from the pulse P1 to pulse P3, i.e., a high level over _{k 1} clock, the internal signal 122 is the output of the SR latch 112 is the pulse P1 period until the pulse P2, i.e., a high level over k ₂ clock.

  As shown in FIG. 10, the internal signals 121 and 122 are supplied to NAND circuits 131 and 132, respectively. In addition to the internal signal 121, the NAND circuit 131 is supplied with a corresponding column selection signal CS (CS1 to CSn) and an inverted signal of the internal signal 51. In addition to the internal signal 122, the corresponding column selection signal CS (CS 1 to CSn) and the internal signal 51 are supplied to the NAND circuit 132. As described with reference to FIG. 6, the internal signal 51 is a signal obtained by latching the write data Data with the corresponding column selection signal CS (CS1 to CSn).

  With such a circuit configuration, if the write data Data is at a low level, the NAND circuit 131 generates the set pulse 31 in synchronization with the internal signal 121. On the other hand, if the write data Data is at the high level, the NAND circuit 132 generates the reset pulse 32 in synchronization with the internal signal 122.

  The circuit configuration of the main part of the semiconductor memory device according to the present embodiment has been described above. Next, the write control operation using the semiconductor memory device according to the present embodiment will be explained.

  FIG. 11 is a timing chart for explaining the write control operation according to the present embodiment. In FIG. 11, in consideration of the legibility of the drawing, for the timing signals TS1 to TS5 and the timing selection signals SEL1 to SEL5, only the part actually used for the write operation is displayed, and the pulses before and after that are omitted. It is.

  As shown in FIG. 11, when a row address is supplied from the outside in response to an ACT command and a column address is supplied in response to a WRIT command, a predetermined word line WL is activated in response to this. At the same time, the selection signal Ysel is activated. Then, write data is continuously supplied from the outside in synchronization with the clock signal CLK.

  Then, column selection signals CS1, CS2, CS3,... Corresponding to the write data D1, D2, D3,... Are sequentially activated, whereby each of the write control circuits WC1, WC2, WC3,. Timing signals TS1, TS2, TS3... Are selected. Such selection is performed by the selector 42 in the write control circuit WC as described above.

In the example shown in FIG. 11, the first and third data D1, D3 of the write data Data are “0”, and the second data D2 is “1”. For this reason, the write control circuits WC1 and WC3 activate the set pulse 31 over a period from the pulse P1 to the pulse P3, that is, for 4 clocks (= k ₁ ) in synchronization with the timing signals TS1 and TS3. On the other hand, the write control circuit WC2 activates the reset pulse 32 in a period from the pulse P1 to the pulse P2, that is, for one clock (= k ₂ ) in synchronization with the timing signal TS2. In FIG. 11, hatching is applied during a period in which the set pulse 31 or the reset pulse 32 is activated.

  As a result, the bit lines BL1 and BL3 are connected to the set potential wiring Vset over 4 clocks. As a result, the nonvolatile memory element PC included in the memory cell MC is given the temperature history shown by the curve b in FIG. 3, and as a result, the phase change material is crystallized. On the other hand, the bit line BL2 is connected to the reset potential wiring Vreset for one clock. Thereby, the temperature history shown by the curve a in FIG. 3 is given to the nonvolatile memory element PC included in the memory cell MC, and as a result, the phase change material becomes amorphous.

  As described above, in a state in which the predetermined word line WL is activated, the column selector 12 is used to sequentially select a predetermined write control circuit for each clock, and the memory cell to be crystallized takes 4 clocks. A set current is applied, and a reset current is applied to the memory cell to be amorphized over one clock. As a result, it appears to the outside that one write operation is completed in one clock regardless of the logic level of the write data Data. Therefore, compatibility with a memory that performs a write operation in synchronization with the clock signal CLK, such as a synchronous DRAM, can be ensured.

  Further, since the semiconductor memory device according to the present embodiment uses the timing signals TS1 to TS5, it is possible to ensure the pulse width of the set pulse even when the frequency of the clock signal CLK is increased. Become. For example, when the frequency of the clock signal CLK is doubled, the actual pulse width of the set pulse can be ensured by doubling the number of clocks from the pulse P1 to the pulse P3. Therefore, it is possible to correctly execute the set operation / reset operation regardless of the frequency of the clock signal CLK.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

For example, in the above embodiment performs the setting operation in the period from the pulse P1 which defines the k ₁ clock until the pulse P3, and performing a reset operation in the period from the pulse P1 which defines the k ₂ clock to the pulse P2 However, the method for defining the period during which the set operation / reset operation is performed is not limited to this.

Accordingly, as shown in FIG. 12, the active edge # 1 of clock signal CLK, and using a pulse group including a pulse P1~P3 synchronized to # 4 and # 5, from the pulse P1 which defines the _{k 1} clock to pulses P3 performs a set operation in the period, may be performed a reset operation in the period from the pulse P2 which defines a k ₂ clock to the pulse P3.

Furthermore, as shown in FIG. 13, the active edge # 1 of clock signal CLK, # 2, using a pulse group including a pulse P1~P4 synchronized with # 3 and # 5, the pulse P1 which defines the _{k 1} clock performs a set operation in the period until the pulse P4, it may be performed a reset operation in the period from the pulse P2 which defines a k ₂ clock to the pulse P3.

  In the above-described embodiment, the column selector 12 itself generates the column selection signals CS1 to CSn that are activated in parallel. However, the column selector 12 itself only has a timing signal that is the activation start point of the column selection signals CS1 to CSn. May be generated and expanded to generate column selection signals CS1 to CSn having a predetermined width. FIG. 14 is a block diagram showing a circuit necessary for such an operation, and FIG. 15 is a timing diagram showing the operation up to n = 5.

  The circuit shown in FIG. 14 includes a column selector 12a and pulse width adjustment circuits PW1 to PWn. The column selector 12a is a circuit that generates original signals CS1a to CSna, and the pulse widths of the original signals CS1a to CSna are expanded by the pulse width adjustment circuits PW1 to PWn, thereby generating column selection signals CS1 to CSn.

As shown in FIG. 15, the original signals CS1a to CSna (CS1a to CS5a shown in the figure) generated by the column selector 12a are activated every j clocks, and the pulse width is also j clocks. That is, the original signals CS1a to CSna are exclusively activated, and two or more original signals are not activated in parallel. The pulse width adjustment circuit PW1~PWn receiving these original signal CS1a~CSna starts the activation of the column selection signal CS1~CSn in response to activation of a corresponding original signal, active over _{k 1} clock Maintain the state.

  If the column selection signals CS1 to CSn are generated by such a method, the operation of the column decoder 12a and the like can be speeded up. In addition, circuit design is facilitated.

  In the above embodiment, j = 1 and the write control circuit is sequentially selected for each clock. However, write data is supplied in synchronization with both edges of the clock signal CLK as in a DDR synchronous DRAM. In this case, j = 0.5, and the write control circuit may be sequentially selected every 0.5 clock. That is, j may not be an integer.

  FIG. 16 is a timing chart showing an example of the operation when j = 0.5, and shows an example in which the write latency is set to 2 clocks. In the example shown in FIG. 16, the pulse P1 of the timing signal TS1 is synchronized with the half cycle # 1 of the clock signal CLK, the pulse P2 is synchronized with the half cycle # 3, and the pulse P3 is synchronized with the half cycle # 9. If such timing signals TS1, TS2,... Are generated by shifting by half a cycle, it is possible to realize the same operation as that of a DDR type synchronous DRAM as viewed from the outside.

  Furthermore, in the above embodiment, the write control circuits WC1 to WC5 are sequentially selected every j clocks to execute the write operation for a plurality of bit lines in parallel. In the present invention, such a parallel operation is performed. That is not essential.

11 Row selector 12, 12a Column selector 13 Timing signal generation circuit 21 Set transistor 22 Reset transistor 31 Set pulse 32 Reset pulse 41 Write data latch circuit 42 Selector 43 Shift register 44 Write pulse generator 51-56, 121, 122 Inside Signals 61-65 Transparent latch circuits 71-75 Transfer gates 81-83 Latch circuits with reset function 93-95 One-shot pulse generation unit 96 Reset circuit units 103-105 One-shot pulse 111, 112 SR latch 131, 132 NAND circuit BL bit Line CS Column selection signal Data Write data MC Memory cell PC Non-volatile memory element SEL Timing selection signal Tr Selection transistor TS Timing signal No. Vreset Reset potential wiring Vset Set potential wiring WC Control circuit WD Write driver WL Word line Y1-Yn Y switch Ysel Y selection signal PW Pulse width adjustment circuit

Claims (7)

The first memory is arranged at the intersection of the first word line, the first bit line intersecting with the first word line, and the first word line and the first bit line, and the time required for writing varies depending on the logical value. Elements,
A first bias node;
A first switch circuit connected between the first bit line and the first bias node and conducting between the first bit line and the first bias node during a write operation of the first memory element. When,
A first current supply circuit connected to the first bias node and applying a first write current to the first bias node when activated;
A second current supply circuit connected to the first bias node and applying a second write current to the first bias node when activated;
A first latch circuit that temporarily latches write data indicating one of the first and second logic values;
A first light control circuit,
The first write control circuit activates the first current supply circuit, deactivates the second current supply circuit according to the first logic value of the write data latched by the first latch circuit, and And deactivating the first current supply circuit and activating the second current supply circuit in accordance with the second logic value of the write data latched by the first latch circuit,
The first write control circuit receives each of the first write current application time and the second write current application time in response to receiving a first control signal periodically having first to third pulses. A semiconductor device, wherein The second memory is arranged at the intersection of the second word line, the second bit line intersecting with the second word line, and the second word line and the second bit line, and the time required for writing differs according to the logical value. Elements,
A second bias node;
A second switch circuit connected between the second bit line and the second bias node and conducting between the second bit line and the second bias node during a write operation of the second memory element; When,
A third current supply circuit which is connected to the second bias node and applies a third write current to the second bias node when activated;
A fourth current supply circuit which is connected to the second bias node and applies a fourth write current to the second bias node when activated;
A second latch circuit for temporarily latching write data indicating one of the first and second logic values;
A second light control circuit,
The second write control circuit activates the third current supply circuit, deactivates the fourth current supply circuit according to the first logic value of the write data latched by the second latch circuit, and In response to the second logical value of the write data latched by the second latch circuit, the third current supply circuit is deactivated, the fourth current supply circuit is activated,
The second write control circuit receives the second control signal having the fourth to sixth pulses periodically, respectively, and applies each of the third write current application time and the fourth write current application time. The semiconductor device according to claim 1, wherein:   3. The semiconductor device according to claim 2, wherein the first switch circuit and the second switch circuit are turned on in response to a common switch signal.   The first latch circuit and the first write control circuit are selected in common in response to receiving a predetermined logic value of a first column selection signal, and the second latch circuit and the second write control circuit are 4. The semiconductor device according to claim 1, wherein the semiconductor device is selected in common in response to receiving a predetermined logical value of a second column selection signal having a phase different from that of the first column selection signal. . The first write control circuit includes a first control signal that periodically includes the first to third pulses, a shift register that receives a feedback signal,
The output of the shift register and the output of the first latch circuit are received, the feedback signal is output, and the first signal indicating the application time of the first write current and the application time of the second write current are indicated. The semiconductor device according to claim 1, further comprising: a write pulse generator that generates a second signal.   The first voltage supply circuit includes a first transistor having a control terminal that receives a first signal indicating an application time of the first write current, and the second voltage supply circuit sets an application time of the second write current. 6. The semiconductor device according to claim 5, further comprising a second transistor having a control terminal for receiving a second signal to be displayed.   The semiconductor device according to claim 6, wherein the first and second transistors are transistors having the same conductivity type.

Images