JP2013143524A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves good wire bonding with a simple structure, and to provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device 1 includes: a wiring board 10 having a first surface 11 and a second surface 12, which are arranged opposite to each other, and connection pads 15; a first semiconductor chip 20 mounted on the first surface 11 of the wiring board 10; a second semiconductor chip 30 which is laminated and mounted on the first semiconductor chip 20 so that an overhang part 32 extending beyond the first semiconductor chip 20 in a direction parallel to the wiring board 10 is formed, the second semiconductor chip 30 having electrode pads 31; and wires 50, each of which electrically connects the connection pad 15 with the electrode pad 31. The electrode pads 31 of the second semiconductor chip 30 are formed on a surface of the overhang part 32 that faces the wiring board 10 side.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board and a manufacturing method thereof.

  Conventionally, in an MCP (Multi Chip Package) type semiconductor device incorporating a plurality of semiconductor chips, a stacked structure in which an upper semiconductor chip overhangs from a lower semiconductor chip has been disclosed (for example, Patent Document 1 to Patent Document 1). 3).

JP 2011-086943 A JP 2009-194189 A JP 2009-099697 A

  However, in the above-described conventional technology, the overhang portion of the upper semiconductor chip is supported by the support member made of bumps or bonding wires, but the portion supported by the support member and the portion not supported by the overhang portion There is a problem that when the thickness of the upper semiconductor chip is thin, there is a possibility that wire bonding cannot be satisfactorily performed.

  Therefore, the present invention solves the conventional problems, that is, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that realizes good wire bonding with a simple structure.

  The semiconductor device of the present invention includes a wiring board having first and second surfaces and connection pads opposite to each other, a first semiconductor chip mounted on the first surface of the wiring board, Second semiconductor chip having electrode pads stacked and mounted on the first semiconductor chip so as to form an overhang portion extending beyond the first semiconductor chip in a direction parallel to the wiring substrate And a wire for electrically connecting the connection pad and the electrode pad, and the electrode pad of the second semiconductor chip is formed on a surface of the overhang portion facing the wiring substrate side. This solves the above-mentioned problems.

  The method of manufacturing a semiconductor device of the present invention includes a step of preparing a wiring board having connection pads, a step of mounting a first semiconductor chip on the wiring board, and a surface provided with electrode pads of the second semiconductor chip. Mounting the second semiconductor chip on the first semiconductor chip so that the electrode pads are exposed with the circuit board facing toward the wiring board, and the connection pads of the wiring board and the first The problem mentioned above is solved by including the process of connecting the said electrode pad of 2 semiconductor chips with a wire.

  In the present invention, wire bonding can be performed in a state where the entire surface of the second semiconductor chip opposite to the surface on which the electrode pads are provided is held on the wire bonding stage. Further, it is possible to reliably suppress the occurrence of chip cracks in the overhang portion and realize good wire bonding.

1 is a plan view schematically showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device taken along the line A-A ′ in FIG. 1. FIG. 2 is a cross-sectional view of the semiconductor device at the B-B ′ line position in FIG. 1. It is process drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is process drawing which shows the die-bonding process and wire bonding process of the semiconductor device of 1st Embodiment. FIG. 5 is a plan view schematically showing a semiconductor device according to a second embodiment of the present invention. FIG. 7 is a cross-sectional view of the semiconductor device taken along the line A-A ′ in FIG. 6. FIG. 7 is a cross-sectional view of the semiconductor device at the B-B ′ line position in FIG. 6.

  Hereinafter, a plurality of embodiments of a semiconductor device of the present invention will be described with reference to the drawings.

  In the following description, the direction parallel to the wiring board is the first direction X, the direction orthogonal to the first direction X and parallel to the wiring board is the second direction Y, and the direction perpendicular to the wiring board is the third direction Z. It prescribes as

  A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS.

  The semiconductor device 1 of the present embodiment is configured as an MCP type semiconductor device. As shown in FIGS. 1 to 3, the wiring substrate 10, the first semiconductor chip 20, the second semiconductor chip 30, 1 wire 40, second wire 50, sealing resin 60, and external terminal 70.

  As shown in FIGS. 1 to 3, the wiring substrate 10 is formed in a substantially rectangular plate shape, and has a first opening 17 formed along both sides in the second direction Y, and the first direction. And a second opening 18 formed along both ends of X. As shown in FIGS. 2 and 3, the first opening 17 and the second opening 18 penetrate in the third direction Z, in other words, the second opening from the first surface 11 side of the wiring substrate 10. It penetrates to the surface 12 side.

  As shown in FIGS. 1 to 3, the wiring substrate 10 is formed on an insulating base 13 made of, for example, glass epoxy and formed in a substantially rectangular plate shape, and on the second surface 12 side of the insulating base 13. It has a wiring pattern and an insulating film 14 formed on the second surface 12 side of the insulating base 13.

  As shown in FIGS. 1 to 3, the wiring pattern of the wiring substrate 10 is formed in a region surrounded by the first opening 17 and the second opening 18 on the second surface 12 of the wiring substrate 10. ing. As shown in FIGS. 1 to 3, the wiring pattern of the wiring substrate 10 is arranged in a grid pattern with a plurality of connection pads 15 arranged in the vicinity of the first opening 17 and the second opening 18. The plurality of lands 16 are composed of wirings that electrically connect the connection pads 15 and the corresponding lands 16.

  The insulating film 14 is, for example, a solder resist film, and is selectively formed on the second surface 12 of the wiring substrate 10 so that the connection pads 15 and the lands 16 are exposed as shown in FIG.

  As shown in FIGS. 1 to 3, the first semiconductor chip 20 is formed in a substantially rectangular plate shape, and the longitudinal direction of the first semiconductor chip 20 is changed through an adhesive member 80 made of, for example, DAF (Die Attached Film) or paste. The circuit board 10 is mounted on the first surface 11 side of the wiring board 10 in the state of facing in the two directions Y.

  As shown in FIGS. 1 to 3, the first semiconductor chip 20 has a plurality of first electrode pads 21 formed along each short side thereof and a predetermined circuit facing the wiring substrate 10 side. In other words, the first semiconductor chip 20 is mounted on the wiring substrate 10 in a so-called face-down manner with the circuit surface facing the wiring substrate 10 side. As shown in FIG. 2, the first electrode pad 21 faces the first opening 17 in the third direction Z in a state where the first semiconductor chip 20 is mounted on the wiring substrate 10. As shown in FIG. 2, the first electrode pad 21 and the connection pad 15 are connected by a first wire 40 wired through the first opening 17.

  The second semiconductor chip 30 is formed the same as the first semiconductor chip 20. As shown in FIGS. 1 to 3, the second semiconductor chip 30 is formed in a substantially rectangular plate shape, and the first semiconductor chip 30 is in a state where the longitudinal direction thereof is directed to the first direction X via the adhesive member 80. The semiconductor chip 20 is stacked and mounted. As shown in FIG. 1, the second semiconductor chip 30 is rotated by 90 degrees with respect to the first semiconductor chip 20 in the plane defined by the first direction X and the second direction Y. It is stacked on the semiconductor chip 20. As shown in FIG. 3, the second semiconductor chip 30 has an overhang portion 32 that protrudes beyond both ends of the first semiconductor chip 20 in the first direction X.

  As shown in FIGS. 1 to 3, the second semiconductor chip 30 has a plurality of second electrode pads 31 formed along each short side thereof and a predetermined circuit facing the wiring substrate 10 side. In other words, the second semiconductor chip 30 is mounted on the wiring substrate 10 in a so-called face-down manner with the circuit surface facing the wiring substrate 10 side. As shown in FIG. 3, the second electrode pad 31 is provided in the overhang portion 32, and the second semiconductor chip 30 is mounted on the wiring substrate 10, and the second electrode pad 31 is inserted into the second opening 18 in the third direction Z. Opposite to. As shown in FIG. 3, the second electrode pad 31 and the connection pad 15 are connected by a second wire 50 wired through the second opening 18.

  The first wire 40 and the second wire 50 are made of, for example, a conductive metal such as Au. As shown in FIGS. 2 and 3, the first surface 11 side to the second surface 12 side of the wiring board 10 are used. It is wired so as not to exceed the external terminal 70 in the direction toward the.

  The sealing resin 60 is made of an insulating resin such as an epoxy resin. As shown in FIGS. 2 and 3, the first semiconductor chip 20 and the second semiconductor chip are formed on the first surface 11 side of the wiring substrate 10. 30, the first wire 40, the second wire 50, and a part of the first surface 11 of the wiring substrate 10, and on the second surface 12 side of the wiring substrate 10, The second wire 50 and a part of the second surface 12 of the wiring board 10 are covered. As described above, in the present embodiment, the sealing resin 60 passes through the first opening 17 and the second opening 18 as well as the first surface 11 side of the wiring board 10, and the second of the wiring board 10. By reaching the surface 12 side, the adhesion strength between the members is improved, and the reliability with respect to peeling is improved. Further, the sealing resin 60 is formed so as not to exceed the external terminal 70 in the direction from the first surface 11 side to the second surface 12 side of the wiring substrate 10 as shown in FIGS. In other words, the height of the protrusion of the sealing resin 60 from the second surface 12 of the wiring substrate 10 is set lower than the height of the external terminal 70. Thereby, it can be avoided that the protruding portion of the sealing resin 60 protruding from the second surface 12 of the wiring substrate 10 obstructs the mounting of the semiconductor device 1.

  In this embodiment, the external terminal 70 is configured as a solder ball and is mounted on the land 16 of the wiring board 10.

  Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described below with reference to FIGS. 4 (a) to 4 (e).

  First, FIG. 4A shows a wiring mother board 10a including a plurality of product formation regions R partitioned by dicing lines L. FIG. These product formation regions R are regions that are later cut individually along the dicing line L to become the wiring substrate 10. In each product formation region R, an insulating film 14, a connection pad 15, a land 16, a first opening 17, and a second opening 18 are formed.

  Next, as shown in FIG. 4B, the first semiconductor chip 20 and the second semiconductor chip 30 are sequentially mounted on the first surface 11 of the wiring board 10 (wiring mother board 10a). Using the first wire 40 and the second wire 50, the wiring substrate 10 (wiring mother substrate 10a), the first semiconductor chip 20 and the second semiconductor chip 30 are electrically connected. Details of the die bonding process and the wire bonding process shown in FIG. 4B will be described later with reference to FIG.

  Next, as shown in FIG. 4C, the sealing resin 60 is formed by performing a collective molding on the wiring motherboard 10a that has undergone the die bonding process and the wire bonding process. A transfer mold apparatus (not shown) including an upper mold (not shown) and a lower mold (not shown) is used for the batch molding. Specifically, in this collective mold, in a space formed by an upper mold (not shown) and a lower mold (not shown), a wiring mother board 10a that has undergone a die bonding process and a wire bonding process is disposed, and the space It is performed by allowing a thermosetting epoxy resin or the like to flow into the inside.

  Next, as shown in FIG. 4D, external terminals (solder balls) 70 are mounted on the lands 16 provided on the second surface 12 side of the wiring board 10 (wiring mother board 10a). The external terminal 70 can be mounted using, for example, a suction mechanism (not shown) provided with a plurality of suction holes (not shown) arranged in correspondence with the plurality of lands 16. In this case, a plurality of external terminals 70 are sucked and held by a suction mechanism (not shown), a flux is transferred and formed on the held external terminals 70, and are collectively mounted on the lands 16. Thereafter, the connection between the external terminal 70 and the land 16 is fixed by reflow processing.

  Next, as shown in FIG. 4E, the wiring mother board 10a and the sealing are formed using a dicing blade (not shown) in a state where a dicing tape (not shown) is attached to and supported by the sealing resin 60. The resin 60 is cut along the dicing line L. Thereby, the wiring mother board 10a is separated into pieces for each product forming region R, and then the separated wiring board 10 (wiring mother board 10a) and the sealing resin 60 are picked up from a dicing tape (not shown). Thus, the semiconductor device 1 as shown in FIGS. 1 to 3 is obtained.

  Next, a die bonding process and a wire bonding process of the semiconductor device 1 will be described below with reference to FIGS. 5 (a) to 5 (d).

  First, as shown in FIG. 5A, the first semiconductor chip 20 is mounted on the wiring board 10 (wiring mother board 10a). Specifically, as shown in FIG. 5A, the wiring board 10 (wiring mother board) placed on the die bonding stage S1 with the first surface 11 coated with the adhesive member 80 facing upward. 10a), the first semiconductor chip 20 held by the bonding tool T is lowered in the third direction Z with the surface on which the first electrode pads 21 are provided facing downward, whereby the wiring substrate 10 The first semiconductor chip 20 is mounted on the (wiring motherboard 10a). At this time, the first semiconductor chip 20 is mounted on the wiring substrate 10 (wiring mother substrate 10a) so that the first opening 17 and the first electrode pad 21 face each other in the third direction Z.

  Next, as shown in FIG. 5B, the connection pad 15 and the first electrode pad 21 are connected using the first wire 40. Specifically, as shown in FIG. 5B, the first semiconductor chip 20 and the wiring board 10 (wiring mother board 10a) with the surface on which the first electrode pads 21 are provided facing upward. Is placed on the wire bonding stage S2, and from the upper side in the third direction Z, the first wire 40 is subjected to thermocompression bonding while applying ultrasonic vibration to both ends of the first wire 40 using a capillary C as a pressing jig. The end of the wire 40 is bonded to the first electrode pad 21 and the connection pad 15. At this time, since the first electrode pad 21 is exposed to the upper side in the third direction Z through the first opening portion 17, one end of the first wire 40 and the first electrode pad 21 are joined. Can be easily achieved. In the present embodiment, the first electrode pad 21 is provided on the surface of the first semiconductor chip 20 facing the wiring substrate 10 (wiring mother substrate 10a), and the connection pad 15 is connected to the wiring substrate 10 ( 5 is provided on the second surface 12 of the wiring mother board 10a), whereby the wire loop portion 41 formed on the first wire 40 connecting the first electrode pad 21 and the connection pad 15 is formed as shown in FIG. As shown in (b), the wiring board 10 (wiring motherboard 10a) is positioned on the second surface 12 side.

  Next, as shown in FIG. 5C, the second semiconductor chip 30 is mounted on the first semiconductor chip 20. Specifically, as shown in FIG. 5C, the surface on which the second electrode pad 31 is provided faces downward with respect to the first semiconductor chip 20 placed on the die bonding stage S1. The second semiconductor chip 30 is mounted on the first semiconductor chip 20 by lowering the second semiconductor chip 30 held by the bonding tool T in the third direction Z in this state. At this time, as shown in FIG. 5C, the portion of the second semiconductor chip 30 provided with the second electrode pad 31 overhangs in the first direction X beyond both ends of the first semiconductor chip 20. The second semiconductor chip 30 is mounted on the first semiconductor chip 20 so that the second electrode pad 31 and the second opening 18 face each other in the third direction Z.

  Next, as shown in FIG. 5D, the connection pad 15 and the second electrode pad 31 are connected using the second wire 50. Specifically, as shown in FIG. 5D, the second semiconductor chip 30 and the first semiconductor chip 30 with the second electrode pad 31 provided on the second semiconductor chip 30 facing upward. After the semiconductor chip 20 and the wiring board 10 (wiring mother board 10a) are placed on the wire bonding stage S2, both ends of the second wire 50 are used from the upper side in the third direction Z by using the capillary C which is a pressing jig. The end of the second wire 50 is bonded to the second electrode pad 31 and the connection pad 15 by thermocompression bonding while applying ultrasonic vibration to the first electrode pad 31 and the connection pad 15. At this time, since the second electrode pad 31 is exposed to the upper side in the third direction Z through the second opening 18, the end of the second wire 50 and the second electrode pad 31 are joined. Can be easily achieved. In the present embodiment, the second electrode pad 31 is provided on the surface of the second semiconductor chip 30 facing the wiring board 10 (wiring mother board 10a), and the connection pad 15 is provided on the wiring board 10 ( A wire loop portion 51 formed in the second wire 50 connecting the second electrode pad 31 and the connection pad 15 is provided on the second surface 12 of the wiring mother board 10a). As shown to (d), it will be located in the 2nd surface 12 side of the wiring board 10 (wiring motherboard 10a).

  In the semiconductor device 1 of the present embodiment thus obtained, the second semiconductor chip 30 is mounted with the surface on which the second electrode pads 31 are provided facing the wiring substrate 10 as shown in FIG. By stacking and mounting on the wiring substrate 10, as shown in FIG. 5D, the entire surface of the surface of the second semiconductor chip 30 opposite to the surface on which the second electrode pads 31 are provided is disposed on the wire bonding stage S2. Since it is possible to perform wire bonding with the capillary C in a state of being held well above, generation of chip cracks in the overhang portion 32 during wire bonding can be suppressed. In addition, this makes it possible to satisfactorily apply a load and an ultrasonic wave to the overhang portion 32 of the second semiconductor chip 30 with the capillary C, improve the reliability of wire bonding, and improve the reliability of the semiconductor device 1. it can. Further, as described above, since the generation of chip cracks in the second semiconductor chip 30 is suppressed, there is no need to set the second semiconductor chip 30 thick in order to suppress chip cracks. 30 thickness reduction can be realized.

  Further, in the semiconductor device 1 of the present embodiment, the second semiconductor chip 30 is mounted in a state where the surface on which the second electrode pad 31 is provided faces the wiring substrate 10, thereby forming the second wire 50. As shown in FIG. 5D, the wire loop portion 51 is positioned on the second surface 12 side of the wiring board 10 on which the external terminals 70 are protruded. Thereby, in the semiconductor device 1 of the present embodiment, the wire loop portion 51 and the wire loop portion are utilized using the space on the second surface 12 side of the wiring substrate 10 (wiring mother substrate 10a) provided with the external terminals 70. Since the sealing resin 60 covering 51 can be disposed, the wire loop portion 51 is disposed on the surface opposite to the surface facing the wiring substrate 10 of the second semiconductor chip 30. The height of the semiconductor device 1 in the third direction Z can be avoided by an amount corresponding to the wire loop portion 51 and the sealing resin 60 that covers the wire loop portion 51, and the semiconductor device 1 can be thinned.

  In the semiconductor device 1 of the present embodiment, the wiring pattern of the wiring substrate 10 (connection pads 15, lands 16, wirings connecting the connection pads 15 and lands 16) is formed only on the second surface 12 of the wiring substrate 10. As a result, the thickness of the wiring board 10 in the third direction Z can be reduced as compared with the case where the wiring pattern is also formed on the first surface 11 of the wiring board 10.

  Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS.

  Here, in the semiconductor device according to the second embodiment, the first semiconductor chip is mounted face up (with the surface opposite to the circuit surface facing the wiring substrate) with respect to the wiring substrate. Only the part of the configuration of the wiring board is different from the first embodiment. Therefore, only the differences between the first embodiment and the second embodiment will be described below.

  First, in the wiring substrate 10 of the second embodiment, as shown in FIG. 7, the wiring pattern (connection pad 15, wiring) and the insulating film 14 are not only on the second surface 12 but also on the first surface 11. A via 19 is further provided to connect the wiring pattern on the first surface 11 side and the wiring pattern on the second surface 12 side.

  Further, as shown in FIG. 6, only the second openings 18 formed along the both ends in the first direction X are formed in the wiring board 10 of the second embodiment. The first opening 17 in the form is not formed.

  Further, as shown in FIG. 7, the first semiconductor chip 20 of the second embodiment has the first electrode pad 21 and a predetermined circuit on the surface opposite to the surface facing the wiring substrate 10 side. In other words, the first semiconductor chip 20 is mounted on the wiring substrate 10 in a so-called face-up state in which the surface opposite to the circuit surface faces the wiring substrate 10 side. As shown in FIG. 7, the first electrode pad 21 is connected to the connection pad 15 formed on the first surface 11 side of the wiring substrate 10 by the first wire 40.

  In the second embodiment thus obtained, in addition to the effects of the first embodiment, as shown in FIG. 6, the first opening 17 extending in the first direction X in the first embodiment. Is formed, and only the second opening 18 extending in the second direction Y is formed, so that the molten resin that is the raw material of the sealing resin 60 in the molding process flows along the second direction Y. Since it is possible to improve the fluidity of the molten resin in the molding process, it is possible to suppress the generation of voids during molding.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to the said embodiment, and can be variously changed in the range which does not deviate from the summary.

  In the above-described embodiment, the semiconductor device in which two semiconductor chips having the same pad arrangement are cross-stacked has been described. However, any semiconductor device may be used as long as the semiconductor chip having an overhang portion is stacked in multiple stages. You may apply.

  In the above-described embodiment, the lower semiconductor chip is connected to the wiring board by wire bonding. However, bump electrodes are provided on the electrode pads of the lower semiconductor chip and mounted on the wiring board by flip chip mounting. You may comprise.

  Moreover, although the wiring board which consists of a glass epoxy base material was demonstrated in embodiment mentioned above, you may apply to the flexible wiring board which consists of a polyimide base material.

  In the above-described embodiment, the BGA (ball grid array) type semiconductor device on which solder balls are mounted has been described. However, the present invention can also be applied to an LGA (land grid array) type semiconductor device.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Wiring board 10a ... Wiring mother board 11 ... 1st surface 12 ... 2nd surface 13 ... Insulating base material 14 ... Insulating film 15 Connection pad 16 ... Land 17 ... First opening 18 ... Second opening 19 ... Via 20 ... First semiconductor chip 21 ... First electrode pad DESCRIPTION OF SYMBOLS 30 ... 2nd semiconductor chip 31 ... 2nd electrode pad 32 ... Overhang part 40 ... 1st wire 41 ... Wire loop part 50 ... 2nd wire 51- .... Wire loop part 60 ... Sealing resin 70 ... External terminal 80 ... Adhesive member L ... Dicing line R ... Product formation area S1 ... Die bonding stage S2 ... Wire bonding The Over di C · · · capillary T · · · bonding tool X · · · first direction Y · · · second direction Z · · · third direction

Claims (5)

A wiring board having first and second surfaces opposite to each other and connection pads;
A first semiconductor chip mounted on the first surface of the wiring board;
A second semiconductor having electrode pads stacked and mounted on the first semiconductor chip so as to form an overhang portion that extends beyond the first semiconductor chip in a direction parallel to the wiring board. Chips,
A wire for electrically connecting the connection pad and the electrode pad;
The electrode pad of the second semiconductor chip is formed on a surface of the overhang portion facing the wiring board side.   The semiconductor device according to claim 1, wherein the wiring board has the connection pads on at least the second surface. The wiring board has an opening penetrating from the first surface side to the second surface side,
3. The electrode pad of the second semiconductor chip is provided at a position facing the opening of the wiring board in a direction perpendicular to the wiring board. The semiconductor device described. An external terminal provided on the second surface of the wiring board;
4. The wire according to claim 1, wherein the wire is wired so as not to exceed the external terminal in a direction from the first surface side toward the second surface side. 2. A semiconductor device according to item 1. Preparing a wiring board having connection pads;
Mounting a first semiconductor chip on the wiring board;
Mounting the second semiconductor chip on the first semiconductor chip so that the electrode pad is exposed in a state where the surface of the second semiconductor chip on which the electrode pad is provided faces the wiring substrate side. When,
A method for manufacturing a semiconductor device, comprising: connecting the connection pads of the wiring board and the electrode pads of the second semiconductor chip with wires.

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