JP2011258910A - 電磁気バンドギャップ構造物を含むemiノイズ遮蔽基板 - Google Patents
電磁気バンドギャップ構造物を含むemiノイズ遮蔽基板 Download PDFInfo
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0236—Electromagnetic band-gap structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】本発明によるEMIノイズ遮蔽基板は、上面に電子製品が搭載され、電子製品への信号伝達及び電力伝達のための回路が形成される第1基板領域と、第1基板領域の下面に位置し、第1基板領域から伝達されるEMIノイズの基板外部への放射を遮蔽するように帯域阻止周波数特性を有する電磁気バンドギャップ構造が挿入される第2基板領域とを含むことを特徴とする。
【選択図】図6
Description
420 第1誘電層
430 金属板
440 ステッチングビア
441 第1ビア
442 第2ビア
443 接続パターン
450 第1クリアランスホール
Claims (11)
- 上面に電子製品が搭載され、前記電子製品への信号伝達及び電力伝達のための回路が形成される第1基板領域と、
前記第1基板領域の下面に位置し、前記第1基板領域から伝達されるEMIノイズの基板外部への放射を遮蔽するように帯域阻止周波数特性を有する電磁気バンドギャップ構造が挿入される第2基板領域と、
を含むEMIノイズ遮蔽基板。 - 前記電磁気バンドギャップ構造は、
第1平面に位置する複数の導電板と、前記導電板のうちの隣接する2つの導電板間を夫々電気的に接続させるステッチングビアと、を含み、
前記ステッチングビアは、
誘電層を貫通し、一端が前記隣接する2つの導電板のうちの1つと接続する第1ビアと、
誘電層を貫通し、一端が前記隣接する2つの導電板のうちの他の1つと接続する第2ビアと、
前記導電板とは異なる平面に位置し、一端が前記第1ビアの他端と接続し、他端が前記第2ビアの他端と接続する導電性接続パターンと、
を含むことを特徴とする請求項1に記載のEMIノイズ遮蔽基板。 - 前記第1平面は、前記導電性接続パターンが位置する平面に比べ前記第1基板領域の上面からより遠く離れて位置することを特徴とする請求項2に記載のEMIノイズ遮蔽基板。
- 前記第1ビア及び前記第2ビアのうちの少なくとも1つが貫通する前記誘電層は、高誘電体からなることを特徴とする請求項2または3に記載のEMIノイズ遮蔽基板。
- 前記導電板は、前記第2基板領域の内部に位置し、
前記導電性接続パターンは、前記第1基板領域と前記第2基板領域との境界面または前記第1基板領域の内部の一平面に位置することを特徴とする請求項2から4の何れか1項に記載のEMIノイズ遮蔽基板。 - 前記電磁気バンドギャップ構造は、前記導電板が位置する前記第1平面を第1層とし、前記導電性接続パターンが位置する平面を第2層とする2層構造を有し、
前記2層構造の電磁気バンドギャップ構造は、前記第2基板領域の内部に、高さ方向に繰り返し積層形成されることにより、2の倍数層の構造に拡張されることを特徴とする請求項2から5の何れか1項に記載のEMIノイズ遮蔽基板。 - 前記電磁気バンドギャップ構造は、前記導電板が位置する前記第1平面と、前記導電性接続パターンが位置する平面との間に少なくとも1つの導電層を介在することにより3層以上の構造を有することを特徴とする請求項2から6の何れか1項に記載のEMIノイズ遮蔽基板。
- 前記導電板のうちの一部は、その他の導電板とは面積、形状、大きさのうちの少なくとも1つが異なるように製作されることを特徴とする請求項2から7の何れか1項に記載のEMIノイズ遮蔽基板。
- 前記導電板は、前記第2基板領域の全体領域にわたって配列位置されることを特徴とする請求項2から8の何れか1項に記載のEMIノイズ遮蔽基板。
- 前記導電板は、前記第2基板領域の一部領域に配列位置し、
前記導電板が配列位置する前記第2基板領域の前記一部領域は、前記第1基板領域から伝達されるEMIノイズの主要伝達経路を含むことを特徴とする請求項2から9の何れか1項に記載のEMIノイズ遮蔽基板。 - 前記第2基板領域の下面に位置し、前記第2基板領域から伝達されるEMIノイズの基板外部への放射を遮蔽するように帯域阻止周波数特性を有する電磁気バンドギャップ構造が挿入される第3基板領域をさらに含むことを特徴とする請求項1から10の何れか1項に記載のEMIノイズ遮蔽基板。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020100054057A KR20110134200A (ko) | 2010-06-08 | 2010-06-08 | 전자기 밴드갭 구조물을 포함하는 emi 노이즈 차폐 기판 |
| KR10-2010-0054057 | 2010-06-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2011258910A true JP2011258910A (ja) | 2011-12-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010203868A Pending JP2011258910A (ja) | 2010-06-08 | 2010-09-13 | 電磁気バンドギャップ構造物を含むemiノイズ遮蔽基板 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8699234B2 (ja) |
| JP (1) | JP2011258910A (ja) |
| KR (1) | KR20110134200A (ja) |
| CN (1) | CN102281748B (ja) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017034086A (ja) * | 2015-07-31 | 2017-02-09 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
| JP2019080029A (ja) * | 2017-10-19 | 2019-05-23 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 半導体パッケージ |
| WO2020213122A1 (ja) * | 2019-04-18 | 2020-10-22 | 三菱電機株式会社 | 信号伝送回路 |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101007288B1 (ko) * | 2009-07-29 | 2011-01-13 | 삼성전기주식회사 | 인쇄회로기판 및 전자제품 |
| CN103296008B (zh) * | 2012-02-22 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | Tsv或tgv转接板,3d封装及其制备方法 |
| CN103296009B (zh) * | 2012-02-22 | 2016-02-03 | 华进半导体封装先导技术研发中心有限公司 | 带有ebg的屏蔽结构、3d封装结构及其制备方法 |
| JP5710558B2 (ja) * | 2012-08-24 | 2015-04-30 | 株式会社東芝 | 無線装置、それを備えた情報処理装置及び記憶装置 |
| US10403973B2 (en) * | 2014-04-22 | 2019-09-03 | Intel Corporation | EBG designs for mitigating radio frequency interference |
| CN104105388B (zh) * | 2014-05-29 | 2017-03-15 | 北京宇航系统工程研究所 | 一种测量综合控制器的电磁屏蔽系统 |
| KR102252382B1 (ko) * | 2014-07-22 | 2021-05-14 | 엘지이노텍 주식회사 | 레이더 장치 |
| KR102528687B1 (ko) * | 2016-09-06 | 2023-05-08 | 한국전자통신연구원 | 전자기 밴드갭 구조물 및 그 제조 방법 |
| JP6809600B2 (ja) * | 2017-04-03 | 2021-01-06 | 株式会社村田製作所 | 高周波モジュール |
| US20240196525A1 (en) * | 2022-12-12 | 2024-06-13 | Rolls-Royce North American Technologies Inc. | Circuit board assembly having a security shield |
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-
2010
- 2010-06-08 KR KR1020100054057A patent/KR20110134200A/ko not_active Ceased
- 2010-09-13 JP JP2010203868A patent/JP2011258910A/ja active Pending
- 2010-09-19 CN CN201010288237.6A patent/CN102281748B/zh not_active Expired - Fee Related
-
2011
- 2011-01-05 US US12/984,935 patent/US8699234B2/en active Active
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| JP2008010859A (ja) * | 2006-06-02 | 2008-01-17 | Renesas Technology Corp | 半導体装置 |
| JP2009044151A (ja) * | 2007-08-07 | 2009-02-26 | Samsung Electro Mech Co Ltd | 電磁気バンドギャップ構造物及び印刷回路基板 |
| JP2009141326A (ja) * | 2007-12-07 | 2009-06-25 | Samsung Electro Mech Co Ltd | 電磁気バンドギャップ構造物及び印刷回路基板 |
| WO2009082003A1 (ja) * | 2007-12-26 | 2009-07-02 | Nec Corporation | 電磁バンドギャップ素子及びそれを用いたアンテナ並びにフィルタ |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017034086A (ja) * | 2015-07-31 | 2017-02-09 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
| JP2019080029A (ja) * | 2017-10-19 | 2019-05-23 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 半導体パッケージ |
| US10756023B2 (en) | 2017-10-19 | 2020-08-25 | Samsung Electronics Co., Ltd. | Semiconductor package |
| WO2020213122A1 (ja) * | 2019-04-18 | 2020-10-22 | 三菱電機株式会社 | 信号伝送回路 |
| JPWO2020213122A1 (ja) * | 2019-04-18 | 2021-09-13 | 三菱電機株式会社 | 信号伝送回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| US8699234B2 (en) | 2014-04-15 |
| KR20110134200A (ko) | 2011-12-14 |
| CN102281748B (zh) | 2014-06-25 |
| US20110299264A1 (en) | 2011-12-08 |
| CN102281748A (zh) | 2011-12-14 |
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