JP2011243116A - Memory system and data transfer method therefor - Google Patents

Abstract

A circuit area of a memory system is reduced.
A memory system includes an ECC encoder that generates a parity bit for error correction for a data portion, a nonvolatile memory that stores data in units of pages, and a parity bit used to store the data portion. An ECC decoder 18 for correcting an error, a first memory buffer 15 for temporarily storing a page read from the nonvolatile memory 11 or a frame transferred from the ECC encoder 17, and immediately before a parity bit is added. The second memory buffer 19 for temporarily storing the data portion of the data, or the data portion whose error has been corrected by the ECC decoder 18, and the data transfer between the nonvolatile memory 11 and the second memory buffer 19, and Data transfer control for serially accessing the first memory buffer 15 during a data copy operation And a 22.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a memory system and a data transfer method thereof.

  As a nonvolatile semiconductor memory, a NAND flash memory which is a kind of EEPROM (Electrically Erasable Programmable Read Only Memory) that electrically writes and erases data is known. NAND-type flash memory has been highly integrated, and one of the technologies for achieving high integration is multilevel. Multi-leveling refers to a mechanism in which data of 2 bits or more can be recorded when 1 bit data is normally recorded in one cell.

  For example, if it is possible to record 3-bit data (eight-value data) in one cell, a data unit is configured to include data in each of three pages, and an ECC parity bit is set for this data unit. In the case of addition, it is necessary to read out data for three pages from the NAND flash memory when reading data, and these three pages are stored in the memory buffer. Therefore, as the data size of one page increases, the capacity of the memory buffer increases and the circuit area of the memory buffer increases.

  Further, the multi-level flash memory takes time to read data. For this reason, it is conceivable to increase the reading speed by reading the next three pages of the currently processed three pages. In this case, however, a memory buffer having a capacity for six pages is required. The circuit area of the memory buffer is increased.

  Further, at the time of data copying, data reading from the memory buffer and data writing to the memory buffer are executed simultaneously. For this reason, the memory buffer needs to be composed of a memory having a dual port of a read port and a write port, and if this memory buffer having a dual port is used, the circuit scale increases.

JP 2003-233529 A

  Embodiments provide a memory system and a data transfer method thereof capable of reducing a circuit area.

  The memory system according to the embodiment includes an ECC encoder that generates a parity bit for error correction for a data portion, a frame is configured from the data portion and the parity bit, and a page is configured from a plurality of frames. A nonvolatile memory that stores data in units of pages, an ECC decoder that corrects an error in the data portion using the parity bit, a page read from the nonvolatile memory, or a frame transferred from the ECC encoder A first memory buffer that temporarily stores a data portion immediately before the parity bit is added, or a second memory buffer that temporarily stores a data portion in which an error is corrected by the ECC decoder, Controlling data transfer between the non-volatile memory and the second memory buffer; And it includes a data transfer controller for accessing said first memory buffer into serial in data copying operation.

1 is a block diagram showing a configuration of a memory system 10 according to a first embodiment. 2 is a circuit diagram showing a configuration of a memory cell array 12. FIG. FIG. 3 is a schematic diagram illustrating a data structure stored in a first memory buffer 15. 7 is a flowchart showing a data copy operation of the controller 13. 4 is a timing chart for explaining a data copy operation of the controller 13; 9 is a timing chart for explaining a data copy operation of the controller 13 according to the second embodiment. 4 is a timing chart for explaining a data copy operation of the controller 13; 4 is a timing chart for explaining a data copy operation of the controller 13;

  Hereinafter, embodiments will be described with reference to the drawings. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is specified by the shape, structure, arrangement, etc. of components. Is not to be done. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a memory system 10 according to the first embodiment. The memory system 10 includes a NAND flash memory 11 that is a nonvolatile semiconductor memory, and a controller 13 that controls the NAND flash memory 11. The memory system may be in the form of a memory card such as an SD card (registered trademark), or may be configured such that a set of a nonvolatile semiconductor memory and a controller is incorporated in an electronic device.

  The NAND flash memory 11 includes a memory cell array 12 in which memory cells are arranged in a matrix. FIG. 2 is a circuit diagram showing a configuration of the memory cell array 12.

  The memory cell array 12 includes j blocks BLK0 to BLKj-1 (j is an integer of 1 or more). The block BLK is a data erasing unit. Each block BLK includes m NAND strings arranged in order along the row direction (m is an integer of 1 or more). The selection transistor ST1 included in the NAND string has a drain connected to the bit line BL and a gate commonly connected to the selection gate line SGD. The selection transistors ST2 included in the NAND string have a source commonly connected to the source line SL and a gate commonly connected to the selection gate line SGS.

  Each memory cell transistor MT is composed of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a stacked gate structure formed on a p-type well. The stacked gate structure includes a charge storage layer (floating gate electrode) formed on a p-type well with a gate insulating film interposed therebetween, and a control gate electrode formed on the floating gate electrode with an inter-gate insulating film interposed therebetween. Contains. In the memory cell transistor MT, the threshold voltage changes according to the number of electrons stored in the floating gate electrode, and data is stored according to the difference in threshold voltage. The memory cell transistor MT may be configured to store binary data (1 bit data), or may be configured to store multilevel data (data of 2 bits or more). In the present embodiment, the memory cell transistor MT is assumed to store, for example, 3-bit data (8-value data) as multi-value data.

  In each NAND string, each of n (n is an integer of 1 or more) memory cell transistors MT is connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. Has been placed. That is, n memory cell transistors MT are connected in series in the column direction so that adjacent ones share a diffusion region (source region or drain region).

  In each NAND string, the control gate electrodes are connected to the word lines WL0 to WLn−1 in order from the memory cell transistor MT located closest to the source. Accordingly, the drain of the memory cell transistor MT connected to the word line WLn−1 is connected to the source of the selection transistor ST1, and the source of the memory cell transistor MT connected to the word line WL0 is connected to the drain of the selection transistor ST2. Yes.

  The word lines WL0 to WLn-1 connect the control gate electrodes of the memory cell transistors MT in common between the NAND strings in the block BLK. That is, the control gate electrodes of the memory cell transistors MT in the same row in the block are connected to the same word line WL. The m memory cell transistors MT connected to the same word line WL are handled as pages, and data is written and read for each page. In this embodiment, since one memory cell transistor MT stores 3-bit data, m memory cell transistors MT connected to the same word line WL store three pages.

  The bit lines BL0 to BLm-1 connect the drains of the selection transistors ST1 in common between the blocks BLK. That is, NAND strings in the same column in the blocks BLK0 to BLKj-1 are connected to the same bit line BL.

  Although not shown, the NAND flash memory 11 includes a circuit for writing, reading, and erasing data with respect to the memory cell array 12. For example, the NAND flash memory 11 holds a column decoder that selects a column of the memory cell array 12, a row decoder that selects a row of the memory cell array 12, a sense amplifier circuit for reading data from the memory cell, and read and write data. Includes data cache.

  The controller 13 includes a flash interface 14, a first memory buffer 15, a data selection circuit 16, an ECC (Error Checking and Correcting) encoder 17, an ECC decoder 18, a second memory buffer 19, a bus bridge 20, a system bus 21, and A data transfer control unit 22 is provided.

  The flash interface 14 executes interface processing with the NAND flash memory 11. Specifically, the flash interface 14 supplies commands and addresses to the NAND flash memory 11 and exchanges data with the NAND flash memory 11.

  The ECC encoder 17 receives the write data and generates an error correction code (parity bit) for the write data. The ECC encoder 17 generates a parity bit using a predetermined data size as a calculation unit. The parity bit is added to the write data and is written in the NAND flash memory 11 together with the write data. In the present embodiment, a frame is called by combining a data part as an ECC calculation unit and a parity bit. The ECC decoder 18 receives the read data and corrects an error in the read data using a parity bit added to the read data.

  The data selection circuit 16 sends write data sent from the ECC encoder 17 to the first memory buffer 15 during a data copy operation. Data copy is a process of moving all or part of the data stored in the first block of the NAND flash memory 11 to the second block. Since the NAND flash memory 11 can erase data only in units of blocks, when rewriting a part of pages in the first block, the page to be rewritten is written in the second block and rewritten in the first block. Unable pages are also written to the second block. Alternatively, in order to extend the life of the NAND flash memory, data copy is performed between the first block with high usage frequency and the second block with low usage frequency.

  The first memory buffer 15 temporarily stores read data from the NAND flash memory 11 or write data to which a parity bit is added by the ECC encoder 17 immediately before writing to the NAND flash memory 11. The first memory buffer 15 has a bank structure, and includes a plurality of banks including a first bank 15-1 and a second bank 15-2. When multi-valued data is read from the NAND flash memory 11, it takes time because the reading process is complicated. Therefore, in this embodiment, the data for three pages are alternately stored in the first bank 15-1 and the second bank 15-2, so that the reading time can be shortened.

  The input / output port (I / O port) of the first memory buffer 15 is a single port. Accordingly, writing and reading cannot be performed simultaneously on the first memory buffer 15, and when accessing the first memory buffer 15, only serial access, that is, only one of writing and reading is possible. . When the first memory buffer 15 has a bank structure as in the present embodiment, each of the first bank 15-1 and the second bank 15-2 has a single port structure. By making the first memory buffer 15 a single port, the circuit area can be reduced as compared with the case where the first memory buffer 15 is a double port.

  The second memory buffer 19 temporarily stores the write data immediately before the parity bit is added or the read data that has been corrected by the ECC decoder 18. Each of the memory buffers 15 and 18 is constituted by a RAM, for example. The bus bridge 20 executes interface processing between the second memory buffer 19 and the system bus 21.

  The data transfer control unit 22 executes data transfer processing between the NAND flash memory 11 and the system bus 21 by hardware processing. For this purpose, the data transfer control unit 22 sends a control signal to each module shown in FIG. 1 and receives a status flag signal from each module. The data transfer control unit 22 controls data transfer while confirming the data transfer status of each module based on the status flag signal.

  In addition, although not shown, the system bus 21 is connected to a central processing unit (CPU) and a read only memory (ROM). The CPU controls the overall operation of the memory system 10 using firmware stored in the ROM. The CPU sends a control signal to the data transfer control unit 22 via a control bus (not shown), and exchanges data with various modules via the system bus 21. The system bus 21 is also connected to a RAM (Random Access Memory) necessary for the operation of the memory system 10 and a host interface.

  FIG. 3 is a schematic diagram illustrating the data structure stored in the first memory buffer 15. As described above, in this embodiment, since one memory cell transistor MT stores 3-bit data, three pages (first page to third page) from m memory cell transistors MT connected to the same word line WL. Page) is read. These three pages are stored in one bank of the first memory buffer 15. In FIG. 3, one horizontal row is one page.

  Since the first to third pages have different error rates, if the frames are allocated within the same page, the error rates are different between frames. For this reason, the reliability of the data stored in the NAND flash memory 11 is lowered. Therefore, in the present embodiment, the first page to the third page are divided into a plurality of parts in the vertical direction, and a frame is defined over the first page to the third page. Thereby, since the error occurrence rate can be leveled between frames, data reliability can be improved. As shown in FIG. 3, the first page to the third page are configured by collecting a plurality of frames (F0 to Fi: i is an integer of 1 or more), and one frame includes a data portion (data portions 1 to 1). It consists of a data part 3) and a parity part.

(Operation)
Next, the operation of the memory system 10 configured as described above will be described. FIG. 4 is a flowchart showing the data copy operation of the controller 13. FIG. 5 is a timing chart for explaining the data copy operation of the controller 13. For example, it is assumed that 3 pages are composed of (i + 1) frames F0 to Fi.

  First, the flash interface 14 reads out three pages from the NAND flash memory 11 (step S101). Subsequently, the data transfer control unit 22 transfers the three pages read from the NAND flash memory 11 to the first memory buffer 15 (specifically, the first bank 15-1). As a result, the three pages read from the NAND flash memory 11 are stored in the first memory buffer 15 (step S102).

  Subsequently, the data transfer control unit 22 transfers the frame F0 stored in the first memory buffer 15 to the ECC decoder 18 (step S103). Subsequently, the ECC decoder 18 corrects an error in the data portion in the frame F0 using the parity bit in the frame F0 (step S104).

  Subsequently, the data transfer control unit 22 transfers the data part in the frame F0 for which error correction has been completed to the second memory buffer 19 (step S105). The second memory buffer 19 temporarily stores the data part transferred from the ECC decoder 18. The storage area of the second memory buffer 19 is, for example, one frame.

  Subsequently, the data transfer control unit 22 transfers the data part stored in the second memory buffer 19 to the ECC encoder 17 (step S106). Subsequently, the ECC encoder 17 generates a parity bit for the data portion transferred from the ECC encoder 17 (step S107).

  Subsequently, the data transfer control unit 22 transfers the frame F <b> 0 configured by adding a parity bit to the data unit to the data selection circuit 16. The data selection circuit 16 selects the frame F0 and transfers it to the first bank 15-1 of the first memory buffer 15. Accordingly, the frame F0 is transferred from the ECC encoder 17 to the first bank 15-1 of the first memory buffer 15 (step S108).

  Thereafter, the frames F1 to Fi are sequentially transferred from the first bank 15-1 of the first memory buffer 15 to the ECC decoder 18, the second memory buffer 19 and the ECC encoder in the same procedure as steps S103 to S108. Then, the data is transferred again to the first bank 15-1 of the first memory buffer 15 (step S109).

  Subsequently, the data transfer control unit 22 transfers the three pages stored in the first bank 15-1 of the first memory buffer 15 to the flash interface 14. The flash interface 14 writes these three pages into the NAND flash memory 11 (step S110). In this way, the copy operation of the NAND flash memory 11 is completed.

  In addition, after three pages are read from the NAND flash memory 11 to the first bank 15-1 of the first memory buffer 15, the first flash memory 11 from the NAND flash memory 11 continues to the first of the first memory buffer 15. The next three pages are read into the bank 15-2. As a result, the copying operation for the next three pages can be executed immediately after the copying operation for the first three pages is completed, so that the copying operation can be speeded up.

  In this way, one frame of data is transferred from the first memory buffer 15 to the ECC decoder 18, and the data portion that has been error-corrected by the ECC decoder 18 is temporarily stored in the second memory buffer 19. Data transfer (1)). Next, the data part stored in the second memory buffer 19 is transferred to the ECC encoder 17, and a parity bit is added to the data part by the ECC encoder 17, so that one frame consisting of the data part and the parity bit is again the first frame. The data is temporarily stored in the memory buffer 15 (hereinafter, data transfer (2)). The data transfer control unit 22 determines whether to execute data transfer (1) or data transfer (2) based on the priority order. Therefore, as shown in FIG. 5, the data transfer control unit 22 repeats data transfer (1) and data transfer (2), so that the first memory buffer 15 is serially accessed.

  Next, a data read operation from the NAND flash memory 11 will be described. Data read from the NAND flash memory is temporarily stored in the first memory buffer 15 via the flash interface 14. In this data transfer, three pages of data are transferred continuously. Thereafter, data is transferred from the first memory buffer 15 to the ECC decoder 18 in units of one frame, and after the data correction is completed, the corrected data is temporarily stored in the second memory buffer 19. Then, data is transferred from the second memory buffer 19 to the system bus 21 via the bus bridge 20. By repeating this operation for the number of frames of 3 pages, the operation of reading 3 pages from the NAND flash memory 11 is completed.

  Next, a data write operation to the NAND flash memory 11 will be described. One frame of data input from the system bus 21 side is temporarily stored in the second memory buffer 19. The data stored in the second memory buffer 19 is transferred to the ECC encoder 17 to generate a parity bit of the data part, and one frame consisting of the data part and the parity bit is temporarily stored in the first memory buffer 15. . This operation is repeated for the number of frames of 3 pages. Thereafter, three pages of data are written from the first memory buffer 15 to the NAND flash memory 11 via the flash interface 14. Data transfer control necessary for such read and write operations is executed by the data transfer control unit 22.

(effect)
As described above in detail, in the first embodiment, three pages read from the NAND flash memory 11 are temporarily stored in the first memory buffer 15 in the data copy operation of the NAND flash memory 11. Then, the data transfer control unit 22 transfers data in the order of the ECC decoder 18, the second memory buffer 19, the ECC encoder 17, and the first memory buffer 15 in units of one frame, so that the first memory buffer 15 Serial access.

  Therefore, according to the first embodiment, the input / output port of the first memory buffer 15 can be a single port. Thereby, the circuit area of the first memory buffer 15 can be reduced, and as a result, the circuit area of the memory system 10 can be reduced.

  In addition, the memory cell transistor MT can store a plurality of bits (in this embodiment, 3 bits as an example). For this reason, the first memory buffer 15 temporarily stores three pages in one data transfer. To do. A frame made up of a data part and a parity bit, which is an ECC calculation unit, is configured to include a part of each of the three pages. Thereby, even when the error occurrence rate differs between pages, the error occurrence rate can be leveled between frames. For this reason, the reliability of the data stored in the NAND flash memory 11 can be improved.

  The first memory buffer 15 has a bank structure. Therefore, after reading three pages from the NAND flash memory 11 to the first bank, it is possible to start reading the next three pages to the second bank continuously. As a result, it is possible to increase the reading speed, and consequently to increase the data copy operation.

  In addition, the data transfer control unit 22 performs data transfer processing between the NAND flash memory 11 and the system bus 21. That is, since the CPU does not have to perform data transfer processing between the NAND flash memory 11 and the system bus 21, the processing load on the CPU can be reduced.

[Second Embodiment]
The data transfer unit at the time of data copying is not limited to one frame as in the first embodiment, and other data sizes can be used. The second embodiment shows another example of a data transfer unit at the time of data copying.

  FIG. 6 is a timing chart for explaining the data copy operation of the controller 13 according to the first example. As shown in FIG. 6, the first memory buffer 15 can be serially accessed in units of two frames. In this case, the processes in steps S103 to S108 may be performed in two frames in the flowchart of FIG. In the first example, the storage capacity of the second memory buffer 19 is 2 frames.

  FIG. 7 is a timing chart for explaining the data copy operation of the controller 13 according to the second example. In the second example, the storage capacity of the second memory buffer 19 is 2 frames. As shown in FIG. 7, data transfer (1) is executed for the first two frames, and when the second memory buffer 19 is full, data transfer (2) and data transfer (1) in units of one frame. May be repeated.

  FIG. 8 is a timing chart for explaining the data copy operation of the controller 13 according to the third example. The storage capacity of the second memory buffer 19 is 3 pages (F0 to Fi). In this case, as shown in FIG. 8, data transfer (1) may be continuously performed for three pages, and then data transfer (2) may be continuously performed for three pages.

  Even when the data transfer described in the second embodiment is executed, the same effect as in the first embodiment can be obtained.

  The present invention is not limited to the above embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. Further, the above embodiments include inventions at various stages, and are obtained by appropriately combining a plurality of constituent elements disclosed in one embodiment or by appropriately combining constituent elements disclosed in different embodiments. Various inventions can be configured. For example, even if some constituent elements are deleted from all the constituent elements disclosed in the embodiments, the problems to be solved by the invention can be solved and the effects of the invention can be obtained. Embodiments made can be extracted as inventions.

  BLK ... block, MT ... memory cell transistor, ST1, ST2 ... select transistor, BL ... bit line, WL ... word line, SL ... source line, SGD, SGS ... select gate line, 10 ... memory system, 11 ... NAND flash Memory, 12 ... Memory cell array, 13 ... Controller, 14 ... Flash interface, 15 ... First memory buffer, 16 ... Data selection circuit, 17 ... ECC encoder, 18 ... ECC decoder, 19 ... Second memory buffer, 20 ... Bus bridge, 21... System bus, 22.

Claims (6)

An ECC encoder that generates parity bits for error correction for the data portion;
A non-volatile memory configured to form a frame from the data portion and the parity bit, to form a page from a plurality of frames, and to store data in units of pages,
An ECC decoder for correcting an error in the data portion using the parity bit;
A first memory buffer for temporarily storing a page read from the non-volatile memory or a frame transferred from the ECC encoder;
A second memory buffer for temporarily storing a data part immediately before the parity bit is added or a data part in which an error is corrected by the ECC decoder;
A data transfer control unit that controls data transfer between the non-volatile memory and the second memory buffer and serially accesses the first memory buffer during a data copy operation;
A memory system comprising: The nonvolatile memory includes a plurality of memory cells capable of storing n-bit data (n is an integer of 2 or more), and stores data in units of n pages.
The memory system according to claim 1, wherein the first memory buffer temporarily stores n pages read from the nonvolatile memory.   The memory system according to claim 2, wherein the frame is configured to include a part of each of the n pages.   The data transfer control unit includes the nonvolatile memory, the first memory buffer, the ECC decoder, the second memory buffer, the ECC encoder, the first memory buffer, and the nonvolatile memory during the data copy operation. 4. The memory system according to claim 1, wherein data transfer is performed in the order of the memories. A data transfer method for a memory system,
The memory system includes:
An ECC encoder that generates parity bits for error correction for the data portion;
A non-volatile memory configured to form a frame from the data portion and the parity bit, to form a page from a plurality of frames, and to store data in units of pages,
An ECC decoder for correcting an error in the data portion using the parity bit;
A first memory buffer for temporarily storing a page read from the non-volatile memory or a frame transferred from the ECC encoder;
A second memory buffer that temporarily stores a data part immediately before the parity bit is added or a data part in which an error is corrected by the ECC decoder;
The data transfer method includes:
Controlling data transfer between the non-volatile memory and the second memory buffer;
Serially accessing the first memory buffer during a data copy operation;
A data transfer method for a memory system, comprising:   The step of controlling the data transfer includes the nonvolatile memory, the first memory buffer, the ECC decoder, the second memory buffer, the ECC encoder, the first memory buffer, 6. The data transfer method for a memory system according to claim 5, further comprising a step of executing data transfer in the order of the nonvolatile memory.

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