JP2011100876A - P-channel nonvolatile memory and semiconductor device, and method of manufacturing p-channel nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a P-channel nonvolatile memory whose rewrite voltage is reducible and a semiconductor device, and a method of manufacturing the P-channel nonvolatile memory. <P>SOLUTION: The P-channel nonvolatile memory includes an N-type well region 2 provided on a silicon substrate 1, a first P-type diffusion region (source) and a second P-type diffusion region (drain) provided in the N-type well region 2 in a mutually isolated state, a tunnel insulating film 14b provided on the second P-type diffusion region, a gate insulating film 14a provided on a region of the N-type well region 2 sandwiched between the first P-type diffusion region and second P-type diffusion region (namely, a region serving as a channel), and a floating gate electrode 15 provided continuously from on the gate insulating film 14a to on the tunnel insulating film 14b, wherein the second P-type diffusion region is arranged over an entire region right below the tunnel insulating film 14b. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a P-channel nonvolatile memory, a semiconductor device, and a method for manufacturing a P-channel nonvolatile memory.

8A and 8B are a cross-sectional view and a main part enlarged view showing a configuration example of a semiconductor device 200 according to a conventional example.
As shown in FIG. 8A, the semiconductor device 200 includes an N-channel nonvolatile memory 110 and an N-channel select gate transistor 120, and one memory cell is constituted by these two elements. .
Among these, the N-channel nonvolatile memory 110 includes low-concentration N-type diffusion regions (N− regions) 108 and 112 formed on a single crystal P-type silicon substrate (Psub) 101, and the N− High-concentration N-type diffusion regions (N + regions) 109 and 113 formed in the regions 108 and 112, an insulating film 114 formed on the silicon substrate 101, and a floating gate electrode formed on the insulating film 114, respectively. 115, an interelectrode insulating film 116 formed on the upper surface and side surfaces of the floating gate electrode 115, and a control gate electrode 117 formed so as to cover the floating gate electrode 115 via the interelectrode insulating film 116. .

  Here, the insulating film 114 has a thick film portion 114 a and a thin film portion 114 b, the thick film portion 114 a is located on the P-type silicon substrate 101, and the thin film portions 114 b are all located on the N− region 112. ing. As a result, the thick film portion 114a functions as a gate insulating film, and the thin film portion 114b functions as a tunnel insulating film.

When data is written in the N-channel nonvolatile memory 110, a positive voltage is applied to the control gate electrode 117, and the N-type nonvolatile memory 110 causes an N- Electrons are injected from the region 112 into the floating gate electrode 115 via the tunnel insulating film 114b. That is, electrons which are majority carriers in the N− region 112 are injected from the N− region 112 into the floating gate electrode 115 via the tunnel insulating film 114b.
As a result, the potential of the floating gate electrode 115 changes and the threshold voltage of the N-channel nonvolatile memory 110 changes, whereby data “1” or “0” is stored. In addition, the structure as shown to Fig.8 (a) and (b) is disclosed by patent document 1, for example.

Japanese Patent No. 2604863

Incidentally, in the semiconductor device 200 shown in FIGS. 8A and 8B, the tunnel insulating film 114b needs to have a thickness of about 10 nm. The reason for this is to prevent electrons stored in the floating gate electrode 115 from being lost due to the Fowler-Nöderheim tunnel current in the data retention state. Therefore, when writing data into the N-channel non-volatile memory 110, it is necessary to apply a certain amount of voltage to the control gate electrode 117. For example, in order to correctly write data to the N-channel nonvolatile memory 110, it is necessary to apply a voltage of about 20 V to the control gate electrode.
Accordingly, the present invention has been made in view of such circumstances, and a P-channel nonvolatile memory and a semiconductor device, a P-channel, which can reduce a voltage required for data rewriting (that is, a rewriting voltage). An object of the present invention is to provide a method for manufacturing a type nonvolatile memory.

In order to solve the above problem, the present inventor makes the diffusion region immediately below the tunnel insulating film P-type instead of N-type, and uses electrons that are minority carriers in the P-type diffusion region as injection seeds. It has been found that the thickness of the tunnel insulating film can be made thinner than before, and as a result, the rewriting voltage in the nonvolatile memory can be lowered.
That is, the P-channel nonvolatile memory according to the present invention includes an N-type diffusion region provided in a semiconductor substrate, a first P-type diffusion region provided in a state separated from each other in the N-type diffusion region, and a first 2 P-type diffusion regions, a tunnel insulating film provided on the second P-type diffusion region, and the first P-type diffusion region and the second P-type diffusion of the N-type diffusion regions A gate insulating film provided on a region sandwiched between the regions, and a floating gate electrode provided continuously from the gate insulating film to the tunnel insulating film, the second P-type diffusion The region is arranged in the entire region immediately below the tunnel insulating film.

  With such a configuration, for example, as shown in FIG. 2 to be described later, due to the work function difference between the N-type diffusion region and the second P-type diffusion region, the floating gate electrode is transferred to the second P-type diffusion region. The energy barrier is high, and electrons stored in the floating gate electrode are unlikely to escape to the second P-type diffusion region via the tunnel insulating film. Speaking of a specific structure, since the entire region immediately below the tunnel insulating film is the second P-type diffusion region, electrons are unlikely to escape from the floating gate electrode to the substrate side. Therefore, the tunnel insulating film can be thinned and the rewriting voltage can be lowered.

  In the P-channel nonvolatile memory, the tunnel insulating film may be smaller in thickness than the gate insulating film. With such a configuration, the rewrite voltage can be lowered by reducing the thickness of only the tunnel insulating film without damaging the electrical characteristics such as withstand voltage and leakage current depending on the thickness of the gate insulating film. In other words, when the tunnel insulating film and the gate insulating film have the same thickness, if the tunnel insulating film is made thinner, the gate insulating film is also made the same thickness. There is a possibility that the breakdown voltage of the gate insulating film is lowered or the leakage current is increased. On the other hand, according to the present invention, it is possible to make only the tunnel insulating film thinner while the gate insulating film has a certain thickness or more. Therefore, the rewriting voltage can be lowered without impairing the electrical characteristics depending on the thickness of the gate insulating film.

  The P-channel nonvolatile memory may include an interelectrode insulating film provided on the floating gate electrode and a control gate electrode provided on the interelectrode insulating film. . With such a configuration, for example, by applying a positive voltage to the control gate electrode, electrons can be injected from the second P-type diffusion layer to the floating gate electrode, and data can be written. Further, by applying a zero or negative voltage to the control gate electrode, electrons can be discharged from the floating gate electrode to the second P-type diffusion layer, and data can be erased.

In the P-channel nonvolatile memory, the floating gate electrode may be made of an N-type semiconductor. With such a configuration, since the energy barrier from the floating gate electrode to the second P-type diffusion region can be further increased, the tunnel insulating film can be further thinned and the rewriting voltage can be further decreased. be able to.
Further, in the above P channel type nonvolatile memory, electrons are injected from the second P type diffusion region into the floating gate electrode by the FN tunnel phenomenon via the tunnel insulating film, so that the P channel type Data may be written to the nonvolatile memory.

  A P-channel non-volatile memory according to another aspect of the present invention includes an N-type diffusion region provided in a semiconductor substrate and a first P-type diffusion region provided in a separated state within the N-type diffusion region. And the second P-type diffusion region, and the second P-type diffusion region from the region sandwiched between the first P-type diffusion region and the second P-type diffusion region of the N-type diffusion region. And a floating gate electrode provided continuously over the diffusion region via an insulating film, the insulating film having a thick film portion and a thin film portion, and the thick film portion is on the N-type diffusion region The thin film portion is provided only on the second P-type diffusion region, and electrons are transferred from the second P-type diffusion region to the floating gate electrode due to the FN tunnel phenomenon passing through the thin film portion. By being injected, the P-channel nonvolatile memory Wherein the data is written.

  With such a configuration, for example, as shown in FIG. 2 to be described later, due to a work function difference between the N-type diffusion region and the second P-type diffusion region, an energy barrier from the floating gate electrode to the N-type diffusion region. However, the energy barrier from the floating gate electrode to the second P-type diffusion region is higher. This makes it difficult for electrons stored in the floating gate electrode to escape to the second P-type diffusion region via the insulating film. Therefore, the insulating film can be thinned and the rewriting voltage can be lowered.

Further, the insulating film (that is, the tunnel insulating film) on the second P-type diffusion region is a thin film portion, and the insulating film (that is, the gate insulating film) on the N-type diffusion region is a thick film portion. The rewriting voltage can be lowered without impairing electrical characteristics such as a withstand voltage and a leakage current depending on the thickness of the insulating film.
A semiconductor device according to still another aspect of the present invention includes the P-channel nonvolatile memory described above and a P-channel transistor provided on the semiconductor substrate, the drain of the P-channel nonvolatile memory, The source of the P-channel transistor is electrically connected.

  With such a configuration, for example, a P-channel transistor can function as a selection gate transistor. One P-channel transistor (that is, a selection gate transistor) and one P-channel nonvolatile memory can constitute one memory cell. Such a memory cell can be applied to, for example, a NAND type nonvolatile memory using the FN tunnel phenomenon.

The semiconductor device may further include a third P-type diffusion region provided in the second P-type diffusion region and having a P-type impurity concentration higher than that of the second P-type diffusion region, The third P-type diffusion region may be the drain of the P-channel nonvolatile memory and the source of the P-channel transistor.
With such a configuration, the area of the P-type diffusion region can be reduced compared to the case where the drain of the P-channel type nonvolatile memory and the source of the P-channel type transistor are composed of separate P-type diffusion regions. it can. Further, wiring for electrically connecting the drain of the memory and the source of the transistor is unnecessary. Therefore, it is possible to contribute to the reduction of the area occupied by the memory cell.

According to still another aspect of the present invention, there is provided a method for manufacturing a P-channel nonvolatile memory, the step of forming an N-type diffusion region in a semiconductor substrate, and a first P-type diffusion region and a first P-type diffusion region in the N-type diffusion region. Forming two P-type diffusion regions apart from each other, forming a tunnel insulating film only on the second P-type diffusion region, and the first P of the N-type diffusion region Forming a gate insulating film having a thickness larger than that of the tunnel insulating film on a region sandwiched between the type diffusion region and the second P-type diffusion region, and the tunnel insulating film from above the gate insulating film. And a step of continuously forming floating gate electrodes over the top.
With such a method, it is possible to provide a P-channel nonvolatile memory in which the rewrite voltage is lowered without impairing the electrical characteristics depending on the thickness of the gate insulating film.

  According to the present invention, for example, the rewrite voltage (that is, the voltage that needs to be applied to the control gate electrode or the second P-type diffusion region at the time of data rewrite) can be lowered to 14 V or less. As a result, the size of the nonvolatile memory and the peripheral circuit can be reduced.

FIG. 6 illustrates a configuration example of a semiconductor device 100 according to an embodiment. 3 is a diagram showing an energy band of a P-channel nonvolatile memory 10. FIG. The figure which shows the rewriting characteristic of a non-volatile memory. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 (part 1); FIG. 2 is a diagram illustrating a method for manufacturing the semiconductor device 100 (No. 2). FIG. 3 is a diagram illustrating a method for manufacturing the semiconductor device 100 (No. 3). FIG. 4 is a diagram illustrating a method for manufacturing the semiconductor device 100 (part 4); The figure which shows the structural example of the semiconductor device 100 which concerns on a prior art example. The figure which shows the energy band of the N channel type non-volatile memory 110.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
[Configuration example of semiconductor device]
1A and 1B are cross-sectional views showing a configuration example of a semiconductor device 100 according to an embodiment of the present invention. Specifically, FIG. 1A shows one memory cell including a P-channel nonvolatile memory 10 and a select gate transistor 20. FIG. 1B is an enlarged view of a main part of the P-channel nonvolatile memory 10 shown in FIG.

As shown in FIG. 1A, the semiconductor device 100 includes a single crystal P-type silicon substrate 1 (Psub) 1, an N-type well region (Nwell) 2 formed on the silicon substrate 1, and A P-channel nonvolatile memory 10 formed in the N-type well region 2 and a P-channel select gate transistor 20 formed in the N-type well region 2 are provided.
Among these, the N-type well region 2 is a diffusion layer containing an N-type impurity such as phosphorus or arsenic. In this N-type well region 2, an N− region 3 containing a low concentration of N-type impurities is provided. In this N− region 3, an N + region 4 containing a high concentration of N-type impurities is provided. ing. A predetermined voltage can be applied to the N-type well region 2 through the N + region 4 and the N− region 3.

The P-channel nonvolatile memory 10 includes a first P-type diffusion region and a second P-type diffusion region, a gate insulating film 14a, a tunnel insulating film 14b, a floating gate electrode 15, and an interelectrode insulating film. 16 and a control gate electrode 17.
Here, the first P-type diffusion region and the second P-type diffusion region are diffusion layers containing, for example, a P-type impurity such as boron, and are provided in a state separated from each other in the N-type well region 2. Yes. As shown in FIG. 1A, the first P-type diffusion region has a P− region 8 containing a P-type impurity at a low concentration and a P + region 9 containing a P-type impurity at a high concentration. The second P-type diffusion region has a P− region 12 containing P-type impurities at a low concentration and a P + region 13 containing P-type impurities at a high concentration.

The first P-type diffusion region is used as a source (S) of the P-channel nonvolatile memory 10, for example, and the second P-type diffusion region is used as a drain (D) of the P-channel nonvolatile memory 10, for example. As will be described later, the second P-type diffusion region is also used as the source of the selection gate transistor 20 (that is, the second P-type diffusion region includes the P-channel nonvolatile memory 10 and the selection gate transistor 20). And shared with.)
The gate insulating film 14 a is provided on a region of the N-type well region 2 sandwiched between the P− region 8 and the P− region 12 (that is, a region that becomes a channel of the P-channel nonvolatile memory 10). For example, a silicon oxide film. The tunnel insulating film 14b is an insulating film provided only on the P− region 12, and is, for example, a silicon oxide film (SiO ₂ ).

  As shown in FIG. 1B, the tunnel insulating film 14b and the gate insulating film 14a are made of, for example, one continuous (that is, not separated) insulating film 14. The gate insulating film 14 a is a thick film portion of the continuous insulating film 14, and the tunnel insulating film 14 b is a thin film portion of the continuous insulating film 14. When the thickness of the gate insulating film 14a (that is, the thick film portion) is T1, and the thickness of the tunnel insulating film 14b (that is, the thin film portion) is T2, T1 is, for example, 18 to 80 nm, and T2 is, for example, 3 .5-20 nm.

  The floating gate electrode 15 is an electrode provided continuously from the gate insulating film 14a to the tunnel insulating film 14b. The floating gate electrode 15 is made of, for example, polysilicon containing N-type impurities such as phosphorus or arsenic, and all the surfaces (that is, the upper surface, the lower surface, and the side surfaces) are insulating films (that is, the tunnel insulating film 14b and the gate insulating film). 14a and the interelectrode insulating film 16). As a result, the floating gate electrode 15 is electrically insulated from the surroundings, and the potential is in a floating state (that is, not fixed).

The interelectrode insulating film 16 is an insulating film provided continuously on the upper surface and side surfaces of the floating gate electrode 15, for example. The interelectrode insulating film 16 is, for example, an insulating film having a three-layer structure in which a silicon oxide film, a silicon nitride film (Si ₃ N ₄ ), and a silicon oxide film are stacked in order from the lower side to the upper side. (That is, an ONO film). The control gate electrode 17 is provided so as to cover the upper surface and side surfaces of the floating gate electrode 15 via the interelectrode insulating film 16. The control gate electrode 17 is made of polysilicon containing an N-type impurity such as phosphorus or arsenic.

On the other hand, as shown in FIG. 1A, the P-channel type select gate transistor 20 includes a second P-type diffusion region, a third P-type diffusion region, a gate insulating film 24, a gate electrode 27, and the like. Have.
Here, as described above, the second P-type diffusion region is, for example, a diffusion region shared with the P-channel nonvolatile memory 10 and is used as the source in the selection gate transistor 20. The third P-type diffusion region is a diffusion layer containing a P-type impurity such as boron, and is used as the drain of the selection gate transistor 20. The third P-type diffusion region has a P− region 21 containing P-type impurities at a low concentration and a P + region 23 containing P-type impurities at a high concentration.

The gate insulating film 24 is an insulating film provided on a region sandwiched between the P− region 12 and the P− region 21 (that is, a region serving as a channel of the selection gate transistor 20), and is a silicon oxide film, for example. . The gate electrode 27 is provided on the gate insulating film 24. The gate electrode 27 is made of polysilicon containing an N-type impurity such as phosphorus or arsenic.
As shown in FIG. 1A, terminals are electrically connected to the N + region 4, the P + regions 9, 13, 23, the control gate electrode 17 and the gate electrode 27, respectively. Through this, a voltage can be applied to each region and each electrode, or a current can be passed through each region.
[Operation example of semiconductor device]
Next, an operation example of the semiconductor device 100 illustrated in FIGS. 1A and 1B will be described.
Table 1 shows an example of voltage values in each region and each electrode when data is rewritten.

  As shown in Table 1, when data is written, the selection gate transistor 20 is turned on, the N-type diffusion regions (N− region 3, N + region 4) are set to 14V, and the first P-type diffusion is performed. The region (P− region 8 and P + region 9) is floated (that is, the potential is not fixed), the second P-type diffusion region (P− region 12 and P + region 13) is set to 0V, and the control gate electrode 17 is set to Set to 14V.

  As a result, electrons that are minority carriers in the second P-type diffusion region are injected into the floating gate electrode 15 via the tunnel insulating film 14b by the “Fowler-Nöderheim tunnel” phenomenon. When electrons are injected into the floating gate electrode 15, the potential of the floating gate electrode 15 changes and the threshold voltage of the P-channel nonvolatile memory 10 changes compared to before the injection. This change in threshold voltage is stored in the P-channel nonvolatile memory 10 as data “1” or “0”. The stored (ie, written) data applies a predetermined voltage to the control gate electrode 17 and a voltage between the first and second P-type diffusion regions (ie, between the source and drain). Is applied and P channel type nonvolatile memory 10 is identified as ON or OFF (off).

  As shown in Table 1, when erasing data, the selection gate transistor 20 is turned on, the N-type diffusion region is set to 14V, the first P-type diffusion region is floated, and the second P-type The diffusion region is set to 14V, and the control gate electrode 17 is set to 0V. As a result, electrons stored in the floating gate electrode 15 are emitted to the second P-type diffusion region via the tunnel insulating film 14b due to the “Fowler-Noderheim tunnel” phenomenon, and the data is erased. .

In addition, the voltage value in each region and each electrode as shown in Table 1 is set by applying a voltage from the outside of the memory cell via a terminal electrically connected to each region and each electrode, or applying a voltage. This can be realized by not (that is, the potential is not fixed).
Next, regarding the energy band of each region and each electrode in the nonvolatile memory and the rewrite characteristics thereof, the P-channel nonvolatile memory 10 shown in FIG. 1B and the N-channel type shown in FIG. A description will be given while comparing with a non-volatile memory.

[About energy bands]
FIG. 2 is a diagram showing an energy band in a cross section when the P-channel nonvolatile memory 10 shown in FIG. 1B is cut along the aa ′ line. 2, P− corresponds to the P− region 12 shown in FIG. 1B, N + poly1 (FG) corresponds to the floating gate electrode 15 shown in FIG. 1B, and N + poly2 (CG) This corresponds to the control gate electrode 17 shown in FIG. Further, TNox corresponds to the tunnel insulating film 14b shown in FIG. 1B, and ONO corresponds to the interelectrode insulating film 16 shown in FIG.

  FIG. 9 is a diagram showing an energy band in a cross section when the N-channel nonvolatile memory 110 shown in FIG. 8B is cut along the line bb ′. In FIG. 9, N− corresponds to the N− region 112 shown in FIG. 8B, N + poly1 (FG) corresponds to the floating gate electrode 115 shown in FIG. 8B, and N + poly2 (CG) This corresponds to the control gate electrode 117 shown in FIG. TNox corresponds to the tunnel insulating film 114b shown in FIG. 8B, and ONO corresponds to the interelectrode insulating film 116 shown in FIG. 8B.

2 and 9, Ec represents the energy level of the conduction band, Ef represents the Fermi level, and Ev represents the energy level of the valence band.
As can be seen by comparing FIG. 2 and FIG. 9, the memory structure in which the tunnel insulating film is formed on the P− region (that is, the structure according to the present invention) is a memory in which the tunnel insulating film is formed on the N− region. Compared with the structure (that is, the structure according to the conventional example), the insulating film barrier from the floating gate electrode to the substrate side is high, and electrons stored in the floating gate electrode are difficult to escape. This is due to the difference in work function between the N-type diffusion region and the P-type diffusion region. In terms of a specific structure, if the entire surface immediately below the tunnel insulating film is the P − region, electrons are unlikely to escape from the floating gate electrode to the substrate side.

  The majority carriers in the N type diffusion region are electrons (e−), the majority carriers in the P type diffusion region are holes (h +), and the N type diffusion region contains more electrons than the P type diffusion region. In the prior art, it was naturally considered that the N-type diffusion region was more suitable as an electron supply source. Therefore, it has become common knowledge in memory design technology to arrange an N-type diffusion region as an electron supply source directly under a tunnel insulating film.

  In contrast, as shown in FIGS. 1 (a) and 1 (b) and FIG. 2, the present inventor considers the energy level of each region and each electrode, and the entire region immediately below the tunnel insulating film 14b. The P− region 12 is deliberately arranged, and electrons which are minority carriers are injected from the P− region 12 into the floating gate electrode 15. As a result, the energy barrier from the floating gate electrode 15 to the P− region 12 becomes higher than before, and electrons stored in the floating gate electrode 15 are less likely to escape to the P− region 12 via the tunnel insulating film 14b. .

[Rewriting characteristics]
FIG. 3 is a diagram showing a result of an experiment conducted by the present inventor regarding the rewrite characteristics of the nonvolatile memory. The horizontal axis in FIG. 3 represents the applied voltage (that is, the rewrite voltage) at the time of rewriting, and the vertical axis represents the threshold voltage of the type nonvolatile memory after the rewriting process.
As is apparent from FIG. 3, the threshold voltage of the P-channel nonvolatile memory 10 is more dependent on the applied voltage than the threshold voltage of the N-channel nonvolatile memory. It has changed greatly.

  For example, when attention is paid when the applied voltage is 12 V, the threshold voltage after the writing process of the P-channel nonvolatile memory 10 exceeds 2.0 V, whereas the threshold voltage after the writing process of the N-channel nonvolatile memory The voltage is in the range of 1.0 to 2.0V. Further, the threshold voltage after the erasing process of the P-channel nonvolatile memory 10 is lower than −2.0 V, whereas the threshold voltage after the erasing process of the N-channel nonvolatile memory is the same as that after the writing process. It is in the range of 0 to 2.0V. In other words, when attention is paid when the applied voltage is 12 V, the P-channel nonvolatile memory 10 correctly performs the writing process and the erasing process, whereas the N-channel nonvolatile memory performs each process correctly due to insufficient voltage. I have not been told.

  When attention is paid when the applied voltage is 14 V, the threshold voltage after the writing process of the P-channel nonvolatile memory 10 is higher than 4.0 V, and the threshold voltage after the erasing process is lower than -4.0 V. On the other hand, although a slight difference is recognized in each threshold voltage after the writing process and the erasing process in the N-channel type nonvolatile memory, those values are still in the range of 1.0 to 2.0V.

  As described above, it was confirmed that the P-channel nonvolatile memory 10 can perform data writing and erasing even with a low applied voltage as compared with the N-channel nonvolatile memory. That is, by making the tunnel insulating film 14b of the P-channel nonvolatile memory 10 thin, the threshold voltage Vth of the memory element is greatly changed even with an applied voltage as low as about 14v. Further, according to the element structure of the P-channel type nonvolatile memory 10, the charge retention characteristic (threshold voltage fluctuation of 100 mV or less) of 100 years or more can be realized in an environment of 85 ° C. Next, a method for manufacturing the semiconductor device 100 shown in FIGS. 1A and 1B will be described.

[About manufacturing method of semiconductor device]
4A to 7C are process diagrams showing an example of a method for manufacturing the semiconductor device 100 according to the embodiment of the present invention.
As shown in FIG. 4A, first, for example, an N-type diffusion region is formed in a region (that is, a memory cell region) where a memory cell of a single-crystal P-type silicon substrate (that is, Psub) 1 is formed. As a result, the N-type well region 2 is formed. The N-type well region 2 is formed, for example, by covering a desired region of the silicon substrate 1 with a resist pattern or the like, and using this resist pattern as a mask, phosphorus, which is an N-type impurity, is ion-implanted at a dose of 5e12 / cm ^2. To do. Next, the resist pattern is removed and then formed by performing thermal diffusion at 1200 degrees for 3 hours.

Next, as shown in FIG. 4B, a silicon oxide film 5 for element isolation is formed on the silicon substrate 1 on which the N-type well region 2 is formed. The silicon oxide film 5 is formed by, for example, LOCOS oxidation (wet oxidation) at 1000 ° C. for 40 minutes. The thickness after the formation of the silicon oxide film 5 is, for example, about 300 nm.
Next, as shown in FIG. 4C, a silicon oxide film 14 ′ to be a later gate insulating film is formed on the memory cell region of the silicon substrate 1. The thickness after the formation of the silicon oxide film 14 'is, for example, about 30 nm. The formation of the silicon oxide film 14 'may be performed using, for example, either dry oxidation or wet oxidation.

Next, as shown in FIG. 5A, a photoresist is applied on the silicon oxide film 14 ', exposed to light, opened on the region that becomes P-, and covered on the other region. A resist pattern R1 is formed. Next, using the resist pattern R1 as a mask, for example, boron, which is a P-type impurity, is ion-implanted at a dose of 1e14 / cm ² to form P− regions 8, 12, and 21 in the N-type well region 2. To do. After the P− regions 8, 12, and 21 are formed, the resist pattern R1 is removed.

  Next, as shown in FIG. 5B, a photoresist is applied on the silicon oxide film 14 ', and an exposure process is performed to open the region where the tunnel insulating film is formed and cover the other region. A resist pattern R2 having a shape is formed. Next, using this resist pattern R2 as a mask, the silicon oxide film 14 'is removed by wet etching. By this wet etching, the silicon oxide film 14 ′ is completely removed in the region where the tunnel insulating film is formed, and the surface of the P− region 12 is exposed. Thereafter, as shown in FIG. 5C, the resist pattern is removed, and the surface of the P− region 12 is wet-oxidized at a temperature of, for example, 850 ° C. to form a tunnel insulating film 14b. The thickness after formation of the tunnel insulating film 14b is, for example, 5.5 nm.

Next, in FIG. 6A, a polysilicon film to be a floating gate electrode is deposited to 200 nm, for example. A method for forming this polysilicon film is, for example, a CVD method. Next, for example, phosphorus, which is an N-type impurity, is ion-implanted into the polysilicon film at a dose of 5e15 / cm ² to form a first N-type polysilicon film 15 ′. Here, the N-type impurity is introduced into the polysilicon film after the film formation, not in the film formation process (ie, in-situ). As a result, the impurity concentration in the first N-type polysilicon film 15 ′ can be accurately controlled, and the accelerated oxidation of the first N-type polysilicon film 15 ′ is suppressed in the subsequent thermal oxidation step. be able to.

  Next, an interelectrode insulating film 16 is formed on the first N-type polysilicon film 15 ′. For example, as the interelectrode insulating film 16, a three-layered insulating film (that is, an ONO film) in which a silicon oxide film / silicon nitride film / silicon oxide film is laminated is formed. When forming this ONO film, for example, a silicon oxide film is formed by subjecting a polysilicon film to thermal oxidation (1050 ° C., 20 seconds). Next, the silicon oxide film is subjected to nitriding (730 ° C., 30 minutes) to form a silicon nitride film. Here, the nitriding treatment is a heat treatment in an atmosphere containing nitrogen. Further, thermal oxidation (1000 ° C., 43 minutes) is performed on the silicon nitride film. As a result, an ONO film having a structure in which three layers of silicon oxide film / silicon nitride film / silicon oxide film are stacked can be formed to a thickness of about 18 nm.

  Note that the processing temperature and processing time shown in parentheses above are merely examples of processing conditions, and each of the ONO films may be formed at other temperatures and other processing times. Further, the method for forming the silicon nitride film constituting the ONO film is not limited to nitriding treatment, and other static film methods such as CVD may be used. Similarly, the method for forming the silicon oxide film constituting the ONO film is not limited to thermal oxidation, and other film forming methods such as a CVD method may be used.

  Next, only the region to be the floating gate electrode of the memory cell is covered with a resist pattern (not shown), and the interelectrode insulating film 16 and the first N-type polysilicon film 15 ′ in other regions are dried using this resist pattern as a mask. Remove by etching. Thereby, the floating gate electrode 15 is formed as shown in FIG. Note that the thick film portion of the silicon oxide film 14 immediately below the floating gate electrode 15 becomes the gate insulating film 14a.

Next, for example, phosphorus, which is an N-type impurity, is ion-implanted at a dose of 1.1e13 / cm ² to form the N− region 3. The N− region 3 is an impurity diffusion layer for reducing the contact resistance to the N-type well region 2. The N− region 3 can also be used as an N well of a CMOS circuit (not shown). In this N− region 3 formation step, since the phosphorus dose is relatively small, ion implantation may be performed without using a resist pattern or the like as a mask (of course, a mask may be used). ).

Next, as shown in FIG. 6C, the side surface of the floating gate electrode 15 is thermally oxidized. As described above, after the floating gate electrode 15 is formed by photolithography and etching techniques, a new insulating film is formed on the side surface thereof, thereby forming the interelectrode insulating film 16 only on the upper surface of the floating gate electrode 15. In comparison, the capacity of the P-channel nonvolatile memory 10 can be increased.
Subsequently, a polysilicon film is deposited to a thickness of 150 nm by, for example, a CVD method, and phosphorus, which is an N-type impurity, is ion-implanted into the polysilicon film at a dose of 8e15 / cm ² to form a second N-type polysilicon film. To do. Also here, the impurity concentration in the second N-type polysilicon film can be accurately controlled by introducing the N-type impurity into the polysilicon film after the film formation rather than in-situ.

  Further, in order to reduce the resistance of the second N-type polysilicon film, a tungsten silicide film is deposited on the second N-type polysilicon film to a thickness of about 150 nm, for example. Then, the tungsten silicide film and the second N-type polysilicon film are partially etched (that is, patterned) by photolithography and etching techniques. As a result, as shown in FIG. 7A, the control gate electrode 17 is formed so as to cover the upper surface and the side surface of the floating gate electrode 15, and at the same time, the silicon oxide film is interposed on the region serving as the channel of the selection gate transistor 20. Thus, the gate electrode 27 is formed. Note that the silicon oxide film immediately below the gate electrode 27 becomes the gate insulating film 24 of the select gate transistor 20.

Next, as illustrated in FIG. 7B, for example, a resist pattern R <b> 3 having an opening above the N− region 3 and covering the other region is formed on the silicon substrate 1. Then, using the resist pattern R3 as a mask, arsenic is ion-implanted as an N-type impurity at a dose of 5e15 / cm ² . Thereby, the N + region 4 is formed. The N + region 4 is an impurity diffusion layer for reducing the contact resistance of the N-type well region 2. The N + region 4 can also be used as an N-type source or an N-type drain of a CMOS circuit (not shown). After the N + region 4 is formed, the resist pattern R4 is removed.

Next, as illustrated in FIG. 7C, a resist pattern R <b> 4 having a shape that opens above the P− regions 8, 12, and 21 and covers other regions is formed on the silicon substrate 1. Then, using this resist pattern R4 as a mask, boron is ion-implanted as a P-type impurity at a dose of 2.5e15 / cm ² . Thereby, P + regions 9, 13, and 23 are formed. After forming the P + regions 9, 13, and 23, the resist pattern R4 is removed.

  Although not shown in the drawings, for example, the interlayer insulating film forming step, the contact hole / via hole forming step, the wiring forming step, etc. are performed once or a plurality of times, for example, to be electrically connected to the N + region 4. A wiring, a wiring electrically connected to each of the P + regions 9, 13, and 23, a wiring electrically connected to the control gate electrode 17, and a wiring electrically connected to the gate electrode 27 are formed. In this manner, the semiconductor device 100 shown in FIGS. 1A and 1B is completed.

  Thus, according to the embodiment of the present invention, for example, as shown in FIG. 2, the energy barrier from the floating gate electrode to the P− region 12 due to the work function difference between the N-type diffusion region and the P-type diffusion region. The electrons stored in the floating gate electrode 15 are unlikely to escape to the P− region 12 via the tunnel insulating film 14b. Therefore, the tunnel insulating film 14b can be thinned and the rewriting voltage can be lowered.

  In addition, according to the embodiment of the present invention, only the tunnel insulating film 14b is thinned and the rewrite voltage is lowered without impairing the electrical characteristics such as breakdown voltage and leakage current depending on the thickness of the gate insulating film 14a. Can do. In other words, when the tunnel insulating film and the gate insulating film have the same thickness, if the tunnel insulating film is made thinner, the gate insulating film is also made the same thickness. There is a possibility that the breakdown voltage of the gate insulating film is lowered or the leakage current is increased. On the other hand, in the present invention, only the tunnel insulating film 14b can be thinned while the gate insulating film 14a has a certain thickness or more. Therefore, the rewriting voltage can be lowered without impairing the electrical characteristics depending on the thickness of the gate insulating film 14a.

  Further, according to the embodiment of the present invention, the drain of the P-channel nonvolatile memory 10 and the source of the P-channel select gate transistor 20 are connected to the second P-type diffusion region (P− region 12, P + region). 13) is shared. Therefore, the area occupied by the memory cell including the P-channel nonvolatile memory 10 and the select gate transistor 20 can be reduced, which can contribute to the reduction of the semiconductor device and the manufacturing cost.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 N type well area | region 3 N- area | region 4 N + area | region 5 Silicon oxide film 8, 12, 21 P- area | region 9, 13, 23 P + area | region 10 P channel type non-volatile memory 14 Insulating film (silicon oxide film)
14a, 24 Gate insulating film (thick film part)
14b Tunnel insulating film (thin film part)
14 'silicon oxide film 15 floating gate electrode 15' first N-type polysilicon film 15 floating gate electrode 16 interelectrode insulating film 17 control gate electrode 20 selection gate transistor 27 gate electrode 100 semiconductor devices R1 to R4 resist pattern

Claims (9)

An N-type diffusion region provided in the semiconductor substrate;
A first P-type diffusion region and a second P-type diffusion region provided in a separated state in the N-type diffusion region;
A tunnel insulating film provided on the second P-type diffusion region;
A gate insulating film provided on a region sandwiched between the first P-type diffusion region and the second P-type diffusion region of the N-type diffusion region;
A floating gate electrode provided continuously from above the gate insulating film to the tunnel insulating film,
The P-channel type nonvolatile memory, wherein the second P-type diffusion region is disposed in the entire region immediately below the tunnel insulating film. The P-channel nonvolatile memory according to claim 1,
The P-channel nonvolatile memory according to claim 1, wherein the tunnel insulating film is smaller in thickness than the gate insulating film. A P-channel nonvolatile memory according to claim 1 or 2,
An interelectrode insulating film provided on the floating gate electrode;
A P-channel nonvolatile memory, comprising: a control gate electrode provided on the interelectrode insulating film. The P-channel nonvolatile memory according to any one of claims 1 to 3,
The P-channel type nonvolatile memory, wherein the floating gate electrode is made of an N-type semiconductor. A P-channel nonvolatile memory according to any one of claims 1 to 4,
By writing electrons into the floating gate electrode from the second P-type diffusion region by the FN tunneling phenomenon via the tunnel insulating film, data is written to the P-channel nonvolatile memory. A p-channel type non-volatile memory characterized. An N-type diffusion region provided in the semiconductor substrate;
A first P-type diffusion region and a second P-type diffusion region provided in a separated state in the N-type diffusion region;
Of the N-type diffusion region, the region sandwiched between the first P-type diffusion region and the second P-type diffusion region and the second P-type diffusion region are interposed via an insulating film. A floating gate electrode provided continuously,
The insulating film has a thick film portion and a thin film portion,
The thick film portion is provided on the N-type diffusion region, and the thin film portion is provided only on the second P-type diffusion region,
Data is written to the P-channel nonvolatile memory by injecting electrons from the second P-type diffusion region to the floating gate electrode by the FN tunnel phenomenon via the thin film portion. A P-channel nonvolatile memory. The P-channel type nonvolatile memory according to any one of claims 1 to 6,
A P-channel transistor provided on the semiconductor substrate,
A semiconductor device, wherein a drain of the P-channel nonvolatile memory and a source of the P-channel transistor are electrically connected. The semiconductor device according to claim 7,
A third P-type diffusion region provided in the second P-type diffusion region and having a higher concentration of P-type impurities than the second P-type diffusion region;
The semiconductor device, wherein the third P-type diffusion region is a drain of the P-channel nonvolatile memory and also a source of the P-channel transistor. Forming an N-type diffusion region in a semiconductor substrate;
Forming a first P-type diffusion region and a second P-type diffusion region in the N-type diffusion region apart from each other;
Forming a tunnel insulating film only on the second P-type diffusion region;
A gate insulating film having a thickness larger than that of the tunnel insulating film is formed on a region sandwiched between the first P-type diffusion region and the second P-type diffusion region in the N-type diffusion region. Process,
Forming a floating gate electrode continuously from the gate insulating film to the tunnel insulating film. A method for manufacturing a P-channel type nonvolatile memory, comprising:

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