JP2009266981A - Trench gate type semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a trench gate structure and a method for manufacturing the same, and in particular, a trench gate type using a wide band gap semiconductor such as a silicon carbide semiconductor (hereinafter abbreviated as SiC) or a group III nitride semiconductor including an AlGaN-based semiconductor. The present invention relates to a semiconductor device and a manufacturing method thereof.

Silicon carbide semiconductor (hereinafter also referred to as SiC) or group III nitride semiconductor (hereinafter abbreviated as AlGaN. Here, AlGaN is a mixed crystal of AlN and GaN, but also includes only GaN.) If a high-voltage power device is manufactured using, there is a possibility that the on-resistance can be greatly reduced. An on-resistance of 5 mΩcm ² or less is obtained by a MISFET having a breakdown voltage of 1 to 1.2 kV using SiC, which is higher than that of a silicon semiconductor (hereinafter abbreviated as Si) IGBT of the same breakdown voltage class. Resistance is less than half. If cost reduction and performance improvement proceed in the future, it is possible that most of IGBTs made of Si will be replaced as inverter parts.
The on-resistance can be greatly reduced by using SiC, AlGaN, etc., because SiC, AlGaN, etc. have a higher breakdown electric field with a wider band gap than Si. This is because the resistance can be reduced by two orders of magnitude or more as compared with Si by thinning the layer and increasing the doping density of the breakdown voltage layer.
MISFET, IGBT, etc. maintain the withstand voltage by the pn junction between the n-type withstand voltage layer and the p-type body region. Further, the doping amount or impurity density of the body region in the MISFET or IGBT has a greater influence on the channel mobility and (gate) threshold voltage than on the breakdown voltage. If the doping amount or impurity density of the body region is too high, the threshold voltage becomes unnecessarily high and the channel mobility is remarkably lowered, which is not preferable. From this point, there is a restriction that the impurity density of the body region in the SiC or AlGaN MISFET or IGBT cannot be made much higher than that in the case of Si.

On the other hand, with respect to the impurity density of the breakdown voltage layer, SiC, AlGaN, etc. are one to two orders of magnitude higher than Si if the breakdown voltage is the same. Therefore, especially in the case of SiC, AlGaN, etc., the depletion layer tends to extend not only in the breakdown voltage layer but also in the body region where the impurity density difference with the breakdown voltage layer is small.
By the way, in the MISFET using SiC, AlGaN, or the like, the resistance of the breakdown voltage layer is reduced. As a result, the resistance component other than the breakdown voltage layer, that is, in the case of a so-called DMOS type structure, It becomes relatively large and becomes a resistance component that cannot be ignored. It is known that the JFET resistance component is removed by adopting a so-called trench gate structure. Another method for reducing the channel resistance is to reduce the channel length. However, in the case of the trench gate structure, it is necessary to reduce the thickness of the body region in order to shorten the channel length. When the thickness of the body region is reduced, a punch-through state in which the body region is entirely depleted by an off-voltage is likely to occur, which adversely affects the high withstand voltage characteristics expected from a high dielectric breakdown electric field such as SiC or AlGaN.
Another way to reduce channel resistance is to increase the channel density per unit area. In general, in a power device, an active region through which a main current flows is configured as an assembly of unit cells arranged in the active region. Since each unit cell always includes a channel, the channel density per unit area can be increased by reducing the size of one unit cell, in other words, by reducing the repetition width of the unit cell (referred to as cell pitch). In other words, the cell pitch may be reduced to reduce the channel resistance.

Next, a method for reducing the cell pitch will be described below. In general, a photolithography process is essential in the manufacture of semiconductor devices. In the case where a plurality of photolithography processes are performed in the manufacturing process, a process of masking the photo pattern of the next process with the photo pattern of the previous process is required. In general, when the number of mask alignment processes increases, a decrease in mask alignment accuracy cannot be ignored compared to the resolution. For example, in the case of a commercially available g-line stepper, the resolution limit is 1 μm, but a mask alignment error of 0.4 to 0.8 μm at a maximum occurs. The maximum value has a range because the device limit is 0.4 μm, but in reality, it is necessary to allow up to about 0.8 μm in view of productivity. If the photolithography process is performed once (no mask alignment), the cell pitch can be reduced to, for example, 2 μm at a minimum. If the photolithography process is performed twice (one mask alignment), the cell pitch is minimized, for example, 3.6 to 5.2 μm is also required. Therefore, the minimum cell pitch must be increased as the number of mask alignments increases.
On the other hand, in the case of a high-resolution (high-performance) stepper or similar device (referred to as a stepper or the like) designed for Si, GaAs, or the like, a mask alignment mechanism that normally has a small mask alignment error is incorporated. However, such a high-performance stepper or the like often uses a short wavelength light source and thus has a shallow depth of focus. However, because SiC is a special bulk growth method, and AlGaN is mainly formed by heteroepitaxial growth on sapphire, SiC, or Si substrate, a large and non-uniform warp occurs in the laminated substrate. With a shallow depth of focus, such as a high-performance stepper, a situation in which exposure cannot be properly performed on the entire surface within one shot is likely to occur. Therefore, for the time being, until the warpage of the laminated substrate described above is improved by another technical advance, the depth of focus is deep, i.e., the stepper must be able to align the mask even if there is some warpage. I don't get it. Therefore, in order to reduce the cell pitch in SiC or AlGaN, it is impossible to adopt a stepper with a high resolution as described above. Therefore, a manufacturing process with a small number of mask alignments is performed, and accuracy is reduced due to accumulation of alignment errors. It is desirable to make it smaller.

When impurity doping can be performed by a thermal diffusion method as in a Si semiconductor, for example, a unit cell structure is formed in a self-aligned manner by the following Si trench gate type MOSFET and its manufacturing method. Thus, a method that can reduce the number of mask alignments is known.
A specific example of the cell pitch and the trench width in the Si wafer process will be described below for comparison with the cell pitch in the process of SiC, AlGaN, or the like. When the g-line stepper is used, the trench width is, for example, 1 μm (corresponding to the resolution limit), but the cell pitch is, for example, 4 μm due to restrictions in the manufacturing process.
Details of the restrictions in the manufacturing process will be described with reference to the main part sectional view of the Si trench gate type MOSFET shown in FIG. 13 and FIGS. .
First, a bulk n-type Si semiconductor substrate 1 is prepared as shown in the cross-sectional view of the main part of the Si wafer (laminated substrate) in FIG. On one main surface (referred to as a front surface) of the substrate 1, an n-type Si epitaxial growth layer having a predetermined doping amount and layer thickness is formed. Hereinafter, when the reference numeral 1 is added to the back of the substrate as in the case of the substrate 1, the substrate is a bulk substrate, and when it is simply referred to as a semiconductor substrate, laminated substrate, wafer, Si wafer, SiC wafer, etc. The whole laminated substrate in which the functional layer and the functional region are laminated and formed thereon is referred to. Next, boron is thermally diffused from the surface of the n-type Si epitaxial growth layer to the active region portion through which the main current flows to form a p-type body region 5. Of the n-type Si epitaxial growth layer having the body region 5 formed on the surface, the lower layer portion or the remaining portion of the body region (the Si epitaxial growth layer portion other than the body region 5) becomes the breakdown voltage layer 3. Subsequently, an oxide film having a predetermined thickness is formed on the entire front surface of the wafer, and a mask oxide film 101 is formed by appropriately patterning. Here, if desired, the width of the mask oxide film 101 and the interval between the adjacent mask oxide films 101 can be reduced to the resolution limit of the stepper used, and the width and interval thereof are, for example, 1 μm. . However, in this example, the width of the mask oxide film 101 is a little wide, for example, 3 μm, for convenience of later thermal diffusion. The cell pitch of the unit cell to be formed in the following description is 4 μm, which is a combination of the mask oxide film interval of 1 μm and the width of 3 μm. Thereafter, phosphorus is ion-implanted from the wafer surface at the interval (opening) between the mask oxide films 101, and heat treatment is performed to form the source region 6 (FIG. 15). At this time, since the ion-implanted phosphorus is thermally diffused, the source region 6 is also diffused in a direction parallel to the main surface (sometimes referred to as a lateral direction) as shown in FIG. Wrap around under 101. The wraparound width is, for example, 1 μm. The depth at which phosphorus can be ion-implanted using a general ion implantation apparatus is about 0.8 μm at most, but the depth (pn junction depth) of the source region 6 is about 2 μm, for example, by thermal diffusion. Can be.

Next, using the same mask oxide film 101 as an etching mask, the Si wafer is anisotropically etched from the surface, and the trench 10 having a depth reaching the breakdown voltage layer 3 is formed as shown in the cross-sectional view of the main part in FIG. Form. Thereafter, a gate insulating film 11 is formed on the inner wall surface of the trench 10 as shown in the cross-sectional view of the main part in FIG. Subsequently, highly doped (high doping amount or high impurity density) polycrystalline silicon is deposited on the entire surface of the Si wafer, and the vicinity of the gate pad (not shown) is protected, and then etched back to thereby form the trench 10. The gate electrode 12 is embedded inside to a required height. As a result, the gate electrode 12 inside the trench faces the source region 6, the body region 5, and the breakdown voltage layer 3 through the gate insulating film 11.
Similarly, an appropriately doped SiO ₂ film is formed on the entire surface of the Si wafer and etched back appropriately to embed an interlayer insulating film 21 on the gate electrode 12 in the trench 10. As shown in FIG. 17, the upper end of the gate electrode 12 must be between the lower end and the upper end of the source region 6. Further, since the interlayer insulating film 21 is formed by a deposition method, the breakdown voltage is lower than that of the thermal oxide film, and a certain thickness is required to obtain a predetermined gate breakdown voltage. Further, a manufacturing margin (dimensional margin) at the time of etch back is also necessary. This manufacturing margin is given solely by the thickness of the source region 6, similarly to the gate electrode 12. For this reason, the thickness of the source region 6 needs to be about 2 μm as described above.

Finally, after removing unnecessary deposits and the like on the front surface and the back surface of the Si wafer, respectively, a predetermined source electrode 23, drain electrode 22, and gate pad electrode (not shown) are formed. The Si trench gate MOSFET shown in FIG. 13 is completed.
Of the conventional Si trench gate type MOSFET and its manufacturing method described with reference to FIGS. 13 to 17, what is important is that the photolithography process for forming the unit cell is performed by patterning the mask oxide film 101. It only needs to be done once. In the process of etching back the polysilicon layer or the SiO ₂ film, a photolithography process is required to form a gate pad and the like, but the unit cell does not have a pattern to be aligned and self-aligns. The cell pitch value can be determined regardless. As a result, the cell pitch can be reduced.
As described above, forming unit cells in a self-aligned manner means that the number of photolithography steps required to form unit cells can be reduced, and pattern alignment errors can be reduced at the same time. Means. As described above, since impurity doping using both the ion implantation method and the thermal diffusion method is possible in Si, by forming the unit cell in a self-aligned manner, a manufacturing method that does not need to take into account pattern alignment errors should be adopted. Therefore, it becomes easy to reduce the cell pitch.

However, in the case of wide band gap semiconductors such as SiC and AlGaN, the diffusion coefficient of impurities that become donors and acceptors is remarkably small, so the thermal diffusion method is too hot and unrealistic as a mass production method. Since it is difficult to incorporate the thermal diffusion method into the production line, the unit cell cannot be formed in a self-aligned manner by a manufacturing method similar to Si. That is, as described above, in order to form a conventional self-aligned unit cell, a predetermined or obtained impurity doping that combines an ion implantation method and a thermal diffusion method at the time of selective or local impurity doping. This is because it is necessary to form an impurity profile. In other words, since there is almost no impurity diffusion in the lateral direction in the ion implantation method, the arrangement pattern of the source region 6 and the trench 10 as shown in the cross-sectional pattern of the Si wafer described in FIGS. It is not possible to adopt a process of forming in a self-aligned manner using a mask (that is, without pattern alignment).
When ion implantation is performed using a general ion implantation apparatus, the ion implantation depth of the source region is at most 1 μm or less. For this reason, there are often insufficient manufacturing margins when the gate electrode 12 and the interlayer insulating film 21 are etched back. Therefore, in the case of an SiC trench gate type MOSFET, conventionally, for example, the following unit cell structure and manufacturing method thereof must be used.

FIG. 18 shows a cross-sectional view of a principal part of a unit cell in a conventional SiC trench gate type MOSFET. Since the main structure is the same as that of the Si trench gate MOSFET shown in FIG. 13, the same components are denoted by the same reference numerals, and redundant description is omitted. In FIG. 18, the characteristic point different from FIG. 13 is that the interlayer insulating film 21 protrudes above the trench 10. Further, the source electrode 23 is in ohmic contact with the surface of the SiC wafer by filling the contact hole 20 provided in the interlayer insulating film 21. Further, in FIG. 18, a highly doped second conductivity type body contact region 7 is provided in a region (not indicated) corresponding to the surface layer of the portion where the body region 5 is exposed on the Si wafer surface in FIG. Yes. Similarly, in FIG. 18, the region corresponding to the source region 6 in FIG. 13 includes a highly doped first conductivity type source contact region 6a corresponding to the surface layer of the source region 6 and a first conductivity type source extension region corresponding to the lower layer. 6b. The source electrode 23 is in ohmic contact with the surface of the body contact region 7 and the surface of the source contact region 6a in common.
The trench width and cell pitch in the SiC trench gate type MOSFET are not dimensionally accurate in FIG. 18 and FIG. 13, so they appear to be the same in the drawing but are actually manufactured using the same g-line stepper. Therefore, the cell pitch of 4 μm in the case of Si shown in FIG. 13 must be increased by at least 25% to 5 μm. In view of productivity, the cell pitch needs to be designed with a wider interval between the trenches 10 so that the cell pitch is further increased by 175% or more to 11 μm.

A conventional method for manufacturing a SiC trench gate type MOSFET will be described below in order with reference to FIGS. 19 to 22 and FIG. As shown in the cross-sectional view of the main part of the SiC trench gate type MOSFET of FIG. 19, on one main surface (referred to as the front surface) of the n-type SiC semiconductor substrate 1 by epitaxial growth, a predetermined n-type is formed on the entire surface. A pressure-resistant layer 3 having a doping density and a film thickness and a body layer having a predetermined doping density and film thickness which are p-type are formed in this order. The doping density of the body layer matches the doping density of the body region 5 shown in FIG. The film thickness of the body layer at this stage matches the sum of the thicknesses of the body region 5 and the body contact region 7.
Next, a marker (not shown) used for alignment in the photolithography process is formed in the same manner as the manufacturing process of the Si trench gate MOSFET described above. Subsequently, for example, an SiO ₂ film is deposited by plasma CVD, and is patterned to have a predetermined opening by photolithography similar to the Si, thereby forming an ion implantation mask for a body contact region (FIG. Not shown). This process requires a photolithography process. Subsequently, after the wafer is heated to, for example, 500 ° C., aluminum is ion-implanted from the surface to about 0.4 μm. The ion implantation depth is generally determined by the acceleration energy that can be stably realized with a general 400 keV ion implantation apparatus using monovalent aluminum. Next, heat treatment (called activation annealing) is performed in an inert gas (a small amount of SiH ₄ or the like may be added) at a predetermined temperature and time to electrically activate the ion-implanted aluminum. Recover injection damage. FIG. 19 is a fragmentary cross-sectional view of the body contact region 7 after the activation annealing is completed.

Next, ion implantation and activation annealing are performed for the source contact region 6a and the source extension region 6b by the same method. The source contact region 6a is implanted to about 0.35 μm from the surface by using monovalent ions of phosphorus that can be highly doped. For example, 1 to 2 valent nitrogen ions are implanted into the source extension region 6b to about 0.8 μm. Note that the same mask can be used for the source contact region 6a and the source extension region 6b, and activation annealing may be performed simultaneously. However, since the positional relationship with the body contact region 7 is determined by the alignment of photolithography, the body contact region 7 is completely included in the source contact region 6a in plan view even when the maximum displacement occurs. Therefore, it must be designed appropriately so that it will not be lost. For example, when the g-line stepper is used, the width of the body contact region 7 needs to be 0.8 to 1.6 μm or more, and considering the pattern conversion error, it is safe to set it to 1 to 2 μm or more. FIG. 20 shows a cross-sectional view of the main part in the state where the activation annealing of the source contact region 6a and the source extension region 6b has been completed.
Thereafter, as in the case of the Si trench gate type MOSFET, using an etching mask (not shown) having an appropriate opening made of, for example, a SiO ₂ film, as shown in the cross-sectional view of the main part of FIG. Form. At this time, a photolithography process is required to provide an appropriate opening in the etching mask. The width of the trench 10 may be as small as desired within the range in which the gate insulating film 11 and the gate electrode 12 can be formed. The trench 10 must be inside the source contact region 6a in a plan view except for the terminal portion. Further, the end portion of the contact hole 20 to be formed later must be between the trench 10 and the body contact region 7 in plan view. Therefore, the end of body contact region 7 and the end of contact hole 20 and the end of contact hole 20 and the end of trench 10 are 0.8 to 1.6 μm, respectively, when the g-line stepper is used, for example. It is necessary to separate them above, and considering the pattern conversion error, it is safe to separate them by 1 to 2 μm or more. As described above, the cell pitch needs to be at least 5 to 9 μm or more, and considering the pattern conversion error, it is safe to set the cell pitch to 6 to 11 μm or more. FIG. 21 shows a cross-sectional view of a main part in a state where the formation up to the trench 10 is completed.

Subsequently, after forming a gate insulating film 11 on the inner wall surface of the trench 10, a highly doped polysilicon layer is deposited and etched back in the same manner as the Si trench gate type MOSFET. It is buried at a required height in the trench 10. Thereafter, an interlayer insulating film 21 is deposited on the entire surface of the wafer. Unlike the case of Si, etch back is not performed, but instead, a contact hole 20 is formed in the interlayer insulating film 21. At this time, photolithography is required. The positional relationship between the body contact region 7 and the trench 10 in plan view is as described above. FIG. 22 shows a cross-sectional view of the main part in a state where the contact hole 20 is completed.
Next, for example, a nickel film and a titanium film are sequentially formed by sputtering and patterned. However, at the time of patterning, there is no pattern to be matched with the cell, and a nickel and titanium film (or a reaction product of these and SiC) may remain on the entire surface of the cell. That is, nickel and titanium films may be in contact with both the source contact region 6a and the body contact region 7 in the same manner. There are several methods for patterning these metals, but the simplest is to perform etching after simply performing photolithography. As another method, a pattern can be formed by a so-called salicide process in which heat treatment is performed to react SiC with a metal, and then the unreacted metal is dissolved and removed in a chemical. Thereafter, the front surface of the wafer is protected with a photoresist or the like, unnecessary deposits on the back surface are removed, and, for example, a nickel film and a titanium film are sequentially formed on the back surface by sputtering. After removing the photoresist on the front surface of the wafer, heat treatment is performed to obtain ohmic contact between the drain electrode 22 and the source electrode 23 and the SiC wafer surface. In this case, the heat treatment temperature is preferably higher than the melting point of aluminum (about 630 ° C.). Therefore, in a normal MOSFET in which an aluminum film is often laminated on a nickel and titanium film as the uppermost layer of the source electrode, the heat treatment must be completed before forming the aluminum film. Thereafter, similarly to Si, an aluminum film or the like is appropriately formed and patterned to form the remaining portion of the source electrode 23 (source electrode portion not shown) and a gate pad electrode not shown. The remaining portion of the drain electrode 22 (drain electrode portion not shown) is deposited with a predetermined metal in the same manner as Si to complete the SiC trench gate type MOSFET of FIG.

In addition to the SiC trench gate type MOSFET described above, there are the following well-known techniques for manufacturing other well-known SiC semiconductor devices. An n-type impurity is ion-implanted into the p-type polycrystalline silicon layer using the remaining portion obtained by selectively etching the hard mask deposited on the p-type polycrystalline silicon layer and the shallow n-type polycrystalline silicon layer as a mask. An n-type polycrystalline silicon layer is formed. Next, isotropically depositing a film as a material for the side wall and performing anisotropic etching, forming a side wall on the side surface of the hard mask, and etching the n-type polycrystalline silicon layer using the hard mask and the side wall as a mask By doing so, a method of sufficiently narrowing the width of the n-type polycrystalline silicon layer in a self-aligned manner is known (Patent Document 1).
There is a description about forming an element isolation region by self-alignment (Patent Document 2). There is a description relating to the formation of multi-step recess grooves in a self-aligned manner with good yield (Patent Documents 3 and 4). There is a description of a recess structure in which a two-step groove structure is formed by wet etching using a first mask (Patent Document 5). There is a description of a self-aligned double oxide UMOSFET (Patent Document 6).
JP 2007-27491 A (Summary, paragraph 0011) JP-A-4-209541 Japanese Patent Laid-Open No. 3-184334 Japanese Laid-Open Patent Publication No. Hei 4-206838 Japanese Patent Laid-Open No. 4-196542 JP 2005-505138 A

As described above, in SiC, a good ohmic contact can be obtained with the surface of the highly doped n-type source contact region 6a mainly by the action of nickel, and the highly doped p-type body contact region. Ohmic contact is also obtained on the 7 surface (FIG. 22).
However, when a nickel film is used, the ohmic contact with the surface of the body contact region 7 generally has a relatively high resistance. If this high resistance becomes a problem depending on the application, a metal other than the surface of the source contact region 6a is brought into contact with the surface of the body contact region 7 to reduce the contact resistance. There is a need to.
The ohmic contact in the case of AlGaN or the like is a more difficult situation, and a good ohmic contact can be obtained with titanium or aluminum on the surface of the n-type region. It is not easy to obtain ohmic contact.
To solve these problems, it is possible to improve ohmic contact by using a metal electrode different from the source contact region 6a to contact the body contact region 7 by using photolithography technology. Due to the mask alignment margin, a new problem arises in which the cell pitch is significantly widened. For example, when the g-line stepper is used, the cell pitch when the same metal is brought into contact with the source contact region 6a and the body contact region 7 can be set to 2 microns (twice the resolution limit) as described above. On the other hand, when different metals are brought into contact as described above, the cell pitch is at least 3.6 to 5.2 microns, and actually 4 to 6 microns are required in consideration of the pattern conversion error. Therefore, there is a problem that the cell pitch spreads 2 to 3 times.

  The present invention has been made in view of the above points, and an object of the present invention is to improve ohmic contact and utilize lateral diffusion by a thermal diffusion method even when a wide bandgap semiconductor material is used. It is an object to provide a trench gate type semiconductor device and a manufacturing method thereof that can reduce the cell pitch without reducing the on-resistance.

  According to the present invention, the trench gate type MOS structure is formed by the self-alignment method, and the first mask of the first mask having the first insulating film and the second insulating film used for forming the first trench 10a. The insulating film is left after the second trench 10b is formed, and the electrode material that should be in contact with only the source contact region 6a in the source electrode 23 is used to lift off, thereby improving the ohmic contact and reducing the cell pitch. Thus, the object of the present invention can be achieved by a method of manufacturing a trench gate type MOSFET having a low on-resistance.

According to the present invention, even when a wide band gap semiconductor material is used, the ohmic contact can be improved, the cell pitch can be reduced without using the lateral diffusion by the thermal diffusion method, and the on-resistance can be reduced. A trench gate type semiconductor device and a manufacturing method thereof can be provided.

Hereinafter, a trench gate type semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist. For example, the present invention can also be applied to a MOS semiconductor device having another trench gate structure such as a trench IGBT.
FIGS. 1-8 is principal part sectional drawing of the unit cell for demonstrating the manufacturing method of the AlGaN trench gate type MOSFET concerning Example 1 of this invention. 9 to 12 are cross-sectional views of main parts of a unit cell for explaining a method of manufacturing an AlGaN trench gate type MOSFET according to Embodiment 2 of the present invention.

In Example 1, an AlGaN trench gate type MOSFET whose cross-sectional view is shown in FIG. 1 will be described. The source electrode is divided into a source contact electrode 23a, which is a first metal electrode, a body contact electrode 23b, which is a second metal electrode, and a top electrode 23c made of a laminated film of titanium, titanium nitride, aluminum, or the like. The entire laminated metal film exhibits the same function as a normal source electrode.
The body contact region 7 has a highly doped surface density by, for example, co-doping with magnesium and oxygen, and / or has an aluminum composition, for example, to facilitate ohmic contact with the p-type. By changing in the growth direction, a quantum well structure can be obtained. The n-type source contact region 6a and the n-type source extension region 6b are formed by, for example, ion implantation of silicon.
The n-type source contact region 6a has a box profile with a depth of, for example, 0.3 μm and an atomic density of, for example, 2 × 10 ²⁰ cm ⁻³ , and the n-type source extension region 6b extends from the bottom surface of the trench 10a. The box profile is such that the depth is, for example, 0.9 μm and the atomic density is, for example, 5 × 10 ¹⁸ cm ⁻³ . In the first embodiment, since there is not enough manufacturing margin for etching back the gate electrode 12 and the interlayer insulating film 21, silicon is grown to a depth of about 0.9 μm by using an uncommon MeV class ion implantation apparatus. Ion implantation.

The substrate 1 may be a free-standing substrate such as AlGaN (a mixed crystal of AlN and GaN), or may be one that can heteroepitaxially grow AlGaN or the like, for example, Si. Further, if the substrate 1 is not conductive like the sapphire substrate, the drain electrode 22 is connected to the front surface side of the substrate 1 in the same manner as a conventionally known InGaN light emitting diode formed on a sapphire substrate. You may make it the structure formed in.
In the following, for the sake of simplicity, the description will be continued assuming that the substrate 1 is n-type Si and the AlGaN layer after the breakdown voltage layer 3 is heteroepitaxially grown through an appropriate buffer layer. The cell pitch of the AlGaN trench gate type MOSFET of FIG. 1 is, for example, 2 μm. The width of the first trench 10a can be, for example, 1 μm (corresponding to the resolution limit), and the width of the second trench 10b can be, for example, 0.6 μm. A layer structure in which the n-type and p-type conductivity types are interchanged is also possible, but like SiC, AlGaN has higher mobility than holes, so that the main carrier is preferably an electron. Therefore, the above-described layer configuration is preferable.
A method of manufacturing the AlGaN trench gate type MOSFET will be described step by step with reference to FIGS. 2 to 8 and FIG. First, as shown in FIG. 2, a breakdown voltage layer 3, a body layer 5-1, and a body contact layer 7-1 are sequentially formed on the Si substrate 1 by heteroepitaxial growth of AlGaN. The composition of AlGaN (the ratio of AlN to GaN) may be the same in all layers or different, but for the sake of simplicity, the body contact layer 7-1 including a quantum well structure will be described below. Except for, the description will be continued assuming that all layers are GaN layers.

The doping and film thickness of the breakdown voltage layer 3 and the body layer 5-1 should be appropriately selected so as to obtain desired characteristics in consideration of manufacturing errors. For example, in the case of a withstand voltage of 600 V, the withstand voltage layer 3 has a doping of, for example, 1.2 × 10 ¹⁶ cm ⁻³ and a film thickness of, for example, 7 μm, and the body layer 5-1 has a doping of, for example, 2 × 10 ¹⁷ cm ⁻³ 5 is adjusted to be 1.5 μm, for example, which is the thickness between the source extension region 6b and the breakdown voltage layer 3 and corresponds to the channel length. The thickness of the body contact layer 7-1 can be any thickness as long as it can be controlled by epitaxial growth and has no risk of being lost inadvertently in subsequent manufacturing steps. For example, it is 0.5 μm.
Next, a silicon nitride film (which may contain oxygen and hydrogen) as a first insulating film is deposited on the entire surface of the wafer to a predetermined film thickness, for example, 1 μm, and an SiO ₂ film as a second insulating film is further formed. After film formation on the entire surface, both the SiO ₂ film and the silicon nitride film are etched with a common pattern to form a first mask 106a. The first mask 106a includes a lower silicon nitride film 107a and an upper SiO ₂ film 107b. Since the lower silicon nitride film 107a of the first mask is used later to lift off the source contact electrode 23a, a certain degree of film thickness and resistance to subsequent heat treatment are required. For example, another film may be used as long as it is a material that can be selectively removed by etching with respect to the source contact electrode 23a, such as dissolved in hot phosphoric acid.

The upper SiO ₂ film 107b of the first mask is for anisotropically etching the body contact layer 7-1 and the body layer 5-1 to form the first trench 10a and the second trench 10b. It is sufficient that the thickness is sufficient for the purpose, for example, 1 μm is sufficient. However, the lower silicon nitride film 107a and the upper SiO ₂ film 107b of the first mask together have an impurity density and a film thickness sufficient as a mask material for ions (for example, silicon) implanted into the source extension region 6b. Need to be.
Subsequently, as shown in FIG. 3, the body contact layer 7-1 is anisotropically etched using the first mask 106a to form a first trench 10a having a depth reaching the body layer 5-1. The remaining part of the body contact layer 7-1 becomes the body contact region 7. In general, a Cl-based gas is mainly used for anisotropic etching of an AlGaN layer or the like, but a silicon nitride film may be subjected to side etching to some extent. If the side etching amount is too large, a side wall protective film can be formed in the same manner as the side wall protective film 107c described later before the etching for forming the first trench 10a.
Next, as shown in FIG. 4, the SiO ₂ film is again formed on the entire surface, and then the SiO ₂ film is anisotropically etched on the entire surface of the wafer, so that at least the sidewall of the opening of the lower silicon nitride film 107a of the first mask. Then, a sidewall protective film 107c made of a SiO ₂ film is formed. At this time, the SiO ₂ film may or may not be formed on the side wall and the upper surface of the opening of the upper SiO ₂ film 107b of the first mask, and further, the upper SiO ₂ of the first mask. The film 107b may be partially etched. The thickness of the side wall protective film 107c (referring to the length to the side) may be 0.1 μm, for example.

Subsequently, as shown in FIG. 5, for example, silicon is ion-implanted into the surface of the body layer 5-1 using the first mask 106 a and the sidewall protective film 107 c as a mask. Next, if surface roughness or change in the composition of the semiconductor surface becomes a problem when performing heat treatment on the entire surface of the wafer, prior to the heat treatment, the second insulating film such as a silicon oxide film and the GaN layer are After forming a cap material such as silicon nitride that can be selectively removed by etching, heat treatment is performed at 1300 ° C. in a nitrogen atmosphere, for example, to activate the ion-implanted silicon, and thereby the source contact region 6a and the source extension Region 6b is formed. Unlike SiC, the activation annealing temperature may be 1300 ° C. On the other hand, if the first mask is a SiO ₂ film, the function as a mask is not lost until about 1350 ° C. Annealing can be completed. If a temperature exceeding 1350 ° C. is necessary for the activation annealing, as in the case of SiC, here, only a heat treatment for preventing alteration is performed if necessary, and the second trench 10b is formed to form the second mask. After removing 110b, the sidewall protective film 107c, and the upper SiO ₂ film 107b of the first mask, activation annealing may be performed again. If only the lower silicon nitride film 107a of the first mask is used, it can withstand up to at least 1400 ° C., although it depends on the film forming conditions. Thereafter, the cap made of silicon nitride is removed by dipping in, for example, hot phosphoric acid.

Next, as shown in FIG. 6, with the first mask 106a and the sidewall protective film 107c left, an SiO ₂ film is further formed on the entire surface of the wafer, and the SiO ₂ film is anisotropically etched on the entire surface of the wafer. Thus, the second mask 110b is formed at least on the side surface of the sidewall protective film 107c. Similar to the side wall protective film 107c, an SiO ₂ film may or may not be formed on the side wall and the upper surface of the opening of the upper SiO ₂ film 107b of the first mask. The upper SiO ₂ film 107b of the mask may be partially etched. The thickness (referring to the length to the side) of the second mask 110b is, for example, 0.1 μm.
Subsequently, anisotropic etching is performed to a depth reaching the breakdown voltage layer 3 from the surface of the source contact region 6a using the second mask 110b, the sidewall protective film 107c, and the first mask 106a, thereby forming the second trench 10b. (FIG. 7). Next, for example, the substrate is immersed in dilute hydrofluoric acid to remove the second mask 110b made of the SiO ₂ film, the sidewall protective film 107c, and the upper SiO ₂ film 107b (second insulating film) of the first mask. At this time, attention should be paid to the processing conditions so that the lower silicon nitride film 107a of the first mask is not lost.
Next, a silicon nitride film and a SiO ₂ film are sequentially formed, and a gate insulating film 11 made of a silicon nitride film and a SiO ₂ film is formed at least on the side wall surface and the bottom surface of the second trench 10b. Actually, at this time, the silicon nitride film and the SiO ₂ film are also formed on the side wall surface and the bottom surface of the first trench 10a and the side surface and the top surface of the lower silicon nitride film 107a of the first mask. Next, polycrystalline silicon doped with boron at a high density is formed on the entire surface of the wafer, the vicinity of the gate pad (not shown) is protected, and then etched back, whereby the gate electrode 12 is placed in the second trench 10b. Embed. Similarly, an appropriately doped SiO ₂ film is formed on the entire surface of the wafer and etched back appropriately to embed the interlayer insulating film 21 in the second trench 10b. At this time, the portion of the SiO ₂ film in the side wall surface and the bottom surface of the first trench 10a and the gate insulating film 11 formed on the side surface and the upper surface of the lower silicon nitride film 107a of the first mask is simultaneously removed. . Thereafter, the silicon nitride film remaining on at least the bottom surface of the first trench 10a is removed by immersing in, for example, hot phosphoric acid for a very short time or anisotropically etching with a fluorine-chlorine mixed plasma. However, care is taken not to lose the lower silicon nitride film 107a of the first mask.

Subsequently, as shown in FIG. 8, for example, titanium and palladium are deposited in this order by, for example, 10 nanometers by EB (Electron Beam) deposition. After that, when immersed in hot phosphoric acid, the lower silicon nitride film 107a (first insulating film) of the first mask is removed, so that titanium and palladium formed on the body contact region 7 are lifted off, and the source contact The source contact electrode 23a remains on the region 6a.
Next, a resist pattern (not shown) having an opening only in the vicinity of the cell is formed by photolithography, and further, for example, palladium is deposited by, for example, EB deposition, and then the resist is removed by immersion in an organic solvent. The palladium is lifted off, and as shown in FIG. 1, the body contact electrode 23b remains on the body contact region 7 and the source contact region 6a. Since the metal on the source contact electrode 23a becomes a part of the top electrode 23c, it is not necessary to remove it. Thereafter, heat treatment is performed in a nitrogen atmosphere at 800 ° C., for example, to obtain ohmic contact with the source contact region 6 a and the body contact region 7.
Thereafter, similarly to the process in the case of Si, for example, titanium, titanium nitride, and aluminum are sequentially stacked and patterned to form the top electrode 23c portion. Finally, the drain electrode 22 is formed on the back surface side as in the case of Si.

  Thus, the AlGaN trench gate type MOSFET shown in FIG. 1 is completed. Thus, according to the present invention, in spite of the metal electrode configuration in which different metal electrodes are brought into contact with the n-type region surface and the p-type region surface to obtain a good ohmic contact, the self-alignment is achieved. Since the cell structure can be formed, the cell pitch can be reduced.

In Example 2, an AlGaN trench gate type MOSFET whose cross-sectional view is shown in FIG. 9 will be described. Since many of the components are the same as those in the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted. In the second embodiment, the source region 6 is formed by selective epitaxial growth at least inside the first trench 10a (may protrude over the first trench 10a). In this case, since the thickness of the source region 6 can be arbitrarily determined by the depth of the first trench 10a, the gate electrode 12 and the source electrode 6 can be formed without depending on the uncommon high energy ion implantation as in the first embodiment. It is characterized in that a margin for etching back the interlayer insulating film 21 can be secured. When the same stepper as that of the first embodiment is used, the width of the first trench 10a is, for example, 0.8 μm. The width of the second trench 10b is, for example, 0.6 μm as in the first embodiment. The cell pitch is the same as in the first embodiment, for example, 2 μm.
A method of manufacturing the AlGaN trench gate type MOSFET will be described step by step with reference to FIGS. 10 to 12 and FIG. Since most of them are the same as those in the first embodiment, the description will focus on the differences from the first embodiment. First, as shown in FIG. 10, the breakdown voltage layer 3, the body layer 5-1, and the body contact layer 7-1 are sequentially formed on the Si substrate 1 by heteroepitaxial growth of AlGaN as in the first embodiment. To do.

Next, after a silicon nitride film and a SiO ₂ film are formed on the entire surface of the wafer, patterning is performed to form a lower silicon nitride film 107a and an upper SiO ₂ film 107b in the first mask 106a, respectively. Next, an SiO ₂ film is again formed on the entire surface and etched back to form a sidewall protective film 107c made of an SiO ₂ film at least on the sidewall of the opening of the lower silicon nitride film 107a of the first mask. The thickness of the side wall protective film 107c (referring to the length to the side) is, for example, 0.1 μm. Thereafter, anisotropic etching is performed from the surface of the body contact layer, which is a GaN layer, using the sidewall protective film 107c and the first mask 106a to form the first trench 10a. Since FIG. 10 is a view after forming the first trench 10a, the body contact region 7 after the body contact layer is divided by the first trench 10a is shown. The etching depth of the first trench 10a is determined according to the desired thickness of the source region 6 and is, for example, 1.5 μm.
Thereafter, as shown in FIG. 11, selective epitaxial growth is performed inside the first trench 10a using the first mask 106a and the sidewall protective film 107c as a mask to form a highly doped n-type source region 6. In FIG. 11, the surface of the source region 6 coincides with the surface of the body contact region 7, but the surface of the source region 6 depends on the conditions of selective epitaxial growth and does not necessarily have to be this way.

Subsequently, as shown in FIG. 12, with the first mask 106a and the sidewall protective film 107c remaining, an SiO ₂ film is further formed on the entire surface of the wafer, and the SiO ₂ film is anisotropically etched on the entire surface of the wafer. Thus, the second mask 110b is formed at least on the side surface of the sidewall protective film 107c. The thickness (referring to the length to the side) of the second mask 110b is, for example, 0.1 μm.
Subsequently, anisotropic etching is performed from the surface of the n-type source region 6 using the second mask 110b, the sidewall protective film 107c, and the first mask 106a to form the second trench 10b. The subsequent steps are the same as in the first embodiment. First, it is immersed in, for example, dilute hydrofluoric acid to remove the second mask 110b made of SiO ₂ film, the sidewall protective film 107c, and the upper SiO ₂ film 107b of the first mask. Next, a silicon nitride film and a SiO ₂ film are sequentially formed, and a gate insulating film 11 made of a silicon nitride film and a SiO ₂ film is formed at least on the side wall surface and the bottom surface of the second trench 10b. Thereafter, highly doped polysilicon is formed and etched back, and the gate electrode 12 is embedded in the second trench 10b. Similarly, an appropriately doped SiO ₂ film is formed and etched back to embed an interlayer insulating film 21 on the gate electrode 12 in the second trench 10b.
Next, the silicon nitride film remaining on at least the bottom surface of the first trench 10a is removed. Subsequently, for example, titanium and palladium are formed by EB vapor deposition. Thereafter, the lower silicon nitride film 107a of the first mask is removed by dipping in hot phosphoric acid to lift off titanium and palladium, thereby forming the source contact electrode 23a. Next, for example, palladium is lifted off to form the body contact electrode 23b. Subsequently, heat treatment is performed to obtain ohmic contact with the source contact region 6a and the body contact region 7. Thereafter, similarly to the process in the case of Si, the top electrode 23c portion is formed. Finally, the drain electrode 22 is formed in the same manner as Si. Thus, the AlGaN trench gate type MOSFET of FIG. 9 is completed.

  As described above, according to the present invention, the cell structure can be formed in a self-aligned manner despite the fact that different metal electrodes are brought into contact with the n-type and the p-type to achieve good ohmic contact. This is useful for reducing the cell pitch and reducing the on-resistance. In particular, the second embodiment has an advantage that a margin for etching back the gate electrode 12 and the interlayer insulating film 21 can be secured without relying on high energy ion implantation, as compared with the first embodiment.

Sectional drawing (the 8) of the principal part of the cell of the trench gate type MOSFET made from AlGaN concerning Example 1 of this invention is shown. Sectional drawing (the 1) of the principal part of the cell of the trench gate type MOSFET made from AlGaN concerning Example 1 of this invention is shown. Sectional drawing (the 2) of the principal part of the cell of the AlGaN trench gate type MOSFET concerning Example 1 of this invention is shown. Sectional drawing (the 3) of the principal part of the cell of the AlGaN trench gate type MOSFET concerning Example 1 of this invention is shown. Sectional drawing (the 4) of the principal part of the cell of the trench gate type MOSFET made from AlGaN concerning Example 1 of this invention is shown. Sectional drawing (the 5) of the principal part of the cell of the trench gate type MOSFET made from AlGaN concerning Example 1 of this invention is shown. Sectional drawing (the 6) of the principal part of the cell of the trench gate type MOSFET made from AlGaN concerning Example 1 of this invention is shown. Sectional drawing (the 7) of the principal part of the cell of the trench gate type MOSFET made from AlGaN concerning Example 1 of this invention is shown. Sectional drawing (the 4) of the principal part of the cell of the trench gate type MOSFET made from AlGaN concerning Example 2 is shown. Sectional drawing (the 1) of the principal part of the state which completed formation of the 1st trench 10a in the manufacturing process of the trench gate type MOSFET made from AlGaN concerning Example 2 is shown. Sectional drawing (the 2) of the principal part of the state which completed formation of the source region 6 in the manufacturing process of the AlGaN trench gate type MOSFET concerning Example 2 is shown. Sectional drawing (the 3) of the principal part of the state which completed formation of the source region 6 in the manufacturing process of the AlGaN trench gate type MOSFET concerning Example 2 is shown. Sectional drawing (the 5) of the principal part of the cell for demonstrating the manufacturing method of the conventional trench gate type MOSFET made from Si is shown. Sectional drawing (the 1) of the principal part of the cell for demonstrating the manufacturing method of the conventional Si trench gate type MOSFET is shown. Sectional drawing (the 2) of the principal part of the cell for demonstrating the manufacturing method of the conventional Si trench gate type MOSFET is shown. Sectional drawing (the 3) of the principal part of the cell for demonstrating the manufacturing method of the conventional Si trench gate type MOSFET is shown. Sectional drawing (the 4) of the principal part of the cell for demonstrating the manufacturing method of the conventional Si trench gate type MOSFET is shown. The principal part sectional drawing (the 5) for demonstrating the manufacturing method of the conventional SiC trench gate type MOSFET is shown. Sectional drawing (the 1) of the principal part of the cell for demonstrating the manufacturing method of the conventional SiC trench gate type MOSFET is shown. Sectional drawing (the 2) of the principal part of the cell for demonstrating the manufacturing method of the conventional SiC trench gate type MOSFET is shown. Sectional drawing (the 3) of the principal part of the cell for demonstrating the manufacturing method of the conventional SiC trench gate type MOSFET is shown. Sectional drawing (the 4) of the principal part of the cell for demonstrating the manufacturing method of the conventional SiC trench gate type MOSFET is shown.

Explanation of symbols

1 Substrate 3 Pressure-resistant layer (drift layer)
5 Body region 5-1 Body layer 6 Source region 6a Source contact region 6b Source extension region 7 Body contact region 7-1 Body contact layer 10a First trench 10b Second trench 11 Gate insulating film 12 Gate electrode 21 Interlayer insulating film 22 Drain Electrode 23 Source electrode 23a Source contact electrode 23b Body contact electrode 23c Top electrode 106a First mask 107a Lower silicon nitride film 107b Upper SiO ₂ film 107c Side wall protective film 110b Second mask.

Claims (14)

A first conductivity type withstand voltage layer and a second conductivity type body layer, each of which is composed mainly of a mixed crystal semiconductor of AlN and GaN in a required ratio on one main surface of a bulk substrate that can be epitaxially grown. A first step of laminating a body contact layer of a second conductivity type in this order by epitaxial growth; a first insulating film on the surface of the body contact layer; and a second insulating film having a different solution from the first insulating film. Are formed in this order, and a first opening penetrating the first insulating film and the second insulating film is formed by anisotropic etching to form a first mask. A second step of forming a first trench having a depth reaching the body layer from the first opening by etching; and a solution different from the first insulating film on the side wall of the first insulating film in the first trench. The third absolute After forming the film, a third step of forming a source contact region and a source extension region at the bottom of the first trench and a fourth insulating film are formed, and a second opening is formed by anisotropic etching at the bottom of the first trench. Forming a second mask to form a second mask, and forming a second trench having a depth reaching the breakdown voltage layer from the second opening by anisotropic etching using the second mask; The insulating film was removed, the gate electrode and the interlayer insulating film were embedded via the gate insulating film formed on the inner surface of the second trench, and a first metal electrode film that gave ohmic contact with the surface of the source contact region was formed. Then, a fifth step of removing the first metal electrode film on the first insulating film by removing the first insulating film and simultaneously removing the first insulating film, and providing ohmic contact to the surface of the body contact region Method of manufacturing a trench gate type semiconductor device which comprises a sixth step of forming a second metal electrode film in this order. 2. The method of manufacturing a trench gate type semiconductor device according to claim 1, wherein the bulk substrate capable of epitaxial growth is an AlGaN mixed crystal semiconductor substrate, a silicon semiconductor substrate, or a sapphire substrate. 3. The method of manufacturing a trench gate type semiconductor device according to claim 1, wherein the first insulating film is a silicon nitride insulating film, and the second to fourth insulating films are silicon oxide films. The metal in which the first metal electrode film is in contact with the surface of the source contact region is titanium and palladium, and the metal in which the second metal electrode film is in contact with the surface of the body contact region is palladium. 4. A method for manufacturing a trench gate type semiconductor device according to 3. 5. The method of manufacturing a trench gate type semiconductor device according to claim 4, wherein the lift-off of the first metal electrode film in the fifth step is performed by removing the first insulating film with hot phosphoric acid. 2. The method of manufacturing a trench gate type semiconductor device according to claim 1, wherein a single GaN semiconductor is used instead of the mixed crystal semiconductor of AlN and GaN of the required ratio. In the third step of forming the source contact region and the source extension region at the bottom of the first trench, each region is formed by ion implantation, and after the ion implantation, a fourth insulating film is formed as the second mask. 2. The method of manufacturing a trench gate type semiconductor device according to claim 1, wherein an activation heat treatment of implanted ions is performed before. 8. The method of manufacturing a trench gate type semiconductor device according to claim 7, wherein a temperature of the activation heat treatment is 1350 [deg.] C. or less. 9. The trench according to claim 8, wherein a silicon nitride film having a selectivity by etching with respect to the second insulating film and the AlN / GaN mixed crystal semiconductor material is formed as a cap material before the activation heat treatment. A method for manufacturing a gate type semiconductor device. A mixed crystal composition is formed so that the body contact region is formed by simultaneous doping during epitaxial growth so as to have a predetermined surface impurity density at which ohmic contact can be obtained and / or to form the predetermined quantum well structure. 2. The method of manufacturing a trench gate type semiconductor device according to claim 1, further comprising a step controlled in a growth direction. A plurality of second conductivity types of a first conductivity type pressure-resistant layer, a second conductivity type body layer, and a highly doped and selectively placed on one main surface of a bulk substrate that can be epitaxially grown. A body contact region in this order, and a source contact region of an upper first conductivity type and a source of a lower first conductivity type on a surface layer of the body layer between the plurality of selectively placed body contact regions. An extension region, and a trench having a width narrower than a distance between the plurality of body contact regions and a depth reaching the breakdown voltage layer from the surface of the source contact region of the first conductivity type. A gate insulating film provided on the inner surface, and a gate electrode buried so as to face the breakdown voltage layer, the body layer, and the source extension region through the gate insulating film, In a semiconductor device having a source contact region surface and a source electrode that forms ohmic contact with the body contact region surface, the source electrode that forms ohmic contact with the source contact region surface and the body contact region surface includes: A trench gate type semiconductor device comprising: a first metal electrode in ohmic contact with the surface of the source contact region; and a second metal electrode in ohmic contact with the surface of the body contact region. The trench gate type semiconductor device according to claim 11, wherein the second metal electrode covers the first metal electrode. 13. The trench gate type semiconductor device according to claim 12, wherein the uppermost layer of the metal electrode laminated on the second metal electrode is an aluminum electrode. 12. The trench gate type semiconductor device according to claim 11, wherein the body contact region includes a quantum well structure suitable for obtaining ohmic contact.

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