JP2009038140A

JP2009038140A - Semiconductor device and manufacturing method thereof

Info

Publication number: JP2009038140A
Application number: JP2007199693A
Authority: JP
Inventors: Mitsuhiro Hamada; 充弘浜田; Koichi Tomita; 光一富田
Original assignee: Panasonic Corp
Current assignee: Panasonic Corp
Priority date: 2007-07-31
Filing date: 2007-07-31
Publication date: 2009-02-19

Abstract

【課題】反りを低減し、ボンディング性能が高い外部接続（パッド）構造をもつ半導体装置を提供する。また、低コストで製造作業性が良好な外部接続構造をもつ半導体装置を提供する。
【解決手段】所望の素子領域の形成された半導体基板と、前記半導体基板表面に設けられた素子電極と前記素子電極の表面に形成されためっき層とを具備した外部接続用端子部と、前記外部接続用端子部の外部接続領域の周縁を覆うように形成された保護膜とを具備した半導体装置であって、前記外部接続領域において、前記めっき層が、分離領域を介して複数の領域に分離されたことを特徴とする。
【選択図】図１A semiconductor device having an external connection (pad) structure with reduced warpage and high bonding performance is provided. In addition, a semiconductor device having an external connection structure with low cost and good manufacturing workability is provided.
An external connection terminal portion comprising a semiconductor substrate having a desired element region formed thereon, an element electrode provided on the surface of the semiconductor substrate, and a plating layer formed on the surface of the element electrode; And a protective film formed so as to cover a peripheral edge of the external connection region of the external connection terminal portion. In the external connection region, the plating layer is formed in a plurality of regions via the separation region. It has been separated.
[Selection] Figure 1

Description

本発明は、半導体装置およびその製造方法にかかり、特に半導体ウェハの反り防止対策に関するものである。 The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to measures for preventing warpage of a semiconductor wafer.

近年、半導体ウェハの大口径化は進む一方であり、８インチから１５インチ、さらに大口径へと発展しており、収率の向上にも著しいものがある。その一方で、大口径化が進むにつれて製造工程における半導体ウェハの反りの発生が深刻な問題となっている。中でも、めっき工程においては、薄膜に比べて比較的厚い膜を形成する点、ウェットプロセスである点などから、特にめっき工程における反りは深刻である。 In recent years, the diameter of semiconductor wafers has been increasing, and it has been developed from 8 inches to 15 inches and further to a large diameter, and there is a remarkable improvement in yield. On the other hand, the warpage of the semiconductor wafer in the manufacturing process becomes a serious problem as the diameter increases. In particular, in the plating process, warping in the plating process is particularly serious because a relatively thick film is formed as compared with a thin film and a wet process.

一方、近年、半導体装置の消費電力の低減が望まれており、その手段の一つとして、半導体装置の動作時の実質的な抵抗成分である接続抵抗の低減が進められている。この抵抗成分のうち、半導体素子を保護するとともに外部接続端子としての役割を果たすパッケージの占める割合も大きいことがわかっている。 On the other hand, in recent years, reduction of power consumption of semiconductor devices has been desired. As one of the means, reduction of connection resistance, which is a substantial resistance component during operation of the semiconductor device, has been promoted. It has been found that a large proportion of the resistance component is occupied by a package that protects the semiconductor element and serves as an external connection terminal.

半導体装置の製造工程のうち、組立工程の一例は、以下のとおりである。まず、所望の素子領域および配線の形成されたウェハから切り出された半導体素子は、銅を主成分とする板状体を加工して形成され、アイランド部（半導体素子搭載部）と、このアイランド部に先端が近接するように形成されたリード端子からなるリード部とを備えたリードフレームのアイランド部に搭載される。次に、半導体素子の表面上に形成された素子電極は、金線やアルミニウム線などの連結導体を用いて、アイランド部の周縁に近接して設けられたリード端子と電気的に接続される。その後、半導体素子及びリードフレームは、リード端子の先端の一部を残して、樹脂等で封止されてパッケージ化され、半導体装置となる。ここでパッケージとは、リードを含むリードフレームと、封止樹脂とをあわせたものをいうこととする。 An example of the assembly process among the manufacturing processes of the semiconductor device is as follows. First, a semiconductor element cut out from a wafer in which a desired element region and wiring are formed is formed by processing a plate-shaped body mainly composed of copper, and an island portion (semiconductor element mounting portion) and the island portion are formed. The lead frame is mounted on an island portion of a lead frame having a lead portion formed of a lead terminal formed so that the tip is close to the lead portion. Next, the element electrode formed on the surface of the semiconductor element is electrically connected to a lead terminal provided in the vicinity of the periphery of the island portion using a connecting conductor such as a gold wire or an aluminum wire. Thereafter, the semiconductor element and the lead frame are packaged by being sealed with a resin or the like, leaving a part of the tip of the lead terminal, thereby forming a semiconductor device. Here, the package means a combination of a lead frame including leads and a sealing resin.

ここで、半導体素子とリードとの接続に、ボンディングワイヤと呼ばれる金線やアルミニウム線などの連結導体を用いた場合、１本あたりの線径が数十から数百μｍ程度である。接続抵抗を低減するためには、数十から数百本の金線やアルミニウム線などを用いる必要があり、コストの増大や組立工程の複雑化を招く。 Here, when a connection conductor such as a gold wire or an aluminum wire called a bonding wire is used for connection between the semiconductor element and the lead, the wire diameter per one is about several tens to several hundreds μm. In order to reduce the connection resistance, it is necessary to use several tens to several hundreds of gold wires, aluminum wires, and the like, which increases the cost and complicates the assembly process.

そのため、金属細線に代えて銅からなる板状の連結導体を用いて、半導体素子とリード端子を電気的に接続する方法が用いられている。そして素子電極とリード端子とを連結導体で電気的に接続するために、半田接合を用いるか超音波接合を用いるかの方法がとられている。 Therefore, a method of electrically connecting a semiconductor element and a lead terminal using a plate-like connecting conductor made of copper instead of a thin metal wire is used. In order to electrically connect the element electrode and the lead terminal with a connecting conductor, a method of using solder bonding or ultrasonic bonding is employed.

このように、素子電極とリード端子とを連結導体を用いて電気的に接続するに際しては、図１０に示すように、半導体素子１０１の素子電極に形成されるめっき層１０４からなる外部接続領域が画定されており、この周りはポリイミド樹脂などの保護膜１０６で被覆されている。ここで１０４ｓはソース電極としての外部接続領域、１０４ｇはゲート電極としての外部接続領域であるが、ソース電極は電流供給端子であるため、大電流を流すことができるように面積も大きくとる必要がある。 As described above, when the element electrode and the lead terminal are electrically connected using the connecting conductor, as shown in FIG. 10, the external connection region formed of the plating layer 104 formed on the element electrode of the semiconductor element 101 is formed. The periphery is covered with a protective film 106 such as polyimide resin. Here, 104s is an external connection region as a source electrode, and 104g is an external connection region as a gate electrode. However, since the source electrode is a current supply terminal, the area needs to be large so that a large current can flow. is there.

ところで、このめっき層１０４は、保護膜１０６の開口に選択的に形成するという方法がとられるが、めっきによる応力に起因してウェハに反りが生じるという問題があった。
このような半導体ウェハの反りは、キャリアに収納して搬送する際、キャリアにウェハが装着できないという問題を引き起こす。さらにまた、ダイシングにより個々のチップに分割し、実装する際、真空ピペットで吸引する場合に、吸引が困難となったり、半導体ウェハにクラックが入ったり、ワレが生じたりするという問題もあった。 The plating layer 104 is selectively formed in the opening of the protective film 106. However, there is a problem that the wafer is warped due to the stress due to plating.
Such warpage of the semiconductor wafer causes a problem that the wafer cannot be mounted on the carrier when it is housed in the carrier and transported. Furthermore, when dividing into individual chips by dicing and mounting, there is a problem that when sucking with a vacuum pipette, suction becomes difficult, cracks occur in the semiconductor wafer, and cracks occur.

そこで、例えば接続用のバンプと呼ばれる突起電極を形成するためのめっき工程においては、めっきによる反り対策として、半導体ウェハの裏面に応力緩和膜を形成する方法も提案されている（特許文献１）。
しかしながら、ディスクリートのＭＯＳＦＥＴの場合は裏面をドレイン端子として半導体素子搭載部にダイボンディングするため、裏面に応力緩和膜を形成するには制約が大きく、困難である場合が多い。 Therefore, for example, in a plating process for forming protruding electrodes called connection bumps, a method of forming a stress relaxation film on the back surface of a semiconductor wafer has been proposed as a countermeasure against warping by plating (Patent Document 1).
However, in the case of discrete MOSFETs, since the back surface is used as a drain terminal and die-bonded to the semiconductor element mounting portion, it is often difficult and difficult to form a stress relaxation film on the back surface.

特開2000-200799号公報JP 2000-200799 A

このように、外部接続領域におけるボンディング性能を向上するためのめっき層の形成に際し、ウェハの反りが深刻な問題となっている。これは半導体ウェハの大口径化が進むにつれて深刻となっている。
したがって、ウェハの反りを低減し、ボンディング性能が良好で、実装の容易な半導体装置が望まれていた。 As described above, when the plating layer for improving the bonding performance in the external connection region is formed, the warpage of the wafer is a serious problem. This becomes serious as the diameter of the semiconductor wafer increases.
Therefore, a semiconductor device that reduces warpage of the wafer, has good bonding performance, and is easy to be mounted has been desired.

本発明は、前記実情に鑑みてなされたもので、反りを低減し、ボンディング性能が高い、外部接続（パッド）構造をもつ半導体装置を提供することを目的とする。
また、低コストで製造作業性が良好な外部接続構造をもつ半導体装置を提供することを目的とする。 The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having an external connection (pad) structure with reduced warpage and high bonding performance.
It is another object of the present invention to provide a semiconductor device having an external connection structure that is low in cost and has good manufacturing workability.

そこで本発明は、所望の素子領域の形成された半導体基板と、前記半導体基板表面に設けられた素子電極と前記素子電極の表面に形成されためっき層とを具備した外部接続用端子部と、前記外部接続用端子部の外部接続領域の周縁を覆うように形成された保護膜とを具備した半導体装置であって、前記外部接続領域において、前記めっき層が、分離領域を介して複数の領域に分離されたことを特徴とする。
この構成により、開口している素子電極表面に分離領域が形成され、この分離領域によってめっき層が分離されているため、チップに加わる応力が低減し、ウェハの反りが低減される。また、素子電極が一体的に形成されているため、電極面積としては変化がない。さらに最表面に露呈する領域が分離領域の存在によって低減されるため、汚染のおそれが低減される。 Accordingly, the present invention provides a semiconductor substrate having a desired element region formed thereon, an element electrode provided on the surface of the semiconductor substrate, and a terminal portion for external connection comprising a plating layer formed on the surface of the element electrode; And a protective film formed so as to cover a peripheral edge of the external connection region of the external connection terminal portion. In the external connection region, the plating layer includes a plurality of regions via the separation region. It is characterized by being separated.
With this configuration, an isolation region is formed on the surface of the open element electrode, and the plating layer is separated by this isolation region, so that the stress applied to the chip is reduced and the warpage of the wafer is reduced. Further, since the element electrodes are integrally formed, there is no change in the electrode area. Furthermore, since the area exposed on the outermost surface is reduced by the presence of the separation area, the risk of contamination is reduced.

また本発明は、上記半導体装置において、前記分離領域は前記素子電極表面に形成された第２の保護膜である。
上記効果に加え、さらに最表面に露呈する領域が第２の保護膜で被覆され、この第２の保護膜の存在によって低減されるため、汚染のおそれが低減される。 According to the present invention, in the semiconductor device, the isolation region is a second protective film formed on the surface of the element electrode.
In addition to the above effect, the region exposed on the outermost surface is covered with the second protective film and is reduced by the presence of the second protective film, so that the risk of contamination is reduced.

また本発明は、上記半導体装置において、前記第２の保護膜は、前記保護膜と同一工程で形成された絶縁膜であるものを含む。 According to the present invention, in the semiconductor device, the second protective film is an insulating film formed in the same process as the protective film.

また本発明は、上記半導体装置において、前記めっき層はニッケルめっき層であるものを含む。なおニッケルめっき層上にボンディング性向上のために金あるいはパラジウムなどの薄いめっき層を形成してもよい。 The present invention includes the above semiconductor device, wherein the plating layer is a nickel plating layer. A thin plating layer such as gold or palladium may be formed on the nickel plating layer to improve bonding properties.

また本発明は、上記半導体装置において、前記第２の保護膜は無機膜であるものを含む。 According to the present invention, in the semiconductor device, the second protective film is an inorganic film.

また本発明は、上記半導体装置において、前記第２の保護膜はポリイミド樹脂で構成されたものを含む。 According to the present invention, in the semiconductor device, the second protective film includes a polyimide resin.

また本発明は、上記半導体装置において、前記半導体装置はディスクリートトランジスタであるものを含む。 According to the present invention, in the above semiconductor device, the semiconductor device is a discrete transistor.

また本発明は、上記半導体装置において、前記半導体装置は前記基板表面に複数の半導体素子が集積化された半導体集積回路であり、前記外部接続端子部は前記基板の周縁に沿って形成された複数のボンディングパッドであるものを含む。 According to the present invention, in the above semiconductor device, the semiconductor device is a semiconductor integrated circuit in which a plurality of semiconductor elements are integrated on the surface of the substrate, and the external connection terminal portions are formed along the periphery of the substrate. Including those that are bonding pads.

また本発明は、上記半導体装置において、前記めっき層の膜厚は、前記保護膜の膜厚よりも薄いものを含む。 In the semiconductor device according to the present invention, the plating layer includes a film having a thickness smaller than that of the protective film.

また本発明は、所望の素子領域の形成された半導体基板と、前記半導体基板表面に設けられた素子電極と前記素子電極の表面に形成されためっき層とを具備した外部接続用端子部と、前記外部接続用端子部の外部接続領域の周縁を覆うように形成された保護膜とを具備した半導体装置の製造方法であって、前記素子電極の表面にめっき層を形成する工程が、所望の素子領域の形成された半導体基板の外部接続用端子部の外部接続領域の周縁を覆うように保護膜を形成するとともに、前記外部接続領域を分離する分離領域を形成する工程と、前記保護膜および分離領域を除く前記素子電極表面に選択的にめっき層を形成するめっき工程とを含む。 Further, the present invention provides an external connection terminal portion comprising a semiconductor substrate in which a desired element region is formed, an element electrode provided on the surface of the semiconductor substrate, and a plating layer formed on the surface of the element electrode; A method of manufacturing a semiconductor device comprising a protective film formed so as to cover a peripheral edge of an external connection region of the external connection terminal portion, wherein the step of forming a plating layer on the surface of the element electrode includes a desired step Forming a protective film so as to cover a peripheral edge of the external connection region of the external connection terminal portion of the semiconductor substrate on which the element region is formed, and forming an isolation region for separating the external connection region; And a plating step of selectively forming a plating layer on the surface of the device electrode excluding the separation region.

また本発明は、上記半導体装置の製造方法において、前記分離領域を形成する工程は前記素子電極表面に、第２の保護膜を形成する工程を含む。 According to the present invention, in the method for manufacturing a semiconductor device, the step of forming the isolation region includes a step of forming a second protective film on the surface of the element electrode.

また本発明は、上記半導体装置の製造方法において、前記第２の保護膜は、前記保護膜と同一工程で形成されるものを含む。 According to the present invention, in the semiconductor device manufacturing method, the second protective film is formed in the same process as the protective film.

また本発明は、上記半導体装置の製造方法において、前記めっき工程は無電解ニッケルめっき工程であるものを含む。 According to the present invention, in the method for manufacturing a semiconductor device, the plating step includes an electroless nickel plating step.

また本発明は、上記半導体装置の製造方法において、前記めっき工程は最終工程が無電解金めっき工程であるものを含む。 The present invention also includes the method for manufacturing a semiconductor device, wherein the plating step includes an electroless gold plating step as a final step.

また本発明は、上記半導体装置の製造方法において、前記第２の保護膜は無機膜であるものを含む。 According to the present invention, in the method of manufacturing a semiconductor device, the second protective film is an inorganic film.

また本発明は、上記半導体装置の製造方法において、前記第２の保護膜はポリイミド樹脂で構成されたものを含む。 According to the present invention, in the method of manufacturing a semiconductor device, the second protective film includes a polyimide resin.

また本発明は、上記半導体装置の製造方法において、前記半導体装置はディスクリートトランジスタであるものを含む。 According to the present invention, in the method for manufacturing a semiconductor device, the semiconductor device is a discrete transistor.

また本発明は、上記半導体装置の製造方法において、前記半導体装置は前記基板表面に複数の半導体素子が集積化された半導体集積回路であり、前記外部接続端子部は前記基板の周縁に沿って形成された複数のボンディングパッドであるものを含む。 According to the present invention, in the semiconductor device manufacturing method, the semiconductor device is a semiconductor integrated circuit in which a plurality of semiconductor elements are integrated on the surface of the substrate, and the external connection terminal portion is formed along the periphery of the substrate. A plurality of bonded pads.

また本発明は、上記半導体装置の製造方法において、前記めっき工程は、前記めっき層の膜厚が、前記保護膜の膜厚よりも薄くなるようにしたものを含む。 The present invention includes the method for manufacturing a semiconductor device, wherein the plating step includes a thickness of the plating layer that is smaller than a thickness of the protective film.

以上詳述したように、本発明は、開口している素子電極表面に分離領域が形成され、この分離領域によってめっき層が分離されているため、チップに加わる応力が低減され、ウェハの反りが低減される。また、素子電極が一体的に形成されて入るため、電極面積としては変化がない。さらに最表面に露呈する領域が低減されるため、汚染のおそれが低減される。 As described above in detail, according to the present invention, since the separation region is formed on the surface of the open element electrode, and the plating layer is separated by this separation region, the stress applied to the chip is reduced, and the warpage of the wafer is reduced. Reduced. In addition, since the element electrodes are integrally formed, there is no change in the electrode area. Furthermore, since the area exposed on the outermost surface is reduced, the risk of contamination is reduced.

以下、本発明の実施の形態について、図面を参照しながら説明する。
（実施の形態１）
図１および図２は、本発明による半導体装置を示す上面図および断面図である。
この半導体装置は、ＭＯＳＦＥＴであり、ｎ型シリコンで構成された半導体基板１にトレンチ（図示せず）を形成し、このトレンチにゲート絶縁膜を介してゲート電極を形成するとともに、表面側にソース領域（図示せず）、半導体基板1側にドレイン領域（図示せず）を形成し、表面に酸化シリコン膜からなる絶縁膜（図示せず）を形成するとともにこの絶縁膜に開口されたコンタクト窓でＰ型の拡散層にコンタクトするように外部接続端子部としてアルミニウム薄膜からなる素子電極３表面をこの上に十字状パターンとして形成されたポリイミド樹脂からなる保護膜６Ｓで４分割し、膜厚５μｍのニッケルめっき層４と、膜厚０．５μｍの金めっき層５とを積層して電極パッド（ボンディングパッド）を形成したものである。またこの電極パッドの周りにも保護膜６としてのポリイミド樹脂が形成されている。なおめっき層の膜厚は保護膜６Ｓ（分離領域の膜厚）よりも若干小さいのが望ましい。これにより半田が十分に供給され接合強度が増大する。３ｇはゲート電極、３ｓはソース電極である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1 and 2 are a top view and a cross-sectional view showing a semiconductor device according to the present invention.
This semiconductor device is a MOSFET, in which a trench (not shown) is formed in a semiconductor substrate 1 made of n-type silicon, a gate electrode is formed in this trench via a gate insulating film, and a source is formed on the surface side. A region (not shown), a drain region (not shown) is formed on the semiconductor substrate 1 side, an insulating film (not shown) made of a silicon oxide film is formed on the surface, and a contact window opened in this insulating film The surface of the element electrode 3 made of an aluminum thin film as an external connection terminal portion is divided into four parts by a protective film 6S made of polyimide resin formed thereon as a cross-shaped pattern so as to contact the P-type diffusion layer at a thickness of 5 μm. The nickel plating layer 4 and the gold plating layer 5 having a thickness of 0.5 μm are stacked to form an electrode pad (bonding pad). A polyimide resin as a protective film 6 is also formed around the electrode pad. The thickness of the plating layer is preferably slightly smaller than the protective film 6S (the thickness of the separation region). As a result, the solder is sufficiently supplied and the bonding strength is increased. 3g is a gate electrode, 3s is a source electrode.

この十字状パターンとして形成されるポリイミド樹脂からなる保護膜６Ｓと電極パッドの周りに形成される保護膜とは同一工程で形成され、フォトリソグラフィのパターンを変えるのみで形成される。
なおここでチップサイズは１０００μｍ程度、パッドサイズは４００から６００μｍであった。 The protective film 6S made of polyimide resin formed as a cross pattern and the protective film formed around the electrode pad are formed in the same process, and are formed only by changing the photolithography pattern.
Here, the chip size was about 1000 μm, and the pad size was 400 to 600 μm.

次にこの半導体装置の製造方法について説明する。
図３に示すように、ｎ型シリコンで構成された半導体基板１に、フォトリソグラフィにより拡散用のマスクを介してＰ型の拡散層１Ｐ、Ｎ型の拡散層１Ｎを形成する。
この後、上記マスクを剥離し、表面に酸化シリコン膜からなる絶縁膜２を形成する。 Next, a method for manufacturing this semiconductor device will be described.
As shown in FIG. 3, a P-type diffusion layer 1P and an N-type diffusion layer 1N are formed on a semiconductor substrate 1 made of n-type silicon by photolithography through a diffusion mask.
Thereafter, the mask is removed, and an insulating film 2 made of a silicon oxide film is formed on the surface.

そしてフォトリソグラフィにより、図４に示すように、この絶縁膜２にコンタクト窓を開口し、絶縁膜２上にゲート電極１Ｇを形成し、さらにこのゲート電極の表面を酸化する。
そして、図５に示すように、開口されたＰ型の拡散層１Ｐ及びＮ型の拡散層１Ｎにコンタクトするように素子電極３としてアルミニウム薄膜を形成する。
この後、ポリイミド樹脂膜を形成し、フォトリソグラフィにより、外部接続領域となる領域に開口を形成する。このとき、この電極パッド形成用のマスクに付加パターンを形成し、図６に示すように、この電極パッドパターンとともにこの電極パッドパターン上に十字状の分離領域となる保護膜６Ｓを形成する。 Then, by photolithography, as shown in FIG. 4, a contact window is opened in the insulating film 2, a gate electrode 1G is formed on the insulating film 2, and the surface of the gate electrode is oxidized.
Then, as shown in FIG. 5, an aluminum thin film is formed as the element electrode 3 so as to contact the opened P-type diffusion layer 1P and N-type diffusion layer 1N.
Thereafter, a polyimide resin film is formed, and an opening is formed in a region to be an external connection region by photolithography. At this time, an additional pattern is formed on the electrode pad forming mask, and as shown in FIG. 6, a protective film 6S serving as a cross-shaped separation region is formed on the electrode pad pattern together with the electrode pad pattern.

そしてこの保護膜６および保護膜６Ｓをマスクとして、無電解ニッケルめっきを行い、図７に示すように、膜厚５μｍのニッケルめっき層４を形成し、最後に金めっきを行い膜厚０．５μｍの金めっき層５を形成する。
このようにして図１および２に示した半導体装置が形成される。 Then, using the protective film 6 and the protective film 6S as a mask, electroless nickel plating is performed to form a nickel plating layer 4 having a film thickness of 5 μm as shown in FIG. The gold plating layer 5 is formed.
In this way, the semiconductor device shown in FIGS. 1 and 2 is formed.

このようにして形成された半導体装置によれば、この分離領域６Ｓによって素子電極が４分割されているため、めっき層は分離領域６Ｓおよび保護膜６には形成されず、チップに加わる応力は大幅に低下し、分離領域を形成しない場合５ｍｍであった反りは３ｍｍ以下となった。 According to the semiconductor device formed in this way, since the element electrode is divided into four by the separation region 6S, the plating layer is not formed in the separation region 6S and the protective film 6, and the stress applied to the chip is greatly increased. When the separation region was not formed, the warpage that was 5 mm was 3 mm or less.

したがって搬送時にキャリアに装着できないというような事故はなく、また、クラックが生じたりすることもなく、歩留まりが大幅に向上した。 Therefore, there was no accident that it could not be mounted on the carrier during transportation, and there was no cracking, and the yield was greatly improved.

このようにしてめっきを行った後、ダイシングにより個々のチップに分離するが、この十字状の分離領域６Ｓを構成するパターンは位置あわせ用のパターンとしても使用することができ、リードフレームへの実装に際し真空ピペットの装着位置を決定する際の位置ずれを防止することができる。 After plating in this way, the chips are separated into individual chips by dicing. The pattern constituting the cross-shaped separation region 6S can also be used as an alignment pattern, and can be mounted on a lead frame. In this case, it is possible to prevent a displacement when determining the mounting position of the vacuum pipette.

また、めっき層は分離されているが、素子電極は一体であるため、接続抵抗、特に電気的な接続性については、十分に維持される。 Further, although the plating layer is separated, the element electrodes are integrated, so that connection resistance, particularly electrical connectivity, is sufficiently maintained.

なお、前記実施の形態１では、分離領域６Ｓをポリイミド樹脂からなる保護膜６の形成工程で同時形成したが、別途形成してもよく、分離領域６Ｓの構成材料としても酸化シリコン膜などの無機膜であってもよい。 In the first embodiment, the separation region 6S is simultaneously formed in the process of forming the protective film 6 made of polyimide resin. However, it may be formed separately, and the separation region 6S may be formed of an inorganic material such as a silicon oxide film. It may be a membrane.

（実施の形態２）
次に本発明の実施の形態２について説明する。
前記実施の形態１ではディスクリートのＭＯＳＦＥＴについて説明したが、本実施の形態では、図８に示すように、チップの周縁に沿って多数の電極パッドの配列された半導体集積回路（ＬＳＩ）について説明する。 (Embodiment 2)
Next, a second embodiment of the present invention will be described.
In the first embodiment, the discrete MOSFET has been described. In this embodiment, as shown in FIG. 8, a semiconductor integrated circuit (LSI) in which a large number of electrode pads are arranged along the periphery of the chip will be described. .

また、ＬＳＩの電極パッドに用いた場合には、特に位置あわせ用のパターンとして特別な領域を設けることなく位置あわせパターンを形成することができ、有効である。 Further, when used for an electrode pad of an LSI, an alignment pattern can be formed without providing a special area as an alignment pattern, which is effective.

（実施の形態３）
次に本発明の実施の形態３について説明する。
前記実施の形態１および２では、分離領域を保護膜で形成したが図９に示すようにフォトレジストＲを用いてもよい。
この場合は、保護膜６の形成後、フォトレジストを塗布しパターニングすることで形成される。 (Embodiment 3)
Next, a third embodiment of the present invention will be described.
In the first and second embodiments, the isolation region is formed of a protective film, but a photoresist R may be used as shown in FIG.
In this case, after the protective film 6 is formed, a photoresist is applied and patterned.

以上のように、本発明の半導体装置では、めっきによるウェハの反りを低減することができることから、ＭＯＳＦＥＴなどのディスクリート素子からＬＳＩにいたるまで外部接続構造に適用可能であり、特に大口径ウェハへの適用が有効である。 As described above, the semiconductor device of the present invention can reduce the warpage of the wafer due to plating, and thus can be applied to an external connection structure from a discrete element such as a MOSFET to an LSI, and particularly to a large-diameter wafer. Application is effective.

本発明の実施の形態１の半導体装置を示す上面図The top view which shows the semiconductor device of Embodiment 1 of this invention 本発明の実施の形態１の半導体装置を示す断面図Sectional drawing which shows the semiconductor device of Embodiment 1 of this invention 本発明の実施の形態１の半導体装置の製造工程を示す図The figure which shows the manufacturing process of the semiconductor device of Embodiment 1 of this invention. 本発明の実施の形態１の半導体装置の製造工程を示す図The figure which shows the manufacturing process of the semiconductor device of Embodiment 1 of this invention. 本発明の実施の形態１の半導体装置の製造工程を示す図The figure which shows the manufacturing process of the semiconductor device of Embodiment 1 of this invention. 本発明の実施の形態１の半導体装置の製造工程を示す図The figure which shows the manufacturing process of the semiconductor device of Embodiment 1 of this invention. 本発明の実施の形態１の半導体装置の製造工程を示す図The figure which shows the manufacturing process of the semiconductor device of Embodiment 1 of this invention. 本発明の実施の形態２の半導体装置を示す上面図The top view which shows the semiconductor device of Embodiment 2 of this invention 本発明の実施の形態３の半導体装置を示す断面図Sectional drawing which shows the semiconductor device of Embodiment 3 of this invention 従来例の半導体装置を示す上面図Top view showing a conventional semiconductor device

Explanation of symbols

１半導体基板
２絶縁膜
３素子電極
４ニッケルめっき層
５金めっき層
６保護膜
６Ｓ分離領域（保護膜）
Ｒレジスト DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Element electrode 4 Nickel plating layer 5 Gold plating layer 6 Protective film 6S Separation region (protective film)
R resist

Claims

A semiconductor substrate on which a desired element region is formed;
Formed so as to cover an external connection terminal portion provided with an element electrode provided on the surface of the semiconductor substrate and a plating layer formed on the surface of the element electrode, and a peripheral edge of the external connection region of the external connection terminal portion A semiconductor device comprising a protective film,
The semiconductor device in which the plating layer is separated into a plurality of regions through the separation region in the external connection region.

The semiconductor device according to claim 1,
The semiconductor device, wherein the isolation region is a second protective film formed on the surface of the element electrode.

3. The semiconductor device according to claim 2, wherein the second protective film is an insulating film formed in the same process as the protective film.

A semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the plating layer is a nickel plating layer.

The semiconductor device according to claim 1,
The plating layer is a semiconductor device in which the uppermost layer is a gold plating layer.

A semiconductor device according to claim 1,
The semiconductor device, wherein the second protective film is an inorganic film.

A semiconductor device according to claim 1,
The second protective film is a semiconductor device made of polyimide resin.

A semiconductor device according to claim 1,
The semiconductor device is a discrete transistor.

A semiconductor device according to claim 1,
The semiconductor device is a semiconductor integrated circuit in which a plurality of semiconductor elements are integrated on the surface of the substrate, and the external connection terminal portion is a plurality of bonding pads formed along the periphery of the substrate.

A semiconductor device according to claim 1,
The thickness of the plating layer is a semiconductor device thinner than the thickness of the protective film.

A semiconductor substrate on which a desired element region is formed;
Formed so as to cover an external connection terminal portion provided with an element electrode provided on the surface of the semiconductor substrate and a plating layer formed on the surface of the element electrode, and a peripheral edge of the external connection region of the external connection terminal portion A method for manufacturing a semiconductor device comprising a protective film,
Forming a plating layer on the surface of the element electrode,
Forming a protective film so as to cover the periphery of the external connection region of the external connection terminal portion of the semiconductor substrate on which the desired element region is formed, and forming an isolation region for separating the external connection region;
And a plating step of selectively forming a plating layer on the surface of the element electrode excluding the protective film and the isolation region.

A method for manufacturing a semiconductor device according to claim 11, comprising:
The step of forming the isolation region includes a step of forming a second protective film on the surface of the element electrode.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the second protective film is formed in the same process as the protective film.

A method of manufacturing a semiconductor device according to claim 11,
The method for manufacturing a semiconductor device, wherein the plating step is an electroless nickel plating step.

A method of manufacturing a semiconductor device according to claim 11,
The plating step is a method for manufacturing a semiconductor device, the final step of which is an electroless gold plating step.

A method of manufacturing a semiconductor device according to claim 11,
The method for manufacturing a semiconductor device, wherein the second protective film is an inorganic film.

A method for manufacturing a semiconductor device according to claim 12, comprising:
The method for manufacturing a semiconductor device, wherein the second protective film is made of a polyimide resin.

A method for manufacturing a semiconductor device according to claim 11, comprising:
A method of manufacturing a semiconductor device, wherein the semiconductor device is a discrete transistor.

A method for manufacturing a semiconductor device according to claim 11, comprising:
The semiconductor device is a semiconductor integrated circuit in which a plurality of semiconductor elements are integrated on the surface of the substrate, and the external connection terminal portion is a plurality of bonding pads formed along the periphery of the substrate. .

A method for manufacturing a semiconductor device according to any one of claims 11 to 19,
The plating step is a method of manufacturing a semiconductor device in which the thickness of the plating layer is made thinner than the thickness of the protective film.