JP2009003537A - calculator - Google Patents

Abstract

Provided is a computer having a reliability and a real-time fault tolerant function when a failure occurs while effectively utilizing a processor.
The sequential execution units 121 and 122 execute processes requiring reliability and a real-time fault tolerant function when a failure occurs, and the parallel processing unit 123 executes other processes. In the sequential execution unit, the processors are arranged in the active system 125 and the standby system 126, and the same processing is executed in the corresponding processors (101 and 103 and 102 and 104) in the active system and the standby system. When a normal system failure occurs in the sequential execution unit processor, the standby system is switched to the normal system to realize hot standby. When the failed processor is restored, it operates as a standby system. In addition, tasks are processed in parallel by the parallel processing unit processor, and when a failure occurs in the parallel processing unit processor, the task of the processor in which another parallel processing unit processor has failed is executed.
[Selection] Figure 1

Description

  The present invention relates to a distributed parallel processing technique whose main purpose is to ensure real-time performance and resilience in a system that requires a processing speed for event input and does not allow processing delay, for example.

In general, systems that require both distributed processing and redundant processing do not use the regular / standby system from the viewpoint of effective use of computing resources, and perform distributed processing using all CPUs (Central Processing Units). To do.
As an invention for simultaneously realizing improvement in processing performance and reliability, for example, Japanese Patent Laid-Open No. 2002-342300 (name: distributed processing system, distributed processing method, and distributed processing control program) (hereinafter referred to as Patent Document 1) is disclosed. Has been.

The technique described in Patent Document 1 simultaneously improves processing performance and reliability by implementing a combination of distributed processing and redundant processing using redundant computer module resources.
Specifically, when a failure occurs, it is possible to maintain the reliability and function / performance related to the important task by stopping the less important task first and degrading the function / performance. It can be allocated to important purposes.
Therefore, the technique described in Patent Document 1 is very effective when there are high and low importance tasks.

However, if a CPU that is executing a task with a limited processing time fails, processing must be allocated to another CPU and recalculated, so that there is a possibility that the execution time limit cannot be secured.
In addition, since the processing is based on event input, there is a possibility that the calculation result cannot be guaranteed, and this is a fatal problem for a computer in a system that cannot accept these results.

  An example of a system that cannot tolerate the above problem is a combat system computer. In this computer, a plurality of CPUs are installed to ensure real-time performance and redundancy for event inputs such as when a threat target is input from a shooting system. The system is divided into a normal system / standby system and is configured in a hot standby system (always operating the normal system and the standby system, and the event input is calculated in both the normal system and the standby system).

In the above computer, the CPU of the computer is divided into a normal system / standby system, and the corresponding CPU performs the same processing in the normal system and the standby system.
When an abnormality occurs in any regular CPU, all the CPUs are switched from the regular system to the standby system.
In such a system, since the fault tolerant function is emphasized, half of the CPUs cannot utilize the effectiveness even in a situation where the computer is heavily loaded.
In addition, when one normal CPU fails, all the normal CPUs shift to the standby system, which causes a problem that normal normal CPUs cannot be used for calculation.
JP 2002-342300 A

  In the system of Patent Document 1, the CPU can be used effectively, but there are problems in recovery time and reliability in the event of a failure. There is a problem that the CPU cannot be effectively used.

  Therefore, one of the main objects of the present invention is to provide a computer configuration that effectively uses a CPU mounted on a computer while placing importance on the switching time / reliability when a failure occurs.

The computer according to the present invention is:
A first processing unit including an active processor and a standby processor that replaces the active processor when a failure occurs in the active processor;
A second processing unit that includes two or more parallel processors, and the two or more parallel processors cooperate to perform distributed parallel processing;
When a failure occurs in any one of the two or more parallel processing processors included in the second processing unit that is executing processing involving communication with the processor included in the first processing unit Is designated as a takeover parallel processing processor that takes over the faulty processor execution process that was being executed by the faulty parallel processing processor in which the fault occurred, and was the communication destination of the faulty parallel processing processor in the faulty processor execution process And a processor management unit that notifies the takeover parallel processing processor to at least one of a normal processor and a standby processor.

  Even when a failure occurs in the parallel processing processor that is executing processing involving communication with the processor included in the first processing unit, the processor management unit sets the takeover parallel processing processor as the first communication partner. Since the processor of the processing unit is notified, a configuration in which a first processing unit having a fault-tolerant function and a second processing unit that performs distributed parallel processing for effective utilization of processor resources can be performed in parallel. While making effective use, it is possible to ensure reliability at the time of failure and a real-time fault-tolerant function.

Embodiment 1 FIG.
FIG. 1 is a system configuration diagram illustrating an overview of a processor configuration of a computer 1 according to the first embodiment.
In order to clarify the difference from the conventional system, the configuration of the conventional system is shown in FIG.
In FIG. 1, 101 to 110 are CPUs connected by a network 130 mounted on the computer 1.
The CPU is classified into sequential execution units 121 and 122, a parallel processing unit 123, and a parallel management unit 124.
A CPU that operates as a sequential execution unit is referred to as a sequential execution unit CPU or a sequential execution unit processor.
A CPU that operates as a parallel processing unit is referred to as a parallel processing unit CPU or a parallel processing unit processor.
A CPU that operates as a parallel management unit is referred to as a parallel management unit CPU or a parallel management unit processor.
The CPU is also classified into a normal system 125 and a standby system 126 for the sequential execution units 121 and 122 and the parallel management unit 124.
A CPU classified as a regular system is referred to as a regular system CPU or a regular processor.
A CPU classified as a standby system is referred to as a standby system CPU or a standby system processor.

The sequential execution units 121 and 122 include normal processors 101 and 102 and standby processors 103 and 104 that replace the normal processor when a failure occurs in the normal processor. The sequential execution units 121 and 122 are examples of a first processing unit.
The parallel processing unit 123 includes two or more parallel processing unit processors (parallel processing processors) 105 to 108, and the two or more parallel processing units processors 105 to 108 cooperate to perform distributed parallel processing. The parallel processing unit 123 is an example of a second processing unit.
The parallel management unit 124 includes a normal processor 109 and a standby processor 110 that replaces the normal processor when a failure occurs in the normal processor. The parallel management unit 124 is an example of a processor management unit.
In addition, the parallel management unit 124 executes any process involving communication with the processors included in the sequential execution units 121 and 122 among the two or more parallel processing unit processors 105 to 108 included in the parallel processing unit 123. Takeover parallel processing in which the active processor 109 or the standby processor 110 takes over and executes the failed processor execution process that was being executed by the failed parallel processor when the failure occurred in the processor of the parallel processor The processor is specified, and the takeover parallel processing processor is notified to at least one of the active processor and the standby processor of the sequential execution units 121 and 122 that are communication destinations of the failed parallel processing processor in the failed processor execution processing.

In this embodiment, the processing that requires the reliability at the time of failure and the real-time fault tolerant function is executed by the sequential execution units 121 and 122, and the other processing is executed by the parallel processing unit 123. In the sequential execution units 121 and 122, the respective processors are arranged in the normal system 125 or the standby system 126, and the processors (101 and 103 and 102 and 104) corresponding to the normal system and the standby system execute the same processing. When a normal system failure occurs in the sequential execution unit processor, the standby system is switched to the normal system to realize hot standby. When the failed processor is restored, it operates as a standby system. In addition, tasks are processed in parallel by the parallel processing unit processor, and when a failure occurs in the parallel processing unit processor, the task of the processor in which another parallel processing unit processor has failed is executed.
With such a configuration, in a system in which the processing performance of the entire system is required, the computer 1 having a reliability when a failure occurs for a specific process and a real-time fault tolerant function is realized.

In FIG. 1, reference numerals 111 to 114 denote tasks that are statically arranged and executed in the sequential execution units CPU 101 to 104.
Reference numerals 115 to 118 denote tasks dynamically allocated and executed by the parallel processing units CPU105 to 108.
Reference numerals 119 to 120 denote tasks for managing the parallel processing unit 123 processed by the parallel management units CPU 109 and 110 (operation status monitoring of the parallel processing unit, load status monitoring, calculation of the number of parallel processing units CPU and parallel processing unit Task management) and tasks for managing communication within the computer are shown.

The number of CPUs mounted in the computer 1 and the number of components of the sequential execution unit / parallel processing unit / parallel management unit do not have to be as shown in FIG.
The number of regular CPUs and the number of standby CPUs in the sequential execution units 121 and 122 are the same, and are 1 or more.
The number of CPUs in the parallel processing unit 123 is two or more.
The number of CPUs of the parallel management unit 124 is 1 or more and the same number in the normal / standby system, and 1 CPU is recommended. The parallel management unit 124 preferably has a redundant configuration of a normal system / standby system, but this is not essential, and the parallel management unit 124 may be configured by a single CPU.
The normal system and standby system in FIG. 1 have separate power supply systems. Although it is not necessary to use independent power sources for the normal system and the standby system, the redundancy at the time of abnormality of the power system shown in FIG. 4 is lost. FIG. 4 will be described in detail later.

In the configuration shown in FIG. 1, the sequential execution units 121 and 122 execute tasks required to guarantee the switching time and the calculation result when the CPU fails.
The sequential execution units 121 and 122 perform static task placement and always perform the same processing in the corresponding CPUs of the active / standby system, thereby realizing high-speed switching at the time of failure.
All events input to the sequential execution units 121 and 122 are input to both the normal system and the standby system for processing.
It is desirable that static task assignment in the sequential execution unit CPU should not communicate with other sequential execution unit CPUs as much as possible in consideration of changes in the communication partner due to CPU switching at the time of failure.

2 and 3 show an example of the CPU and communication switching operation at the time of CPU failure in the system having the configuration shown in FIG.
FIG. 2 shows an example of CPU switching operation when communication is not performed between the sequential execution unit and the parallel processing unit, and FIG. 3 shows an example of CPU switching operation during communication between the sequential execution unit and the parallel processing unit.
As in FIG. 1, 101 to 104 are sequential execution unit CPUs, 105 to 108 are parallel processing unit CPUs, and 109 and 110 are parallel management unit CPUs.
Reference numerals 211, 212, 311, and 312 denote communication examples between CPUs before the occurrence of a failure, and reference numerals 213, 214, 313, and 314 denote communication examples between CPUs after the occurrence of a failure.

In FIG. 2, when the sequential execution unit CPU 101 fails, the processing result of the corresponding sequential execution unit CPU 103 is used as a system. At this time, the CPU 102 continues processing as a regular system, and the communication partner of the CPU 102 is changed from the CPU 101 to the CPU 103.
The CPU 104 is a standby resource for the CPU 102. When the CPU 101 recovers from the failure, the processing result of the CPU 103 is used. When the CPU 103 fails, the calculation result of the CPU 101 is used again.

In FIG. 2, when the parallel processing unit 108 fails, the parallel processing unit 109 continues to operate with the CPUs 105 to 107 operating normally.
That is, when the CPU 108 fails, the parallel management unit CPU 109 detects the failure and allocates the task allocated to the CPU 108 to any one of the CPUs 105 to 107.
In the example of FIG. 2, the parallel management unit CPU 109 designates the CPU 105 as an allocation destination of processing of the CPU 108. The CPU 108 in which a failure has occurred is an example of a faulty parallel processing processor, and the CPU 105 to which the processing of the CPU 108 is assigned is an example of a takeover parallel processing processor.
Then, the CPU 107 communicating with the CPU 108 before the failure resumes communication with the CPU 105 assigned the task of the CPU 108 in accordance with an instruction from the parallel management unit CPU 109.

FIG. 3 shows an operation example in the case where a CPU failure occurs in a communication state extending over the sequential execution unit and the parallel processing unit.
When the sequential execution unit CPU 101 fails while the sequential execution unit CPU 101 and the parallel processing unit CPU 107 are communicating 311, the communication partner of the CPU 107 is switched to the CPU 103 by the instruction of the parallel management unit CPU 109 and performs communication of 313.
Similarly, if the parallel processing unit CPU 108 fails while the sequential execution unit CPU 102 and the parallel processing unit CPU 108 are communicating 312, the task of the CPU 108 is assigned to one of the parallel processing units CPU 105 to 107 by the parallel management unit CPU 109. Then, the communication partner of the CPU 102 switches to the CPU 105 to which the task of the CPU 108 is assigned according to the instruction of the parallel management unit CPU 109 and performs communication of 314. In this case, the CPU 104 operating as a standby system of the CPU 102 is also notified of the CPU 105 to which the task of the CPU 108 is assigned.
Also in FIG. 3, the CPU 108 in which a failure has occurred is an example of a failure parallel processing processor, and the CPU 105 to which the processing of the CPU 108 is allocated is an example of a takeover parallel processing processor.

  As described above, in the present embodiment, the parallel management units CPU 109 and 110 execute any one of the parallel processing units CPUs 105 to 108 that is executing processing involving communication with the sequential execution units CPU 101 to 104. When the failure occurred, the parallel processing unit CPU that took over the process that was being executed by the parallel processing unit CPU in which the failure occurred was specified, and was the communication destination of the parallel processing unit CPU in which the failure occurred Take over the processing of the parallel processing unit CPU in which the failure has occurred in both the normal system CPU and the standby system CPU of the sequential execution unit CPU (only one of the normal system CPU or the standby system CPU has a fault). Notify the parallel processing unit CPU.

  Next, an operation example of the computer 1 according to the present embodiment will be described with reference to FIGS.

FIG. 9 and FIG. 10 are flowcharts showing task and communication switching operations when a CPU abnormality occurs in the first embodiment.
The operation differs depending on whether the abnormality occurrence CPU (hereinafter referred to as CPU (1)) is the sequential execution unit CPU, the parallel processing unit CPU, or the parallel management unit CPU (step 901).

When CPU (1) is a sequential execution unit CPU, if the standby CPU is in operation (YES in step 902), the standby CPU is switched to the regular CPU (step 903). At this time, communication with the sequential execution unit CPU is performed for both the active system and the standby CPU, and the standby system CPU does not transmit a message in the transmission from the sequential execution unit CPU, but the standby system CPU communicates. The communication switching process does not occur because the partner is known. That is, when a failure occurs in the sequential execution unit CPU, if the standby CPU is operating, the standby CPU takes over the processing of the normal CPU without the parallel management unit CPU intervening. Further, since the standby CPU of the sequential execution unit CPU knows the parallel processing unit CPU that is the communication partner, the standby CPU sends a message to the parallel processing unit CPU that is communicating with the failed normal CPU. The parallel management unit CPU does not need to notify the parallel processing unit CPU of the communication partner.
On the other hand, when the standby CPU is stopped in step 902, there is no CPU that switches the processing of the normal CPU, so that the degenerate operation is performed in a state where the function of the CPU is lost.

In step 901, when the CPU (1) is the parallel processing unit CPU, the parallel management unit CPU processes all the following flows.
In step 904, the parallel management unit CPU determines a CPU (hereinafter referred to as CPU (2)) to which the task of CPU (1) is assigned.
Next, in step 905, the parallel management unit CPU determines whether the task of the CPU (1) includes communication processing with another CPU.
If the task does not include communication (NO in step 905), the task of CPU (1) is assigned to CPU (2) selected in step 904 (step 906).
On the other hand, when communication is included in the task of CPU (1) (YES in step 905), the communication partner CPU (hereinafter referred to as CPU (3)) is the sequential execution unit CPU, parallel processing unit CPU, or parallel management unit CPU. The processing differs depending on whether or not (step 907).
At this time, when the communication included in the task is a combination of the sequential execution unit CPU, the parallel processing unit CPU, or the parallel management unit CPU, the flow (steps 908 to 913) for all communication partners except the task switching process is performed. After that, task switching processing is performed (step 906 or 921).
The parallel management unit CPU determines whether or not the assigned task includes communication when assigning a task to the parallel processing unit CPU, and records the communication partner attribute if communication is included. Whether or not each task includes communication and the attribute of the communication partner are set in advance so that the parallel management unit CPU can confirm them.
Therefore, the parallel management unit CPU can determine whether or not the communication process is included in the task of the CPU (1) in step 905, and can determine the attribute of the communication partner CPU (3) in step 907. it can.

When the CPU (3) is the parallel processing unit CPU, the parallel management unit CPU notifies the CPU (3) of the change of the communication partner (CPU (1) to CPU (2)) (step 908), and the CPU (2) The task of CPU (1) is assigned to (step 906).
When the CPU (3) is the sequential execution unit CPU, the parallel management unit CPU confirms whether the normal system CPU and the standby system CPU corresponding to the CPU (3) are operating (step 909).
When both the normal system and the standby system are operating (YES in step 909), the communication partner is changed to both the normal CPU and the standby CPU corresponding to the CPU (3) (CPU (1) to CPU (2)). (Step 910), and the task of CPU (1) is assigned to CPU (2) (step 906).
When either the normal CPU or the standby CPU of the CPU (3) is stopped (NO in step 909, YES in step 911), the communication partner is changed (from CPU (1) to the operating CPU (3)). CPU (2)) is notified (step 912), and the task of CPU (1) is assigned to CPU (2) (step 906).
When the CPU (3) is stopped for both the active system and the standby system (NO in step 909, NO in step 911), it is confirmed whether or not the communication with the CPU (3) includes synchronous communication (step 913). If communication is not included, the task of CPU (1) is assigned to CPU (2) (step 906). If synchronous communication is included, the task of CPU (1) is discarded (step 914).
When synchronous communication is included in the communication with the CPU (3), when the task is allocated to the CPU (2) in a situation where the CPU (3) is stopped for both the normal system and the standby system, the CPU (2) In order to prevent this, since the CPU (2) will continue to wait for a message from the CPU (3) that has stopped operating, and the CPU (2) will fall into a deadlock state. , The task of CPU (1) is to be discarded.
When the CPU (3) is the parallel management unit CPU, the parallel management unit CPU controls the communication of the parallel processing unit CPU, so that the communication switching process is unnecessary, and the task switching process of step 921 is performed.

If the CPU (1) is the parallel management unit CPU in step 901 and the standby CPU of the parallel management unit is operating (YES in step 914), the standby CPU is switched to the regular CPU ( Step 915), the parallel management unit CPU notifies all of the parallel processing units CPU of switching of the parallel management unit CPU (step 916).
On the other hand, when the parallel management unit CPU is in a stopped state in step 914, there is no active CPU in the parallel management unit, and unless the parallel processing unit CPU communicates with the parallel management unit CPU, The task processing is continued (step 917).
When the parallel processing unit CPU needs to communicate with the parallel management unit CPU (YES in step 918), the CPU waits until one of the parallel processing units CPU is restarted (step 919).
When one of the parallel management units CPU is restarted in step 919, the restarted parallel management unit CPU issues a restart notification to all the parallel processing units CPU (step 916), and the processing is continued.

FIG. 4 shows an example of the CPU switching operation when the power supply system is abnormal in the system having the configuration shown in FIG.
An active system 413 composed of CPUs 101, 102, 105, 106, 109 and a standby system 414 composed of CPUs 103, 104, 107, 108, 110 are an independent power system 1 (411) and 2 (power supply 2). 412).
The distinction between the normal system 413 and the standby system 414 in FIG. 4 is a distinction in the power supply system, and does not necessarily match the regular system 125 and the standby system 126 in FIG.
Specifically, in FIG. 1, the CPUs 105 to 108 that are the parallel processing units CPU are not distinguished from the normal system / standby system, but in FIG. 4, the CPUs 105 and 106 are distinguished from the regular system as the power system, and the CPU 107 , 108 are classified into standby systems.
When an abnormality occurs in the power supply 1 (411) that is the normal system power supply, the processing of the normal CPUs 101, 102, 105, 106, and 109 is switched to the processing of the standby CPUs 103, 104, 107, 108, and 110.
That is, when a failure occurs in the power supply 1 (411) that is the normal power supply, the standby CPUs 103 and 104 of the sequential execution unit take over and execute the processing that was performed by the normal CPUs 101 and 102 of the sequential execution unit. The processing executed by the parallel processing units CPU 105 and 106 is executed by the parallel processing units CPU 107 and 108, and the processing executed by the active CPU 109 of the parallel management unit is taken over by the standby CPU 110 of the parallel management unit. Execute.
For example, the CPU 107 and the CPU 108 that performed the periodic process C before the occurrence of the failure of the power supply 1 take over the periodic process A and the periodic process B that were performed by the CPU 105 and the CPU 106 due to the occurrence of the failure of the power supply 1. Thereafter, the periodic processes A to C are performed.
Note that switching from the service system 413 to the standby system 414 is performed by the processing shown in FIG. Specifically, the target of the CPU (1) in step 901 in FIG. 9 is all the sequential execution unit CPU, parallel processing unit CPU, and parallel management unit CPU, and the sequential execution unit CPUs 101 and 102 are transferred to step 902. The parallel processing units CPU 104 and 106 perform the process of step 904, and the parallel management unit CPU 109 performs the process of step 914, thereby switching from the normal system 413 to the standby system 414.

Next, an operation example of task assignment to the parallel processing unit by the parallel management unit will be described.
Task allocation to the parallel processing unit may be a general method in the distributed / parallel processing field, but here, a CPU to be processed in parallel is calculated using task execution time prediction, and is assigned to a CPU with a low load.

FIG. 5 shows a system in which tasks are executed with as few CPUs as possible within a range that satisfies user requirements.
In the following, the description will be made on the assumption that the task of the parallel processing unit CPU by the parallel management unit CPU before the failure occurs, but the method shown in FIG. 5 may be applied to the task allocation of the parallel processing unit CPU after the failure occurs. Good.

First, the user defines an execution time threshold value X and a shortened time threshold value Y (X and Y are set to values larger than 0).
As the execution time threshold value X, an execution time allowable for one process is input, and the execution time threshold X is executed by the minimum CPU capable of processing with an execution time lower than X. That is, the execution time threshold value X indicates the upper limit allowable value of the execution time of distributed parallel processing by the parallel processing unit processor.
The shortening time threshold Y is a shortening time of the execution time required when the number of CPU usage is increased by 1. When Y is not satisfied, the processing is performed without increasing the number of CPUs even if the processing time is not less than X. That is, the shortening time threshold Y indicates a lower limit allowable value with respect to the shortening range of the execution time when the number of parallel processing unit processors is increased by one.

The parallel management unit CPU predicts task execution times P (1) to P (N), where N is the number of CPUs installed in the computer 1 (step 501). P (1) is a predicted execution time when a task is executed by one CPU, and P (N) is a predicted execution time when a task is executed by distributed parallel processing by N CPUs.
The parallel management unit CPU determines whether the predicted execution time (P (1)) when the number of CPUs is 1 is equal to or less than X (steps 502 and 503). If the condition is satisfied (YES in step 503), the parallel processing unit A task is assigned to the CPU with the lowest load factor in the CPU.
If the condition is not satisfied in step 503 (NO in step 503), does the parallel management unit CPU satisfy the user-defined execution time reduction request (reduction time threshold Y) when the CPU usage number is increased by 1? If it is determined (step 504) and the condition is satisfied (YES in step 504), the determination in step 503 is performed when the CPU is increased by 1 (step 505), and the process is repeated until the maximum number of CPUs is reached.
If the condition of step 504 is not satisfied (NO in step 504), or if the allocation determination in the maximum number of CPUs has passed (YES in step 506), the parallel management unit CPU refers to the load status of the parallel processing unit (step 507), the task is divided for execution by n CPUs (step 508).
Then, the parallel management unit CPU assigns the divided tasks in order from the CPU with the lowest load factor (step 509). However, when executing with the maximum number of CPUs, the load status is not referred to, and divided tasks are assigned to all CPUs.

A specific example of the process shown in FIG. 5 is shown in FIG.
In FIG. 11A, when the number of CPUs n = 1, the predicted execution time P (1) is larger than the execution time threshold value X, and the reduction width in P (2) -P (1) is the reduction time. It is larger than the threshold Y.
For this reason, the parallel management unit CPU increases the number of CPUs by one and sets the number of CPUs n = 2. In this case, the predicted execution time P (2) is larger than the execution time threshold value X, and the shortening range in P (3) -P (2) is larger than the shortening time threshold value Y.
For this reason, the parallel management unit CPU increments the number of CPUs by one to set the number of CPUs n = 3. In this case, since the predicted execution time P (3) is smaller than the execution time threshold value X, the parallel management unit CPU determines to execute the task with three CPUs.

In FIG. 11B, when the number of CPUs n = 1, the predicted execution time P (1) is larger than the execution time threshold value X, and the reduction width in P (2) -P (1) is the reduction time. It is larger than the threshold Y.
For this reason, the parallel management unit CPU increases the number of CPUs by one and sets the number of CPUs n = 2. In this case, the predicted execution time P (2) is larger than the execution time threshold value X, but since the reduction width in P (3) -P (2) is smaller than the reduction time threshold value Y, the parallel management unit CPU The two CPUs are determined to execute the task.

As described above, the parallel management unit CPU obtains from the user the upper limit allowable time of the distributed parallel processing by the parallel processing unit CPU as an execution time threshold, and executes when the number of parallel processing units CPU is increased by one. Obtaining the lower limit allowable value for the reduction width of time from the user as a reduction time threshold, calculating the predicted execution time when executing a specific task by distributed parallel processing while increasing the number of parallel processing units CPU one by one, Each predicted execution time is compared with the execution time threshold value, and the shortening range from each predicted execution time to the predicted execution time when the parallel processing unit CPU is increased by one is compared with the reduced time threshold value. Based on the comparison result between the execution time and the execution time threshold, and the comparison result between the shortening range of the predicted execution time and the reduction time threshold, the number of parallel processing units CPU to which a specific task is assigned is determined.
Specifically, when the parallel management unit CPU compares the reduction width of the predicted execution time with the reduction time threshold, and the reduction width is less than the reduction time threshold, the parallel management unit CPU determines the number of parallel processing units CPU of the predicted execution time. The number of parallel processing units CPU to which a specific task is assigned is determined, and as a result of comparing the shortening range of the predicted execution time with the shortening time threshold value, The predicted execution time increased by one and the execution time threshold value are compared, and if the comparison result shows that the predicted execution time is less than or equal to the execution time threshold value, the number of parallel processing units CPU of the predicted execution time is specified Decrease as the number of parallel processing units CPU to which tasks are assigned, and when the predicted execution time exceeds the execution time threshold, the reduction range from the predicted execution time to the predicted execution time when the number of parallel processing units CPU is increased by one When Comparing the reduced time threshold.

  As described above, by adopting the computer configuration shown in the first embodiment, it is possible to guarantee the execution time of a specific task and ensure the resilience of the entire computer, and minimize the degradation of processing performance when a failure occurs. It is possible to suppress.

  In the present embodiment, the distributed processing system is configured by a plurality of processors and performs distributed processing. Each processor selectively operates as an active system and a standby system, and one of processes input to the system. A distributed parallel processing device including means for parallel processing of the tasks of a part and fault tolerance processing means for performing fault tolerance processing together with the distributed parallel processing has been described.

  In this embodiment, part of the fault tolerance means is provided in a management processor that does not perform distributed parallel processing, and a processor that executes both distributed parallel processing and fault tolerance means, and a processor that executes parallel distributed processing. The distributed parallel processing device composed of processors that execute fault tolerance processing has been described.

  Further, in the present embodiment, there are means for physically having a plurality of power supply systems, a means for arranging a processor in each power supply system, means for selectively selecting and switching the power supply system, means for detecting an abnormality in the power supply system, The distributed parallel processing device including means for switching to a power system of another system when the power system is abnormal has been described.

Embodiment 2. FIG.
FIG. 6 is a system configuration diagram showing an overview of the processor configuration of the computer 1 according to the second embodiment.
The configurations of the sequential execution units CPU601 to 604, the parallel processing units CPU605 to 608, the computer normal system 613, and the standby system 614 are the same as those of the first embodiment shown in FIG.
In the second embodiment, the parallel processing unit tasks 609 to 612 shown in FIG. 6 are different from the parallel processing unit tasks 115 to 118 shown in FIG. 1, and the parallel management unit 124 shown in FIG. 1 does not exist.
That is, some or all of the tasks 119 to 120 of the parallel management unit CPU shown in FIG. 1 are processed by the parallel processing unit tasks 609 to 612 of FIG.
1 may be processed by the parallel processing unit of FIG. 6, but here the load status of the parallel processing unit is monitored in consideration of the processing load and the number of CPUs of the parallel processing unit shown in FIG. No calculations will be performed.

  The operation when a failure occurs in the sequential execution unit CPU and the parallel processing unit CPU shown in FIG. 6 is the same as that of the first embodiment shown in FIGS. 2 and 3, but communication across the sequential execution unit and the parallel processing unit. This control is performed by the parallel processing unit CPU.

  Thus, in the present embodiment, the parallel processing unit processor included in the parallel processing unit (second processing unit) operates as the parallel management unit (processor management unit) described in the first embodiment, and Similar to the parallel management unit described in the first aspect, when a failure occurs in any of the parallel processing units that were executing processing involving communication with the sequential execution unit processor, the failed parallel processing processor in which the failure occurred Specifies the takeover parallel processing processor that takes over the faulty processor execution process that was executing and executes the faulty processor execution process. At least one of the active processor and standby processor that was the communication destination of the faulty parallel processing processor in the faulty processor execution process Notify the takeover parallel processing processor.

As for task allocation when a CPU failure occurs in the parallel processing unit CPU, a generally disclosed method such as the method disclosed in Patent Document 1 may be used.
Here, as shown in FIG. 7, the CPU to which the task of the CPU in which the failure has occurred is sequentially arranged in the order of the CPU number.
Reference numerals 701 to 708 in FIG. 7 denote parallel processing units CPU, and the configuration is changed from that in FIG. 2 for easy explanation.
When the first CPU failure 709 occurs in the parallel processing unit, the task of the CPU 705 in which the CPU failure 709 has occurred is assigned to the CPU 701 with the CPU number # 2.
Next, when the CPU failure 710 occurs, the task of the CPU 703 in which the CPU failure 710 has occurred is assigned to the CPU 702 with the CPU number # 3.
Further, when the CPU failure 711 occurs, since the CPU 703 having the CPU number # 4 has failed, the task of the CPU 707 in which the CPU failure 711 has occurred is assigned to the CPU 704 having the CPU number # 5.

  In the case of the method of FIG. 7, each CPU periodically changes its own operation status so that each CPU can recognize the number of normal operation CPUs (or the number of faulty CPUs) and normal operation CPU numbers (or faulty CPU numbers). Report to CPU. In addition, each CPU can share the same parallel task management information, and by arranging the program so that each CPU can execute all the processing, it is possible for another CPU to substitute the task of the failed CPU. Become.

As described above, by adopting the computer configuration shown in the second embodiment (FIG. 6), it is possible to guarantee the execution time of a specific task and ensure the resilience of the entire computer, and to reduce the processing performance when a failure occurs. Can be minimized.
In addition, the number of CPUs can be reduced by two or more compared to the configuration shown in Embodiment 1 (FIG. 1).

  As described above, in the present embodiment, the fault tolerance means is provided in each of the processors, and the switching means between the normal system and the standby system when an arbitrary processor fails, and when the processor executing parallel processing fails A distributed parallel processing apparatus including task allocation means for other processors and means for causing each processor to process the fault tolerance means together with distributed parallel processing has been described.

Finally, a hardware configuration example of the computer 1 shown in the first and second embodiments will be described.
FIG. 12 is a diagram illustrating an example of hardware resources of the computer 1 illustrated in the first and second embodiments.
Note that the configuration of FIG. 12 is merely an example of the hardware configuration of the computer 1, and the hardware configuration of the computer 1 is not limited to the configuration described in FIG. 12, but may be another configuration.

The computer 1 includes a CPU 911 (also referred to as a central processing unit, a central processing unit, a processing unit, a processing unit, a microprocessor, a microcomputer, and a processor) that executes a program, as shown in FIGS. . The CPU 911 is connected to, for example, a ROM (Read Only Memory) 913, a RAM (Random Access Memory) 914, a communication board 915, a display device 901, a keyboard 902, a mouse 903, and a magnetic disk device 920 via a bus 912. Control hardware devices. Further, the CPU 911 may be connected to an FDD 904 (Flexible Disk Drive), a compact disk device 905 (CDD), a printer device 906, and a scanner device 907. Further, instead of the magnetic disk device 920, a storage device such as an optical disk device or a memory card read / write device may be used.
The RAM 914 is an example of a volatile memory. The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of the storage device.
The communication board 915, the keyboard 902, the scanner device 907, the FDD 904, and the like are examples of input devices.
The communication board 915, the display device 901, the printer device 906, and the like are examples of output devices.

The communication board 915 may be connected to a LAN (Local Area Network), the Internet, a WAN (Wide Area Network), etc., for example.
The magnetic disk device 920 stores an operating system 921 (OS), a window system 922, a program group 923, and a file group 924. The programs in the program group 923 are executed by the CPU 911, the operating system 921, and the window system 922.

  The program group 923 stores programs that execute the functions described as “sequential execution unit”, “parallel processing unit”, and “parallel management unit” in the description of the first and second embodiments. The program is read and executed by the CPU 911.

In the description of the first and second embodiments, the file group 924 includes “determination of”, “calculation of”, “comparison of”, “calculation of”, “assignment of”, and “setting of”. ”,“ Registering ”, etc., information, data, signal values, variable values, and parameters indicating the results of the processing are stored as“ ˜file ”and“ ˜database ”items.
The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory. Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit, and extracted, searched, referenced, compared, Used for CPU operations such as calculation, calculation, processing, editing, output, printing, and display.
Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the CPU operations of extraction, search, reference, comparison, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
The arrows in the flowcharts described in the first and second embodiments mainly indicate input / output of data and signals. The data and signal values are the memory of the RAM 914, the flexible disk of the FDD904, the compact disk of the CDD905, and the magnetic field. Recording is performed on a recording medium such as a magnetic disk of the disk device 920, other optical disks, mini disks, DVDs, and the like. Data and signals are transmitted online via a bus 912, signal lines, cables, or other transmission media.

  In addition, what is described as the operation of “˜unit” in the description of the first and second embodiments may be “˜step”, “˜procedure”, and “˜processing”.

  Thus, the computer 1 shown in the first and second embodiments includes a CPU as a processing device, a memory as a storage device, a magnetic disk, a keyboard as an input device, a mouse, a communication board, etc., a display device as an output device, a communication board, etc. The predetermined processing is realized by using these processing devices, storage devices, input devices, and output devices.

FIG. 3 is a block diagram showing a basic configuration of a computer in the first embodiment. 6 is a diagram illustrating an example of a processor switching operation when a computer failure occurs in the first embodiment. FIG. 6 is a diagram illustrating an example of switching operation of communication between processors when a computer failure occurs in the first embodiment. FIG. 6 is a diagram illustrating an example of a switching operation when the power supply system of the computer according to the first embodiment is abnormal. FIG. 3 is a flowchart illustrating an operation of allocating a parallel execution task of a computer to a processor in the first embodiment. FIG. 6 is a block diagram showing a basic configuration of a computer in a second embodiment. 10 is a diagram illustrating an example of a processor switching operation when a computer failure occurs in the second embodiment. FIG. It is a block diagram which shows the structure of the distributed system which attaches importance to the fault tolerant function in the past. FIG. 6 is a flowchart illustrating an operation example when a failure occurs in a computer according to the first embodiment. FIG. 6 is a flowchart illustrating an operation example when a failure occurs in a computer according to the first embodiment. FIG. 11 is a diagram illustrating a specific example of allocation of processors to parallel execution tasks in the first embodiment. FIG. 3 is a diagram illustrating a hardware configuration example of a computer in the first and second embodiments.

Explanation of symbols

  1 computer, 121 sequential execution unit, 122 sequential execution unit, 123 parallel processing unit, 124 parallel management unit, 125 regular system, 126 standby system, 413 regular system, 414 standby system, 613 regular system, 614 standby system.

Claims (10)

A first processing unit including an active processor and a standby processor that replaces the active processor when a failure occurs in the active processor;
A second processing unit that includes two or more parallel processors, and the two or more parallel processors cooperate to perform distributed parallel processing;
When a failure occurs in any one of the two or more parallel processing processors included in the second processing unit that is executing processing involving communication with the processor included in the first processing unit Is designated as a takeover parallel processing processor that takes over the faulty processor execution process that was being executed by the faulty parallel processing processor in which the fault occurred, and was the communication destination of the faulty parallel processing processor in the faulty processor execution process And a processor management unit for notifying at least one of a normal processor and a standby processor of the takeover parallel processing processor. The processor management unit
An active processor and a standby processor that replaces the active processor in the event of a failure of the active processor,
At least one of an active processor and a standby processor
The fault that the faulty parallel processing processor in which the fault occurred was executing when a fault occurred in any of the parallel processing processors that were executing processing involving communication with the processor included in the first processing unit The takeover parallel processing processor which designates a takeover parallel processing processor to take over and execute the processor execution processing, and is set as at least one of a normal processor and a standby processor which are communication destinations of the faulty parallel processing processor in the faulty processor execution processing The computer according to claim 1, wherein: One or more parallel processing processors included in the second processing unit,
Fault parallel processing in which a fault has occurred when a fault has occurred in any of the parallel processing processors operating as the processor management unit and executing processing involving communication with the processor included in the first processing unit Designating a takeover parallel processing processor to take over the failed processor execution process that was being executed by the processor, and at least one of a normal processor and a standby processor that were communication destinations of the failed parallel processing processor in the failed processor execution process The computer according to claim 1 or 2, wherein the takeover parallel processing processor is notified to any one of them. The processor management unit
When the fault processor execution process executed by the fault parallel processor includes communication with any other parallel processor, the parallel that was the communication destination of the fault parallel processor in the fault processor execution process 4. The computer according to claim 1, wherein the processor is notified of the takeover parallel processing processor. The normal processor of the first processing unit, some parallel processing processors included in the second processing unit, and the normal processor of the processor management unit are connected to a normal power supply, and the normal power supply Powered,
The standby processor of the first processing unit, the remaining parallel processors included in the second processing unit, and the standby processor of the processor management unit are connected to a standby system power supply, and power is supplied from the standby system power supply. Supplied
When a failure occurs in the normal power supply, the standby processor of the first processing unit takes over and executes the processing that was performed by the normal processor of the first processing unit, and the second processing The processing executed by a part of the parallel processing processors included in the processing unit was executed by the remaining parallel processing processors included in the second processing unit, and was executed by the normal processor of the processor management unit. The computer according to claim 2, wherein the standby processor of the processor management unit takes over and executes the processing. The processor management unit
Get the upper limit of the execution time of distributed parallel processing by the parallel processor as the execution time threshold,
Get the lower limit allowable value for the execution time reduction width when the number of parallel processing processors is increased by one as the reduction time threshold,
Calculate the predicted execution time when executing a specific task by distributed parallel processing while increasing the number of parallel processors one by one, compare each predicted execution time with the execution time threshold, and each predicted execution Compares the reduction range from the time to the predicted execution time when the number of parallel processors is increased by one and the reduction time threshold, the comparison result between the predicted execution time and the execution time threshold, and the reduction range and reduction time of the predicted execution time. 6. The computer according to claim 1, wherein the number of parallel processing processors to which the specific task is assigned is determined based on a comparison result with a threshold value. The processor management unit
As a result of comparing the predicted execution time reduction width with the reduction time threshold, if the reduction width is less than the reduction time threshold, the number of parallel processing processors to which the specific task is assigned is determined as the number of parallel processing processors with the predicted execution time. Determined as
As a result of comparing the reduction width of the predicted execution time and the reduction time threshold, if the reduction width is equal to or greater than the reduction time threshold, the prediction execution time obtained by increasing the number of parallel processors by one and the execution time threshold are compared. As a result of the comparison, when the predicted execution time is less than or equal to the execution time threshold, the number of parallel processing processors of the predicted execution time is determined as the number of parallel processing processors to which the specific task is assigned, and the predicted execution time The reduced time threshold is compared with a shortened range from the predicted execution time to a predicted execution time when the number of parallel processing processors is increased by one when the execution time threshold is exceeded. calculator. Two or more parallel processors that cooperate to perform distributed parallel processing;
A processor management unit that determines the number of parallel processing processors to which a specific task is assigned;
The processor management unit
Get the upper limit of the execution time of distributed parallel processing by the parallel processor as the execution time threshold,
Get the lower limit allowable value for the execution time reduction width when the number of parallel processing processors is increased by one as the reduction time threshold,
Calculate the predicted execution time when executing a specific task by distributed parallel processing while increasing the number of parallel processors one by one, compare each predicted execution time with the execution time threshold, and each predicted execution Compares the reduction range from the time to the predicted execution time when the number of parallel processors is increased by one and the reduction time threshold, the comparison result between the predicted execution time and the execution time threshold, and the reduction range and reduction time of the predicted execution time. A computer which determines the number of parallel processing processors to which the specific task is assigned based on a comparison result with a threshold value. The processor management unit
As a result of comparing the predicted execution time reduction width with the reduction time threshold, if the reduction width is less than the reduction time threshold, the number of parallel processing processors to which the specific task is assigned is determined as the number of parallel processing processors with the predicted execution time. Determined as
As a result of comparing the reduction width of the predicted execution time and the reduction time threshold, if the reduction width is equal to or greater than the reduction time threshold, the prediction execution time obtained by increasing the number of parallel processors by one and the execution time threshold are compared. As a result of the comparison, when the predicted execution time is less than or equal to the execution time threshold, the number of parallel processing processors of the predicted execution time is determined as the number of parallel processing processors to which the specific task is assigned, and the predicted execution time 9. The shortened time threshold is compared with the shortened range from the predicted execution time to the predicted execution time when the number of parallel processors is increased by one when the execution time threshold is exceeded. calculator. The processor management unit
The specific task is divided by the determined number of parallel processing processors, the load state of each parallel processing processor is investigated, and the divided tasks are allocated in order from the parallel processing processor having the smallest load. The computer according to 8 or 9.

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