JP2009003461A - Display device and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device that controls the power, while maintaining the continuity of gradation in the display device, and to provide a driving method for the device. <P>SOLUTION: In this driving method for the display device, predetermined one or more light-emitting blocks are provided in each field, and the halftone is displayed by the combination of the light emission block. For the discontinuous part of light emission luminance caused by combination of the light emission blocks, addition or subtraction processing of gradation level is performed for the discontinuous gradation by calculations according to the input gradation level. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device and a driving method thereof, and in particular, has a plurality of light-emitting blocks composed of a plurality of light-emitting pulses in each field such as a plasma display panel (PDP), and the light-emitting block The present invention relates to a display device that displays halftones in combination, and a driving method of such a display device.

  2. Description of the Related Art In recent years, with the increase in size of display devices, thin display devices are required, and various types of thin display devices are provided. For example, matrix panels that display digital signals as they are, that is, gas discharge panels such as PDPs, matrix panels such as DMD (Digital Micromirror Device), EL display elements, fluorescent display tubes, and liquid crystal display elements are provided. . Among such thin display devices, the gas discharge panel is easy to enlarge because of a simple process, is self-luminous, has good display quality, and has a high response speed. It is considered as the most promising candidate for a large-screen direct-view HDTV (high-definition television) display device.

  For example, in a PDP, each field has a plurality of light emission blocks (subfield: SF) composed of a plurality of light emission pulses, and a halftone is displayed by a combination of the light emission blocks. The power consumed by the light emission of the PDP is substantially proportional to the number of light emission pulses (sustain discharge pulse: sustain pulse) contributing to the light emission, and by controlling the total number of light emission pulses in each field, Power consumption can be controlled. The number of light emission pulses must be controlled without creating an image quality degradation factor. However, when the determined number of light emission pulses is distributed to each subfield, a discontinuous portion occurs in the gradation depending on the total number of light emission pulses. . Therefore, in a display device that displays halftones by combining light emitting blocks, the gradation that is a discontinuous portion (step) is controlled so that the luminance changes smoothly to compensate for the continuity of light emission and light emission. It is desired to provide a display device that can control the power consumed by the power supply and a driving method thereof.

  In this specification, the term “field” is used assuming that, for example, two frames of an odd number and an even number for interlaced display of an image of one frame are used. When an image is displayed progressively, the word “field” can be applied as it is by replacing it with “frame”.

  Conventionally, the setting of the light emission pulse is performed, for example, by calculating the display load factor for each frame from the display data, and calculating based on the display load factor for each frame (field), so that the power consumption of the display device is constant. It is controlled not to exceed the value. References disclosing such technology include, for example, Japanese Unexamined Patent Publication Nos. 06-332397 and 2000-098970.

  Specifically, Japanese Patent Application Laid-Open No. 06-332397 discloses an integration unit that integrates the number of pixel signals of a predetermined level given during a predetermined period, and a frequency change unit that changes the panel drive frequency based on the integration result of the integration unit. Japanese Patent Laid-Open No. 2000-098970 discloses integrating means for integrating the number of pixel signals given during a predetermined period in units of bit signals for gradation display. A plasma display device is disclosed that includes frequency changing means for changing the frequency of the sustain discharge waveform based on the integration result of the integrating means.

  FIG. 1 is a block diagram showing an example of a display device to which the present invention is applied, and shows an example of a plasma display device (plasma display panel: PDP). In FIG. 1, reference numeral 1 is a data converter, 2 is a frame memory, 3 is a power control circuit, 4 is a driver control circuit, 5 is a power supply, 6 is an address driver, 7 is a Y driver, 8 is an X driver, and 9 Indicates a display panel.

  As shown in FIG. 1, the data converter 1 receives an image signal and a vertical synchronization signal Vsync from the outside, and data for PDP (data for displaying an image by a plurality of light emission blocks (subfields SF)). Convert to The frame memory 2 holds the data for the next field converted by the data converter 1 for PDP. Then, the data converter 1 supplies the data previously held in the frame memory 2 as address data to the address driver 6 and supplies the display load factor to the driver control circuit 4. Here, the display load factor is a load factor obtained by counting the number of lighting cells (light emitting dots) in each light emission block.

  The driver control circuit 4 receives from the power control circuit 3 the control signal of the number of light emission pulses (sustain pulse number) of each light emission block (SF) and the internally generated vertical synchronization signal Vsync2, and sends drive control data to the Y driver 7. Supply. Note that the display load factor data signal from the data converter 1 is supplied to the power control circuit 3 via the driver control circuit 4.

  The display panel 9 is provided with address electrodes A1 to Am, Y electrodes Y1 to Yn, and an X electrode X, which are driven by an address driver 6, a Y driver 7, and an X driver 8, respectively. The power supply 5 supplies power to the address driver 6, Y driver 7 and X driver 8, and detects the voltage and current for the address driver 6, Y driver 7 and X driver 8 and supplies them to the power control circuit 3. . That is, the address voltage and current of the address driver 6 and the detected values of the sustain voltage and current of the Y driver 7 and the X driver 8 are supplied from the power supply 5 to the power control circuit 3 and used for processing in the power control circuit 3. . Here, the display panel unit includes an address driver 6, a Y driver 7, an X driver 8, and a display panel 9.

  FIG. 2 is a diagram for explaining an example of a driving method in the display device shown in FIG.

  The driving method shown in FIG. 2 displays an image of one frame by interlacing in two fields, odd and even, and each odd and even field has a plurality of light-emitting blocks (subfields: for example, seven subfields). Fields SF0 to SF6). Each of the light emission blocks SF0 to SF6 has an address period in which address discharge of the lighted cell is performed according to address data, and a light emission period in which a light emission pulse (sustain pulse) is given to the selected cell (lighting cell) to emit light ( Sustain discharge period).

  FIG. 3 is a diagram showing how the total number of light emission pulses is distributed according to the weight ratio of each subfield.

  As shown in FIG. 3, the total number of light emission pulses determined by the display load factor is distributed according to the weight ratio of each subfield. That is, for example, when the total number of light emission pulses is 508, the number of light emission pulses in each of the subfields SF0 to SF6 is SF0 = 4, SF1 = 8, SF2 = 16, SF3 = 32, SF4 = 64, SF5 = 128, and SF6 = 256.

  FIG. 4 is a diagram for explaining a problem in a conventional display device driving method. FIG. 4A shows a relationship between the number of light emission pulses and luminance, and FIG. 4B shows an input floor. The relationship between the tone and the output luminance is shown.

  As shown in FIG. 4A, since there is luminance saturation of the phosphor between the number of light emission pulses and the luminance, the relationship between them is not directly proportional, and the luminance of each subfield (SF) is A luminance level difference (see FIG. 4B) due to the lowering of the assumed luminance, or a luminance level difference due to a discharge spreading to pixels that are not originally lit due to an overlay process or the like occurs.

  That is, gradation continuity cannot be ensured only by distributing the total number of light emission pulses according to the weight ratio of each subfield. In view of this, it is considered to perform an addition process of the number of light pulses in consideration of luminance saturation for each subfield, or to perform a subtraction process of the number of light pulses in consideration of an increase in luminance due to the spread of discharge.

  As described above, it is not possible to completely ensure gradation continuity simply by adjusting the number of light pulses in each subfield. This is because even if the luminance of each subfield alone is in accordance with the weight ratio, a luminance step is generated depending on the combination of the light emitting subfields.

  Conventionally, a light emission SF (subfield) pattern that compensates for continuity of gradation is held in a table (memory), and the step can be corrected by devising a combination of light emission subfields. Proposed. Further, as a related technique, it is considered that the luminance step is compensated by performing calculation without providing a table for holding the light emitting SF pattern.

  FIG. 5 is a diagram for explaining an example of a driving method in a display device as a related technique, and FIG. 6 is a block diagram showing a configuration example for realizing the driving method of FIG. In FIG. 6, reference numeral 101 denotes an image processing unit, 102 denotes an error diffusion processing unit, 103 denotes an addition / subtraction determination unit, 104 denotes an addition / subtraction processing operation unit, and 105 denotes a subfield (SF) data conversion unit. ing.

  The driving method shown in FIG. 5 has a theoretical luminance value of 3 when the input gradation level is 3, but the actual luminance is 1 when the actual luminance is 1 when the calculated gradation level is 3. Is calculated so that the calculated gradation level 5 corresponding to the theoretical value of 3 corresponds to the input gradation level 3.

  As shown in FIG. 6, the input signal Din is immediately supplied to the error diffusion processing unit 102 via the image processing unit 101, and the output of the addition / subtraction determination unit 103 is performed on the image signal subjected to the error diffusion processing. The value is added (subtracted) by the addition / subtraction processing operation unit 104. Specifically, in the case as shown in FIG. 5, an ideal luminance value and a luminance difference of −2 occur at the input gradation level 3 (after the input gradation level 3), so that the output of the error diffusion processing unit 102 And the addition / subtraction determination unit 103 that performs addition / subtraction determination outputs the compensation value “+2” to the addition / subtraction processing operation unit 104 at the input gradation level 3, and thereby the error diffusion processing unit 102. A signal obtained by adding +2 to the output is supplied to the SF data converter 105.

  In other words, the SF data conversion unit 105 outputs the gradation level obtained by adding “+2” to the input gradation level after the input gradation level 3 as the output signal Dout, thereby eliminating the level difference of the luminance. A display that maintains continuity is performed. In FIGS. 5 and 6, for example, a case where only one luminance step is generated due to the combination of the light emitting subfields has been described, but actually, there are a plurality of such luminance steps (for example, about six locations). The above addition (subtraction) process is performed at each luminance step.

  As described above, the conventional driving method of the display device using the table holding the light emission SF pattern to compensate for the continuity of gradation stores a huge amount of table covering all the combinations of subfields. Therefore, a large capacity memory (table) is required.

  FIG. 7 is a diagram for explaining a problem in a driving method in a display device as a related technique.

  As shown in FIG. 7, in the related technology described with reference to FIGS. 5 and 6, for example, the luminance for the input gradation level 3 is set to “14” by performing an operation (addition process), and the input floor The luminance level difference from the luminance level “8” with respect to the tone level 2 is “6”. The minimum unit of the weight of the subfield is “4”.

  At this time, in the related art, since the luminance can be controlled only by the step of the minimum unit “4” of the subfield weight, for example, the process of adding “+2” of the gradation level to the luminance of the input gradation level 3 is performed. Even if it does, a brightness | luminance level difference cannot be eliminated completely.

  That is, the driving method of the display device using the arithmetic processing of the related art performs the addition / subtraction processing immediately before the lighting subfield determination, and therefore can be controlled only by the minimum unit of the weight of the subfield. When the total number of light emission pulses is varied by power control, there is a problem in that the ratio of the number of light emission pulses set in each subfield deviates from an ideal value and continuity is lost.

  An object of the present invention is to provide a display device capable of performing power control while maintaining continuity of gradation and a driving method thereof in view of the problems in the conventional display device described above.

  According to the first aspect of the present invention, there is provided a driving method of a display device having a plurality of predetermined light emitting blocks in each field, and displaying a halftone by a combination of the light emitting blocks. A method for driving a display device, wherein a gradation level addition / subtraction process is performed on a discontinuous gradation according to an input gradation level by a calculation for a discontinuous portion of light emission luminance generated by the combination of Is provided.

  According to the second aspect of the present invention, there is provided a driving method of a display device having a plurality of predetermined light emitting blocks in each field and displaying a halftone by a combination of the light emitting blocks. For the discontinuous part of the light emission luminance generated by the combination of the above, the gradation level addition / subtraction processing is performed on the discontinuous gradation according to the input gradation level before the error diffusion processing. A display device driving method is provided.

  According to the third aspect of the present invention, each field has a plurality of predetermined light emission blocks each composed of a plurality of light emission pulses, and displays a halftone by combining the light emission blocks. When the number of light emission pulses is adjusted to control power, the number of light emission pulses of the plurality of light emission blocks is determined without changing the number of light emission pulses of the light emission block having a small number of light emission pulses. A display device driving method is provided.

  According to the fourth aspect of the present invention, there is provided a display device that has a plurality of predetermined light emission blocks in each field, and displays a halftone by a combination of the light emission blocks. An addition / subtraction determination unit that determines addition / subtraction with respect to the discontinuity portion of the light emission luminance generated by the combination of the light emission blocks, and the discontinuity portion of the light emission luminance according to the output of the addition / subtraction determination unit On the other hand, there is provided a display device comprising: an addition / subtraction processing operation unit that executes addition / subtraction processing of gradation levels to discontinuous gradations according to input gradation levels.

  According to the fifth aspect of the present invention, there is provided a display device that has a plurality of predetermined light emission blocks in each field, and displays a halftone by a combination of the light emission blocks. An addition / subtraction determination unit that determines addition / subtraction for a discontinuous portion of light emission luminance generated by the combination of the light emission blocks, an error diffusion processing unit that performs error diffusion processing of the image signal, and the error diffusion processing unit In accordance with the output of the addition / subtraction determination unit, gradation level addition / subtraction processing is performed for the discontinuous gradation according to the input gradation level for the discontinuity portion of the light emission luminance. An addition / subtraction processing operation unit is provided.

  According to the sixth aspect of the present invention, the display panel unit and the image signal that is received and supplied to the display panel unit are supplied to the display panel unit, and the display load factor is calculated from the image signal and output. A data converter, a power supply unit that supplies power to the display panel unit and outputs power information consumed by the display panel unit, and receives the display load factor and the power consumption information to control power A light emission pulse number control circuit that determines the number of light emission pulses of the plurality of light emission blocks without changing the number of light emission pulses of the light emission block having a small number of light emission pulses when adjusting the number of light emission pulses. A display device is provided.

  In the present invention, processing for compensating for continuity of gradation is not performed in a table (memory), but is performed by calculation, thereby preventing an increase in program capacity. In addition, according to the present invention, the arithmetic processing is placed before the error diffusion processing, so that the addition / subtraction processing is not an integer arithmetic processing but a decimal arithmetic processing. Furthermore, in the present invention, when the total number of light emission pulses is limited by power control, the ratio of the number of light emission pulses in each subfield collapses. However, by correcting the luminance step generated thereby by the addition / subtraction process, Therefore, the calculation coefficient is changed for each display load factor or the total number of light emission pulses.

  In this specification, the term “field” is used assuming that, for example, two frames of an odd number and an even number for interlaced display of an image of one frame are used. When an image is displayed progressively, the word “field” can be applied as it is by replacing it with “frame”.

  As described above in detail, according to the present invention, it is possible to provide a display device capable of performing power control while maintaining gradation continuity and a driving method thereof.

  Hereinafter, embodiments of a display device and a driving method thereof according to the present invention will be described in detail with reference to the drawings. The display device and the driving method thereof according to the present invention are not limited to the interlaced PDP, and can be widely applied to various display devices.

  FIG. 8 is a block diagram showing an example of a configuration for realizing the display device driving method according to the present invention. 8, reference numeral 201 denotes an image processing unit, 202 denotes an error diffusion processing unit, 203 denotes an addition / subtraction determination unit, 204 denotes an addition / subtraction processing calculation unit, and 205 denotes subfield (SF: light emission block) data conversion. Shows the part. Note that the addition / subtraction determination unit 203 and the addition / subtraction processing operation unit 204 constitute a gradation continuity compensation circuit 200.

  As is clear from a comparison between FIG. 8 and FIG. 6 described above, in the configuration shown in FIG. 8, an addition / subtraction process determination unit 203 and an addition / subtraction process calculation unit 204 are provided before the error diffusion calculation processing unit 202. It is like that.

  As shown in FIG. 8, the input signal Din is supplied to the addition / subtraction determination unit 203 and the addition / subtraction processing operation unit 204 via the image processing unit 201, and the addition / subtraction processing operation unit 204 performs addition / subtraction. The output value of the determination unit 203 is added (subtracted). The output of the addition / subtraction processing operation unit 204 is supplied to the error diffusion processing unit 202, and error diffusion processing is performed on the signal that has undergone the arithmetic processing (addition / subtraction processing). The broken signal is supplied to the SF data conversion unit 205.

  FIG. 9 is a block circuit diagram showing an example of a gradation continuity compensation circuit in the display device according to the present invention. Here, the gradation continuity compensation circuit 200 corresponds to the addition / subtraction determination unit 203 and the addition / subtraction processing operation unit 204 in FIG.

  As shown in FIG. 9, the gradation continuity compensation circuit 200 includes a comparator 211, an AND gate group 212, a pre-adder 213, and an adder 214. The comparator 211 converts the upper 8 bits (DI [9: 2]) of the 10-bit input data DI [9: 0] into 8-bit correction coefficient addition positions Yn [7: 0] (Y0 [7: 0] ] To Y15 [7: 0]: see FIG. 12), and outputs the results (outputs Z0 to Z15) to the AND gate group 212. Needless to say, the correction coefficient addition position Yn is not limited to 16 positions Y0 to Y15, and can be changed variously depending on the configuration of the light emission block.

  The AND gate group 212 calculates the logical product of the outputs (Z0 to Z15) of the comparator 211 and the 4-bit correction coefficients Xn [3: 0] (X0 [3: 0] to X15 [3: 0]). A plurality of AND gates are provided, and the outputs of the 4-bit AND gates are added by the pre-adder 213 and supplied to the adder 214 as 8-bit outputs. The adder 214 adds the output of the pre-adder 203 to the input data DI [9: 0], and outputs a 10-bit output DO [9: 0].

  10 is a flowchart for explaining an example of the operation of the gradation continuity compensation circuit shown in FIG. 9, and FIG. 11 is a diagram for explaining an example of the operation of the gradation continuity compensation circuit shown in FIG. FIG. 12 is a diagram showing the relationship between the output luminance and the input gradation for explaining an example of the operation of the gradation continuity compensation circuit shown in FIG.

  First, when the input data Din is input to the tone continuity compensation circuit 200 (addition / subtraction determination unit 203) via the image processing unit 201, in step ST1, the input data Din (10-bit input data DI [9 : 0]), the upper 8 bits (DI [9: 2]) are set to A (DI [9: 2] = A), the correction coefficient addition position is set to Yn [7: 0], and the correction coefficient is set to Set to Xn [3: 0]. Note that the output data (10-bit output data) of the tone continuity compensation circuit 200 (addition / subtraction processing operation unit 204) is set to DO [9: 0]. Next, the process proceeds to step ST2, where n = 0, and further proceeds to step ST3, where A and Yn are compared (comparator 211 in FIG. 9).

  If it is determined in step ST3 that A ≧ Yn holds, the process proceeds to step ST4, and the correction coefficient is added to the correction coefficient sum B [7: 0] (B [7: 0] = B [7: 0]. ] + Xn [3: 0]). Further, the process proceeds to step ST5, 1 is added to n (n = n + 1), the process returns to step ST3, and the same processing is repeated until it is determined that A ≧ Yn is not satisfied (A <Yn is satisfied). That is, all the correction coefficient addition positions are corrected with Yn (for example, the 16 correction coefficient addition positions Y0 to Y15 with the correction coefficient Xn (X0 to X15) (see FIG. 12).

  If it is determined in step ST3 that A ≧ Yn is not established, the process proceeds to step ST6, and correction coefficient sum B [7: 0] (pre-adder 213 in FIG. 9) is applied to input data DI [9: 0]. Output data DO [9: 0] is calculated (adder 214 in FIG. 9).

  In this way, the calculation process (calculation for compensating the luminance step of the input data DI [9: 0]) as shown in FIG. 11 is executed, and the output data D0 [9: 0] is output. The output data of the tone continuity compensation circuit 200 (addition / subtraction processing operation unit 204) is supplied to the error diffusion processing unit 202 in the next stage to be subjected to error diffusion processing.

  FIG. 13 is a diagram for explaining a first embodiment of a display device driving method according to the present invention.

  As is apparent from a comparison between FIG. 13 and FIG. 7 described above, in the first embodiment, an addition / subtraction process determination unit 203 and an addition / subtraction process calculation unit 204 ( Since the gradation continuity compensation circuit 200) is provided to perform the arithmetic processing, for example, the gradation level “+1.5” may be added to the luminance of the input gradation level 3. It becomes possible. That is, by performing the calculation (addition process), the luminance with respect to the input gradation level 3 can be set to “12”, and the luminance step with respect to the input gradation level 2 with “8” can be set to “4”. It is possible to completely eliminate the luminance step. Note that the error diffusion processing by the error diffusion processing unit 202 is performed on the output of the addition / subtraction processing calculation unit 204 in which the luminance step is compensated.

  FIG. 14 is a diagram for explaining a second embodiment of the driving method of the display device according to the present invention.

  First, when the number of light emission pulses (sustain pulse: SUS) is distributed to each subfield, it is assumed that the ideal value of the number of light emission pulses for each subfield is one term in FIG. That is, when the total number of light emission pulses of 254 is distributed to the subfields SF0 to SF6, the ideal values of the light emission pulse numbers of the subfields SF0, SF1, SF2, SF3, SF4, SF5, and SF6 are 2, 4, 8, 16 , 32, 64, 128.

  On the other hand, when the total number of light emission pulses is suppressed by power control, for example, when the total number of light emission pulses is suppressed to 200, as shown in item 2 of FIG. 14, each subfield SF0, SF1, SF2, SF3. , SF4, SF5, and SF6 are 2, 3, 6, 13, 25, 50, and 101, respectively. In this case, a deviation occurs from the above ideal luminance value, and the luminance ratio of each subfield is lost. Such a deviation in luminance ratio is particularly affected when it occurs in subfields with small weights (for example, SF0, SF1, and SF2). Therefore, in the second embodiment, as shown in item 3 of FIG. The number of light emission pulses in the subfield having a small weight is fixed. That is, in the second embodiment, the luminance ratio of the subfields (SF0 to SF2) having a small weight is fixed, and the number of light emission pulses necessary for power control is reduced to the subfields (SF3 to SF6) having a large weight. It is supposed to be done with. Note that the luminance level difference that occurs when a subfield with a large weight and a reduced number of light emission pulses is turned on is determined by the addition / subtraction processing determination unit 203 and the addition / subtraction processing calculation provided in the preceding stage of the error diffusion calculation processing unit 202 described above. Compensation is performed by calculation by the unit 204.

  FIG. 15 is a view for explaining a third embodiment of the display device driving method according to the present invention.

  First, it is assumed that the ideal value of the number of light emission pulses in each subfield with respect to each total number of light emission pulses is the items 1 to 4 in FIG. That is, the ideal value of the number of light emission pulses in each of the subfields SF0, SF1, SF2, SF3, SF4, SF5, and SF6 is, for example, 1, 2, 4, 8, 16, 32, when the total number of light emission pulses is 127. 64 (1 term in FIG. 15: ideal value 1), and when the total number of light emission pulses is 254, 2, 4, 8, 16, 32, 64, 128 (2 terms in FIG. 15: ideal value 2) When the number of emission pulses is 381, 3, 6, 12, 24, 48, 96, 192 (3 terms in FIG. 15: ideal value 3), and when the total number of emission pulses is 508, 4, 8, 16 , 32, 64, 128, 256 (four terms in FIG. 15: ideal value 4).

  Thus, in the third embodiment, each subfield (SF0 to SF6) for realizing an ideal luminance ratio based on the number of light emission pulses of the subfield (SF0) with the smallest weight as a reference. Is determined (ideal value 1 to ideal value 4). Here, the switching between the ideal value 1 to the ideal value 4 is, for example, the ideal value of the nearest total light emission pulse number, where the total light emission pulse number of the ideal value is larger than the total light emission pulse number determined by the power control. Is a reference for fixing the number of light emission pulses and for adding / subtracting the number of light emission pulses. Specifically, for example, if the total number of light emission pulses determined by power control is 350, the ideal number of light emission pulses in each reference subfield is the third term (ideal value 3) in FIG.

  Alternatively, switching from the ideal value 1 to the ideal value 4 is performed by, for example, fixing the ideal value of the total number of light emission pulses closest to the total number of light emission pulses determined by the power control. It may be used as a reference for addition / subtraction of the number of light emission pulses. For example, when the total number of light emission pulses determined by the power control is larger than the total number of light emission pulses based on the ideal value, for example, the luminance ratio of the subfields (SF0 to SF2) having a small weight is fixed. The number of light emission pulses may be increased for subfields (SF3 to SF6) having a large weight. In this case, for example, if the total number of light emission pulses determined by power control is 300, the ideal number of light emission pulses in each reference subfield is the second term (ideal value 2) in FIG.

  FIG. 16 is a diagram for explaining an error diffusion process applied to the present invention, and FIG. 17 is a circuit diagram showing an example for realizing the error diffusion process shown in FIG.

  Conventionally known methods can be applied to the error diffusion processing used in each of the above-described embodiments, that is, the error diffusion processing performed in the error diffusion processing unit 202 in FIG. 8, for example, as follows. It is a thing.

  First, as shown in FIG. 16, when displaying predetermined halftone image data for all pixels during image display, attention is paid to a specific pixel portion P0, and a line n to which the specific pixel portion P0 belongs is selected. Note the next scanned line n + 1. Furthermore, a total of four pixel portions P1, one pixel portion P1 adjacent to the specific pixel portion P0 in the scanning direction, and each pixel portion P2, P3, and P4 located at the lower left, lower, and lower right positions of P0 in the line n + 1. Error data is distributed at a predetermined ratio to the pixel portion. Here, a conventionally known error diffusion processing arithmetic circuit used for the above error diffusion processing can be applied, and an example thereof is shown in FIG.

  That is, as shown in FIG. 17, for example, halftone image data DIN (13 to 0) is input to the calculation means OP1, and the output of this calculation means OP1 is output DOUT via the first delay means D1. When outputting to (7-0), it is input to the I4 terminal of the calculation means OP2 via the second delay means D2, thereby generating error data distributed to the pixel portion P4. Further, the output of the calculation means OP1 through the first delay means D1 is directly input to the I1 terminal of the calculation means OP2, thereby generating error data distributed to the pixel portion P1. Here, the first delay means D1 has a delay function (1DT) for one dot, and the second delay means D2 has a delay function (1H-2DT) for one line-2 dots. Yes.

  Further, the output of the second delay means D2 is input to the I3 terminal of the calculation means OP2 via the third delay means D3, thereby generating error data distributed to the pixel portion P3, and The output of the third delay means D3 is input to the I2 terminal of the calculation means OP2 via the fourth delay means D4, thereby generating error data distributed to the pixel portion P2. Here, the third delay means D3 has a delay function (1DT) for one dot, and the fourth delay means D4 also has a delay function (1DT) for one dot.

  The error diffusion method described above is general, and the error at an arbitrary point P0 in FIG. 16 is diffused to surrounding points P1, P2, P3, P4, and the value is P1 = (7/16) × P0, P2 = (1/16) × P0, P3 = (5/16) × P0, P4 = (3/16) × P0. Then, by sequentially processing from the left to the right dot and from the upper line to the lower line, errors are diffused to realize multi-gradation.

  Further, the arithmetic circuit of the error diffusion processing unit shown in FIG. 17 takes several lower bits and lower bits of the data input and uses the dot or line delay elements D1 to D4 to input I1 to I4 of the arithmetic means OP2. The phase of the signal to be supplied is matched, the error diffusion as described above is performed by the calculation means OP2, and if an error is accumulated until the bit for restarting the output data rises, a value one gradation higher is output as the output. Since the remaining error is fed back to the calculation means OP1 again, the error does not disappear within one field, and the number of pseudo gradations can be increased. Needless to say, the error diffusion processing applied to the present invention is not limited to the above.

It is a block diagram which shows an example of the display apparatus with which this invention is applied. It is a figure for demonstrating an example of the drive method in the display apparatus shown in FIG. It is a figure which shows a mode that the total light emission pulse number is distributed according to the weight ratio of each subfield. It is a figure for demonstrating the subject in the drive method of the conventional display apparatus. It is a figure for demonstrating an example of the drive method in the display apparatus as a related technique. FIG. 6 is a block diagram illustrating a configuration example for realizing the driving method of FIG. 5. It is a figure for demonstrating the subject in the drive method in the display apparatus as related technology. It is a block diagram which shows one structural example for implement | achieving the drive method of the display apparatus which concerns on this invention. It is a block circuit diagram which shows an example of the gradation continuity compensation circuit in the display apparatus which concerns on this invention. 10 is a flowchart for explaining an example of the operation of the gradation continuity compensation circuit shown in FIG. 9. It is a figure for demonstrating an example of operation | movement of the gradation continuity compensation circuit shown in FIG. FIG. 10 is a diagram illustrating a relationship between output luminance and input gradation for explaining an example of the operation of the gradation continuity compensation circuit shown in FIG. 9. It is a figure for demonstrating 1st Example of the drive method of the display apparatus which concerns on this invention. It is a figure for demonstrating 2nd Example of the drive method of the display apparatus which concerns on this invention. It is a figure for demonstrating the 3rd Example of the drive method of the display apparatus which concerns on this invention. It is a figure for demonstrating the error diffusion process applied to this invention. It is a circuit diagram which shows an example for implement | achieving the error diffusion process shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Data converter 2 ... Frame memory 3 ... Power control circuit 4 ... Driver control circuit 5 ... Power supply 6 ... Address driver 7 ... Y driver 8 ... X driver 9 ... Display panel 200 ... Gradation continuity compensation circuit 201 ... Image processing part 202 ... Error diffusion processing unit 203 ... Addition / subtraction determination unit 204 ... Addition / subtraction processing operation unit 205 ... SF data conversion unit

Claims (14)

  A driving method of a display device having a plurality of predetermined light emitting blocks in each field and displaying a halftone by the combination of the light emitting blocks, wherein the light emitting luminance discontinuity generated by the combination of the light emitting blocks On the other hand, a method for driving a display device, characterized in that gradation level addition / subtraction processing is performed by calculation on discontinuous gradations according to an input gradation level.   A driving method of a display device having a plurality of predetermined light emitting blocks in each field and displaying a halftone by the combination of the light emitting blocks, wherein the light emitting luminance discontinuity generated by the combination of the light emitting blocks On the other hand, the display device driving method is characterized in that the gradation level addition / subtraction processing is performed on the discontinuous gradation according to the input gradation level before the error diffusion processing.   A driving method of a display device that has a plurality of predetermined light-emitting blocks each composed of a plurality of light-emitting pulses in each field, and displays halftones by a combination of the light-emitting blocks, and controls power Therefore, when adjusting the number of light emission pulses, the number of light emission pulses of the plurality of light emission blocks is determined without changing the number of light emission pulses of a light emission block having a small number of light emission pulses.   4. The method of driving a display device according to claim 3, wherein a plurality of ideal values of combinations of the respective light emitting blocks are set on the basis of the luminance of the light emitting block having the smallest weight, and the total light emission pulse among the plurality of ideal values. A method for driving a display device, characterized in that the number is selected based on the closest number larger than the total number of light emission pulses determined by power control.   4. The method of driving a display device according to claim 3, wherein a plurality of ideal values of combinations of the respective light emitting blocks are set on the basis of the luminance of the light emitting block having the smallest weight, and the total light emission pulse among the plurality of ideal values. A method for driving a display device, characterized in that the number is selected on the basis of the number closest to the total number of light emission pulses determined by power control.   4. The display device driving method according to claim 3, wherein gradation level addition / subtraction processing is executed by calculation according to a display rate for the discontinuous gradation of luminance generated by adjusting the number of light emission pulses. A method for driving a display device.   4. The method of driving a display device according to claim 3, wherein gradation level addition / subtraction processing according to display rate is applied to error diffusion processing for discontinuous luminance gradation generated by adjusting the number of light emission pulses. A method for driving a display device, which is performed before the display.   A display device having a plurality of predetermined light-emitting blocks in each field and displaying a halftone by a combination of the light-emitting blocks, receiving an image signal, and having a light-emitting luminance generated by the combination of the light-emitting blocks. An addition / subtraction determination unit that determines addition / subtraction with respect to the discontinuous part, and a discontinuity according to an input gradation level with respect to the discontinuous part of the light emission luminance according to an output of the addition / subtraction determination unit A display device comprising: an addition / subtraction processing operation unit that performs addition / subtraction processing of gradation levels on gradations by calculation.   A display device having a plurality of predetermined light-emitting blocks in each field and displaying a halftone by a combination of the light-emitting blocks, receiving an image signal, and having a light-emitting luminance generated by the combination of the light-emitting blocks. An addition / subtraction determination unit that determines addition / subtraction for a discontinuous portion, an error diffusion processing unit that performs error diffusion processing of the image signal, and the addition / subtraction provided before the error diffusion processing unit. An addition / subtraction processing operation unit that performs gradation level addition / subtraction processing on the discontinuous gradation in accordance with the input gradation level with respect to the discontinuity portion of the light emission luminance according to the output of the determination unit. A display device characterized by that.   A display panel unit, a data converter that receives an image signal, supplies image data suitable for the display device to the display panel unit, calculates a display load factor from the image signal, and outputs the calculated data; and outputs power to the display panel unit A power supply unit that supplies power information that is consumed by the display panel unit, and receives the display load factor and the power consumption information, and adjusts the number of light emission pulses to control power. A display device comprising: a light emission pulse number control circuit that determines the number of light emission pulses of the plurality of light emission blocks without changing the number of light emission pulses of a small number of light emission blocks.   11. The display device according to claim 10, wherein the light emission pulse number control circuit sets a plurality of ideal values of combinations of the light emission blocks with reference to the luminance of the light emission block having the smallest weight, and among the plurality of ideal values. The display device is characterized in that the total number of light emission pulses is larger than and closest to the total number of light emission pulses determined by power control.   11. The display device according to claim 10, wherein the light emission pulse number control circuit sets a plurality of ideal values of combinations of the light emission blocks with reference to the luminance of the light emission block having the smallest weight, and among the plurality of ideal values. The display device is characterized in that the total number of light emission pulses is selected based on a value closest to the total number of light emission pulses determined by power control.   11. The display device according to claim 10, further comprising: performing gradation level addition / subtraction processing according to a display rate for the discontinuous gradation of luminance generated by adjusting the number of light emission pulses. A display device comprising a gradation continuity compensation circuit that compensates for gradation continuity.   11. The display device according to claim 10, further comprising: an error diffusion processing unit that performs error diffusion processing of the image signal; and a stage that is provided in front of the error diffusion processing unit and that generates luminance by adjusting the number of light emission pulses. A display device comprising: a gradation continuity compensation circuit that compensates for continuity of gradation by performing gradation level addition / subtraction processing according to a display rate for discontinuous gradations.

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