JP2008130798A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device having a full silicide gate electrode capable of stabilizing the threshold voltage of an n-type MOSFET and a p-type MOSFET and preventing deterioration in reliability is provided.
A semiconductor substrate, an n-type MOSFET having a full silicide gate electrode formed on an n-type transistor forming region formed on the semiconductor substrate, and a p-type transistor forming region formed on the semiconductor substrate. And a p-type MOSFET having a full silicide gate electrode 23 having the same film thickness as the full silicide gate electrode 24, and the full silicide gate electrodes 23 and 24 are each made of metal silicide. apparatus.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MOS (Metal Oxide Semiconductor) structure having a gate electrode made of a metal silicide film and a manufacturing method thereof.

2. Description of the Related Art In recent years, metal oxide field effect transistors (MOSFETs) have been miniaturized along with technological progress toward higher integration and higher speed in semiconductor devices. In particular, in order to miniaturize a MOSFET, a gate insulating film made of a silicon oxide film such as silicon oxide (SiO ₂ ) and silicon oxynitride (SiON), which has been conventionally used, is being made thinner. However, with the miniaturization of the gate insulating film, the problem of an increase in gate leakage current due to the tunnel effect becomes obvious. For this reason, in order to realize further thinning without increasing the gate leakage current, measures such as changing the material of the gate electrode from polysilicon to metal to prevent a decrease in capacity due to electrode depletion have been studied. .

Therefore, a full silicide gate electrode has been proposed as one of gate electrodes made of a metal material. The full silicide gate electrode is formed by directly depositing a metal on a polysilicon film deposited on a gate insulating film and silicidizing the entire polysilicon film by heat treatment (for example, Patent Document 1). See). According to this process, a gate electrode made of polysilicon is first formed, and then the gate electrode is completely metal-silicided. Therefore, when the dual metal gate process and the full silicide gate process are compared, in the dual metal gate process, different metal materials are deposited on the n-type MOSFET and the p-type MOSFET, and fine processing with a gate length of 100 nm or less is performed. The metal material must be selectively removed without damaging the gate insulating film. On the other hand, in the full silicide gate process, there is no technical difficulty associated with such miniaturization. For this reason, it is expected that a full silicide gate electrode is used in order to prevent a decrease in capacity due to electrode depletion in a conventional SiO ₂ or SiON gate insulating film.

On the other hand, the gate insulating film may be replaced with a high-dielectric material made of a metal oxide such as hafnium oxide (HfO ₂ ) or zirconium oxide (ZrO ₂ ) instead of silicon oxide such as SiO ₂ or SiON. It is being considered. When a metal oxide is used as the material of the gate insulating film, the physical properties such as increasing the film thickness can be realized while realizing a thinner film thickness than using the silicon oxide film, thereby reducing leakage current. The effect can be expected.

  However, if a metal oxide is used as a gate insulating film for a MOSFET having a gate electrode made of polysilicon, the transistor operates due to a reaction at the upper interface of the gate insulating film, that is, the interface between the gate insulating film and the gate electrode. This causes a problem that the absolute value of the threshold voltage becomes large. Although the cause is not clear, it is suspected that the gate electrode material reacts with the gate insulating film material because the semiconductor substrate is exposed to a high temperature process of about 1000 ° C. in the transistor manufacturing process.

The reaction between the gate electrode material and the gate insulating film material causes a phenomenon (Fermi level pinning) in which the effective work function of the gate electrode material changes. For example, when polysilicon is used as the gate electrode material, the effective work function value of polysilicon is slightly higher than the mid gap (intermediate value of band gap energy) of polysilicon regardless of the type of dopant of polysilicon. It is reported that it is fixed near n ⁺ polysilicon (see Non-Patent Document 1). As a result, the absolute value of the threshold voltage of the p-type MOSFET becomes particularly large, so that when the material of the gate insulating film is a high dielectric material, electrode depletion suppression expected in the SiO ₂ gate insulating film is suppressed. In addition to the above effect, it is necessary to select an optimal work function using an electrode made of metal and control the threshold voltage.

For this reason, in order to avoid an increase in threshold voltage of the p-type MOSFET due to Fermi level pinning in the high dielectric gate insulating film, it is expected to use a full silicide gate electrode as an electrode made of metal.
JP 2006-140319 A C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, “Fermi level pinning at the polySi / metal oxide interface”, Proceedings of the 2003 Symposium on VLSI Technology, 2003, p. 9-10 A. Veloso, T. Hoffmann, A. Lauwers, S. Brus, JF de Marneffe, S. Locorotondo, C. Vrancken, T. Kauerauf, A. Shickova, B. Sijmus, H. Tigelaar, MA Pawlak, HY Yu, C. Demeurisse, S. Kubicek, C. Kerner, T. Chiarella, O. Richard, H. Bender, M. Niwa, P. Absil, M. Jurczak, S. Biesemans, and JA Kittl, “Dual work function controlled Ni -FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process window Improvement by Sacrificial SiGe cap ”, Proceedings of the 2006 Symposium on VLSI Technology, 2006.

  However, in order to provide a threshold voltage suitable for the n-type MOSFET and the p-type MOSFET, the work function of the full silicide gate electrode changes depending on the composition ratio of the metal and silicon, and the composition of the metal and silicon. Metal silicide layers having a ratio of two or more must be formed on the same semiconductor substrate. To solve this problem, for example, after forming the polysilicon film thickness for forming the gate electrode of the p-type MOSFET thinner than the polysilicon film thickness of the n-type MOSFET, the metal film and the polysilicon having the same film thickness are used. There has been proposed an attempt to form a metal silicide gate electrode having a metal excess in the p-type MOSFET as compared with the n-type MOSFET by reacting with the gate electrode. The composition of the metal silicide film formed by the reaction between the thinned polysilicon film and the metal is such that the metal is excessive with respect to silicon, the work function is increased, and a p-type MOSFET realizing a low threshold voltage is manufactured. be able to. However, it is technically difficult to selectively etch only the polysilicon of the p-type MOSFET with good controllability.

  This is because it is difficult to etch a gate electrode made of polysilicon surrounded by a sidewall because of a difference in etching rate due to the shape determined by the relationship between the height of the sidewall and the height of the gate electrode.

  Further, although it is necessary to control the same film thickness for different gate lengths, it is difficult to control the etching shape particularly when the gate length is 100 nm or less.

  In addition, in order to form a thin polysilicon film, the etching must be stopped halfway, so that the etching cannot be controlled by an etching termination detection technique using the light emission phenomenon of plasma during dry etching. Therefore, it is necessary to adjust the film thickness by the etching processing time. However, the adjustment of the film thickness by the etching processing time tends to change the final remaining film thickness due to the dependency of the gate electrode pattern. Therefore, if the remaining film thickness of polysilicon cannot be controlled, the amount of reaction with metal cannot be controlled, the composition ratio of metal silicide is not stabilized, and it is difficult to control the threshold voltage of the transistor.

  Further, as the gate electrode of the p-type MOSFET is made thinner than the n-type MOSFET, the heights from the substrate to the upper surface of the gate electrode are different, and the following problems occur in the process of wiring the gate electrode. . In other words, after forming gate electrodes having different thicknesses, and further depositing an interlayer film, when the contact hole is opened on the gate electrode, the film thickness of the gate electrode of the n-type MOSFET is so thick that the interlayer film on the gate electrode Becomes thinner than the p-type MOSFET, and the etching of the contact hole is completed before the p-type MOSFET. However, since the etching is continued until the etching to the upper surface of the gate electrode of the p-type MOSFET is completed, the gate electrode of the n-type MOSFET is etched longer. In order not to deteriorate the characteristics, it is desirable that the etching time is as small as possible and the etching time can be made equal in both the n-type MOSFET and the p-type MOSFET.

  Another problem is that the optimum metal silicide composition differs between the n-type MOSFET and the p-type MOSFET. An n-type MOSFET that requires a small work function requires a high silicon composition for the metal silicide, and a p-type MOSFET that requires a large work function requires a high metal composition for the metal silicide. For this purpose, it is necessary to cause the metal and silicon to react under the heat treatment reaction conditions for forming the respective compositions. In order to suppress the reaction between the metal and silicon in the n-type MOSFET, a heat treatment reaction at a low temperature for a short time is required. On the other hand, in a p-type MOSFET, it is desirable to perform a heat treatment reaction for a long time at a high temperature in order to promote the reaction between the metal and silicon. However, in the conventional example, since the metal silicide formation of the n-type MOSFET and the p-type MOSFET is simultaneously performed, it is necessary to set the intermediate heat treatment reaction conditions for both, and only the heat treatment conditions in which the process conditions are not sufficient can be performed. There is no problem. In particular, in the n-type MOSFET, when the reaction between the metal and silicon proceeds, the metal becomes excessive and the threshold value rises. Conversely, when the reaction between the metal and silicon is insufficient, the polysilicon does not react with the metal. It remains and does not function as a full silicide gate electrode. Therefore, it is difficult to control variation in threshold voltage with a small process margin.

  In view of the above-described conventional problems, the present invention makes it possible to realize a semiconductor device having a full silicide gate electrode that can stabilize the threshold voltage of an n-type MOSFET and a p-type MOSFET and prevent deterioration in reliability. For the purpose.

  In order to achieve the above object, a semiconductor device of the present invention comprises a gate insulating film formed on a semiconductor substrate and a full silicide gate electrode made of a metal silicide film formed on the gate insulating film, and n The gate electrode structure of the type MOSFET and the p-type MOSFET has the same gate structure.

  Specifically, a semiconductor substrate, a first MOS field effect transistor formed in a first transistor formation region formed on the semiconductor substrate and having a first gate electrode, and a second MOS transistor formed on the semiconductor substrate. A second MOS field effect transistor formed in the transistor formation region and having a second gate electrode having the same film thickness as the first gate electrode, wherein the first gate electrode and the second gate electrode are respectively It consists of a metal silicide.

  According to the semiconductor device of the present invention, since the gate electrodes of the first MOS field effect transistor and the second MOS field effect transistor are formed of metal silicide having the same film thickness, the gate of the p-type MOS field effect transistor In order to increase the metal composition of the electrode, it is not necessary to reduce the thickness of the polysilicon film forming the gate electrode by etching. For this reason, it is possible to suppress variation in characteristics due to the etching process of the polysilicon electrode, particularly variation in threshold voltage. Further, since the heights of the gate electrodes are equal, the optimum etching time at the time of opening the contact hole is equal between the n-type MOS field effect transistor and the p-type MOS field effect transistor, so that there is no influence on excessive etching.

  The second gate electrode is preferably made of a metal silicide having a metal composition ratio higher than that of the first gate electrode.

  The first gate electrode is preferably made of metal silicide having a metal composition ratio of 50% or less.

  The second gate electrode is preferably made of metal silicide having a metal composition ratio of 60% or more.

  With this configuration, it is possible to realize metal silicidation in which the first MOS field effect transistor and the second field effect transistor have the same gate electrode film thickness and only the second gate electrode has a high metal composition ratio. A semiconductor device having a stable work function value and threshold voltage can be realized.

  The metal constituting the metal silicide is preferably at least one of nickel, cobalt, titanium, platinum, ruthenium, iridium, ytterbium, and a transition metal.

  The metal silicide film preferably contains at least one dopant of boron, phosphorus, arsenic, antimony, aluminum, nitrogen, oxygen, ytterbium, and a transition metal.

  With such a configuration, a desired work function and threshold voltage can be obtained by adjusting the work function and the threshold voltage in a semiconductor device including a silicon substrate.

  The first MOS field effect transistor includes a first gate insulating film formed between the first transistor formation region and the first gate electrode, and the second MOS field effect transistor includes 2 has a second gate insulating film formed between the transistor formation region and the second gate electrode, and the first gate insulating film and the second gate insulating film are made of a metal oxide. preferable.

  The metal oxide is preferably an oxide of at least one of hafnium, zirconium, titanium, tantalum, aluminum, silicon, lanthanum, and rare earth elements.

  With such a structure, the gate capacitance can be increased due to the high dielectric constant characteristics of the gate insulating film made of a metal oxide, which improves the characteristics of the transistor.

  The method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first transistor formation region and a second transistor formation region on a semiconductor substrate, and forming a gate insulating film formation film and a gate electrode on the semiconductor substrate. A step (b) of sequentially forming a film and a hard mask, a step (c) of patterning the gate insulating film forming film, the gate electrode forming film, and the hard mask to form a plurality of gate insulating films and gate electrodes; (D) removing the hard mask in the transistor formation region, (e) forming a metal film on the gate electrode in the second transistor formation region, and gate in the second transistor formation region A step (f) of forming a second full silicide gate electrode by reacting the electrode with a metal film to silicidate the gate electrode; Removing the hard mask in the star formation region (g), forming a metal film on the gate electrode in the first transistor formation region (h), and the gate electrode in the first transistor formation region And a step (i) of forming a first full silicide gate electrode by siliciding the silicon electrode by reacting the metal film with the metal film.

  According to the method for manufacturing a semiconductor device of the present invention, since the method includes the step of removing only the hard mask in the second transistor formation region, the gate electrode of the second transistor formation region in the first metal silicidation step. Only fully silicided. Since the first metal silicidation conditions can be set at a high temperature for a long time, a metal silicide layer having a metal-excess composition ratio can be formed even if the thickness of the polysilicon forming the gate electrode is large. it can. For this reason, it is not necessary to thin the polysilicon for forming the gate electrode in order to provide a threshold voltage suitable for the n-type MOSFET and the p-type MOSFET, and variations due to etching can be suppressed. In addition, since the full silicidation of the gate electrode in the formation region of the first transistor can set the conditions of the second metal silicidation process independently of the first full silicidation condition, the second metal silicidation is possible. Conditions can be set in a short time at a low temperature, and a desired metal silicide layer can be obtained. Therefore, it is possible to adjust the work function and the threshold voltage suitable for the n-type MOSFET and the p-type MOSFET.

  Further, it is preferable that the method further includes a step (j) of forming a sidewall on the side surface of the gate electrode after the step (c) and before the step (d).

  A step (k) of forming a source / drain region in each of the first transistor formation region and the second transistor formation region in the semiconductor substrate after the step (c) and before the step (d); It is preferable to further include a step (l) of silicidizing the source / drain region after the step (k) and before the step (d).

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the metal silicide layer forming the gate electrode can be set so as to obtain a work function suitable for both the n-type transistor and the p-type transistor. Can be improved. Furthermore, since the shape and film thickness of the gate electrode are the same, a semiconductor device having a full silicide gate electrode that is easy to be finely processed and has stable characteristics can be realized.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The semiconductor device according to the present invention includes an n-type MOS transistor and a p-type MOS transistor having a full silicide gate electrode formed on a semiconductor substrate.

  FIG. 1 shows an example of a cross-sectional view of the semiconductor device according to the present embodiment.

  As shown in FIG. 1, an element isolation film 12 is selectively formed on a semiconductor substrate 11, and a plurality of n-type transistor formation regions 13A and p-type transistor formation regions 13B are formed. A source / drain region 20 is formed in each of the n-type transistor formation region 13 </ b> A and the p-type transistor formation region 13 </ b> B, and a metal silicide source / drain 21 is formed on the source / drain region 20. In the n-type transistor formation region 13A, a base film 14a is formed on the semiconductor substrate 11, a gate insulating film 15a is formed on the base film 14a, and a full silicide gate electrode 24 is formed on the gate insulating film 15a. Sidewalls 19 are formed on the side surfaces of the gate insulating film 15 a and the full silicide gate electrode 24. In the p-type transistor formation region 13B, a base film 14a is formed on the semiconductor substrate 11, a gate insulating film 15a is formed on the base film 14a, and a full silicide gate electrode 23 is formed on the gate insulating film 15a. Side walls 19 are formed on the side surfaces of the gate insulating film 15 a and the full silicide gate electrode 23. Further, an interlayer film 22 is formed so as to cover the semiconductor substrate 11.

  2 to 4 show the semiconductor device manufacturing method according to this embodiment in the order of steps.

  First, as shown in FIG. 2A, for example, an element isolation film 12 made of shallow trench isolation (STI) is formed on a semiconductor substrate 11 made of silicon whose principal surface has a (100) plane orientation. Selectively form.

  Subsequently, ions are implanted into the semiconductor substrate 11 to form a plurality of n-type transistor formation regions 13A and p-type transistor formation regions 13B, respectively. The n-type transistor formation region 13A has a p-type well, and the p-type transistor formation region 13B has an n-type well.

  Subsequently, a known RCA cleaning and diluted hydrofluoric acid cleaning are sequentially performed on the semiconductor substrate 11 and then heat treatment is performed in an oxidizing atmosphere at a temperature of about 600 ° C. to 1000 ° C. Thereby, the base formation film 14 made of silicon oxide is formed on the n-type transistor formation region 13A and the p-type transistor formation region 13B of the semiconductor substrate 11. The undercoat film 14 is desirably 1.0 nm or less in thickness. Further, the underlying film 14 may be a chemical silicon oxide film formed by a wet process.

Subsequently, a metal oxide film 15 made of a high dielectric material having a thickness of 2 nm is formed on the element isolation film 12 and the base formation film 14 by using, for example, metal organic chemical vapor deposition (MOCVD). Form. For example, when a metal oxide film made of hafnium silicate (HfSiO ₄ ) is formed, the following is performed.

A carrier gas composed of nitrogen or the like is blown into a mixed solution of tertiarybutoxy hafnium (Hf (Ot-C ₃ H ₇ ) ₄ ) and terrial butoxy silicon (Si (Ot-C ₃ H ₇ ) ₄ ). The source gas generated by bubbling is introduced into the reactor together with the carrier gas. When the temperature in the reaction furnace is set to about 500 ° C., a metal oxide film 15 made of hafnium silicate is deposited. At this time, the concentration of Hf relative to Si is adjusted by the supply amount of Hf (Ot-C ₃ H ₇ ) ₄ and Si (Ot-C ₃ H ₇ ) ₄ .

  The metal oxide film 15 is made of at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), silicon (Si), lanthanum (La), and rare earth elements. It may be formed from two oxides.

  After the metal oxide film 15 is formed, a heat treatment at about 700 ° C. to 1000 ° C. is performed in order to remove residual impurities such as carbon or hydrogen. The heating atmosphere at this time is desirably nitrogen containing a small amount of oxygen so that the thicknesses of the metal oxide film 15 and the base formation film 14 do not change greatly. Thereafter, nitriding treatment is performed to prevent the metal oxide film 15 from crystallizing in the heat treatment for activating ions in the source / drain regions. For example, heat treatment is performed at a temperature of 800 ° C. for 1 minute in an ammonia atmosphere. Further, the heat treatment may be performed in a nitrogen atmosphere excited by plasma.

  Note that a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like may be used instead of the metal oxide film made of a high dielectric material.

  Thereafter, a gate electrode formation film 16 made of silicon having a thickness of about 100 nm is deposited on the metal oxide film 15 by chemical vapor deposition (CVD). The gate electrode formation film 16 may be doped. Further, a hard mask forming film 17 made of a silicon oxide film is deposited on the gate electrode forming film 16. Subsequently, a resist mask 28 having a gate pattern is formed on the hard mask forming film 17 by lithography.

  Next, as shown in FIG. 2B, the hard mask formation film 17 to the base formation film 14 are sequentially patterned by dry etching using, for example, chlorine gas. As a result, a laminated pattern 18 is formed. The laminated pattern 18 includes a base film 14a and a gate insulating film 15a, a gate electrode 16a formed on the semiconductor substrate 11 through these, and a hard layer that covers the upper surface of the gate electrode 16a. And a mask 17a. Subsequently, although not shown, ion implantation is performed using the laminated pattern 18 as a mask.

  Next, as shown in FIG. 2C, a sidewall 19 made of a silicon nitride film is formed on the side surface of the laminated pattern 18. Subsequently, ion implantation is performed again on the semiconductor substrate 11 using the sidewalls 19 and the laminated pattern 18 as masks, thereby forming source / drain regions 20. Further, heat treatment is performed at a temperature of 1000 ° C. or higher to electrically activate the implanted impurities.

  Next, after depositing metallic nickel (not shown) on the semiconductor substrate 11, heat treatment is performed at a temperature of 300 ° C. or higher. Thereby, a metal silicide source / drain 21 is formed on the source / drain region 20. At this time, the hard mask 17a functions as a protective insulating film that protects the gate electrode 16a from being silicided. Next, unreacted metallic nickel is removed with a mixed solution of sulfuric acid and hydrogen peroxide, and heat treatment for controlling the crystal phase is performed.

  Next, as shown in FIG. 3A, an interlayer film 22 made of a silicon oxide film is deposited until the hard mask 17a is sufficiently covered, and the interlayer film 22 is flattened using a chemical mechanical polishing (CMP) method. Polishing is performed so as not to reach the hard mask 17a while flattening. Further, the interlayer film 22 is etched back on the entire surface by dry etching, and etching is performed until the hard mask 17a is exposed.

  Next, as shown in FIG. 3B, a resist is applied to the entire surface of the semiconductor substrate 11, and a resist mask 29 for exposing the p-type transistor formation region 13B is formed by photolithography. Thereafter, the hard mask 17a in the p-type transistor formation region 13B is removed by dry etching to expose the silicon electrode 16a in the p-type transistor formation region 13B.

  Next, as shown in FIG. 3C, after removing the resist mask 29, metallic nickel (not shown) is deposited on the semiconductor substrate 11, and heat treatment is performed at a temperature of 300 ° C. or higher. As a result, the gate electrode 16a in the p-type transistor formation region 13B reacts with the nickel metal to be nickel-silicided to become a full-silicide gate electrode 23. Thereafter, unreacted metallic nickel is removed with a mixed solution of sulfuric acid and hydrogen peroxide. The silicidation heat treatment is preferably performed at a sufficient temperature and time so that the metal silicide layer of the full silicide gate electrode 23 has a metal composition ratio of 60% or more.

  Next, as shown in FIG. 4A, the hard mask 17a in the n-type transistor formation region 13A is removed by dry etching to expose the silicon electrode 16a in the n-type transistor formation region 13A.

  Next, as shown in FIG. 4B, metallic nickel (not shown) is deposited on the semiconductor substrate 11, and heat treatment is performed at a temperature of 300 ° C. or higher. As a result, the silicon electrode 16 a in the n-type transistor formation region 13 </ b> A reacts with metallic nickel to be nickel-silicided to become a full-silicide gate electrode 24. Thereafter, unreacted metallic nickel is removed with a mixed solution of sulfuric acid and hydrogen peroxide. The heat treatment for silicidation is preferably performed at such a temperature and time that the metal silicide layer of the full silicide electrode 24 has a metal composition ratio of 50% or less. In this process, the nickel metal is deposited on the full silicide electrode 23 at the same time, and a heat treatment is applied. However, since the metal full silicide is already formed, the film composition is stabilized and the characteristics are changed. Absent. Furthermore, a step of stabilizing the full silicide layers of the full silicide electrodes 23 and 24 by applying a heat treatment at about 500 ° C. may be added. Then, although illustration is abbreviate | omitted, a wiring process etc. are performed. In the present embodiment, the gate electrode 16a is silicided with nickel, but instead of nickel, cobalt (Co), titanium (Ti), platinum (Pt), ruthenium (Ru), iridium (Ir), ytterbium (Y) and at least one of transition metals may be used, and boron (B), phosphorus (P), arsenic (As), antimony (Sb), aluminum (Al), nitrogen (N), oxygen (O ), Ytterbium (Y) and at least one dopant among transition elements.

 In the semiconductor device of this embodiment, the gate electrodes of the n-type MOSFET and the p-type MOSFET are formed to have the same thickness, and only the gate electrode of the p-type MOSFET can be formed in excess of metal in the silicidation of the gate electrode. A semiconductor device having a stable work function value and threshold voltage can be realized. Since only the gate electrode of the p-type MOSFET has a metal-excess silicide composition, an etching process such as thinning the gate electrode is not required, and there is no difficulty associated with etching of the gate electrode surrounded by the sidewall. For this reason, in the process of opening a contact hole on the gate electrode to form an electrical connection, it is easy to process and the electrical characteristics can be stabilized.

 Since the method for manufacturing a semiconductor device according to the present embodiment forms the full silicide gate electrodes of the n-type MOSFET and the p-type MOSFET separately, the optimum silicidation conditions can be set for each. A p-type MOSFET in which the metal composition of the metal silicide gate electrode is desired to be high can form a fully silicided gate electrode with stable characteristics even if it is reacted with the metal multiple times.

  In the semiconductor device and the manufacturing method thereof according to the present invention, the metal silicide layer forming the gate electrode can be set so as to obtain a work function suitable for both the n-type transistor and the p-type transistor, and the gate electrode made of the metal silicide film This is useful for a semiconductor device having a MOS structure having the same, a manufacturing method thereof, and the like.

It is sectional drawing which shows the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention in process order.

Explanation of symbols

11 Substrate 12 Element isolation film 13A n-type transistor formation region 13B p-type transistor formation region 14 base formation film 14a base film 15 metal oxide film 15a gate insulating film 16 gate electrode formation film 16a gate electrode 17 hard mask formation film 17a hard mask 18 Laminated pattern 19 Side wall 20 Source / drain region 21 Metal silicide source / drain 22 Interlayer film 23 Full silicide gate electrode 24 Full silicide gate electrode 28 Resist mask 29 Resist mask

Claims (13)

A first transistor formed in a first semiconductor region of a semiconductor substrate and having a first gate electrode;
A second transistor formed in a second semiconductor region of the semiconductor substrate and having a second gate electrode having the same film thickness as the first gate electrode;
The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are each made of fully silicided metal silicide.   The semiconductor device according to claim 1, wherein the second gate electrode is made of metal silicide having a metal composition ratio higher than that of the first gate electrode.   The semiconductor device according to claim 2, wherein the first gate electrode is made of metal silicide having a metal composition ratio of 50% or less.   The semiconductor device according to claim 2, wherein the second gate electrode is made of metal silicide having a metal composition ratio of 60% or more.   The metal constituting the metal silicide is at least one of nickel, cobalt, titanium, platinum, ruthenium, iridium, ytterbium, and a transition metal, according to any one of claims 1 to 4. Semiconductor device.   6. The metal silicide film according to claim 1, wherein the metal silicide film includes a dopant of at least one of boron, phosphorus, arsenic, antimony, aluminum, nitrogen, oxygen, ytterbium, and a transition metal. Semiconductor device.   The first transistor includes a first gate insulating film formed between the first semiconductor region and the first gate electrode, and the second transistor includes the second semiconductor region. And a second gate insulating film formed between the first gate insulating film and the second gate electrode, wherein the first gate insulating film and the second gate insulating film are made of a metal oxide. The semiconductor device according to claim 1.   8. The semiconductor device according to claim 7, wherein the metal oxide is an oxide of at least one of hafnium, zirconium, titanium, tantalum, aluminum, silicon, lanthanum, and a rare earth element. Forming (a) a first semiconductor region and a second semiconductor region on a semiconductor substrate;
A step (b) of sequentially forming a gate insulating film forming film, a gate electrode forming film and a hard mask on the semiconductor substrate;
By patterning the gate insulating film forming film, the gate electrode forming film, and the hard mask, a first gate insulating film, a first gate electrode, and a first hard mask are formed on the first semiconductor region. And (c) forming a second gate insulating film, a second gate electrode, and a second hard mask on the second semiconductor region;
Removing the second hard mask (d);
Forming a first metal film on the second gate electrode (e);
Forming a second fully silicided gate electrode from the second gate electrode by reacting the second gate electrode with the first metal film to fully silicide the second gate electrode. (F) and
Removing the first hard mask (g);
Forming a second metal film on the first gate electrode (h);
Forming a first fully silicided gate electrode from the first gate electrode by reacting the first gate electrode with the second metal film to fully silicide the first gate electrode; And (i) a method for manufacturing a semiconductor device.   The method further includes the step (j) of forming a sidewall on each side surface of the first gate electrode and the second gate electrode after the step (c) and before the step (d). The method of manufacturing a semiconductor device according to claim 9. The first step in the semiconductor substrate after the step (c) and before the step (j), or after the step (j) and before the step (d). Forming a source / drain region in the semiconductor region and the second semiconductor region, respectively (k);
The method further comprises a step (l) of siliciding each of the source / drain regions after the step (k) and before the step (d). The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the second full silicide gate electrode has a metal composition ratio higher than that of the first full silicide gate electrode.   The method of manufacturing a semiconductor device according to claim 9, wherein the metal composition of the first metal film and the second metal film is the same.

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