JP2008165547A - Communication control device - Google Patents

Abstract

Provided is a communication control device that allows a predetermined control device to preferentially access a target device even when bus use request signals are concentrated.
When an SDRAM busy signal is output from a busy timing adjustment circuit, an SDRAM access request mask circuit 37 masks an SDRAM use request signal output from a control circuit with low immediacy. On the other hand, the SDRAM use request signal from the control circuit having high immediacy is not masked even if the SDRAM busy signal is output from the busy timing adjustment circuit 40 and is input to the SDRAM access arbitration circuit 38. Therefore, when the SDRAM busy signal is output from the busy timing adjustment circuit 40, that is, when the frequency of access to the SDRAM 13 is high, the SDRAM access arbitration circuit 38 has priority over the control circuit having high immediacy. Bus permission can be granted.
[Selection] Figure 7

Description

  The present invention relates to a communication control apparatus, and more particularly to a communication control apparatus that allows a predetermined control apparatus to preferentially access a target apparatus even when bus use request signals are concentrated.

As for a communication control device that arbitrates a plurality of bus use request signals output from a plurality of control devices and grants a bus use permission to a specific control device, for example, a bus arbitration circuit described in Patent Document 1 is known. . In this bus arbitration circuit 103, a mask circuit 104 is provided in front of the input unit for inputting a bus use request signal. When a plurality of bus use request signals are simultaneously output from the control device, the bus arbitration circuit 103 has already granted the bus use permission until all the control devices that output the bus use request signal have granted the bus use permission. It is configured not to accept a new bus use request signal from the controller. That is, even if there is a new bus use request signal from a control device that has already been granted bus use permission, the bus arbitration circuit 103 grants the bus use permission to all the control devices that simultaneously output a plurality of bus use request signals. Until this is done, a new bus use request signal is masked (waited) by the mask circuit 104. Therefore, the bus use permission can always be given to a control device with a low priority.
JP-A-9-128327

  However, in the above-described bus arbitration circuit 103, the bus use permission is already granted by the mask circuit 104 until the bus arbitration circuit 103 grants the bus use permission to all the control devices that simultaneously output a plurality of bus use request signals. The new bus use request signal from the controller is masked. Therefore, after a bus use permission has already been granted, a control device that has output a new bus use request signal immediately needs to grant the bus use permission (a control device with high immediacy, for example, image reading). Even if it is a control device that executes control of the scanner device that performs the above, the bus use request signal is masked by the mask circuit 104, so that the bus use permission cannot be immediately given to the control device. Therefore, there is a problem that the processing executed by the control device is delayed due to delay in granting the bus use permission to the control device having high immediacy, and quick control cannot be executed.

  The present invention has been made in order to solve the above-described problems. Even when bus use request signals are concentrated, a predetermined control device can preferentially access a target device. The object is to provide a device.

  In order to achieve this object, the communication control device according to claim 1 includes a storage means capable of writing or reading, a bus line for transmitting information to be written to or read from the storage means, and the storage means. When a plurality of control means for outputting a bus use request signal for occupying the bus line and a plurality of bus use request signals output from the plurality of control means are input simultaneously, One of a plurality of control units that output the bus use request signal is permitted to occupy the bus line and access the storage unit based on a preset priority. A bus arbitration unit that is provided to the control unit, and one control unit that is granted the permission from the bus arbitration unit occupies the bus line. And accessing the storage means and inputting / outputting information to be written to the storage means or information read from the storage means, and counting means for counting the number of accesses to the storage means from the plurality of control means; Detecting the number of accesses counted by the counting means, calculating an access frequency to the storage means within a predetermined time, and storing the memory according to the access frequency calculated by the access frequency calculating means An access concentration signal output means for outputting an access concentration signal indicating that access to the means is concentrated, and when the access concentration signal is output by the access concentration signal output means, the control means is specified. The bus use request signal output from the control means is prohibited from being input to the bus arbitration means And a request signal inhibiting means that.

  The communication control device according to claim 2 is the communication control device according to claim 1, wherein the request signal prohibiting means is configured to control the plurality of control means when an access concentration signal is output from the access concentration signal output means. An input prohibition setting means capable of setting a specific control means for prohibiting the input to the bus arbitration means from among the bus use request signals output from.

  The communication control device according to claim 3 is the communication control device according to claim 2, wherein the access concentration signal output means calculates an access concentration signal indicating that access to the storage means is concentrated, as the access frequency calculation. An access concentration signal stage output means for outputting as a multi-stage access concentration signal according to the access frequency calculated by the means, and the input prohibition setting means divides the plurality of control means into a plurality of processing groups, The request signal prohibiting means includes the access concentration signal stage output means, the order signal setting means for setting the order of occupying the bus line and accessing the storage means in a plurality of stages for each of the plurality of processing groups. A plurality of control means set by the stage of the access concentration signal output from and the order stage setting means A comparison means for comparing the rank order of the physical group, and the bus use request signal output from the control means belonging to a specific processing group among the plurality of control means according to the comparison result by the comparison means An input to the bus arbitration means is prohibited.

  The communication control device according to claim 4 is the communication control device according to any one of claims 1 to 3, wherein the bus arbitration unit indicates a state in which arbitration of the permission to the plurality of control units is executable. An arbitration execution signal output means for outputting an arbitration execution signal, and when the arbitration execution signal is output from the arbitration execution signal output means, the request for the access concentration signal output from the access concentration signal output means Timing adjustment output means for outputting to the signal inhibition means is provided.

  According to the communication control device of the first aspect, the counting means counts the number of accesses from the control means to the storage means, and the access frequency calculation means calculates the access frequency to the storage means within a predetermined time from the count value. . In accordance with the calculated access frequency, the access concentration signal output means outputs an access concentration signal indicating that access to the storage means is concentrated. When the access concentration signal is output, the request signal prohibiting unit prohibits input of the bus use request signal output from the specific control unit to the bus arbitration unit. That is, the request signal prohibiting unit does not output the bus use request signal output from the specific control unit among the plurality of control units to the bus arbitration unit. As a result, when the access to the storage means is concentrated and the access concentration signal is output from the access concentration signal output means, the specific arbitration means is given permission from the bus arbitration means even if the bus use request signal is output. Therefore, the storage means cannot be accessed by occupying the bus line. Conversely, even when access to the storage means is concentrated, if the bus use request signal is output from a plurality of control means other than the specific control means, the request signal prohibiting means sends the bus arbitration means to the bus arbitration means. Input is not prohibited, and a plurality of control means excluding specific control means are given priority by the bus arbitration means. Therefore, even when access to the storage means is concentrated, there is an effect that a plurality of control means excluding specific control means can preferentially access the storage means.

  According to the communication control apparatus of the second aspect, in addition to the effect of the communication control apparatus of the first aspect, the request signal prohibiting means includes the input prohibition setting means. When the signal is output, it is possible to set a specific control means for prohibiting the input of the bus use request signal to the bus arbitration means by the request signal prohibiting means. Therefore, even when it is desired to change the specific control means according to the usage mode of the communication control device, there is an effect that the specific control means can be freely set by the input prohibition setting means.

  According to the communication control device of claim 3, in addition to the effect of the communication control device of claim 2, the access concentration signal output means includes the access concentration signal stage output means, and this access concentration signal stage output means. Outputs an access concentration signal in a plurality of stages according to the access frequency calculated by the access frequency calculation means. Further, the input prohibition setting unit includes a rank level setting unit. The rank level setting unit divides a plurality of control units into a plurality of processing groups and sets a plurality of levels of ranks for accessing the storage unit for each processing group. Set to. Further, the request signal prohibiting means includes a comparing means, which compares the access concentration signal stage output from the access concentration signal stage output means and the rank level of the processing group set by the rank stage setting means. Compare In response to the comparison result of the comparison means, the request signal prohibition means prohibits input of the bus use request signal output from the control means belonging to a specific processing group to the bus arbitration means. Therefore, the request signal prohibiting means determines whether to prohibit the input of the bus use request signal output from the control means belonging to a specific processing group to the bus arbitration means according to the stage of the access concentration signal output from the access concentration signal stage output means. There is an effect that can be switched.

  According to the communication control device of the fourth aspect, in addition to the effect produced by the communication control device according to any one of the first to third aspects, the bus arbitration means includes the arbitration execution signal output means. The output means outputs an arbitration execution signal indicating a state where permission arbitration to a plurality of control means can be executed. When this arbitration execution signal is output, the timing adjustment output means outputs the access concentration signal output from the access concentration signal output means to the request signal prohibition means. Thereby, the access concentration signal output from the access concentration signal output means is output to the request signal prohibition means when the bus arbitration means is in a state where the bus use request signal can be adjusted. That is, when the bus arbitration means grants one of the plurality of control means permission to occupy the bus line and access the storage means, an access concentration signal is output from the access concentration signal output means. Even so, the access concentration signal is not output to the request signal prohibition means by the timing adjustment output means. Therefore, although the bus arbitration means grants permission for one of the plurality of control means to occupy the bus line and access the storage means, the access concentration signal is output from the access concentration signal output means. The bus use request signal output from the one control means to which the permission is given is output to the bus arbitration means by the request signal prohibiting means, and the granting of permission by the bus arbitration means is not interrupted. Therefore, there is an effect that the permission of the bus arbitration means can be surely executed.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Referring to FIG. 1, the control unit 1 of a multi-function peripheral device (MFD (Multi Function Device that realizes various functions such as a scanner function, a copy function, and a facsimile function)) on which the ASIC 20 as the communication control apparatus is mounted. The electrical configuration will be described. FIG. 1 is a block diagram showing an electrical configuration of a control unit 1 that controls the operation of the multifunction peripheral device.

  The control unit 1 is a microcomputer that comprehensively controls the operation of the multi-function peripheral device. As shown in FIG. 1, the control unit 1 includes an ASIC (Application Specific Integrated Circuit) 20, a ROM (Read Only Memory) 12, and an SDRAM (Synchronous Dynamic). Random Access Memory) 13 is mainly configured. The ASIC 20 includes a USB terminal 2, an operation key 3 connected to a panel gate array (hereinafter referred to as “panel GA”) 3a, and a liquid crystal display connected to a liquid crystal display controller (hereinafter referred to as “LCD controller”) 4a. A printer 5, a scanner 6, a slot 7, a speaker 9, a network control unit (hereinafter referred to as “NCU”) 10, and a modem 11 are connected.

  The ASIC 20 is an integrated circuit including a CPU 30 (see FIG. 2) that controls each unit connected to the bus line in accordance with a program stored in the ROM 12. The ROM 12 is a non-volatile memory that stores various control programs executed by the multifunction peripheral device. The SDRAM 13 is a volatile memory that temporarily stores various types of information when the control program is executed. The ROM 12 is connected to the ASIC 20 via the bus line 14, and the SDRAM 13 is connected to the ASIC 20 via the bus line 15.

  The USB terminal 2 is connected to a USB interface control circuit (hereinafter referred to as “USB I / F control circuit”) 32 in the ASIC 20. When a personal computer (hereinafter referred to as “PC”) is connected to the USB terminal 2, the USB I / F control circuit 32 communicates with the PC and stores image data from the PC in the SDRAM 13. It is a control circuit.

  A user interface control circuit (hereinafter referred to as “user I / F control circuit”) 34 is provided in the ASIC 20, and a panel GA 3 a and an LCD controller 4 a are connected to the user I / F control circuit 34. ing.

  The panel GA 3 a controls the operation key 3 for inputting a desired command to the multi-function peripheral device. The panel GA 3 a detects the pressing (input) of the operation key 3 and outputs a predetermined code signal to the ASIC 20. This code signal is assigned corresponding to the plurality of operation keys 3. When receiving a predetermined code signal from the panel GA 3a, the user I / F control circuit 34 generates an interrupt to the CPU 30 (see FIG. 2). The CPU 30 (see FIG. 2) that has received the interrupt performs control processing to be executed in accordance with a predetermined key processing table. This key processing table is a table in which code signals and control processing are associated with each other, and is stored in the ROM 12, for example.

  The LCD controller 4 a is for displaying on the LCD 4 image data read from a memory card or the like, information on the operation of the printer 5 and the scanner 6, and the like based on a command from the ASIC 20. Specifically, the user I / F control circuit 34 creates image data of an image to be displayed on the LCD 4 on a display memory (not shown) provided in the SDRAM 13, and transfers this data to the LCD controller 4a. . The LCD controller 4a controls the LCD 4 to display the transferred data on the LCD 4.

  The printer 5 prints an image or the like on a recording sheet. The image data read from a memory card connected to the slot unit 7 or the image data transferred from the PC connected to the USB terminal 2 Alternatively, it is configured as an ink jet printer that employs a method of selectively ejecting ink droplets based on image data of an image read by the scanner 6, a so-called ink jet method. The ink jet method is merely an example, and a method such as an electrophotographic method or a thermal transfer method may be employed. The printer 5 is connected to a recording control circuit 35 in the ASIC 20. The recording control circuit 35 is a control circuit for reading out image data or the like after image processing (processing for correcting the image quality of image data or the like) stored in the SDRAM 13 and outputting it to the printer 5. The image data output by the recording control circuit 35 is printed by the printer 5.

  The scanner 6 is a device that reads an image from a recording sheet on which an image or the like is printed, and is connected to a reading control circuit 36 in the ASIC 20. The read control circuit 36 is a control circuit for inputting image data or the like of an image read by the scanner 6, performing image processing on the input image data, and storing it in the SDRAM 13. Image data stored in the SDRAM 13 by the read control circuit 36 is read by the image processing control circuit 33.

  The image processing control circuit 33 is a control circuit that reads image data stored in the SDRAM 13 and performs image processing such as correction of image quality of the read image data. When the image processing is completed, the image processing control circuit 33 stores the image data after completion of the image processing in the SDRAM 13.

  The slot 7 is a terminal for connecting a memory card (portable flash memory or the like). The slot portion 7 has a known configuration and will not be described in detail.

  The amplifier 8 is a device that rings a speaker 9 connected to the amplifier 8 and outputs a ringing tone, a rejection tone, a message, and the like. The amplifier 8 is connected to the ASIC 20 and also to the speaker 9.

  The NCU 10 is a device that performs operations such as sending a dial signal to a telephone network (not shown) and responding to a calling signal from the telephone network. The modem 11 is a device that modulates and demodulates image data and the like via the NCU 10, transmits the data to a partner facsimile machine (not shown), and transmits and receives various procedure signals for transmission control. The NCU 10 and the modem 11 are each connected to the ASIC 20 by a bus line.

  Next, the electrical configuration of the ASIC 20 will be described with reference to FIG. FIG. 2 is a block diagram showing an electrical configuration of the ASIC 20. The ASIC 20 includes a CPU 30, a bus controller circuit 31, a USB I / F control circuit 32, an image processing control circuit 33, a user I / F control circuit 34, a recording control circuit 35, a reading control circuit 36, and an SDRAM. It mainly includes an access request mask circuit 37, an SDRAM access arbitration circuit 38, an SDRAM controller circuit 39, a busy timing adjustment circuit 40, an SDRAM access frequency detection circuit 41, and a ROM controller circuit 43.

  The CPU 30 is an arithmetic unit that controls each unit in the ASIC 20 and controls the outside of the ASIC 20 (for example, the ROM 12 and the SDRAM 13). The CPU 30 controls each control circuit (USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35) in the ROM 12, SDRAM 13, and ASIC 20 via the bus controller circuit 31. And a read control circuit 36).

  The bus controller circuit 31 determines whether a command signal from the CPU 30 is an access to the ROM 12 or an SDRAM 13 according to an address added to the command signal, and whether each control circuit (USB I / F control) Circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and reading control circuit 36). Based on the determination, an instruction signal from CPU 30 is sent. A control circuit for transmission. For example, if the command signal from the CPU 30 is a command signal to each control circuit, the command signal is transmitted to various control circuits via the internal bus 42.

  The bus controller circuit 31 is also connected to the SDRAM access request mask circuit 37. If the command signal from the CPU 30 is a signal for accessing the SDRAM 13, the bus controller circuit 31 outputs an SDRAM use request signal to the SDRAM access request mask circuit 37.

  The bus controller circuit 31, the USB I / F control circuit 32, the image processing control circuit 33, the user I / F control circuit 34, the recording control circuit 35, and the reading control circuit 36 are connected to the internal bus 42, and are connected to the SDRAM. The access request mask circuit 37 is connected.

  When the bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and read control circuit 36 require access to the SDRAM 13, SDRAM access An SDRAM use request signal is output to the request mask circuit 37. For example, when image data is input from the scanner 6 to the read control circuit 36, the read control circuit 36 outputs an SDRAM use request signal to the SDRAM access request mask circuit 37.

  Further, the bus controller circuit 31, the USB I / F control circuit 32, the image processing control circuit 33, the user I / F control circuit 34, the recording control circuit 35, and the reading control circuit 36 are respectively connected from the register 31a to each control circuit. The CPU 30 writes setting data to the registers 31a to 36a in each control circuit using the internal bus 42 after the ASIC 20 is powered on (initialization process). By writing the setting data, each control circuit can be operated.

  The bus controller circuit 31, the USB I / F control circuit 32, the image processing control circuit 33, the user I / F control circuit 34, the recording control circuit 35, and the reading control circuit 36 are continuously transferred to the registers 31 a to 36 a. Counters 31a1 to 36a1 are provided. The value of this continuous transfer counter is determined by each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and reading control circuit 36). Indicates the number of times the SDRAM 13 is accessed with one application (occupation) of the bus line 15 when accessing the SDRAM 13. If the number of times the SDRAM 13 is accessed with one application (occupation) of the bus line 15 increases, the initial value of the continuous transfer counter is set accordingly.

  When a control circuit to which use permission of the bus line 15 is granted by the SDRAM access arbitration circuit 38 described later accesses the SDRAM 13, the SDRAM access arbitration circuit is sent to the control circuit to which use permission of the bus line 15 is given. The SDRAM use request acceptance completion signal is output from 38. As a result, the value of the continuous transfer counter of the control circuit to which use permission of the bus line 15 is given is counted down by one. When the value of the continuous transfer counter becomes “0 (zero)”, the access to the SDRAM 13 of the control circuit to which use permission of the bus line 15 is given is completed. As a result, the control circuit to which use permission of the bus line 15 is given stops outputting the SDRAM use request signal.

  The SDRAM access request mask circuit 37 does not allow the SDRAM access arbitration circuit 38 to input an SDRAM use request signal output from a specific control circuit when an SDRAM busy signal indicating that the frequency of access to the SDRAM 13 is high. This is a circuit (hereinafter, the fact that the SDRAM use request signal is not input to the SDRAM access arbitration circuit 38 is referred to as “masking the SDRAM use request signal”). The SDRAM access request mask circuit 37 includes control circuits (a bus controller circuit 31, a USB I / F control circuit 32, an image processing control circuit 33, a user I / F control circuit 34, a recording control circuit 35, and a reading control circuit 36). The SDRAM access arbitration circuit 38 and the busy timing adjustment circuit 40 are connected. When the SDRAM busy signal is not output from the busy timing adjustment circuit 40, the SDRAM access request mask circuit 37 does not mask the SDRAM use request signal from each control circuit, and sends all the input SDRAM use request signals to the SDRAM. The data is output to the access arbitration circuit 38.

  On the other hand, when the SDRAM busy signal is output from the busy timing adjustment circuit 40, the SDRAM access request mask circuit 37 masks the SDRAM use request signal output from the specific control circuit, and the SDRAM access arbitration circuit 38. Input to is prohibited. However, even when the SDRAM busy signal is output from the busy timing adjustment circuit 40, the SDRAM use request signal output from the control circuit other than the specific control circuit is not masked by the SDRAM access request mask circuit 37, but the SDRAM. The data is output to the access arbitration circuit 38. The specific control circuits in the present embodiment are a bus controller circuit 31, a USB I / F control circuit 32, and an image processing control circuit 33 (see FIG. 4). The SDRAM use request signal is output from the bus controller circuit 31 when a signal for accessing the SDRAM 13 is output from the CPU 30.

  The SDRAM access arbitration circuit 38 is a circuit that arbitrates the SDRAM use request signal output from the SDRAM access request mask circuit 37 and gives permission to use the bus line 15 to the control circuit that has output the SDRAM use request signal. The SDRAM access arbitration circuit 38 is connected to the SDRAM access request mask circuit 37, the SDRAM controller circuit 39, and the busy timing adjustment circuit 40.

  If there is one SDRAM use request signal output from the SDRAM access request mask circuit 37, the SDRAM access arbitration circuit 38 grants the use permission of the bus line 15 to the control circuit that has output the SDRAM use request signal. On the other hand, if there are a plurality of SDRAM use request signals output from the SDRAM access request mask circuit 37 simultaneously, the SDRAM access arbitration circuit 38 gives priority to the SDRAM use request signal from any control circuit set in the internal register in advance. Arbitration is performed according to the priority, and permission to use the bus line 15 is given to one control circuit having a high priority. One control circuit to which use permission is granted can occupy the bus line 15 and access the SDRAM 13. It should be noted that the control circuit which has not been granted use permission continuously outputs the SDRAM use request signal to the SDRAM access request mask circuit 37 until use permission of the bus line 15 is given.

  The SDRAM access arbitration circuit 38 outputs an access request arbitration signal indicating that the SDRAM use request signal output from the SDRAM access request mask circuit 37 can be arbitrated to the busy timing adjustment circuit 40.

  The SDRAM controller circuit 39 is a circuit that selects an SDRAM to be accessed according to an address added to the SDRAM use request signal output from the SDRAM access arbitration circuit 38 and outputs a control signal to the selected SDRAM. In the present embodiment, since there is only one SDRAM 13 SDRAM, the SDRAM controller circuit 39 does not select the SDRAM to be accessed. However, for example, in the case of a multi-functional peripheral device using three SDRAMs, one SDRAM to be accessed is selected by the SDRAM controller circuit 39, and the control circuit that has output the SDRAM use request signal accesses the selected SDRAM. become.

  The SDRAM controller circuit 39 is connected to the SDRAM access arbitration circuit 38, the bus line 15, and the SDRAM access frequency detection circuit 41. When there is an access to the SDRAM 13 from the control circuit to which use permission of the bus line 15 is granted, the SDRAM controller circuit 39 detects the access and sends an SDRAM access detection signal indicating that the access has been made to the SDRAM access frequency detection circuit 41. Output to.

  The SDRAM access frequency detection circuit 41 detects the number of accesses to the SDRAM 13 and calculates the access frequency to the SDRAM 13 within a predetermined period (within a period determined by a value of a period setting register 41a1 described later) from the detected number of accesses. Circuit. The SDRAM access frequency detection circuit 41 is connected to the SDRAM controller circuit 39, the busy timing adjustment circuit 40, and the internal bus 42. The SDRAM access frequency detection circuit 41 includes a period setting register 41a1 and an SDRAM access frequency threshold register 41a2 in a register 41a. The SDRAM access frequency detection circuit 41 has a period counter (not shown) and an SDRAM access counter (not shown) configured by hardware.

  The period setting register 41a1 is a register that determines a period during which the SDRAM access frequency detection circuit 41 calculates the access frequency to the SDRAM 13. When the ASIC 20 is turned on, the CPU 30 writes setting data to the period setting register 41a1 via the internal bus. In the present embodiment, “3F (hexadecimal number)” is set in the period setting register 41a1. The relationship between the value of the period setting register 41a1 and the period counter will be described later.

  The SDRAM access frequency threshold value register 41a2 is a register that determines an access frequency threshold value at which the SDRAM access frequency detection circuit 41 outputs a high access frequency detection signal. Similar to the setting of the period setting register 41a1, when the ASIC 20 is turned on, the CPU 30 writes setting data to the SDRAM access count threshold register 41a2 via the internal bus. In the present embodiment, “24 (hexadecimal number)” is set in the SDRAM access count threshold value register 41a2. The relationship between the value of the SDRAM access count threshold register 41a2 and the SDRAM access counter will be described later.

  The period counter (not shown) receives an internal clock signal output from an internal clock (not shown) and counts up by one for each cycle of the internal clock. The period counter is counted up until the value set in the period setting register 41a1 is reached. When the value of the period counter reaches the value set in the period setting register 41a1 ("3F (hexadecimal number)"), the period counter Is reset to zero (see FIG. 6). The period counter updates the count value during the period in which the operation of the SDRAM access frequency detection circuit 41 is permitted.

  The SDRAM access counter is a counter that receives the SDRAM access detection signal output from the SDRAM controller circuit 39, counts up by one each time the SDRAM access detection signal is input, and counts the number of accesses to the SDRAM. . The SDRAM access counter is counted up until the value of the period counter reaches the value set in the period setting register 41a1 (“3F (hexadecimal number)”). In addition, when the count value of the period counter is reset to zero, the count value of the SDRAM access counter is reset to zero accordingly (see FIG. 6). Note that the SDRAM access counter updates the count value during the period when the operation of the SDRAM access frequency detection circuit 41 is permitted.

  The SDRAM access frequency detection circuit 41 counts the SDRAM access counter (the number of accesses to the SDRAM 13) when the value of the period counter reaches the value set in the period setting register 41a1 (“3F (hexadecimal number)”). And the access frequency to the SDRAM 13 (the number of accesses to the SDRAM 13 during the period set in the period setting register 41a1) is calculated. If the calculated access frequency is greater than the access count (“24 (hexadecimal number)”) set in the SDRAM access count threshold register 41a2, the SDRAM access frequency detection circuit 41 indicates that the access frequency to the SDRAM 13 is high. The access frequency high detection signal shown is output to the busy timing adjustment circuit 40 (see FIG. 6). On the other hand, when the calculated access frequency is equal to or less than the access count (“24 (hexadecimal number)”) set in the SDRAM access count threshold register 41 a 2, the high access frequency detection signal is not output from the SDRAM access frequency detection circuit 41 ( (See FIG. 6).

  The busy timing adjustment circuit 40 is a circuit that adjusts the output timing of the SDRAM busy signal output to the SDRAM access request mask circuit 37. The busy timing adjustment circuit 40 is connected to the SDRAM access request mask circuit 37, the SDRAM access arbitration circuit 38, and the SDRAM access frequency detection circuit 41. The busy timing adjustment circuit 40 is composed of an AND circuit. The output terminal of this AND circuit is connected to the SDRAM access request mask circuit 37, one of the two input terminals of the AND circuit is connected to the SDRAM access arbitration circuit 38, and the other input terminal is connected to the SDRAM access frequency detection circuit 41. ing.

  Since the busy timing adjustment circuit 40 is composed of an AND circuit, even if the high access frequency detection signal is output from the SDRAM access frequency detection circuit 41, the SDRAM use request signal can be adjusted from the SDRAM access arbitration circuit 38. If the access request arbitration signal indicating this is not output, the SDRAM busy signal is not output to the SDRAM access request mask circuit 37. Therefore, although the SDRAM access arbitration circuit 38 grants the use permission of the bus line 15 to any one of the control circuits, the SDRAM busy request signal is output to the SDRAM access request mask circuit 37, and the SDRAM access request mask is output. The circuit 37 stops the SDRAM use request signal output from one control circuit to which the use permission of the bus line 15 is given to the SDRAM access arbitration circuit 38, and the use permission of the bus line 15 of the SDRAM access arbitration circuit 38. Granting will not be interrupted. Therefore, the permission to use the bus line 15 of the SDRAM access arbitration circuit 38 can be reliably executed.

  The ROM controller circuit 43 is a circuit that selects a ROM to be accessed according to an address added to the signal output from the bus controller circuit 31 and outputs a control signal to the selected ROM. The ROM controller circuit 43 is connected to the bus controller circuit 31 and is connected to the ROM 12 through the bus line 14. In the present embodiment, since there is only one ROM 12 ROM, the ROM controller circuit 43 does not select the ROM to be accessed. However, for example, in the case of a multi-function peripheral device using three ROMs, one ROM to be accessed is selected by the ROM controller circuit 43, and the CPU 30 accesses the selected ROM.

  Next, the electrical configuration of the SDRAM access request mask circuit 37 will be described with reference to FIG. FIG. 3 is a block diagram showing an electrical configuration of the SDRAM access request mask circuit 37. The SDRAM access request mask circuit 37 mainly includes a mask register 50, NOT circuits 51a to 51f that are logical NOT circuits, OR circuits 52a to 52f that are logical sum circuits, and AND circuits 53a to 53f that are logical product circuits. Have.

  The mask register 50 corresponds to each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and reading control circuit 36). This is a register for storing a value to be output to one of the input terminals of the OR circuits 52a to 52f. The mask register 50 outputs six signals connected to one of the input terminals of the OR circuits 52a to 52f. Note that the value input to one of the input terminals of the OR circuits 52a to 52f is a fixed value as long as the value stored in the mask register 50 is not rewritten.

  Here, the values stored in the mask register 50 will be described with reference to FIG. FIG. 4 is a list of values stored in the mask register 50. The value stored in the mask register 50 is set for each control circuit as shown in FIG. The value stored in the mask register 50 is “0 (zero)” or “1”. The control circuit in which “0 (zero)” is set in the mask register 50 is assumed to be low in immediacy, and the SDRAM busy indicating that the frequency of access to the SDRAM 13 from the busy timing adjustment circuit 40 to the SDRAM access request mask circuit 37 is high. When the signal is output, the SDRAM access request mask circuit 37 masks the SDRAM use request signal.

  On the other hand, the control circuit set to “1” in the mask register 50 has high immediacy, and even if the SDRAM busy signal is output from the busy timing adjustment circuit 40, the SDRAM access request mask signal 37 is used by the SDRAM access request mask circuit 37. Do not mask. In the present embodiment, the bus controller circuit 31, the USB I / F control circuit 32, and the image processing control circuit 33 are set to “0 (zero)” in the mask register 50. Further, the user I / F control circuit 34, the recording control circuit 35, and the reading control circuit 36 are set to “1” in the mask register 50.

  Thus, since the SDRAM access request mask circuit 37 is provided with the mask register 50, when the SDRAM busy request signal is output from the busy timing adjustment circuit 40, the SDRAM access request mask circuit 37 masks the immediacy. And a control circuit with high immediacy that is not masked by the SDRAM access request mask circuit 37 can be set. Therefore, even when it is desired to change the immediacy of the control circuit in accordance with the usage mode of the multifunction peripheral device, the immediacy can be freely set by the mask register 50.

  Returning to the description of FIG. NOT circuits 51a to 51f are connected to the other input terminals of the OR circuits 52a to 52f (input terminals not connected to the mask register 50), and the NOT circuits 51a to 51f are connected to the busy timing adjustment circuit 40, respectively. Yes. The output terminals of the OR circuits 52a to 52f are connected to one of the input terminals of the AND circuits 53a to 53f, respectively. Since the value input to one of the input terminals of the OR circuits 52a to 52f connected to the mask register 50 is a fixed value, the case where the SDRAM busy signal is output from the busy timing adjustment circuit 40 and the case where the SDRAM busy signal is The value output from the output terminals of the OR circuits 52a to 52f, i.e., the values input to the AND circuits 53a to 53f, respectively, is switched when the signal is not output.

  The other of the input terminals of the AND circuits 53a to 53f is connected to each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and A read control circuit 36) is connected. Therefore, for example, when an SDRAM use request signal is output from the bus controller circuit 31, the SDRAM use request signal is input to the other input terminal of the AND circuit 53a.

  Next, the operation of the SDRAM access request mask circuit 37 will be described. Here, in FIG. 4, when the SDRAM use request signal is output from the bus controller circuit 31 that is set to be low in immediacy (set to “0 (zero)” in the mask register 50), the immediacy is The operation of the SDRAM access request mask circuit 37 when the SDRAM use request signal is output from the recording control circuit 35 set to be high (set to “1” in the mask register 50) will be exemplified.

  The operation when the SDRAM use request signal is output from the USB I / F control circuit 32 and the image processing control circuit 33 is the same as the operation when the SDRAM use request signal is output from the bus controller circuit 31 described below. It is. The operation when the SDRAM use request signal is output from the user I / F control circuit 34 and the read control circuit 36 is the same as the operation when the SDRAM use request signal is output from the user I / F control circuit 34 described later. Are the same.

  First, the operation when the SDRAM use request signal is output from the bus controller circuit 31 will be described. When the SDRAM busy signal is not output from the busy timing adjustment circuit 40, “0 (zero)” is input to the input terminal of the NOT circuit 51a. On the other hand, the value “0 (zero)” stored in the mask register 50 is input to one of the input terminals of the OR circuit 52a. At this time, “1” is output from the output terminal of the OR circuit 52a, and the value is input to one of the input terminals of the AND circuit 53a. Since the SDRAM use request signal is input to the other input terminal of the AND circuit 53a, its value is “1”. Therefore, “1” is output from the output terminal of the AND circuit 53a. That is, the SDRAM use request signal is output from the output terminal of the AND circuit 53a, and the output SDRAM use request signal is output to the SDRAM access arbitration circuit 38.

  On the other hand, when the SDRAM busy signal is output from the busy timing adjustment circuit 40, “1” is input to the input terminal of the NOT circuit 51a. On the other hand, the value “0 (zero)” stored in the mask register 50 is input to one of the input terminals of the OR circuit 52a. At this time, “0 (zero)” is output from the output terminal of the OR circuit 52a, and the value is input to one of the input terminals of the AND circuit 53a. Therefore, even if the SDRAM use request signal is input to the other input terminal of the AND circuit 53a and the other input terminal is “1”, “0 (zero)” is output from the output terminal of the AND circuit 53a. . That is, the SDRAM use request signal is not output from the output terminal of the AND circuit 53a, and the SDRAM use request signal input to the other input terminal of the AND circuit 53a is masked. Therefore, when the SDRAM busy signal is output from the busy timing adjustment circuit 40, the SDRAM use request signal input to the other input terminal of the AND circuit 53a is masked by the SDRAM access request mask circuit 37 and accessed to SDRAM. It is not output to the arbitration circuit 38.

  Next, the operation when the SDRAM use request signal is output from the recording control circuit 35 will be described. The SDRAM use request signal output from the recording control circuit 35 is masked by the SDRAM access request mask circuit 37 regardless of whether the SDRAM busy signal is output from the busy timing adjustment circuit 40 or not. Never happen. The reason for this will be described. The value “1” stored in the mask register 50 is input to one of the input terminals of the OR circuit 52 e. Thus, even if “1” is input to the input terminal of the NOT circuit 51e (even if the SDRAM busy signal is output from the busy timing adjustment circuit 40), “0 (zero)” is input to the input terminal of the NOT circuit 51e. Is input (even if the SDRAM busy signal is not output from the busy timing adjustment circuit 40), "1" is output from the output terminal of the OR circuit 52e, and the value is input to the input terminal of the AND circuit 53e. Input to one side.

  Therefore, when the SDRAM use request signal is output from the recording control circuit 35 and the other input terminal of the AND circuit 53e becomes “1”, the output terminal of the AND circuit 53e becomes “1”. Therefore, when the SDRAM use request signal is output from the recording control circuit 35, the SDRAM use request signal is output regardless of whether the SDRAM busy signal is output from the busy timing adjustment circuit 40 or not. The data is not masked by the SDRAM access request mask circuit 37, but is output to the SDRAM access arbitration circuit 38.

  In this way, the SDRAM access request mask circuit 37 responds to the SDRAM busy signal output from the busy timing adjustment circuit 40 according to each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit). 33, the SDRAM use request signal output from the user I / F control circuit 34, the recording control circuit 35, and the reading control circuit 36) is masked.

  Next, the timing at which the SDRAM access frequency detection circuit 41 determines the output of the high access frequency detection signal will be described with reference to FIG. FIG. 5 shows a timing chart of the internal clock signal, the value of the period counter, the value of the SDRAM access counter, and the high access frequency detection signal. A state where the signal is output is illustrated as H, and a state where the signal is stopped is illustrated as L.

  As described above, the period counter provided in the SDRAM access frequency detection circuit 41 shown in FIG. 5B (not shown) is one of the internal clock signals of the internal clock (not shown) shown in FIG. Count up by 1 for each cycle. The SDRAM access counter (not shown) provided in the SDRAM access frequency detection circuit 41 shown in FIG. 5E is such that the SDRAM access detection signal output from the SDRAM controller circuit 39 is as shown in FIG. Every time it is output, it counts up by one.

  When the value of the period counter shown in FIG. 5B is the same as “3F (hexadecimal number)” set in the period setting register 41a1 of the SDRAM access frequency detection circuit 41 shown in FIG. 5C (at time T1) The SDRAM access frequency detection circuit 41 reads the count value of the SDRAM access counter (at time T1). The SDRAM access frequency detection circuit 41 compares the read count value “26 (hexadecimal number)” with “24 (hexadecimal number)” set in the SDRAM access frequency threshold value register 41a2 shown in FIG. To do.

  Since the count value “26 (hexadecimal)” read by the SDRAM access frequency detection circuit 41 at T1 is larger than “24 (hexadecimal)” set in the SDRAM access frequency threshold register 41a2, the SDRAM access frequency detection circuit 41 As shown in FIG. 5G, an access frequency high detection signal indicating that the access frequency to the SDRAM 13 is high is output to the busy timing adjustment circuit 40 (at time T1).

  Thereafter, when the value of the period counter shown in FIG. 5B again becomes the same as “3F (hexadecimal number)” set in the period setting register 41a1 of the SDRAM access frequency detection circuit 41 shown in FIG. At time T2, the SDRAM access frequency detection circuit 41 reads the count value of the SDRAM access counter (at time T2). The SDRAM access frequency detection circuit 41 compares the read count value “23 (hexadecimal number)” with “24 (hexadecimal number)” set in the SDRAM access frequency threshold register 41a2 shown in FIG. To do.

  The count value “23 (hexadecimal number)” read by the SDRAM access frequency detection circuit 41 at T2 is equal to or less than “24 (hexadecimal number)” set in the SDRAM access frequency threshold register 41a2, so the SDRAM access frequency detection circuit 41 As shown in FIG. 5G, the output of the high access frequency detection signal to the busy timing adjustment circuit 40 is stopped (at time T2).

  In this way, the SDRAM access frequency detection circuit 41 determines the output of the high access frequency detection signal.

  Next, a main process executed by the SDRAM access frequency detection circuit 41 will be described with reference to FIG. FIG. 6 is a flowchart showing a main process executed by the SDRAM access frequency detection circuit 41. The main process is a process of updating the value of the period counter and the value of the SDRAM access counter and determining the output of the high access frequency detection signal, and is repeatedly executed when the operation of the SDRAM access frequency detection circuit 41 is permitted. Process.

  When the power supply of the multifunction peripheral device is turned on, the CPU 30 performs an initialization process of the SDRAM access frequency detection circuit 41 (S1). Initialization of the SDRAM access frequency detection circuit 41 means that “3F (hexadecimal)” (see FIG. 5) is set in the period setting register 41a1, and “24 (hexadecimal)” is set in the SDRAM access frequency threshold register 41a2 (see FIG. 5). Is set to a state in which the operation is permitted (S1). Thereafter, both the value of the period counter and the value of the SDRAM access counter are initialized to “0 (zero)” (S2).

  Next, it is determined whether the value of the period counter is the same as the value of the period setting register 41a1 (S3). If the value of the period counter is not the same as the value of the period setting register 41a1 (S3: No), the value of the period counter is incremented by 1 (S4). Then, it is determined whether an SDRAM access detection signal is input from the SDRAM controller circuit 39 (S5). If it is determined that an SDRAM access detection signal is input (S5: Yes), the value of the SDRAM access counter is incremented by 1 (S6), and the process returns to S3. On the other hand, if it is determined in the process of S5 that there is no SDRAM access detection signal input (S5: No), the process returns to S3 without incrementing the value of the SDRAM access counter.

  In the process of S3, if the value of the period counter is the same as the value of the period setting register 41a1 (S3: Yes), it is determined whether the value of the SDRAM access counter is larger than the value of the SDRAM access count threshold register 41a2 (S7). . If it is determined that the value of the SDRAM access counter is larger than the value of the SDRAM access count threshold register 41a2 (S7: Yes), an access frequency high detection signal indicating that the frequency of access to the SDRAM 13 is high is output (S8). On the other hand, when it is determined that the value of the SDRAM access counter is equal to or less than the value of the SDRAM access count threshold register 41a2 (S7: No), the high access frequency detection signal is not output (S9). When one of the processes of S8 or S9 is completed, both the value of the period counter and the value of the SDRAM access counter are set to “0 (zero)” (S10), and the process returns to S3.

  Through the above processing, the value of the period counter and the value of the SDRAM access counter are updated, and the output determination of the access frequency high detection signal is performed.

  Next, the process executed by the ASIC 20 will be described with reference to FIG. FIG. 7 illustrates the recording control circuit 35 (“1” indicating that immediacy is high in the mask register 50 is set (see FIG. 4)) and the image processing control circuit 33 (indicating that immediacy is low in the mask register 50 “ FIG. 6 is a timing chart of processing executed in the ASIC 20 when an SDRAM use request signal is output from “0 (zero)” (see FIG. 4)). FIG. 7 shows an example when the SDRAM use request signal is output from the recording control circuit 35 and the image processing control circuit 33. Therefore, the processing executed by the ASIC 20 when the SDRAM use request signal is output from another control circuit (the bus controller circuit 31, the USB I / F control circuit 32, the user I / F control circuit 34, and the read control circuit 36). Are processed in the same manner as in the example. Further, a state in which the signal is output is illustrated as H, and a state in which the signal is stopped is illustrated as L.

  As a premise for explaining FIG. 7, as shown in FIG. 7 (j), the access frequency high detection signal indicating that the access frequency to the SDRAM 13 output from the SDRAM access frequency detection circuit 41 is high is busy until T10 o'clock. The signal is output to the timing adjustment circuit 40, and the output is stopped after T10. FIG. 7A shows a clock signal of an internal clock (not shown).

  As shown in FIG. 7B, when an SDRAM use request signal is output from the recording control circuit 35 to the SDRAM access request mask circuit 37 (at time T3), the SDRAM use request signal is shown in FIG. 7C. Are input from the SDRAM access request mask circuit 37 to the SDRAM access arbitration circuit 38 (at time T3). This is because the SDRAM use request signal input to the SDRAM access request mask circuit 37 is only from the recording control circuit 35. In the case of the recording control circuit 35, the initial value of the continuous transfer counter 35a1 indicating the number of times the SDRAM 13 is accessed by occupying the bus line 15 once is 1.

  When an SDRAM use request signal is input from the recording control circuit 35 to the SDRAM access arbitration circuit 38, the SDRAM access arbitration circuit 38 performs arbitration and grants the use permission of the bus line 15 to the recording control circuit 35 (from T3 to T6). Time). The recording control circuit 35 to which use permission of the bus line 15 is given occupies the bus line 15 and accesses the SDRAM 13 (from time T3 to time T6). Note that the recording control circuit 35 does not detect from which point in time the use permission of the bus line 15 is granted, but only detects that one access has been completed by an SDRAM use request acceptance completion signal to be described later. is there. From time T3 to time T6, since the recording control circuit 35 occupies the bus line 15 and accesses the SDRAM 13, the SDRAM access arbitration circuit 38 cannot perform arbitration as shown in FIG. In order to show that there is, the output of the access request arbitration signal to the busy timing adjustment circuit 40 is stopped (from T3 to T5). Accordingly, as shown in FIG. 7L, the busy timing adjustment circuit 40 stops the output of the SDRAM busy signal to the SDRAM access request mask circuit 37 (from time T3 to time T5).

  As shown in FIG. 7F, when an SDRAM use request signal is output from the image processing control circuit 33 to the SDRAM access request mask circuit 37 at T4, which is between T3 and T5, the SDRAM use request signal is The data is not masked by the access mask circuit 37 and output to the SDRAM access arbitration circuit 38 (from time T4 to time T5). This is because the busy timing adjustment circuit 40 stops outputting the SDRAM busy signal to the SDRAM access request mask circuit 37 (from time T3 to time T5) as shown in FIG. However, even if the SDRAM use request signal is input from the image processing control circuit 33 to the SDRAM access arbitration circuit 38 between the time T4 and the time T5, the SDRAM access arbitration circuit 38 does not arbitrate the SDRAM use request signal. The use permission of the bus line 15 is not given to the image processing control circuit 33.

  One clock before the internal clock signal (FIG. 7A), which is the timing when the access to the SDRAM 13 by the recording control circuit 35 is completed, as shown in FIG. An SDRAM use request acceptance completion signal indicating that access to the SDRAM 13 has been completed is output to 35 (at time T5). When this SDRAM use request acceptance completion signal is output, as shown in FIG. 7D, the value of the continuous transfer counter 35a1 of the recording control circuit 35 becomes “0 (zero)” (time T6). As a result, as shown in FIG. 7B, the recording control circuit 35 stops outputting the SDRAM use request signal to the SDRAM access request mask circuit 37 (at time T6). Accordingly, as shown in FIG. 7C, the SDRAM use request signal from the recording control circuit 35 input to the SDRAM access arbitration circuit 38 is also stopped (T6).

  Also, as shown in FIG. 7E, when an SDRAM use request acceptance completion signal indicating that access to the SDRAM 13 is completed is output from the SDRAM access arbitration circuit 38 to the recording control circuit 35 (at time T5), the SDRAM As shown in FIG. 7 (k), the access arbitration circuit 38 outputs an access request arbitration signal indicating that the use permission arbitration of the bus line 15 is possible to the busy timing adjustment circuit 40 (at time T5).

  As shown in FIG. 7J, an access frequency high detection signal indicating that the frequency of access from the SDRAM access frequency detection circuit 41 to the SDRAM 13 is high is also output to the busy timing adjustment circuit 40 (at time T5). . Therefore, as shown in FIG. 7L, the busy timing adjustment circuit 40 outputs an SDRAM busy signal indicating that the frequency of access to the SDRAM 13 is high to the SDRAM access request mask circuit 37 (at time T5). As shown in FIG. 7C, the SDRAM use request signal is output from the recording control circuit 35 to the SDRAM access arbitration circuit 38 from the time T5 to the time T6, but during the time T5 to the time T6, the SDRAM is used. The access arbitration circuit 38 removes the SDRAM use request signal output from the recording control circuit 35 and performs use permission arbitration of the bus line 15.

  Between time T5 and time T7, an SDRAM busy signal is output from the busy timing adjustment circuit 40 to the SDRAM access request mask circuit 37 as shown in FIG. Therefore, the SDRAM use request signal from the image processing control circuit 33 continuously output to the SDRAM access request mask circuit 37 from T4 (FIG. 7 (f)) is the SDRAM access request mask circuit 37 between T5 and T7. It is masked with. Therefore, the SDRAM use request signal from the image processing control circuit 33 is not output to the SDRAM access arbitration circuit 38 (FIG. 7 (g)). Therefore, when the SDRAM busy signal is output from the busy timing adjustment circuit 40 to the SDRAM access request mask circuit 37, the use permission of the bus line 15 from the SDRAM access arbitration circuit 38 is not given to the image processing control circuit 33.

  As shown in FIG. 7B, the SDRAM use request signal is output again from the recording control circuit 35 at T7. The output SDRAM use request signal is not masked by the SDRAM access request mask circuit 37 even if the SDRAM busy signal is output from the busy timing adjustment circuit 40. This is because the recording control circuit 35 is set to “1” indicating that immediacy is high in the mask register 50 (see FIG. 4). Therefore, the SDRAM use request signal output from the recording control circuit 35 is output from the SDRAM access request mask circuit 37 to the SDRAM access arbitration circuit 38 as shown in FIG. 7C (at time T7).

  From time T7 to time T9, the use permission of the bus line 15 is given to the recording control circuit 35 from the SDRAM access arbitration circuit 38 as in the time T3 to T6. Accordingly, the recording control circuit 35 can access the SDRAM 13 while occupying the bus line 15.

  One clock before the internal clock signal (FIG. 7 (a)) at which the access to the SDRAM 13 by the recording control circuit 35 is completed, as shown in FIG. 7 (e), from the SDRAM access arbitration circuit 38 to the recording control circuit. An SDRAM use request acceptance completion signal indicating that access to the SDRAM 13 is completed is output to 35 (at time T8). As a result, as shown in FIG. 7B, the recording control circuit 35 stops outputting the SDRAM use request signal to the SDRAM access request mask circuit 37 (at time T9). Along with this, as shown in FIG. 7C, the SDRAM use request signal from the recording control circuit 35 input to the SDRAM access arbitration circuit 38 is also stopped (T9).

  As shown in FIG. 7E, when an SDRAM use request acceptance completion signal indicating completion of access to the SDRAM 13 is output from the SDRAM access arbitration circuit 38 to the recording control circuit 35 (at time T8), SDRAM access arbitration is performed. The circuit 38 outputs an access request arbitration signal indicating that the use permission arbitration of the bus line 15 is possible as shown in FIG. 7 (k) to the busy timing adjustment circuit 40 (time T8).

  As shown in FIG. 7B, the SDRAM use request signal output from the recording control circuit 35 is not output after T9. However, as shown in FIG. 7J, the high access frequency detection signal is output from the SDRAM access frequency detection circuit 41 to the busy timing adjustment circuit 40 until time T10. Therefore, the SDRAM busy signal is output from the busy timing adjustment circuit 40 as shown in FIG. Therefore, during the period from time T9 to time T10, the SDRAM use request signal output from the image processing control circuit 33 is masked by the SDRAM access request mask circuit 37 and sent to the SDRAM access arbitration circuit 38 as shown in FIG. Not entered.

  After the time T10 has elapsed, as shown in FIG. 7J, the SDRAM access frequency detection circuit 41 stops the output of the high access frequency detection signal indicating that the access frequency to the SDRAM 13 is high. Accordingly, as shown in FIG. 7L, the output of the SDRAM busy signal output from the busy timing adjustment circuit 40 to the SDRAM access request mask circuit 37 is also stopped. As a result, the SDRAM access request mask circuit 37 finishes masking the SDRAM use request signal output from the image control circuit 33 (at time T10).

  Then, the SDRAM use request signal from the image processing control circuit 33 that has been continuously output from T4 (FIG. 7F) is output from the SDRAM access request mask circuit 37 to the SDRAM access arbitration circuit 38 (FIG. 7). 7 (g), at T10).

  When an SDRAM use request signal is input from the image processing control circuit 33 to the SDRAM access arbitration circuit 38, the SDRAM access arbitration circuit 38 performs arbitration and grants the use permission of the bus line 15 to the image processing control circuit 33 (at time T10). To T12 o'clock). The image processing control circuit 33 to which use permission of the bus line 15 is given occupies the bus line 15 and accesses the SDRAM 13 (from T10 to T12). From time T10 to time T12, the image processing control circuit 33 occupies the bus line 15 and accesses the SDRAM 13, so that the SDRAM access arbitration circuit 38 is connected to the bus line 15 as shown in FIG. In order to indicate that the use permission arbitration is impossible, the output of the access request arbitration signal to the busy timing adjustment circuit 40 is stopped (from T10 to T11).

  When one access to the SDRAM 13 by the image processing control circuit 33 is completed, an SDRAM indicating that access to the SDRAM 13 from the SDRAM access arbitration circuit 38 to the image processing control circuit 33 is completed as shown in FIG. A use request acceptance completion signal is output. When this SDRAM use request acceptance completion signal is output twice (at T11), as shown in FIG. 7H, the continuous transfer counter of the image processing control circuit 33 set when the SDRAM use request signal is output. The value of 33a1 is “0 (zero)”. As a result, as shown in FIG. 7F, the image processing control circuit 33 stops outputting the SDRAM use request signal to the SDRAM access request mask circuit 37 (at time T12). Accordingly, as shown in FIG. 7G, the SDRAM use request signal from the image processing control circuit 33 input to the SDRAM access arbitration circuit 38 is also stopped (T12).

  As shown in FIG. 7 (i), when an SDRAM use request acceptance completion signal indicating that access to the SDRAM 13 is completed from the SDRAM access arbitration circuit 38 to the image processing control circuit 33 is output twice (at time T11). ), The SDRAM access arbitration circuit 38 outputs an access request arbitration signal indicating that the use permission arbitration of the bus line 15 is possible to the busy timing adjustment circuit 40 as shown in FIG. 7 (k) (T11). Time).

  As shown in FIG. 7 (g), an SDRAM use request signal is output from the image processing control circuit 33 to the SDRAM access arbitration circuit 38 from T11 to T12, but during this T11 to T12, The SDRAM access arbitration circuit 38 removes the SDRAM use request signal output from the image processing control circuit 33 and grants the use permission of the bus line 15.

  As described above, in the present embodiment described above, an access frequency high detection signal indicating that the SDRAM access frequency detection circuit 41 has a high access frequency to the SDRAM 13 is output, and the SDRAM access arbitration circuit 38 outputs the bus line 15. When an access request arbitration signal indicating that use permission arbitration is possible is output, the busy timing adjustment circuit 40 indicates to the SDRAM access request mask circuit 37 that the SDRAM 13 is frequently accessed. Is output.

  When the SDRAM busy signal is output from the busy timing adjustment circuit 40, the SDRAM access request mask circuit 37 masks the SDRAM use request signal output from the image processing control circuit 33 with low immediacy. On the other hand, the SDRAM use request signal from the recording control circuit 35 with high immediacy is not masked even if the SDRAM busy signal is output from the busy timing adjustment circuit 40 and is input to the SDRAM access arbitration circuit 38. Then, the SDRAM access arbitration circuit 38 grants the use permission of the bus line 15 to the recording control circuit 35.

  Thereby, the recording control circuit 35 can occupy the bus line 15 and preferentially access the SDRAM 13. Therefore, when the SDRAM busy signal is output from the busy timing adjustment circuit 40, that is, when the frequency of access to the SDRAM 13 is high, the use of the bus is given priority to the recording control circuit 35. it can. Therefore, the recording control circuit 35 can preferentially access the SDRAM 13.

  In the above-described embodiment, the SDRAM access request mask circuit 37 is provided with the mask register 50. Therefore, when the SDRAM busy signal is output from the busy timing adjustment circuit 40, the SDRAM access request mask circuit. A control circuit with low immediacy masked by 37 can be set. Therefore, even when it is desired to change the immediacy of the control circuit in accordance with the usage mode of the multifunction peripheral device, the immediacy can be freely set by the mask register 50.

  Furthermore, in the above-described embodiment, the busy timing adjustment circuit 40 is configured by an AND circuit. Therefore, even if an access frequency high detection signal is output from the SDRAM access frequency detection circuit 41, the SDRAM access arbitration circuit 38. If no access request arbitration signal indicating that use permission arbitration of the bus line 15 is possible is output from the SDRAM access request mask circuit 37, no SDRAM busy signal is output. In other words, the SDRAM access arbitration circuit 38 is connected to any one of the control circuits (the bus controller circuit 31, the USB I / F control circuit 32, the image processing control circuit 33, the user I / F control circuit 34, the recording control circuit 35, or the reading). When the use permission of the bus line 15 is given to the control circuit 36), even if the high access frequency detection signal is output from the SDRAM access frequency detection circuit 41, the busy timing adjustment circuit 40 does the SDRAM access request mask circuit 37. The SDRAM busy signal is not output. Therefore, although the SDRAM access arbitration circuit 38 grants the use permission of the bus line 15 to any one of the control circuits, the SDRAM busy request signal is output to the SDRAM access request mask circuit 37, and the SDRAM access request mask is output. The circuit 37 stops the SDRAM use request signal output from one control circuit to which the use permission of the bus line 15 is given to the SDRAM access arbitration circuit 38, and the use permission of the bus line 15 of the SDRAM access arbitration circuit 38. Granting will not be interrupted. Therefore, the permission to use the bus line 15 of the SDRAM access arbitration circuit 38 can be reliably executed.

  Next, a second embodiment will be described with reference to FIGS. FIG. 8 shows an electrical configuration of the SDRAM access request mask circuit 60 in the second embodiment. In addition, about the part same as 1st Embodiment, the same code | symbol is attached | subjected and the description shall be abbreviate | omitted. As shown in FIG. 8, the SDRAM access request mask circuit 60 in the ASIC 20 in the second embodiment is configured such that the mask register 61 can store a 2-bit value. Accordingly, the SDRAM busy signal input from the busy timing adjustment circuit 40 to the SDRAM access request mask circuit 60 of the second embodiment is also a 2-bit signal. The high access frequency detection signal output from the SDRAM access frequency detection circuit 41 to the busy timing adjustment circuit 40 is also a 2-bit signal.

  Therefore, the SDRAM access request mask circuit 60 according to the second embodiment includes each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control). The SDRAM use request signal output from the circuit 35 and the read control circuit 36) can be masked more finely. In this respect, the ASIC 20 of the second embodiment is different from the first embodiment.

  FIG. 8 is a block diagram showing an electrical configuration of the SDRAM access request mask circuit 60. The SDRAM access request mask circuit 60 mainly includes a mask register 61, mask level comparison circuits 62a to 62f, NOT circuits 63a to 63f which are logical negation circuits, and AND circuits 64a to 64f which are logical product circuits. ing.

  First, the SDRAM busy signal output to the SDRAM access request mask circuit 60 will be described. There are three types of SDRAM busy signals output from the busy timing adjustment circuit 40: “00”, “01”, and “10”. Note that the value of the SDRAM busy signal is the same value as the high access frequency detection signal output from the SDRAM access frequency detection circuit 41.

  When the SDRAM busy signal is not output from the busy timing adjustment circuit 40 (when the value of the SDRAM busy signal is “00”), each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit) 33, the frequency of access to the SDRAM 13 from the user I / F control circuit 34, the recording control circuit 35, and the reading control circuit 36) is low. Further, when the output SDRAM busy signal is “01”, it indicates that the frequency of access from each control circuit to the SDRAM 13 is moderate. Further, when the output SDRAM busy signal is “10”, it indicates that the frequency of access from each control circuit to the SDRAM 13 is high. A method for determining the SDRAM busy signal will be described with reference to FIG.

  The mask register 61 is a mask for each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and reading control circuit 36). This is a register for storing a value to be output to one of the input terminals of the level comparison circuits 62a to 62f. The mask register 61 outputs 6 sets of 2-bit signals connected to one of the input terminals of the mask level comparison circuits 62a to 62f. Here, the value input to one of the input terminals of the mask level comparison circuits 62a to 62f is a fixed value unless the value stored in the mask register 61 is rewritten.

  Here, the values stored in the mask register 61 will be described with reference to FIG. FIG. 9 is a list of values stored in the mask register 61. The values stored in the mask register 61 are the control circuits (the bus controller circuit 31, the USB I / F control circuit 32, the image processing control circuit 33, the user I / F control circuit 34, the recording control circuit 35, and the reading control circuit). 36) is set every time. There are three types of values stored in the mask register 61: “01”, “10”, and “11”.

  When the SDRAM use request signal of the control circuit set to “01” in the mask register 61 is low in immediacy, the SDRAM busy signal is not output from the busy timing adjustment circuit 40 (the value of the SDRAM busy signal is “00”). (If any) is not masked by the SDRAM access request mask circuit 60. Further, the SDRAM use request signal of the control circuit set to “10” in the mask register 61 indicates that the immediacy is intermediate and the frequency of access from the busy timing adjustment circuit 40 to the SDRAM 13 is intermediate. When the busy signal “01” is output or when the SDRAM busy signal is not output from the busy timing adjustment circuit 40 (when the value of the SDRAM busy signal is “00”), the SDRAM access request mask circuit 60 Not masked. Further, the SDRAM use request signal of the control circuit set to “11” in the mask register 61 is an SDRAM busy signal indicating that the frequency of access from the busy timing adjustment circuit 40 to the SDRAM 13 is high, assuming that immediacy is high. Even when “10” is output, it is not masked by the SDRAM access request mask circuit 60.

  In the second embodiment, the bus controller circuit 31 and the USB I / F control circuit 32 belong to the same immediacy processing group, and “01” indicating that immediacy is low is set in the mask register 61. Is done. In addition, the image processing control circuit 33 and the user I / F control circuit 34 belong to the same immediacy processing group, and “10” indicating that immediacy is medium is set in the mask register 61. Furthermore, “11” indicating that the recording control circuit 35 and the reading control circuit 36 belong to the same immediacy processing group and the immediacy is high is set in the mask register 61.

  Thus, since the SDRAM access request mask circuit 60 is provided with the mask register 61, when the SDRAM busy signal is output from the busy timing adjustment circuit 40 in three stages, it is masked by the SDRAM access request mask circuit 60. The control circuit can be set in three stages. Therefore, even when it is desired to change the immediacy of the control circuit according to the usage mode of the multifunction peripheral device, the immediacy can be set finely and freely by the mask register 61.

  Returning to the description of FIG. The mask level comparison circuits 62 a to 62 f are circuits that compare the value of the mask register 61 with the value of the SDRAM busy signal output from the busy timing adjustment circuit 40. Mask level comparison circuits 62a to 62f are configured by combining AND circuits, OR circuits, and NOT circuits.

  One of the input terminals of the mask level comparison circuits 62a to 62f is connected to the mask register 61 as described above. The other input terminals of the mask level comparison circuits 62 a to 62 f are connected to the busy timing adjustment circuit 40. The busy timing adjustment circuit 40 is connected to the other input terminal of the mask level comparison circuits 62a to 62f.

  The mask level comparison circuits 62a to 62f have the values of the mask register 61 input to one of the input terminals of the mask level comparison circuits 62a to 62f and the SDRAM busy input to the other of the input terminals of the mask level comparison circuits 62a to 62f. The value output from the output terminals of the mask level comparison circuits 62a to 62f is switched by comparing with the value of the signal.

  If the value of the mask register 61 input to one of the input terminals of the mask level comparison circuits 62a to 62f is larger than the value of the SDRAM busy signal input to the other input terminal of the mask level comparison circuits 62a to 62f, the mask The level comparison circuits 62a to 62f output “0 (zero)” from the output terminals. On the other hand, when the value of the mask register 61 input to one of the input terminals of the mask level comparison circuits 62a to 62f is equal to or less than the value of the SDRAM busy signal input to the other of the input terminals of the mask level comparison circuits 62a to 62f, The mask level comparison circuits 62a to 62f output “1” from the output terminals.

  NOT circuits 63a to 63f are connected to the output terminals of the mask level comparison circuits 62a to 62f, respectively. The NOT circuits 63a to 63f are connected to one of the input terminals of the AND circuits 64a to 64f, respectively. Therefore, the values input to the AND circuits 64a to 64f are switched depending on the values output from the mask level comparison circuits 62a to 62f.

  The other input terminals of the AND circuits 64a to 64f are respectively connected to control circuits (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and A read control circuit 36) is connected. Therefore, for example, when an SDRAM use request signal is output from the bus controller circuit 31, the SDRAM use request signal is input to the other input terminal of the AND circuit 64a.

  The operation of the SDRAM access request mask circuit 60 will be described. Here, in FIG. 9, when the SDRAM use request signal is output from the bus controller circuit 31 that is set to have low immediacy (set to “01” in the mask register 61), the immediacy is moderate. When the SDRAM use request signal is output from the set image processing control circuit 33 (set to “10” in the mask register 61), and when the immediacy is set high (“11” is set in the mask register 61. The operation of the SDRAM access request mask circuit 60 when the SDRAM use request signal is output from the set recording control circuit 35 is illustrated.

  The operation when the SDRAM use request signal is output from the USB I / F control circuit 32 is the same as the operation when the SDRAM use request signal is output from the bus controller circuit 31 of the same processing group described below. . The operation when the SDRAM use request signal is output from the user I / F control circuit 34 is the same as the operation when the SDRAM use request signal is output from the image processing control circuit 33 of the same processing group described later. . Further, the operation when the SDRAM use request signal is output from the read control circuit 36 is the same as the operation when the SDRAM use request signal is output from the recording control circuit 35 of the same processing group described later.

  First, the operation when the SDRAM use request signal is output from the bus controller circuit 31 will be described. When the SDRAM busy signal is not output from the busy timing adjustment circuit 40, “00” is input to the other input terminal of the mask level comparison circuit 62a. On the other hand, the value “01” stored in the mask register 61 is input to one of the input terminals of the mask level comparison circuit 62a. At this time, since one value of the input terminal of the mask level comparison circuit 62a is larger than the other value of the input terminal of the mask level comparison circuit 62a, "0 (zero)" is output from the output terminal of the mask level comparison circuit 62a. The value is input to the NOT circuit 63a. Then, “1” is input to one of the input terminals of the AND circuit 64a.

  Since the SDRAM use request signal is input to the other input terminal of the AND circuit 64a, its value is “1”. Therefore, “1” is output from the output terminal of the AND circuit 64a. That is, an SDRAM use request signal is output from the output terminal of the AND circuit 64a, and the output SDRAM use request signal is input to the SDRAM access arbitration circuit 38.

  On the other hand, when the SDRAM busy signal is output from the busy timing adjustment circuit 40 and the value of the SDRAM busy signal is “01” or “10”, the other input terminal of the mask level comparison circuit 62a has “01”. Alternatively, “10” is input. On the other hand, the value “01” stored in the mask register 61 is input to one of the input terminals of the mask level comparison circuit 62a. At this time, since one value of the input terminal of the mask level comparison circuit 62a is equal to or less than the other value of the input terminal of the mask level comparison circuit 62a, "1" is output from the output terminal of the mask level comparison circuit 62a. The value is input to the NOT circuit 63a. Then, “0 (zero)” is input to one of the input terminals of the AND circuit 64a.

  Therefore, the SDRAM use request signal is input to the other input terminal of the AND circuit 64a, and even if the other input terminal is “1”, the output terminal of the AND circuit 64a outputs “0 (zero)”. Is output. That is, the SDRAM use request signal is not output from the output terminal of the AND circuit 64a, and the SDRAM use request signal input to the other input terminal of the AND circuit 64a is masked. Accordingly, when the SDRAM busy signal is output from the busy timing adjustment circuit 40 and the value of the SDRAM busy signal is “01” or “10”, the SDRAM use request signal input to the other input terminal of the AND circuit 64a. Are not output to the SDRAM access arbitration circuit 38.

  Next, an operation when an SDRAM use request signal is output from the image processing control circuit 33 will be described. When the SDRAM busy signal is not output from the busy timing adjustment circuit 40 or when the SDRAM busy signal is output from the busy timing adjustment circuit 40 and the value of the SDRAM busy signal is “01”, the mask level comparison circuit 62c “00” or “01” is input to the other input terminal. On the other hand, the value “10” stored in the mask register 61 is input to one of the input terminals of the mask level comparison circuit 62 c. At this time, since one value of the input terminal of the mask level comparison circuit 62c is larger than the other value of the input terminal of the mask level comparison circuit 62c, “0 (zero)” is output from the output terminal of the mask level comparison circuit 62c. The value is input to the NOT circuit 63c. Then, “1” is input to one of the input terminals of the AND circuit 64c.

  Since the SDRAM use request signal is input to the other input terminal of the AND circuit 64c, the other input terminal is “1”. Therefore, “1” is output from the output terminal of the AND circuit 64c. That is, the SDRAM use request signal is output from the output terminal of the AND circuit 64c, and the output SDRAM use request signal is input to the SDRAM access arbitration circuit 38.

  On the other hand, when the SDRAM busy signal is output from the busy timing adjustment circuit 40 and the value of the SDRAM busy signal is “10”, “10” is input to the other input terminal of the mask level comparison circuit 62c. . On the other hand, the value “10” stored in the mask register 61 is input to one of the input terminals of the mask level comparison circuit 62 c. At this time, since one value of the input terminal of the mask level comparison circuit 62c is less than or equal to the other value of the input terminal of the mask level comparison circuit 62c, “1” is output from the output terminal of the mask level comparison circuit 62c. The value is input to the NOT circuit 63c. Then, “0 (zero)” is input to one of the input terminals of the AND circuit 64c.

  Therefore, the SDRAM use request signal is input to the other input terminal of the AND circuit 64c, and even if the other input terminal is “1”, the output terminal of the AND circuit 64c outputs “0 (zero)”. Is output. That is, the SDRAM use request signal is not output from the output terminal of the AND circuit 64c, and the SDRAM use request signal input to the other input terminal of the AND circuit 64c is masked. Therefore, when the SDRAM busy signal is output from the busy timing adjustment circuit 40 and the value of the SDRAM busy signal is “10”, the SDRAM use request signal input to the other input terminal of the AND circuit 64c is the SDRAM access arbitration. It is not output to the circuit 38.

  Finally, the operation when the SDRAM use request signal is output from the recording control circuit 35 will be described. The SDRAM use request signal output from the recording control circuit 35 is masked by the SDRAM access request mask circuit 37 regardless of whether the SDRAM busy signal is output from the busy timing adjustment circuit 40 or not. Never happen. The reason for this will be described. The value “11” stored in the mask register 61 is input to one of the input terminals of the mask level comparison circuit 62 e. Then, an SDRAM busy signal is output from the busy timing adjustment circuit 40, and even if “10” or “01” is input to the other input terminal of the mask level comparison circuit 62e, one of the input terminals of the mask level comparison circuit 62e. Is larger than the other value of the input terminal of the mask level comparison circuit 62b. Even if no SDRAM busy signal is output from the busy timing adjustment circuit 40 and “00” is input to the other input terminal of the mask level comparison circuit 62e, one value of the input terminal of the mask level comparison circuit 62e is It becomes larger than the other value of the input terminal of the mask level comparison circuit 62e. Therefore, “0 (zero)” is output from the output terminal of the mask level comparison circuit 62e, and the value is input to the NOT circuit 63e. Then, “1” is input to one of the input terminals of the AND circuit 64e.

  As a result, when the SDRAM use request signal is output from the recording control circuit 35 and the other input terminal of the AND circuit 64e becomes “1”, the output terminal of the AND circuit 64e becomes “1”. Therefore, when the SDRAM use request signal is output from the recording control circuit 35, the SDRAM use request signal is output regardless of whether the SDRAM busy signal is output from the busy timing adjustment circuit 40 or not. The data is not masked by the SDRAM access request mask circuit 37, but is output to the SDRAM access arbitration circuit 38.

  In this way, the SDRAM access request mask circuit 60 includes each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and The mask of the SDRAM use request signal output from the processing group to which the read control circuit 36) belongs can be switched according to the value of the SDRAM busy signal output from the busy timing adjustment circuit 40.

  Next, the main process executed by the SDRAM access frequency detection circuit 41 will be described with reference to FIG. FIG. 10 is a flowchart showing a main process executed by the SDRAM access frequency detection circuit 41. The main process is a process of updating the value of the period counter and the value of the SDRAM access counter and determining the output of the 2-bit high access frequency detection signal, and when the operation of the SDRAM access frequency detection circuit 41 is permitted. This process is repeatedly executed.

  When the power supply of the multifunction peripheral device is turned on, the CPU 30 performs initialization processing of the SDRAM access frequency detection circuit 41 (S21). The initialization of the SDRAM access frequency detection circuit 41 means that “3F (hexadecimal)” (see FIG. 5) is set in the period setting register 41a1, and the first access count threshold “20 (hexadecimal) is set in the SDRAM access count threshold register 41a2. ) ”And the second access frequency threshold value“ 2F (hexadecimal number) ”are set to allow operation (S21). Thereafter, both the value of the period counter and the value of the SDRAM access counter are initialized to “0 (zero)” (S22).

  Next, it is determined whether the value of the period counter is the same as the value of the period setting register 41a1 (S23). If the value of the period counter is not the same as the value of the period setting register 41a1 (S23: No), the value of the period counter is incremented by 1 (S24). Then, it is determined whether an SDRAM access detection signal is input from the SDRAM controller circuit 39 (S25). If it is determined that an SDRAM access detection signal is input (S25: Yes), the value of the SDRAM access counter is incremented by 1 (S26), and the process returns to S23. On the other hand, if it is determined in the process of S25 that no SDRAM access detection signal is input (S25: No), the process returns to S23 without incrementing the value of the SDRAM access counter.

  In the process of S23, if the value of the period counter is the same as the value of the period setting register 41a1 (S23: Yes), the value of the SDRAM access counter is the value of the first access count threshold value stored in the SDRAM access count threshold register 41a2. The following is determined (S27). If it is determined that the value of the SDRAM access counter is equal to or less than the value of the first access count threshold value stored in the SDRAM access count threshold register 41a2 (S27: Yes), the access frequency high detection signal is not output (S28, access frequency). The high detection signal is “00”).

  On the other hand, if it is determined that the value of the SDRAM access counter is larger than the value of the first access count threshold stored in the SDRAM access count threshold register 41a2 (S27: No), the value of the SDRAM access counter is the SDRAM access count threshold register 41a2. It is determined whether the value is equal to or smaller than the second access count threshold value stored in (S29). When it is determined that the value of the SDRAM access counter is equal to or smaller than the value of the second access frequency threshold value stored in the SDRAM access frequency threshold value register 41a2 (S29: Yes), the high access frequency detection signal is output as “01” (S30). .

  On the other hand, if it is determined that the value of the SDRAM access counter is larger than the value of the second access count threshold value stored in the SDRAM access count threshold register 41a2 (S29: No), the access frequency high detection signal is output as “10”. (S31). When the process in any of S28, S30, or S31 is completed, both the value of the period counter and the value of the SDRAM access counter are set to “0 (zero)” (S32), and the process returns to S23.

  Through the above processing, the value of the period counter and the value of the SDRAM access counter are updated, and the output determination of the access frequency high detection signal is performed. In this manner, the SDRAM access frequency detection circuit 41 includes each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and Depending on the frequency of access from the read control circuit 36) to the SDRAM 13, the high access frequency detection signal output to the busy timing adjustment circuit 40 can be finely divided into three stages. Therefore, the SDRAM busy signal output from the busy timing adjustment circuit 40 to the SDRAM access request mask circuit 37 can be finely divided into three stages according to the frequency of access to the SDRAM 13.

  As described above, the present invention has been described based on each embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be easily made without departing from the gist of the present invention. Can be inferred.

  For example, in the second embodiment described above, the mask register 61 of the SDRAM access request mask circuit 60 stores three levels of values. The SDRAM busy signal output from the busy timing adjustment circuit 40 to the SDRAM access request mask circuit 60 is also in three stages. However, the present invention is not limited to this. For example, six stages of values may be stored in the mask register 61 of the SDRAM access request mask circuit 60, and the SDRAM busy signal output from the busy timing adjustment circuit 40 may be of six stages. In this case, each control circuit (bus controller circuit 31, USB I / F control circuit 32, image processing control circuit 33, user I / F control circuit 34, recording control circuit 35, and reading control circuit 36) is masked. By making the values stored in the register 61 different, the SDRAM access request mask circuit 60 masks the SDRAM use request signal in six steps in accordance with the six steps SDRAM busy signal output from the busy timing adjustment circuit 40. Can be executed.

It is a block diagram which shows the electric constitution of the control part which controls operation | movement of a multifunction peripheral device. It is a block diagram which shows the electrical structure of ASIC. 3 is a block diagram showing an electrical configuration of an SDRAM access request mask circuit. FIG. It is a list of values stored in a mask register. FIG. 5 is a timing chart of an internal clock signal, a period counter value, an SDRAM access counter value, and a high access frequency detection signal. It is the flowchart which showed the main process performed with the SDRAM access frequency detection circuit. FIG. 5 is a timing chart of processing executed in an ASIC when an SDRAM use request signal is output from a recording control circuit and an image processing control circuit. 10 shows an electrical configuration of an SDRAM access request mask circuit in a second embodiment. It is a list of values stored in the mask register in the second embodiment. It is the flowchart which showed the main process performed with the SDRAM access frequency detection circuit in 2nd Embodiment.

Explanation of symbols

13 SDRAM (memory means)
15 Bus line 20 ASIC (communication control device)
31 Bus controller circuit (control means)
32 USB I / F control circuit (control means)
33 Image processing control circuit (control means)
34 User I / F control circuit (control means)
35 Recording control circuit (control means)
36 Reading control circuit (control means)
37 SDRAM access request mask circuit (request signal prohibition means)
38 SDRAM access arbitration circuit (bus arbitration means, arbitration execution signal output means)
40 Busy timing adjustment circuit (part of access concentrated signal output means, part of access concentrated signal stage output means, timing adjustment output means)
41 SDRAM access frequency detection circuit (count means, access frequency calculation means, part of access concentration signal output means, part of access concentration signal stage output means)
50 Mask register (input prohibition setting means)
61 Mask register (input prohibition setting means, rank stage setting means)
62a to 62f Mask level comparison circuit (comparison means)

Claims (4)

Storage means capable of writing or reading; and
A bus line for transmitting information to be written to the storage means or information to be read from the storage means;
A plurality of control means for outputting a bus use request signal for occupying the bus line in order to access the storage means;
When a plurality of bus use request signals outputted from the plurality of control means are inputted simultaneously, the bus use request signals inputted simultaneously are occupied by occupying the bus line based on a preset priority. A bus arbitration unit that grants permission to access the storage unit to one of the plurality of control units that output the bus use request signal;
One control means to which the permission is given from the bus arbitration means occupies the bus line, accesses the storage means, and inputs and outputs information written to the storage means or information read from the storage means A device,
Counting means for counting the number of accesses to the storage means from the plurality of control means;
An access frequency calculating means for detecting the number of accesses counted by the counting means and calculating an access frequency to the storage means within a predetermined time;
An access concentration signal output means for outputting an access concentration signal indicating that access to the storage means is concentrated according to the access frequency calculated by the access frequency calculation means;
Request signal prohibition for prohibiting input of a bus use request signal output from a specific control means among the plurality of control means to the bus arbitration means when an access concentration signal is output by the access concentration signal output means And a communication control device. The request signal prohibiting means includes
When an access concentration signal is output from the access concentration signal output means, it is possible to set a specific control means that prohibits input to the bus arbitration means from among the bus use request signals output from the plurality of control means 2. The communication control apparatus according to claim 1, further comprising an input prohibition setting unit. The access concentration signal output means includes:
Access concentration signal stage output means for outputting an access concentration signal indicating that access to the storage means is concentrated as a plurality of stages of access concentration signals according to the access frequency calculated by the access frequency calculation means. ,
The input prohibition setting means includes
The control means is divided into a plurality of processing groups, and has a rank level setting means for setting the ranks for occupying the bus line and accessing the storage means in a plurality of stages for each of the plurality of processing groups,
The request signal prohibiting means includes
Comparing means for comparing the stage of the access concentration signal output from the access concentration signal stage output means and the stage of the processing group to which the plurality of control means set by the order stage setting means belong,
According to the comparison result by the comparison means, the bus use request signal output from the control means belonging to a specific processing group among the plurality of control means is prohibited from being input to the bus arbitration means. The communication control apparatus according to claim 2. The bus arbitration means is
An arbitration execution signal output means for outputting an arbitration execution signal indicating a state in which the permission arbitration to the plurality of control means can be executed;
Timing adjustment output means for outputting the access concentration signal output from the access concentration signal output means to the request signal prohibition means when the arbitration execution signal is output from the arbitration execution signal output means; The communication control device according to any one of claims 1 to 3, wherein

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