JP2007527108A - 応力が加わる系のための基板アセンブリ - Google Patents
応力が加わる系のための基板アセンブリ Download PDFInfo
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- JP2007527108A JP2007527108A JP2006518168A JP2006518168A JP2007527108A JP 2007527108 A JP2007527108 A JP 2007527108A JP 2006518168 A JP2006518168 A JP 2006518168A JP 2006518168 A JP2006518168 A JP 2006518168A JP 2007527108 A JP2007527108 A JP 2007527108A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/03—Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
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- Crystals, And After-Treatments Of Crystals (AREA)
- Measurement Of Force In General (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【選択図】図3B
Description
第2基板の組み合わせ面および/または組み合わせ面とは反対側の第2基板の面から、第2基板にモチーフが形成、作製または蝕刻されている構造を提供する。
第1材料によって構成された第1基板と、第2材料によって構成された第2基板とを、先に述べたように、共に組み合わせる工程と、
基板の一方の一部を分離または分割して、他方の基板上に膜を残す工程と、を含む方法を提供する。
この図は、例えば石英基板(膨張係数5×10−7K−1)または砒化ガリウム(膨張係数6×10−6K−1)、およびシリコン基板(膨張係数2.5×10−6K−1)といった、異なる熱膨張係数c0およびc2を有する、2つの基板40,42を共に組み合わせることに関係している。
Claims (20)
- 第1熱膨張係数および前記第1熱膨張係数とは異なる第2熱膨張係数をそれぞれ有し、且つ第1および第2組み合わせ面(81,83)をそれぞれ有する、膜と基板(85,82)とが組み合わされてなり、
前記基板(82)にモチーフが形成され、
前記モチーフは、前記第1および第2組み合わせ面と平行な平面において、弾力性または柔軟性がある、構造。 - 前記モチーフは、組み合わせ表面から前記基板に蝕刻されている、請求項1記載の構造。
- 前記モチーフは、組み合わせ表面(83)とは反対側の面から前記基板に蝕刻されている、請求項1または請求項2記載の構造。
- 前記基板の組み合わせ表面(83)から蝕刻された前記モチーフは、前記表面で少なくとも部分的に塞がれている、請求項1ないし請求項3のいずれか1項に記載の構造。
- 前記モチーフは、鋲、トレンチまたは鋸の切り口の形状である、請求項1ないし請求項4のいずれか1項に記載の構造。
- 前記膜および前記基板が、雰囲気温度において少なくとも10%異なる熱膨張係数を有する、請求項1ないし請求項5のいずれか1項に記載の構造。
- 前記基板が、以下の材料:シリコン、石英、サファイア、炭化ケイ素およびガラスの1つによって構成されている、請求項1ないし請求項6のいずれか1項に記載の構造。
- 前記膜が、以下の材料:砒化ガリウム、サファイア、ゲルマニウム、窒化ガリウム、シリコン、シリコン−ゲルマニウム(SiGe)、燐化インジウム、窒化アルミニウムおよび炭化ケイ素の1つによって構成されている、請求項1ないし請求項7のいずれか1項に記載の構造。
- 前記膜が、薄層(85)の形状である、請求項1ないし請求項8のいずれか1項に記載の構造。
- 前記薄層の厚さが、0.1μm〜2μmの範囲にある、請求項9記載の構造。
- ヘテロエピタキシーによって材料を堆積させるためのデバイスであって、請求項1ないし請求項10のいずれか1項に記載の構造を含む、デバイス。
- 第1材料から形成された膜を第2材料から形成された基板上に製造するための方法であって、
それぞれ第1熱膨張係数および前記第1熱膨張係数とは異なる第2熱膨張係数を有し、且つそれぞれ第1および第2組み合わせ面(81,83)を有する、第1および第2基板(80,82)を共に組み合わせる工程と、
前記基板の一方の一部を分離し、または前記基板の一方を減厚して、他方の基板上に膜(85)を残す工程と、を含み、
前記第2基板(82)にはモチーフが形成されており、前記モチーフは、前記第1および第2組み合わせ面と平行な平面において、弾力性または柔軟性がある、方法。 - 前記2つの基板が、異なる熱膨張係数を有する、請求項12記載の方法。
- 前記2つの共に組み合わされた基板の組が、当該方法の期間内に温度上昇の段階を経る、請求項12または請求項13記載の方法。
- 前記2つの基板が、ウェーハ結合(wafer bonding)、分子接触(molecular contact)または接着性結合(adhesive bonding)によって、共に組み合わされている、請求項12ないし請求項14のいずれか1項に記載の方法。
- 前記第1基板(80)が、脆弱領域(87)を含む、請求項12ないし請求項14のいずれか1項に記載の方法。
- 前記第2基板(80)が、脆弱領域(87)を含む、請求項12ないし請求項14のいずれか1項に記載の方法。
- 前記脆弱領域が、多孔質層の形成によって作製されている、請求項17記載の方法。
- 前記脆弱領域が、前記第1基板にイオン注入を行うことによって作製されている、請求項16または請求項17記載の方法。
- 前記基板の一方の分離または減厚が、研磨またはエッチングによって実施される、請求項12記載の方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0308447A FR2857502B1 (fr) | 2003-07-10 | 2003-07-10 | Substrats pour systemes contraints |
| PCT/EP2004/007632 WO2005006419A2 (en) | 2003-07-10 | 2004-07-08 | Substrate assembly for stressed systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007527108A true JP2007527108A (ja) | 2007-09-20 |
| JP4576381B2 JP4576381B2 (ja) | 2010-11-04 |
Family
ID=33522933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006518168A Expired - Lifetime JP4576381B2 (ja) | 2003-07-10 | 2004-07-08 | 応力が加わる系のための基板アセンブリ |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US7067393B2 (ja) |
| EP (1) | EP1644967A2 (ja) |
| JP (1) | JP4576381B2 (ja) |
| KR (1) | KR100863081B1 (ja) |
| CN (1) | CN1816897B (ja) |
| FR (1) | FR2857502B1 (ja) |
| TW (1) | TWI310212B (ja) |
| WO (1) | WO2005006419A2 (ja) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012519974A (ja) * | 2009-03-09 | 2012-08-30 | ソイテック | 熱膨張係数が局所的に適合するヘテロ構造の生成方法 |
| KR20180017174A (ko) * | 2015-07-17 | 2018-02-20 | 소이텍 | 기판을 제조하기 위한 방법 |
| US11780732B2 (en) | 2018-12-17 | 2023-10-10 | Tokai Carbon Korea Co., Ltd. | Carbonated tantalum coating material |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100652395B1 (ko) * | 2005-01-12 | 2006-12-01 | 삼성전자주식회사 | 다이-휨이 억제된 반도체 소자 및 그 제조방법 |
| US7374957B2 (en) * | 2005-07-11 | 2008-05-20 | Asml Netherlands B.V. | Method of calibrating or qualifying a lithographic apparatus or part thereof, and device manufacturing method |
| US20070090156A1 (en) * | 2005-10-25 | 2007-04-26 | Ramanathan Lakshmi N | Method for forming solder contacts on mounted substrates |
| US7420202B2 (en) | 2005-11-08 | 2008-09-02 | Freescale Semiconductor, Inc. | Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device |
| US7723224B2 (en) * | 2006-06-14 | 2010-05-25 | Freescale Semiconductor, Inc. | Microelectronic assembly with back side metallization and method for forming the same |
| US9019830B2 (en) | 2007-05-15 | 2015-04-28 | Imagine Communications Corp. | Content-based routing of information content |
| JP5123573B2 (ja) * | 2007-06-13 | 2013-01-23 | ローム株式会社 | 半導体発光素子およびその製造方法 |
| DE102007054856A1 (de) * | 2007-11-16 | 2009-05-20 | Osram Gesellschaft mit beschränkter Haftung | Beleuchtungsvorrichtung mit einer Substratplatte und einem Kühlkörper |
| FR2966285B1 (fr) * | 2010-10-14 | 2013-09-06 | St Microelectronics Crolles 2 | Procédé de formation de circuits intégrés sur substrat semi conducteur contraint |
| FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
| CN102420582A (zh) * | 2011-11-29 | 2012-04-18 | 浙江大学 | 基于柔性衬底的声表面波器件的结构及其制造方法 |
| CN104409411B (zh) * | 2014-11-24 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | 半导体器件及其形成方法 |
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| JPH07254690A (ja) * | 1994-01-26 | 1995-10-03 | Commiss Energ Atom | 半導体板形成方法 |
| JPH08111502A (ja) * | 1994-09-26 | 1996-04-30 | Internatl Business Mach Corp <Ibm> | 電子モジュール |
| EP1043770A1 (en) * | 1999-04-09 | 2000-10-11 | STMicroelectronics S.r.l. | Formation of buried cavities in a monocrystalline semiconductor wafer |
| JP2002511981A (ja) * | 1997-06-30 | 2002-04-16 | マクス−プランク−ゲゼルシャフト ツル フォルデルング デル ヴァイセンシャフト エー ファウ | 基板上の層状構造体の製造方法、及び該方法によって製造された基板及び半導体部品 |
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2003
- 2003-07-10 FR FR0308447A patent/FR2857502B1/fr not_active Expired - Lifetime
-
2004
- 2004-01-08 US US10/755,006 patent/US7067393B2/en not_active Expired - Lifetime
- 2004-07-08 JP JP2006518168A patent/JP4576381B2/ja not_active Expired - Lifetime
- 2004-07-08 WO PCT/EP2004/007632 patent/WO2005006419A2/en not_active Ceased
- 2004-07-08 EP EP04740898A patent/EP1644967A2/en not_active Withdrawn
- 2004-07-08 CN CN2004800193314A patent/CN1816897B/zh not_active Expired - Lifetime
- 2004-07-08 KR KR1020067000232A patent/KR100863081B1/ko not_active Expired - Lifetime
- 2004-07-09 TW TW093120670A patent/TWI310212B/zh not_active IP Right Cessation
-
2006
- 2006-04-27 US US11/411,833 patent/US7279779B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07254690A (ja) * | 1994-01-26 | 1995-10-03 | Commiss Energ Atom | 半導体板形成方法 |
| JPH08111502A (ja) * | 1994-09-26 | 1996-04-30 | Internatl Business Mach Corp <Ibm> | 電子モジュール |
| JP2002511981A (ja) * | 1997-06-30 | 2002-04-16 | マクス−プランク−ゲゼルシャフト ツル フォルデルング デル ヴァイセンシャフト エー ファウ | 基板上の層状構造体の製造方法、及び該方法によって製造された基板及び半導体部品 |
| EP1043770A1 (en) * | 1999-04-09 | 2000-10-11 | STMicroelectronics S.r.l. | Formation of buried cavities in a monocrystalline semiconductor wafer |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012519974A (ja) * | 2009-03-09 | 2012-08-30 | ソイテック | 熱膨張係数が局所的に適合するヘテロ構造の生成方法 |
| US8754505B2 (en) | 2009-03-09 | 2014-06-17 | Soitec | Method of producing a heterostructure with local adaptation of the thermal expansion coefficient |
| KR20180017174A (ko) * | 2015-07-17 | 2018-02-20 | 소이텍 | 기판을 제조하기 위한 방법 |
| JP2018528639A (ja) * | 2015-07-17 | 2018-09-27 | ソイテックSoitec | 基板を製造するための方法 |
| KR102072549B1 (ko) * | 2015-07-17 | 2020-02-03 | 소이텍 | 기판을 제조하기 위한 방법 |
| US10943778B2 (en) | 2015-07-17 | 2021-03-09 | Soitec | Method for manufacturing a substrate |
| US11837463B2 (en) | 2015-07-17 | 2023-12-05 | Soitec | Method for manufacturing a substrate |
| US12272540B2 (en) | 2015-07-17 | 2025-04-08 | Soitec | Method for manufacturing a substrate |
| US11780732B2 (en) | 2018-12-17 | 2023-10-10 | Tokai Carbon Korea Co., Ltd. | Carbonated tantalum coating material |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI310212B (en) | 2009-05-21 |
| US7067393B2 (en) | 2006-06-27 |
| JP4576381B2 (ja) | 2010-11-04 |
| CN1816897B (zh) | 2010-06-23 |
| FR2857502A1 (fr) | 2005-01-14 |
| US20050006740A1 (en) | 2005-01-13 |
| KR100863081B1 (ko) | 2008-10-13 |
| WO2005006419A3 (en) | 2005-02-10 |
| US20060192269A1 (en) | 2006-08-31 |
| TW200509217A (en) | 2005-03-01 |
| FR2857502B1 (fr) | 2006-02-24 |
| WO2005006419A2 (en) | 2005-01-20 |
| KR20060034685A (ko) | 2006-04-24 |
| US7279779B2 (en) | 2007-10-09 |
| EP1644967A2 (en) | 2006-04-12 |
| CN1816897A (zh) | 2006-08-09 |
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