JP2007272289A - Semiconductor integrated circuit design method and semiconductor integrated circuit design program - Google Patents

Abstract

In designing a semiconductor integrated circuit, an RC value of a wiring is extracted more accurately in consideration of a circuit (cell) for driving the wiring.
When creating an RC rule file 43 of wiring resistance values and wiring capacitance values based on process information 41 and variation information 42, variation sensitivity information 44 is created for each wiring structure. The variation sensitivity information 44 includes information including a parameter represented by a magnitude relation with respect to a point where the values of a plurality of primitive components constituting the capacitance of the wiring intersect according to a parameter including a dimension. . If the gate delay time is dominant, one parameter having high sensitivity to the capacity is specified, and a variation corresponding to the parameter is added to the RC rule file 43. When the wiring delay time is dominant, one parameter having high sensitivity to resistance is specified, and a variation corresponding to the parameter is added to the RC rule file 43.
[Selection] Figure 4

Description

  The present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit design program. In particular, in the design stage of a semiconductor integrated circuit, an RC (resistance) of a wiring is considered in consideration of variations that occur in accordance with processing accuracy and wiring patterns during manufacturing. , Capacity) value extraction method and program.

  In order to confirm the operation of the designed circuit at the design stage of the semiconductor integrated circuit, the RC value of the wiring is extracted based on the layout data, and the delay calculation assuming the load after completion using the extracted RC value After performing the above, it is necessary to verify the timing. As a general method for extracting the RC value, there is a table lookup method. In this method, based on the cross-sectional structure considering the dimensions and materials of the wiring, the distance between adjacent wirings and the capacitance value are analyzed, and the correspondence is prepared for each wiring combination, and the wiring per unit length is also prepared. An RC table in which resistance values are prepared and made into a database is used.

  Then, the layout pattern and the RC table are compared, and the value of the table having the matching pattern shape is extracted as the RC value. When performing the timing verification using the extracted RC value, it is necessary to guarantee the operation in consideration of variations caused in accordance with the processing accuracy and the wiring pattern at the time of manufacture.

  As one of the first methods for extracting the RC value in consideration of the conventional variation, the method of the flowchart shown in FIG. 5 is known. This method uses the design target values such as the wiring height, width, interlayer height (interlayer insulating film thickness), dielectric constant, and sheet resistance as process information 1, and performs RC analysis. Perform (step S1), and create an RC rule file 2 (step S2). Subsequently, the RC value is extracted by comparing the obtained RC rule file 2 with the layout data 3 (step S3). The extracted RC value data 4 is uniformly multiplied by the minimum variation coefficient 5 and the maximum variation coefficient 5 to obtain minimum RC value data 6 and maximum RC value data 7 used for delay calculation, respectively. .

  As a second extraction method considering variation, the method of the flowchart shown in FIG. 6 is known. This method further considers variations in the manufacturing process as the process information 11, and performs RC analysis for each of the cases where the variation is minimum and maximum (steps S11 and S12), and the RC rule in each case Files 12 and 13 are created (steps S13 and S14). Subsequently, the obtained RC rule file 12 for the minimum case, the RC rule file 13 for the maximum case, and the layout data 14 are respectively compared, and the RC value in each case is extracted (steps S15 and S16). Thereby, the minimum RC value data 15 and the maximum RC value data 16 used for delay calculation are obtained.

  Incidentally, the present inventor has previously proposed an LCR extraction method in an LSI design process. This LCR extraction method is an LCR extraction method for extracting an LCR value including at least one of resistance, capacitance, and inductance from layout data having wiring pattern data in at least a plurality of wiring layers. An LCR generation step of generating the LCR value based on the layout data of the target wiring pattern; a congestion level generation step of determining a pattern congestion degree in a region where the target wiring pattern exists based on the layout data; and the pattern When the degree of congestion is more congested than a predetermined reference value, the LCR value is corrected based on a pattern width variation value corresponding to a pattern interval between the wiring pattern of interest and an adjacent pattern. (For example, patent document 1) Ether.).

JP 2002-259485 A

  However, in the first extraction method described above, the case where the variation is the smallest and the case where the variation is the largest is assumed without considering the circuit (cell) for driving the wiring. There is a problem that it is underestimated. Further, since the second extraction method does not consider the circuit (cell) that drives the wiring, there is a problem in that the RC value is extracted under conditions that cannot occur in an actual integrated circuit.

  That is, as shown in FIG. 7, when the actual size of the wiring 22 is smaller than the ideal size of the wiring 21 that does not consider variations, that is, the design target value, the capacitance of the wiring is reduced. However, the wiring resistance increases. In the opposite case, as shown in FIG. 8, the actual wiring 22 is thicker than the ideal wiring 21, so that the wiring resistance is reduced, but the capacitance of the wiring is increased. In FIGS. 7 and 8, the ideal wiring 21 and the actual wiring 22 are indicated by a two-dot chain line and a solid line, respectively.

  Therefore, the relationship between the resistance value of the wiring and the capacitance value of the wiring is such that the capacitance value decreases as the resistance value increases, as indicated by a solid line 23 in FIG. However, in the second extraction method, it cannot be determined whether the resistance or the capacitance is more effective in the circuit. Therefore, as shown by a two-dot chain line 24 in FIG. 9, the RC value is maximized and all the conditions are minimized or maximized. A combination that results in Such a combination cannot occur in an actual integrated circuit. Thus, in the first extraction method and the second extraction method, a necessary and sufficient amount of variation cannot be estimated, so that the extracted RC value deviates from the actual value, and the timing analysis accuracy is improved. It will be lower.

  In order to solve the above-described problems caused by the prior art, the present invention considers a circuit (cell) for driving a wiring, and can further accurately extract the RC value of the wiring. An object is to provide an integrated circuit design program.

  In order to solve the above-described problems and achieve the object, the present invention creates a table of wiring resistance values and wiring capacitance values based on process information related to the wiring structure and variation information related to the wiring structure. Based on the information, variation sensitivity information is created for each wiring structure. The variation sensitivity information includes information including a parameter represented by a magnitude relationship with respect to a reference point where the values of a plurality of primitive components constituting the capacitance of the wiring intersect according to the parameter including the dimension.

  In the present invention, in the variation sensitivity information, a primitive component that is determined to have a large proportion of a plurality of primitive components in the combined wiring capacity may be used as a variation parameter for the capacity. Also, the gate delay time information corresponding to the wiring load is compared with the wiring delay time, and when it is determined that the gate delay time is dominant, one parameter having high sensitivity to the capacitance is specified, and the parameter Variations according to the above may be added to the table.

  On the other hand, if it is determined that the wiring delay time is dominant as a result of the comparison, one parameter having high sensitivity to the resistance is specified, and a variation corresponding to the parameter is added to the table. Good. Also, if it is determined that the sensitivity to resistance is high, the variation in the in-plane direction of the wiring layer to which the wiring belongs (hereinafter referred to as the horizontal direction) and the horizontal direction according to the surrounding situation of the wiring of interest. On the other hand, it may be selected which of the variations in the intersecting direction (hereinafter referred to as the vertical direction) is added.

  According to the present invention, for each wiring structure, the dominant parameter for the wiring resistance and the wiring capacity is specified based on the variation value according to the manufacturing or pattern, and the RC value is determined only for the dominant parameter. Since it is extracted as variation, the RC value can be appropriately extracted according to the pattern condition.

  According to the semiconductor integrated circuit design method and semiconductor integrated circuit design program of the present invention, it is possible to extract the RC value of the wiring more accurately in consideration of the circuit for driving the wiring.

  Exemplary embodiments of a semiconductor integrated circuit design method and a semiconductor integrated circuit design program according to the present invention will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited by the following embodiment.

  FIG. 1 is a flowchart showing a processing procedure when a semiconductor integrated circuit is developed by applying the method of the present invention. As shown in FIG. 1, when developing a semiconductor integrated circuit, first, circuit information is prepared (step S21), and circuit arrangement and wiring are performed on the chip based on the circuit information (step S22). . Subsequently, wiring resistance and capacitance information (RC) is extracted as wiring information (step S23). Subsequently, delay calculation is performed based on the extracted RC information (step S24). Subsequently, timing analysis is performed using the delay calculation result (step S25). Up to this point, a design support tool (CAD) and various tools for analysis and verification are used.

  If no error occurs as a result of the timing analysis (step S26: No), the manufacturing process such as device / process design or mask design is designed (step S27). If an error occurs as a result of the timing analysis (step S26: Yes), the process returns to step S22, and the circuit arrangement and wiring processes are repeated. The method of the present invention can also be applied to development procedures other than the flowchart shown in FIG.

  Next, the RC extraction process will be described in detail. First, consider a wiring structure as shown in FIG. In this wiring structure, when attention is paid to the central wiring 31, the capacity of the wiring 31 is subdivided into an adjacent component Cc, a parallel plate component Ca, and a lip component Cf. The adjacent component Cc is a capacitance generated between the wiring 31 and the adjacent wiring 32 in the same wiring layer among the capacitance of the central wiring 31.

  Further, the parallel plate component Ca means that the capacitance of the central wiring 31 is directly above or directly below the wiring 31 in the wiring 31 and the wiring layer immediately above or immediately below the wiring layer to which the wiring 31 belongs. It is a capacitance generated between the wiring (not shown) provided. The edge component Cf is a position of the capacitance of the central wiring 31 that is shifted from directly above or directly below the wiring 31 in the wiring layer immediately above or immediately below the wiring layer to which the wiring 31 belongs. This is a capacitance generated between the wiring and the wiring (not shown).

  When analyzing the capacitance based on the wiring structure and creating a capacitance table (horizontal direction, vertical direction, diagonal direction), the adjacent component Cc, the parallel plate component Ca, and the total capacitance of the wiring when the wiring interval is changed The ratio of the edge component Cf is obtained in advance. For example, it is assumed that the adjacent component Cc, the parallel plate component Ca, and the edge component Cf of the capacitance have a relationship as shown in FIG.

  In this case, when the wiring interval is narrower than the cross point at which the adjacent component Cc and the edge component Cf intersect, the variation of the adjacent component Cc is dominant with respect to the variation of the wiring capacitance. On the other hand, when the interval is wider than the cross point, the variation of the edge component Cf becomes dominant with respect to the variation of the capacitance of the wiring. In this way, information for specifying a dominant capacitance component according to the interval between wirings is information on variation sensitivity for capacitance.

  The same applies to the wiring resistance. That is, when analyzing the resistance based on the wiring structure and creating the resistance table (horizontal direction, vertical direction, diagonal direction), the horizontal direction, vertical direction and the total resistance of the wiring when the wiring interval is changed The ratio of each component in the oblique direction is obtained in advance. This information is information on variation sensitivity for the resistance, and information for specifying a dominant component in accordance with the wiring interval.

  FIG. 4 is a flowchart of a method for extracting an RC value according to the embodiment. As shown in FIG. 4, first, process information 41 including design target values such as wiring height, width, interlayer height (interlayer insulating film thickness between wirings), dielectric constant and sheet resistance, and distance The RC parameter is analyzed using the variation information 42 including the interval information (step S31). Then, an RC rule file 43 when the design target value is used, and information 44 of variation sensitivity of capacitance and resistance are created (step S32).

  Subsequently, the RC rule file 43 and the layout data 45 obtained are compared with each other to search for a pattern and extract an RC value (step S33). Further, the on-resistance of the gate is acquired from the circuit information 46, and the gate delay time and the wiring delay time of the circuit load are obtained (step S34). The gate delay time is a delay determined according to the wiring load, and is determined by a product (R (TR) × C (wiring)) of the gate on-resistance value R (TR) and the wiring capacitance value C (wiring). . The wiring delay time is obtained by the product of the wiring resistance value R (wiring) and the wiring capacitance value C (wiring) (R (wiring) × C (wiring)).

  Subsequently, the gate delay time and the wiring delay time are compared. In this comparison, since the capacitance value C (wiring) of the wiring is common between the gate delay time and the wiring delay time, the on-resistance value R (TR) of the gate is compared with the resistance value R (wiring) of the wiring. Will do. When the gate delay time is longer than the wiring delay time, that is, when the gate on-resistance value R (TR) is larger than the wiring resistance value R (wiring) (step S35), the wiring capacitance value C (wiring) The minimum value and the maximum value (variation) of the overall capacitance of the wiring of interest are determined using the sensitivity of (1) as a key (step S36).

  At this time, based on the variation sensitivity information 44 created in step S32, a dominant parameter is determined from the capacitance of the wiring obtained by synthesizing the primitive component of the capacitance, and the minimum and maximum values of the capacitance value of the parameter are determined. Ask for. If there is another wiring next to the wiring of interest, priority is given to the variation in the horizontal direction of the table to be referenced, and if there is wiring above or below the wiring of interest, priority is given to the vertical variation of the table to be referenced. The sum of the minimum value of the dominant parameter and the capacitance value of the non-dominant parameter is the minimum value of the overall capacitance of the wiring. Further, the sum of the maximum value of the dominant parameter and the capacitance value of the non-dominant parameter is the maximum value of the overall capacitance of the wiring.

  On the other hand, when the gate delay time is the same as or shorter than the wiring delay time, that is, when the ON resistance value R (TR) of the gate is equal to or less than the resistance value R (wiring) of the wiring (step S37). Then, using the sensitivity of the resistance value R (wiring) of the wiring as a key, the minimum value and the maximum value (variation) of the entire resistance of the wiring of interest are determined (step S38). At this time, based on the variation sensitivity information 44, a dominant parameter is determined from the parameters of the horizontal component, the vertical component, and the diagonal component for the entire resistance of the wiring, and the minimum resistance value of the parameter is determined. And find the maximum value.

  If there is another wiring next to the wiring of interest, priority is given to the vertical variation of the table to be referenced, and if there is wiring above or below the wiring of interest, priority is given to the horizontal variation of the table to be referenced. Also, whether there is another wiring next to the wiring of interest is determined by the distance from the adjacent wiring. When it is determined that there is an adjacent wiring, the width of the wiring is variable, and when it is determined that there is no adjacent wiring, the height of the wiring is variable.

  The sum of the minimum value of the dominant parameter and the resistance value of the non-dominant parameter is the minimum value of the overall resistance of the wiring. Further, the sum of the maximum value of the dominant parameter and the resistance value of the non-dominant parameter is the maximum value of the overall resistance of the wiring. As described above, the minimum RC value data 47 and the maximum RC value data 48 are obtained.

  The semiconductor integrated circuit design method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

  As described above, according to the embodiment, for each wiring structure, the dominant parameters for the wiring resistance and the wiring capacity are specified based on the variation value according to the manufacturing or pattern, and the dominant Since only RC parameters are extracted as RC value variations, RC values can be appropriately extracted according to pattern conditions. Therefore, the RC value of the wiring can be extracted more accurately. Further, by using the extracted RC value for logic verification (timing verification), an effect of improving the accuracy of analysis can be obtained.

(Appendix 1) Creating a table of wiring resistance values and wiring capacitance values based on process information on wiring structures and variation information on wiring structures;
Based on the process information related to the wiring structure and the variation information related to the wiring structure, for each wiring structure, the value of a plurality of primitive components constituting the wiring capacitance intersects according to the parameter including the dimension, and the reference Creating variation sensitivity information having information including parameters represented by a magnitude relationship with respect to
A method for designing a semiconductor integrated circuit, comprising:

(Appendix 2) In creating the variation sensitivity information,
The method for designing a semiconductor integrated circuit according to appendix 1, wherein a primitive component that is determined to have a large proportion of the primitive component in the capacitance of the combined wiring of the primitive component is used as a variation parameter for the capacitance. .

(Supplementary Note 3) A step of comparing gate delay time information corresponding to a wiring load and wiring delay time, and determining which of a resistance variation and a capacitance variation is prioritized based on the comparison result The method for designing a semiconductor integrated circuit according to appendix 1, further comprising:

(Appendix 4) In performing the priority determination,
If it is determined that the gate delay time is dominant, specify one parameter that is highly sensitive to capacitance, and if it is determined that the wiring delay time is dominant, the sensitivity to resistance is determined. The method for designing a semiconductor integrated circuit according to appendix 3, further comprising: specifying one high parameter and adding a variation according to any one of the specified parameters to the table.

(Supplementary Note 5) When it is determined that the sensitivity to resistance is high, the variation in the in-plane direction of the wiring layer to which the wiring belongs and the direction intersecting the in-plane direction are determined according to the surrounding situation of the wiring of interest. The method for designing a semiconductor integrated circuit according to appendix 4, wherein which of the variations is added is selected.

(Appendix 6) A semiconductor integrated circuit design program which causes a computer to execute the semiconductor integrated circuit design method according to any one of appendices 1 to 5.

  As described above, the semiconductor integrated circuit design method and the semiconductor integrated circuit design program according to the present invention are useful for designing a semiconductor integrated circuit, and are particularly suitable for designing a wiring of a semiconductor integrated circuit.

It is a flowchart which shows the process sequence at the time of developing a semiconductor integrated circuit by applying the method of this invention. It is a figure which shows an example of a wiring structure. It is a figure explaining the information of the variation sensitivity with respect to the wiring structure shown in FIG. It is a flowchart of the method of extracting the RC value concerning embodiment. It is a figure which shows the flowchart of the method of extracting the conventional RC value. It is a figure which shows the flowchart of the method of extracting the conventional RC value. It is a figure showing the state where wiring became thin by variation. It is a figure which shows the state where wiring became thick by the dispersion | variation. It is a figure which shows the relationship between the resistance value of wiring, and the capacitance value of wiring.

Explanation of symbols

31, 32 Wiring 41 Process information 42 Variation information 43 RC rule file 44 Variation sensitivity information

Claims (5)

Creating a wiring resistance value and wiring capacitance value table based on wiring structure process information and wiring structure variation information;
Based on the process information related to the wiring structure and the variation information related to the wiring structure, for each wiring structure, the value of a plurality of primitive components constituting the wiring capacitance intersects according to the parameter including the dimension, and the reference Creating variation sensitivity information having information including parameters represented by a magnitude relationship with respect to
A method for designing a semiconductor integrated circuit, comprising: In creating the variation sensitivity information,
2. The design of a semiconductor integrated circuit according to claim 1, wherein, among the primitive components, a primitive component that is determined to have a large proportion in the capacitance of a wiring obtained by combining the primitive components is used as a variation parameter for the capacitance. Method.   A step of comparing the gate delay time information corresponding to the wiring load with the wiring delay time and determining which of the resistance variation and the capacitance variation is prioritized based on the comparison result. The method of designing a semiconductor integrated circuit according to claim 1. In making the priority determination,
If it is determined that the gate delay time is dominant, specify one parameter that is highly sensitive to capacitance, and if it is determined that the wiring delay time is dominant, the sensitivity to resistance is determined. 4. The method of designing a semiconductor integrated circuit according to claim 3, further comprising the step of specifying one high parameter and adding a variation according to any of the specified parameters to the table.   5. A semiconductor integrated circuit design program for causing a computer to execute the semiconductor integrated circuit design method according to claim 1.

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