JP2007101893A - Drive control device, image display device, and television device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving control apparatus capable of enhancing luminance when the luminance of an image display falls as a result of the accumulated use thereof due to display of television data etc. <P>SOLUTION: The driving control apparatus is equipped with: a scanning driver capable of simultaneously selecting a plurality of row wiring, and supply a scanning selection signal to the selected row wiring; a data driver which supplies a modulation signal based on image data in synchronization with the scanning selection signal to column wiring; a calculation section which calculates the value associated with the luminance deterioration of the display device; and a control circuit which controls the scanning driver so as to increase the number of the row wiring to be simultaneously selected when the cumulative value associated with the luminance deterioration calculated by the calculation section exceeds the predetermined value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive control device, an image display device, and a television device that perform passive matrix driving.

A self-luminous display driven by a matrix is inevitably darker than a CRT (cathode ray tube), so that it is required to increase luminance.

On the other hand, in a liquid crystal display that is not a self-luminous display, it is required to increase the contrast rather than the luminance. For this reason, there is an active addressing driving method in the STN type liquid crystal.

  For example, Japanese Patent Laid-Open No. 4-311175 (Patent Document 1) discloses a liquid crystal driving method for simultaneously driving a plurality of lines in a liquid crystal.

  Japanese Laid-Open Patent Publication No. 2000-267624 (Patent Document 2) discloses a driving circuit for a matrix display device that performs simultaneous driving only on a plurality of correlated rows.

  Japanese Patent Laid-Open No. 8-50462 (Patent Document 3) discloses a flat panel display device that performs edge enhancement by driving two lines at a time during interlace driving.

Japanese Patent Laying-Open No. 2004-133138 (Patent Document 4) discloses an image display apparatus that is driven simultaneously with a plurality of lines.
JP-A-4-31175 (Patent No. 3262175) JP 2000-267624 A JP-A-8-50462 JP 2004-133138 A

There are the following problems in increasing the brightness of a self-luminous display driven by a passive matrix. Examples of the self-luminous display driven by passive matrix include the following.
A display using a surface conduction electron-emitting device or other electron-emitting device as an electron source.
・ PDP (Plasma Display Panel).
・ LED (light emitting diode) display.
・ EL (electroluminescence) display.

  When the active addressing driving method used in the liquid crystal is applied to a self-luminous display, pixels that should not emit light also emit light, and thus cannot be used in a self-luminous display.

Some PDPs, which are self-luminous displays, have a higher brightness when displaying television data than when displaying computer data. In this case, the computer data is displayed darker by adjusting the drive voltage and display data rather than making the display of the television device brighter. Therefore, the television data is displayed brighter than during normal driving. I couldn't do it.

  If the driving voltage is increased to increase the display luminance, the power consumption is increased and the heat becomes more difficult to dissipate. Therefore, it cannot be commercialized for home use.

In addition, in the FED and the like, a method of increasing the anode voltage is used to increase the luminance. However, if the anode voltage is increased too much, a discharge may occur between the upper and lower substrates, which may destroy the display device. . Further, since the lifetime of the phosphor is shortened, the anode voltage could not be increased too much.

In EL, the brightness can be increased by using TFT (Thin Film Transistor).
Compared to simple matrix driving, there is a problem in that the manufacturing cost is greatly increased.

  In Japanese Patent Laid-Open No. 2000-267624 (Patent Document 2), it is necessary to realize a correlation detection unit, which requires a great deal of cost and design change.

  Japanese Patent Laid-Open No. 8-50462 (Patent Document 3) is a method that can be realized only when an interlaced video is driven by a plurality of rows, and cannot be realized by line-sequential driving.

  Japanese Patent Application Laid-Open No. 2004-133138 (Patent Document 4) discloses a method capable of realizing a long life of an image display device by simultaneously driving a plurality of lines.

  An object of the present invention is to increase the luminance of a display device when the luminance is lowered after repeated use due to display of image data.

  In order to achieve the above object, the present invention can select a plurality of row wirings at the same time, and supplies a scanning selection signal to the selected row wirings, and is based on image data in synchronization with the scanning selection signal. When a data driver that supplies a modulation signal to the column wiring, a calculation unit that calculates a value related to luminance degradation of the display device, and a value related to the luminance degradation calculated by the calculation unit exceeds a predetermined value, And a control circuit for controlling the scan driver so as to increase the number of row wirings to be selected at the same time.

  According to the present invention, a plurality of row wirings can be selected at the same time, a scanning driver that supplies a scanning selection signal to the selected row wirings, and a modulation signal based on image data in a row in synchronization with the scanning selection signal. A data driver to be supplied to the wiring, a first display mode in which only one row wiring is selected and a first drive voltage is applied to the pixels of the display device, and a plurality of row wirings are simultaneously selected. And a second display mode in which a second drive voltage lower than the first drive voltage is applied to the pixel, and a control circuit for selecting one of the second display modes.

  In the present invention, in the display device, the brightness can be increased when the brightness is lowered due to repeated use due to display of image data or the like.

  DETAILED DESCRIPTION Exemplary embodiments of the present invention will be described in detail below with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention only to those unless otherwise specified. Absent. In all the drawings of the following embodiments, the same or corresponding parts are denoted by the same reference numerals.

(Embodiment of a television device)
First, a television device to which the present invention is applicable will be described with reference to FIG. FIG. 23 is a block diagram of a television device according to the present invention. The television device includes a set top box (STB) 501 and an image display device 502.

  The set top box (STB) 501 includes a receiving circuit 503 and an I / F unit 504. The receiving circuit 503 includes a tuner, a decoder, and the like, receives a television signal such as satellite broadcast or terrestrial wave, a data broadcast via a network, and outputs the decoded video data to the I / F unit 504. The I / F unit 504 converts the video data into the display format of the image display device 502 and outputs the image data to the image display device 502.

  The image display device 502 includes a display panel 200, a control circuit 505, and a drive circuit 506. A control circuit 505 included in the image display device 502 performs image processing such as correction processing suitable for the display panel 200 on the input image data, and outputs the image data and various control signals to the drive circuit 506. An example of the control circuit 505 is the control circuit 11 in FIG. The drive circuit 506 outputs a drive signal to the display panel 200 based on the input image data, and a television image is displayed on the display panel 200. As an example of the drive circuit 506, the column drive circuit 104 and the row drive circuit 102 in FIG. In the following embodiment, the display panel 200 is exemplified by the display panel 101 as shown in FIG. As the display panel 101, for example, various display panels such as SED, FED, PDP, LED, and EL display can be used.

  Note that the receiving circuit 503 and the I / F unit 504 may be housed in a separate housing from the image display device 502 as a set top box (STB) 501, or the same housing as the image display device 502 It may be contained in.

Next, the driving device for the self-luminous display according to this embodiment will be described below. The driving device mainly includes driving means for driving two or more adjacent scanning lines to be active at the same time, detecting means for detecting a decrease in luminance (cumulative value related to luminance deterioration), and driving means according to the decrease in luminance. Control means for controlling
(Embodiment of Image Display Device)
Hereinafter, preferred embodiments of an image display device will be described with reference to the accompanying drawings.

  FIG. 8 is a block diagram showing a circuit configuration of a conventional self-luminous display.

In this example, a device using a surface conduction electron-emitting device (SED) is shown as an electron-emitting device in a field emission display (FED).

In FIG. 8, reference numeral 101 denotes a display panel having (M × N) surface conduction electron-emitting devices wired in M rows × N columns. Each of these surface conduction electron-emitting devices is connected to an external circuit via row terminals Dx1 to DxM connected to the row wiring and column terminals Dy1 to DyN connected to the column wiring. Although not shown, a high voltage terminal on the face plate of the display surface of the display panel 101 is also connected to an external acceleration voltage power source 106 so as to accelerate electrons emitted from the surface conduction electron-emitting device toward the face plate. It has become. The row terminals Dx1 to DxM are used to sequentially drive the multi-electron source provided in the display panel 101, that is, the surface conduction electron-emitting devices arranged in a matrix of M rows × N columns one row at a time. A scanning signal is applied. On the other hand, a modulation signal is applied to the column terminals Dy1 to DyN for controlling the emitted electrons of each surface conduction electron-emitting device selected by the scanning signal in accordance with the input image signal. .

Next, the row drive circuit (scan driver) 102 will be described. The row driving circuit 102 is generally composed of a plurality of ICs, and each IC is connected to a plurality of row arrays. The row driving circuit 102 includes a total of M switching elements. Each switching element applies a DC voltage Vs (scanning selection signal, selection voltage) to the wiring terminal of the emission element row of the line to be scanned based on the control signal Tscan input from the control circuit 103. In addition, a DC voltage Vns (non-selection signal, non-selection voltage) is applied to each column terminal of the emission element column that is not being scanned.

  Each of these switching elements can be easily configured by a switching element such as an FET. The drive waveforms of the DC voltages Vs and Vns will be described later.

  The control circuit 103 has a function of matching the operation timing of each unit so that appropriate image display is performed based on an image signal input from the outside. An image signal (video signal) input from the outside may be combined with image data and a synchronization signal, such as an NTSC signal, or may be separated in advance. The latter case will be described. That is, the control circuit 103 generates Tscan, Tsft, and Tmry control signals for each unit based on a synchronization signal Tsync input from the outside. Note that the synchronization signal generally includes a vertical synchronization signal and a horizontal synchronization signal, but is Tsync here for the sake of simplicity. It should be noted that a well-known sync separation circuit is provided for the image signal of the NTSC signal, and the image data and the sync signal can be separated as in the present embodiment.

  On the other hand, image data (luminance data) input from the outside is input to a shift register in the column drive circuit (data driver) 104. The column driving circuit 104 is usually composed of a plurality of ICs, and each IC is connected to a plurality of column wirings. The column driving circuit 104 includes a shift register, a latch circuit, a pulse width modulation circuit, etc., not shown.

The shift register is for serial / parallel conversion of image data input serially in time series in units of one line of the image. The shift register inputs and holds digital image data pixel by pixel based on a control signal (shift clock) Tsft input from the control circuit 103. Thus, the image data for one line held in the shift register (corresponding to the drive data for one line (N element) of the electron-emitting device) is output to the latch circuit as a plurality of parallel signals.

The latch circuit is a storage circuit for storing image data for one line for a necessary time, and latches and stores a plurality of parallel signals simultaneously in accordance with a control signal Tmry sent from the control circuit 103. The image data stored in the latch circuit is output to the pulse width modulation circuit as a plurality of parallel signals.

  The pulse width modulation circuit generates a voltage pulse with a constant peak value according to the image data input from the latch circuit. Here, a pulse width signal corresponding to the input luminance data (multi-value data) is generated. An output pulse width modulation circuit is used.

  More specifically, the voltage signal output from the pulse width modulation circuit has a wider voltage pulse as the luminance level of the image data is larger. For example, the peak value is 10 [V] and the maximum luminance is obtained. In contrast, a pulse with a width of 60 [μsec] is output. The voltage signal is input to the column terminals Dy1 to DyN of the display panel 101. The voltage Ve105 is a power source of a voltage output from the column drive circuit 104.

  In addition, design parameters such as drive voltage are determined as follows. The surface conduction electron-emitting device has an electron-emitting device characteristic having a threshold voltage of Vth = 8 [V], for example. Therefore, in order to prevent unnecessary light emission on the screen, the voltage applied to the non-scanning electron-emitting device array must be less than 8 [V].

For example, if the column drive voltage Ve = 10V, the selection voltage Vs = −5V and the non-selection voltage Vns = 5
V.

  In this way, 15 V is applied to the active element of the column electrode and −5 V is applied to the other elements on the scanning electrode. On the unscanned electrode, the column electrode active element takes 5V and the other elements take -5V.

  Since the absolute value 5V of ± 5V is 8V or less, the condition is cleared.

  The actual voltage value is determined in consideration of the above conditions while maintaining the rated value of the IC.

  The acceleration voltage Va applied to the phosphor using the acceleration voltage power source 106 was determined as follows. That is, the input power to the phosphor necessary to obtain a desired maximum luminance is calculated from the luminous efficiency of the phosphor, and the acceleration voltage Va is determined so that (Iemax × Va) satisfies the input power. For example, 10 [KV].

  As described above, each parameter was determined.

  The input video signal has been described as a digital video signal that allows easier data processing, but the input signal is not limited to a digital video signal, and may be an analog video signal.

  In addition, although a configuration using a shift register that can easily process a digital signal is shown for serial / parallel conversion processing, other configurations are possible. For example, a random access memory having a function equivalent to a shift register may be used by sequentially changing the storage address by controlling the storage address.

  FIG. 9 shows voltage waveforms output from the conventional row driving circuit.

In the figure, 111 is the Ysync signal waveform of Tscan input to the row drive circuit, and 112 is the first row A
, 113 is a waveform for driving the second row B, and hereinafter is a waveform for driving rows C, D, E, and F.

  1 corresponds to “Dx1 = A, Dx2 = B,...” With respect to Dx1 to DxM in FIG.

The non-selection voltage Vns in FIG. 8 is the higher voltage (for example, 5 V) of the waveforms 112 and 113 in FIG.
The selection voltage Vs is the lower voltage (for example, −5 V) of the waveforms 112 and 113 in FIG.

  The selection voltage Vs in these waveforms 112 and 113 shifts to the adjacent row every time the row wiring synchronization signal 111 rises, and only one row wiring always becomes the selection voltage Vs, and the selection voltage Vs in the plurality of row wirings. It will never be Vs. Only the electron-emitting device to which the column driving voltage Ve (for example, 10 V) is applied to the selection voltage Vs in the row driving exceeds the threshold voltage Vth (for example, 8 V) (e.g., becomes 15 V) and emits electrons. I can do it.

  Embodiments of the present invention will be described below with reference to the drawings.

[Example 1]
1, 2 and 3 are diagrams for explaining the first embodiment. FIG. 1 is a block diagram showing a circuit configuration of the self-luminous display according to the first embodiment. In FIG. 1, the display panel 101, the row drive circuit 102, the column drive circuit 104, the column drive voltage Ve105, and the acceleration voltage power source 106 are the same as those in FIG.

  11 is a control circuit that controls the row driving circuit 102 and the column driving circuit 104, 12 is an edge enhancement circuit that edge-enhances the video signal in the row direction, and 13 is an operable range of the column driving circuit. This is a normalization circuit limited to

  The control circuit 11 gives an enable signal and a sink signal to the row driving circuit 102 so as to activate the three row wirings simultaneously.

The edge enhancement circuit 12 performs edge enhancement processing on the video signal in the row direction. For example, to obtain edge-enhanced B line data, use the edge enhancement formula:
New B = 3B-A-C
Data processing such as new B = 2B-A / 2-C / 2 is performed.
Here, A, B, and C indicate output luminance values, respectively. Details will be described later.

  The normalization circuit 13 performs a gradation number limiting process on a portion where the edge-emphasized data exceeds the gradation range of the drive circuit.

  As a method of limiting the number of gradations, in the case of 8-bit gradation for each color, the data range is adjusted to 0 to 255, and the following methods are available.

  (1) As a first method, a negative value is simply 0, and a value exceeding 255 is 255.

  (2) As a second method, half of the negative value is added to the upper and lower pixels, and half of the value exceeding 255 is added to the upper and lower pixels. Thereafter, the corresponding pixel is set to 0 or 255.

  (3) As a third method, for a negative value, a quarter of the value is added to the upper and lower pixels, and for a value exceeding 255, a quarter of the excess is added to the upper and lower pixels. Thereafter, the corresponding pixel is set to 0 or 255.

  (4) As a fourth method, for a negative value, a quarter of the value is added to the left and right pixels, and for a value exceeding 255, a quarter of the excess is added to the upper and lower pixels. Thereafter, the corresponding pixel is set to 0 or 255.

  (5) As a fifth method, a negative value adds a quarter of the value to the top, bottom, left and right pixels, and a value exceeding 255 adds a quarter of the excess to the top and bottom pixels. . Thereafter, the corresponding pixel is set to 0 or 255.

  In addition to these, a normalization method is conceivable. Note that the total value of the pixels is stored in the second method and the fifth method, and the total value is changed in the first method, the third method, and the fourth method.

  FIGS. 3C and 3D to be described later exemplify the case of normalization by the third method.

Here, the edge enhancement circuit 12 and the normalization circuit 13 can also output data to the column drive circuit 104 without performing the respective processes. When the luminance is not deteriorated, the control circuit 11 controls the edge emphasis circuit 12 and the normalization circuit 13 so as to output to the column drive circuit 104 without performing the above-described processing.

  The control circuit 11 outputs a single-line drive waveform as shown in FIG. 9 of the conventional example when the luminance is not deteriorated.

  As a detection method for determining whether or not the luminance is deteriorated, the determination is simply made based on the usage time of the display device (accumulated value related to the luminance deterioration).

  To make a precise determination, a cumulative value of APL (Average Picture Level) of display data (a cumulative value related to luminance deterioration) is stored, and a determination is made based on the cumulative value.

  These configurations and criteria will be described later.

  FIG. 2 shows voltage waveforms output from the row drive circuit 102 of the self-luminous display according to the first embodiment.

  In FIG. 2, reference numeral 21 denotes a Tscan Hsync signal waveform input to the row drive circuit 120, 22 denotes a waveform for driving the first row A, and 23 denotes a waveform for driving the second row B. The following are waveforms for driving rows C, D, E, and F.

  1 corresponds to “Dx1 = A, Dx2 = B,...” With respect to Dx1 to DxM in FIG.

The non-selection voltage Vns is a high voltage (for example, 5V) of the waveforms 22 and 23 in FIG. 2, and the selection voltage Vs is a low voltage (for example, −5V) of the waveforms 22 and 23 in FIG. .

  With respect to the selection voltage Vs in the waveforms 22 and 23, every time the sync signal 21 of the row rises, the adjacent row becomes the selection voltage Vs. At the time of rising, it changes to the non-selection voltage Vns.

  As a result, the selection voltage Vs is simultaneously obtained in three rows. The electron-emitting device to which the column driving voltage Ve (for example, 10 V) is applied to the selection voltage Vs in the row driving has an element voltage of, for example, 15 V, and emits electrons exceeding the threshold voltage Vth (for example, 8 V). As a result, electrons are emitted from the three electron-emitting devices for each column to which the column driving voltage Ve is applied. FIG. 10 shows the relationship between the device voltage and threshold voltage, the device current and the emission current as a reference.

  FIG. 3 is a diagram showing the correlation between the data processing and the output luminance value after the data processing in the first embodiment.

  FIG. 3A shows an example of original image (original video signal) data. FIG. 3B shows an example of data obtained by performing edge enhancement processing on the original image data of FIG. FIG. 3C shows data in the middle of normalization from data obtained by performing edge enhancement processing on the original image of FIG. FIG. 3D shows the data after normalization.

FIG. 3E shows a value obtained by simply multiplying the “original image” data of FIG. FIG. 3F shows a value obtained by shifting the original image data of FIG. For example, the upper left value “240” in FIG. 3F is a value obtained by adding the upper left values “60”, “80”, and “100” in FIG. FIG. 3G is a value obtained by shifting the “data after edge enhancement” in FIG. 3B by shifting by three lines, and FIG. 3H is the “after normalization” in FIG. A value obtained by shifting the data by three lines is shown.

FIG. 3A corresponds to the video signal of FIG. 1, and gradations 0 to 2 corresponding to one color among RGB colors.
This is a part of the data in the area up to 55. The RGB video signal created from the television signal is
In this example, the area to be actually displayed is the third and subsequent lines from the top, and the upper two lines are data used to perform the following processing without any contradiction, because the signal includes a signal that is wider than the actual display area. .

The “original image” data in FIG. 3A is input to the edge enhancement processing circuit 12. The edge enhancement processing performed in the edge enhancement processing circuit 12 is enhancement processing for the row direction, and in the example of FIG.
New B = 2 × B-0.5 × A-0.5 × C
It was.

Besides the example here,
New B = 2.5 × B-0.75 × A-0.75 × C
There are several formulas with different emphasis levels.

  The edge enhancement process is not limited to these, and any method can be employed from the compatibility of the video signal and the display. A second embodiment in which edge enhancement processing is not performed will be described later.

  In FIG. 3B, as a result of edge emphasis, the original gradation areas 0 to 255 protrude upward and downward at some coordinates. The data value is a value such as “290” or “−25”.

  Therefore, a value exceeding the original gradation region is limited within the region by the normalization processing circuit 13. In this embodiment, the method 3 described above with reference to FIG. 1 is illustrated. Fig. 3 (c) shows the first half of the normalization process. “Negative values are added to the upper and lower pixels by a quarter of that value. The result of “add to pixel” is shown. FIG. 3D shows a result of performing the latter half of the normalization process “after that, the corresponding pixel is set to 0 or 255”.

  In FIG. 3 (e) to FIG. 3 (h), the original 8-bit gradation area 0 to 255 is a gradation area from 0 to 767, which is three times upward, and the values in each figure are as follows: This is a gradation intensity value representing a relative gradation intensity. The brightness of each color of the display changes in accordance with the characteristics of the phosphor of the display, precisely in proportion to the relative gradation intensity value.

  FIG. 3F shows a luminance output value obtained when three lines are simultaneously driven by the driving waveform described in FIG. 2 without performing data processing such as edge enhancement processing.

  FIG. 3G shows the luminance output value that should be obtained if the three-line simultaneous drive can be similarly performed on the data subjected to the edge enhancement processing of FIG. This luminance output value is close to the value shown in FIG. However, the edge-enhanced data in FIG. 3B cannot be realized because it includes values outside the region.

  Therefore, in the first embodiment, the luminance output obtained by simultaneously driving the three lines in FIG. 3 (h) is obtained using the normalized data in FIG. 3 (d). Since the luminance output in FIG. 3 (h) is a value close to the value shown in FIG. 3 (e), the luminance is almost three times that of the original image data in FIG. 3 (a).

[Example 2]
Next, as a second embodiment, an example in which the three lines are driven simultaneously without performing edge enhancement processing will be described.

  In this embodiment, the luminance output (corresponding to the gradation intensity value) to be obtained is a value three times that of the original image data shown in FIG. For normal video, a luminance output as close to 3 times as possible is desirable, but a soft display is preferred for movies and the like. If the original video signal has a graininess or block noise is noticeable, a better display output can be obtained without edge enhancement.

  In the present embodiment, in FIG. 1, the edge enhancement processing circuit 12 and the normalization circuit 13 do not perform the above-described processing, and the control circuit 11 adjusts at the same timing as when processing is performed on the video data. Then, the waveform of FIG. 2 is obtained.

  The luminance output at the time of three-line simultaneous driving is luminance corresponding to the gradation intensity when only the three-line simultaneous driving shown in FIG.

[Example 3]
In the first and second embodiments, the example in which the number of lines to be simultaneously driven is “3” has been described. However, in this embodiment, the number of lines to be driven is plural, and 3 lines It is not limited to.

  In the third embodiment, an example in which two lines are simultaneously driven will be described with reference to FIGS. 1, 4 and 5. FIG.

  FIG. 4 shows voltage waveforms output from the row drive circuit of the self-luminous display of the third embodiment.

  In FIG. 4, 21 is a Ysync signal waveform of Tscan input to the row drive circuit, 41 is a waveform for driving the first row A, 42 is a waveform for driving the second row B, and the following rows C, D, E , Shows the waveform driving F.

  The non-selection voltage Vns and the selection voltage Vs are the same as those in FIG.

  The selection voltage Vs in the waveforms 41 and 42 is such that every time the sync signal 21 of the row rises, the adjacent row becomes the selection voltage Vs, and the row once becomes the selection voltage Vs then has the sync signal 21 rises twice. At this point, the voltage changes to the non-selection voltage Vns.

  Thereby, the selection voltage Vs is always applied to the two row wirings. Then, the electron-emitting device to which the column driving voltage Ve (for example, 10 V) is applied to the selection voltage Vs in the row driving exceeds the threshold voltage Vth (for example, 8 V) and emits electrons. As a result, electrons are emitted from the two electron-emitting devices for each column wiring to which the column driving voltage Ve is applied.

  FIG. 5 is a diagram showing the correlation between data processing and output luminance in the third embodiment.

  FIG. 5A shows an example of original image (original video signal) data. FIG. 5B shows an example of data obtained by performing edge enhancement processing on the original image data of FIG. FIG. 5C shows data in the middle of normalization from data obtained by performing edge enhancement processing on the original image of FIG. FIG. 5D shows the data after normalization.

FIG. 5E shows a value obtained by simply doubling the original image data shown in FIG. FIG. 5F shows a value obtained by shifting the original image data of FIG. For example, the upper left value “140” in FIG. 5F is a value obtained by adding the upper left values “60” and “80” in FIG. FIG. 5G shows a value obtained by adding the data after the edge enhancement processing of FIG. FIG. 5H shows a value obtained by adding the data after normalization of FIG. 5D shifted by two lines.

  FIG. 5A corresponds to the video signal of FIG. 1, and data of the area from gradation 0 to 255 corresponding to one color of each of R (red), G (green), and B (blue). Is part of. Since the RGB video signal created from the television signal includes a signal that is wider than the actual display area, in this example, the actual display area is the third and subsequent lines from the top, and the upper two lines are as follows: This data is used for processing without contradiction.

The original image data in FIG. 5A is input to the edge enhancement processing circuit 12. The edge enhancement processing performed in the edge enhancement processing circuit 12 is enhancement processing for the row direction, and in the example of FIG.
New B = 1.5 × B-0.5 × A
It was. Besides the example here,
New B = 2.5 × BA-0.5 × C
There are several formulas with different emphasis levels.

  The edge enhancement processing is not limited to these, and an arbitrary method can be adopted from the compatibility of the video signal and the display. A fourth embodiment in which edge enhancement processing is not performed will be described later.

  In FIG. 5B, as a result of edge emphasis, some coordinates protrude from the original gradation region 0 to 255 mainly downward. For example, the data value is “−30”.

  Therefore, the protruding coordinates are limited within the area by the normalization processing circuit 13. In the present embodiment, the third method described above with reference to FIG. 1 is illustrated. FIG. 5 (c) shows the first half of the normalization process. “Negative values are added to the upper and lower pixels by a quarter of the value. The result of “add to pixel” is shown. FIG. 5D shows a result of performing the latter half of the normalization process “after that, the corresponding pixel is set to 0 or 255”.

In FIG. 5E to FIG. 5H, the original 8-bit gradation region 0 to 255 is set to 2 upward.
This is a gradation region from 0 to 511 that is double-extended, and the values in each figure are gradation intensity values representing relative gradation intensities. The brightness of each color of the display changes in accordance with the characteristics of the phosphor of the display, precisely in proportion to the relative gradation intensity value.

  FIG. 5F shows a luminance output value obtained when two lines are simultaneously driven by the driving waveform described in FIG. 4 without performing data processing such as edge enhancement processing.

  FIG. 5G shows the luminance output value that should be obtained if the two-line simultaneous driving can be similarly performed on the data subjected to the edge enhancement processing of FIG. 5B. This luminance output value is close to the value shown in FIG. However, the edge-enhanced data in FIG. 5B cannot be realized because it includes values outside the region.

  Therefore, in the third embodiment, the luminance output obtained by simultaneously driving two lines in FIG. 5 (h) is obtained using the normalized data in FIG. 5 (e). Since the luminance output in FIG. 5 (h) is a value close to the value shown in FIG. 5 (e), the luminance is almost twice that of the original image data in FIG. 5 (a).

[Example 4]
Next, as a fourth embodiment, an example in which two lines are driven simultaneously without performing edge emphasis processing will be described.

  In the present embodiment, the luminance output (corresponding gradation intensity value) to be obtained is a value twice that of the original image data shown in FIG. For normal video, a luminance output as close as possible to this is desirable, but a soft display such as a movie is preferred. If the original video signal has a graininess or block noise is noticeable, a better display output can be obtained without edge enhancement.

  In the present embodiment, in FIG. 1, the edge enhancement processing circuit 12 and the normalization circuit 13 do not perform the respective processes, and the control circuit 11 adjusts to the same timing as when processing is performed with respect to the data timing. Then, the waveform of FIG. 4 is obtained.

  The output luminance is the luminance corresponding to the gradation intensity corresponding to FIG.

[Example 5]
Next, in the fifth embodiment, an example in which the row drive voltage is driven with three kinds of voltages will be described with reference to FIGS.

  FIG. 6 shows voltage waveforms output from the row driving circuit of the self-luminous display according to the fifth embodiment.

  In FIG. 6, 21 is a Tscan Hsync signal waveform input to the row drive circuit, 61 is a waveform for driving the first row A, 62 is a waveform for driving the second row B, and the following rows C, D, E , F is a waveform for driving F.

The non-selection voltage Vns is a voltage on the higher side of the waveforms 61 and 62 (for example, 5 V) in this figure, and the voltage Vs is a voltage on the lower side of the waveforms 61 and 62 (for example, −5 V) in FIG. In addition, in this embodiment, there is a half-select voltage Vhs, which is the middle voltage of the waveforms 61 and 62.

  The voltages Vhs, Vs, and Vhs in the waveforms 61 and 62 are driven in this order every time the row sync signal 21 rises. Each time the row sync signal 21 rises, the adjacent row changes to voltages Vhs, Vs, Vhs.

  Thus, the selection voltage Vs is always in only one row. At that time, the preceding and succeeding rows become the half-select voltage Vhs.

  In the electron-emitting device column to which the column driving voltage Ve (for example, 10 V) is applied, only the electron-emitting device to which the selection voltage (for example, −5 V) is applied becomes, for example, 15 V, and the half-selection voltage (for example, −2 V). For example, 12V is applied to the two electron-emitting devices to which is added.

These three electron-emitting devices emit electrons that exceed a threshold voltage Vth (for example, 8 V), and as a result, electrons are emitted from the three electron-emitting devices for each column to which the voltage Ve is applied. Become. At this time, in the graph of FIG. 10, it is assumed that the emission current Ie at the element voltage 12V is about half of the emission current at the element voltage 15V. In order to simplify the explanation, the voltage Vhs is determined so that the emission current Ie is exactly half. However, actually, the emission current Ie is not half and may be 1/3 or 2/3. Depending on the value of the voltage Vhs, the emission current Ie can be set to any value between 0 and 1 times.

  FIG. 7 is a diagram showing the correlation between data processing and output luminance in the fifth embodiment of the present invention.

  Since the data shown in FIGS. 7A to 7D are the same as those shown in FIGS. 3A to 3D, description thereof will be omitted.

  FIG. 7E shows a value obtained by simply doubling the “original image” data in FIG. FIG. 7F shows a value obtained by adding each half of the upper and lower lines to each line of the “original image” data in FIG. FIG. 7G shows a value obtained by adding each half of the upper and lower lines to each line of “data after edge enhancement processing” in FIG. FIG. 7H shows a value obtained by adding each half of the upper and lower lines to each line of the “after normalization” data in FIG.

  In FIG. 7 (e) to FIG. 7 (h), the original 8-bit gradation region 0 to 255 is a gradation region extending from 0 to 511, and the values in the figure are relative. This is a gradation intensity value representing the gradation intensity. The brightness of each color of the display changes in accordance with the characteristics of the phosphor of the display, precisely in proportion to the relative gradation intensity value.

FIG. 7F shows the luminance output value obtained when 3-line auxiliary driving is performed with the driving waveform described in FIG. 6 without performing data processing such as edge enhancement processing. Here, the case where the center is driven by the voltage Vs and the upper and lower rows thereof are driven by the voltage Vhs is referred to as “3-line auxiliary driving”.
In the case of 3-line auxiliary driving, the luminance output of each line is added to half the luminance output of the vertical line.

The half here is an example, and takes a value between 0 and 1 depending on the voltage Vhs as described above.

  FIG. 7G shows luminance output values that should be obtained if 3-line auxiliary driving can be performed on the data subjected to the edge enhancement processing of FIG. 7B in the same manner. This luminance output value is close to the value shown in FIG. However, the edge-enhanced data in FIG. 7B cannot be realized because it includes values outside the region.

  Therefore, in the seventh embodiment, the luminance output subjected to the three-line auxiliary driving shown in FIG. 7H is obtained using the data after normalization shown in FIG. 7E. Since the luminance output in FIG. 7 (h) is a value relatively close to the value shown in FIG. 7 (e), a luminance almost twice that of the original image data in FIG. 7 (a) can be obtained. .

[Example 6]
The present invention is applicable not only to the FED and SED, which is one of its advanced forms, but also to all self-luminous displays as long as a passive matrix is used.

  Next, as a sixth embodiment, an embodiment in a display using a PDP is shown.

  FIG. 11 is a block diagram of a drive unit in a PDP (plasma display panel).

  In the figure, 201 is a panel body using plasma emission, 202 is a data side driver circuit (data driver), 203 is a scanning side scanning driver (drive circuit), and 204 is a mixer for setting the scanning signal to a high voltage. 205 denote high-voltage supply circuits.

  FIG. 12 shows an example of an address waveform of the scanning signal of the conventional example.

In FIG. 12, reference numeral 211 denotes a line scanning synchronization signal, 212 denotes a line A scanning signal, 21.
3 is a scanning signal for line B, 214 is an address pulse for activating that line, 2
Reference numeral 15 denotes an erase pulse for stopping the plasma emission.

As shown in FIG. 12, in the conventional PDP, only one line is activated, and only the active pixel portion of the signal from the data side emits plasma.

In addition, in the PDP, there is an interlaced driving method called the ALIS method, which is a method of emitting light by activating two lines and activating a region between the two lines.

  FIG. 13 shows an address waveform of a scanning signal according to the sixth embodiment of the present invention.

In FIG. 13, reference numeral 221 denotes a synchronization signal for line scanning, 222 denotes a scanning signal for line A, 22
Reference numeral 3 denotes a scanning signal of line B. Reference numeral 224 denotes a first address pulse that activates the line, 225 denotes an erase pulse that stops plasma emission, and 226 denotes a second address pulse that activates the line.

As shown in FIG. 13, in the sixth embodiment, two line (address) electrodes in the PDP are simultaneously activated so as to overlap each other. The second address pulse 226 on line A in FIG. 13 and the first address pulse on line B become active simultaneously, and light is emitted from two lines.

  When applied to the ALIS system, it is possible to simultaneously emit light between the upper and lower lines as seen from the center line by simultaneously activating the three lines.

  Similarly to the first to fifth embodiments in FED and SED, the number of lines to be activated is the same regardless of whether it is 2, 3, or more. It is the same.

[Example 7]
In the seventh embodiment, an example in which an organic EL panel is used as an example of another matrix-driven self-luminous display will be described.

  FIG. 14 is a block diagram of a matrix-driven self-luminous display using an organic EL panel.

  In FIG. 14, reference numeral 231 denotes an organic EL panel, 232 denotes a data driver, and 233 denotes a scanning driver.

  The drive waveform of the scan driver 233 is similar to that of FIGS. 2, 4 and 6 although the voltage value is different from that of the FED or SED.

  The video data supplied to the data driver 232 is the same as in FIGS. 3, 5, and 7.

[Example 8]
In the eighth embodiment, an example in which an LED matrix is used as an example of another matrix-driven self-luminous display will be described.

  FIG. 15 is a block diagram of a self-luminous display using an LED matrix.

In FIG. 15, 241 is an LED matrix display, 242 is each LED,
Reference numeral 3 denotes a scanning driver, and 244 denotes a data driver.

  About the drive waveform of the scanning side driver 243, although voltage value differs from FED and SED, it is the same waveform and is the same waveform as FIG.2, FIG4 and FIG.6.

  The video data supplied to the data driver 244 is also the same as that shown in FIGS.

  In the first to eighth embodiments, the edge enhancement circuit 12 and the normalization circuit 13 can pass the data without processing by outputting the data to the column drive circuit 104. Further, by switching the edge emphasis table according to the number of drive lines, it is possible to cope with the number of lines of 2, 3, or more.

  In addition, when the luminance deterioration can be tolerated, the control circuit 11 outputs a single-line driving waveform as shown in FIG. 9 of the conventional example, and outputs a driving waveform in which the number of simultaneous drives is increased with the luminance deterioration.

  Whether or not the luminance is deteriorated can be simply determined by the usage time of the display device. Therefore, the degree of luminance degradation can be evaluated by calculating the usage time (cumulative value of usage time) of the display device.

  To make a precise decision, the cumulative value of APL (Average Picture Level) of the display data is calculated, and the value is judged. Note that the calculation unit that calculates a value related to luminance degradation is not limited to a configuration that calculates a value by executing a program. For example, the display device may include a measuring device such as a photodetector that measures luminance. In this case, the measurement device itself or a signal processing unit that processes the measurement value of the measurement device corresponds to the calculation unit.

  FIG. 16 is a graph showing an outline of the relationship between the number of simultaneous drives and the luminance with an increase in usage time.

  In FIG. 16, 311 is a relationship diagram between the use time and the luminance (FIG. 16A), and 312 is a relationship diagram between the use time and the number of simultaneous drives (FIG. 16B). In FIG. 16, 313 is a graph of luminance deterioration in the simple driving of the conventional example, 314 is a graph of luminance deterioration when switching the simultaneous driving number of the present invention, and 315 is a switching of the simultaneous driving number of the present invention. The shown graph is shown.

  In the conventional display device, as shown in the graph 313, the luminance is deteriorated due to the deterioration of the phosphor or the like as the usage time elapses.

  In the present invention, as the usage time elapses, the number of simultaneous drives is increased from 1 line to 2, 3, 4, 5 lines as shown in the graph 315, and as shown in the graph 314. Maintain a constant brightness.

  Note that, by increasing the number of simultaneous drives, the luminance deterioration of the phosphors and the like per time increases, and the slope of the graph 314 becomes steep, but a region with a certain luminance or higher can be secured for a long time.

When the number of simultaneous drives changes from 1 line to 2 lines, or from 2 lines to 3 lines, the screen is suddenly brightened, so that it does not surprise the user. Executed. Further, if the number of simultaneous driving is changed, if other settings are left as they are, the brightness becomes strangely bright, so that a process for changing the brightness adjustment value (brightness setting, etc.) set by the user is performed.

  The configuration and operation of this operation will be described in detail.

  FIG. 17 is a circuit block diagram for measuring usage time and selecting a drive waveform.

In FIG. 17, reference numeral 321 denotes an MPU (micro processing unit) that measures usage time and selects a driving waveform. Reference numeral 322 denotes a RAM for storing the usage time calculated by the MPU 321, and reference numeral 323 denotes a battery for preventing data in the RAM from being lost when the power is turned off.

  A processing procedure in the MPU 321 will be described with reference to FIGS. 18 and 19. Further, a flash ROM may be used instead of the RAM 322 and the battery 323.

  18 and 19 are diagrams illustrating the processing procedure of the MPU 321. FIG.

  Hereinafter, each processing step will be described.

<Update cumulative usage time>
Processing is started every minute by interrupt processing using the counter in the MPU 321 (step 331).

  In step 332, the MPU 321 reads the accumulated usage time of the display device from the RAM 322. It is assumed that 0 is written as the cumulative usage time at the time of the first factory shipment. Alternatively, the aging time in the factory may be written. After the user starts use, it is the accumulated use time written in the subsequent step 334.

  In step 333, the MPU 321 adds “1” to the read accumulated usage time.

  In step 334, the MPU 321 writes the calculated accumulated usage time in the RAM 322.

  In step 335, the process returns to another process.

<Determining the number of simultaneous drives using accumulated usage time>
The MPU 321 starts processing as part of a startup routine that is executed each time the power of the display device changes from OFF to ON (step 341).

  In step 342, the MPU 321 reads the accumulated usage time from the RAM 322.

  In step 343, the simultaneous drive number is determined based on the numerical value of the accumulated usage time. Parameters for determining the number of simultaneous drives are determined in advance from phosphor deterioration data or the like. For example, if the luminance deteriorates by 40% at 20000 hours, it is determined that a plurality of lines are driven simultaneously after 20000 hours (= 1200000 minutes). For example, the following usage time is determined as follows.

[The following units are minutes]
0 to 1200000: Simple drive 120001 to 2000000: 2 line simultaneous drive 200001 to 2600000: 3 line simultaneous drive 2600001 to 3000000: 4 line simultaneous drive 3000001 to 5 line simultaneous drive Next, in step 344, the edge shown in FIG. A conversion table is set for the emphasis circuit 12 and the normalization circuit 13 according to the number of simultaneous drives determined in the previous step.

  In step 345, similarly, the simultaneous drive number of the control circuit 11 shown in FIG. 1 is set.

  When the setting of the present embodiment is thus completed, the process returns to the next process in the startup routine in step 346.

  As described above, the embodiment in which the number of simultaneous drives is switched according to the accumulated usage time (accumulated value related to luminance degradation) has been described. Next, an embodiment in which the simultaneous drive number is switched according to the accumulated value of the display data will be described.

<Update cumulative APL value>
FIG. 20 is a circuit block diagram for measuring a cumulative value of display data and selecting a drive waveform.

  In FIG. 20, 321 is an MPU that measures the usage time and selects a drive waveform, 322 is a RAM for storing the usage time calculated by the MPU 321, and 323 is a RAM so that data in the RAM is not lost when the power is turned off. The battery for doing is shown. Reference numeral 351 denotes a circuit that measures an APL value from display data for each frame, and reference numeral 352 denotes a circuit that cumulatively adds the outputs of the APL measurement circuit 351.

  In the APL detection circuit 351, the value of the display data is added by an adder for one frame, and a value divided by the number of data for one frame is output. The cumulative adder 352 is a circuit that cumulatively adds the outputs. After the MPU 321 reads, the accumulated value returns to zero.

  21 and 22 are flowcharts showing a processing procedure in the MPU 321.

  Hereinafter, each processing step will be described.

  Processing is started every minute by an interrupt using a counter in the MPU 321 (step 361).

  In step 362, the MPU 321 reads the accumulated APL value of the display device from the RAM 322. This accumulated APL value is written with 0 at the time of the first factory shipment. Alternatively, a value corresponding to the data displayed during the aging period in the factory may be written. After the user starts use, it is the accumulated APL value written in the subsequent step 365.

In step 363, the cumulative APL value for 1 minute is read from the cumulative adder 352. In step 364, the following calculation is performed.
New cumulative APL value = 1 minute cumulative APL value / number of frames per minute + old cumulative APL value

In step 365, a new cumulative APL value is written in the RAM 322. In step 366, the process returns to another process.

<Determining the number of simultaneous drives using the cumulative APL value>
The MPU 321 starts processing as part of a startup routine that is executed each time the power of the display device is changed from OFF to ON (step 341).

In step 372, the accumulated APL value is read from the RAM 322. In step 373, the simultaneous drive number is determined from the accumulated APL value. Parameters for this purpose are determined in advance from phosphor deterioration data and the like. For example, when the APL for one minute is 30% and the display device is used for 20000 hours, it is determined that the display device has a 40% luminance deterioration and a plurality of lines are driven simultaneously. At this time, 20000 hours is 1200000 minutes. When the APL value “0.3” is applied to convert the accumulated APL value to 360000 (minutes), a plurality of lines are simultaneously driven. The accumulated APL values thereafter are also determined as follows, for example.

[The following units are minutes]
0 to 360000: Simple drive 360001 to 600000: 2 line simultaneous drive 600001 to 780000: 3 line simultaneous drive 780001 to 900000: 4 line simultaneous drive 900001 to: 5 line simultaneous drive

For example, (i) 100% (= 1) is displayed when white is displayed for 1 minute, (ii) 30 seconds 120 data is displayed, and 30 seconds 64 data is displayed 36% (= 0.36). )become. The APL values for 1 minute are (i) “1” and (ii) “0.36”, respectively, and the accumulated APL value for 2 minutes is “1.36 (= 136%)”.
At this time, when the displays (i) and (ii) are repeatedly executed 264706 times (529412 minutes), the cumulative APL value is “1.36 × 264706 = 360000.16 (minutes)”. After the accumulated APL value is 360001 minutes (actual time 5294413 minutes), two lines are driven simultaneously.

  Next, in step 344, a table is set in accordance with the number of simultaneous drivings determined in the previous step for the edge enhancement circuit 12 and normalization circuit 13 shown in FIG.

  In step 345, similarly, the simultaneous drive number of the control circuit shown in FIG. 1 is set.

  When the setting of the embodiment of the present invention is thus completed, the process returns to the next process in the startup routine at step 346.

  In this way, it is possible to substantially extend the luminance life of the display device by changing the number of simultaneous drives.

  When the display device is used as a display of a TV device for a long time, the luminance decreases due to deterioration of the phosphor and the electron source of the display device. Even in such a case, by performing line doubler or line tripler, it is possible to secure luminance, extend the period of using the display device, and delay the life of the TV device. .

  In addition, when used as a display device such as a PC, the period of use of the display device can be lengthened by increasing the brightness of the display device by operating the present embodiment, thereby delaying the life of the display device. It becomes possible.

It is a block diagram which shows the circuit structure of the self-light-emitting display of 1st Example of this invention. It is a voltage waveform which the row drive circuit of the self-luminous display of the first embodiment of the present invention outputs. FIG. 4 is a diagram showing a correlation between data processing and output luminance in the first embodiment of the present invention. It is a voltage waveform which the row drive circuit of the self-luminous display of 3rd Example of this invention outputs. FIG. 10 is a diagram showing a correlation between data processing and output luminance in the third embodiment of the present invention. It is a voltage waveform which the row drive circuit of the self-luminous display of 5th Example of this invention outputs. FIG. 10 is a diagram showing a correlation between data processing and output luminance in the fifth embodiment of the present invention. It is a block diagram which shows the circuit structure of the self-luminous type display of a prior art example. It is a voltage waveform which the row drive circuit of a prior art example outputs. It is a figure which shows the relationship between element voltage and threshold voltage, element current, and emission current. It is a block diagram of the drive part in PDP (plasma display panel). It is a figure which shows the scanning signal of a prior art example. It is a figure which shows the scanning signal of 6th Example of this invention. It is a block diagram of a matrix driving self-luminous display using an organic EL panel. It is a block diagram of a self-luminous display using an LED matrix. It is the graph which showed the outline of the relationship between the number of simultaneous drives by use time, and a luminance. It is a circuit block diagram for measuring a usage time and selecting a drive waveform. It is the figure which showed the content which MPU321 processes. It is the figure which showed the content which MPU321 processes. It is a circuit block diagram for measuring the cumulative value of display data and selecting a drive waveform. It is the figure which showed the content which MPU321 processes. It is the figure which showed the content which MPU321 processes. It is a block diagram of the television apparatus which concerns on a present Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Control circuit 12 Edge emphasis circuit 13 Normalization circuit 101 Display panel 102 Row drive circuit 104 Column drive circuit 105 Power supply 106 Acceleration voltage power supply

Claims (5)

A plurality of row wirings can be selected at the same time, and a scan driver that supplies a scanning selection signal to the selected row wirings;
A data driver for supplying a modulation signal based on image data to a column wiring in synchronization with the scan selection signal;
A calculation unit for calculating a value related to luminance degradation of the display device;
A control circuit that controls the scan driver to increase the number of row wirings to be selected simultaneously when a value related to luminance degradation calculated by the calculation unit exceeds a predetermined value;
A drive control device for a display device. A plurality of row wirings can be selected at the same time, and a scanning driver that supplies a scanning selection signal to the selected row wirings;
A data driver for supplying a modulation signal based on image data to a column wiring in synchronization with the scan selection signal;
A first display mode in which only one row wiring is selected and a first driving voltage is applied to the display element of the display device, and a plurality of row wirings are selected at the same time, and a second lower than the first driving voltage is selected. A control circuit for selecting one of a second display mode in which a driving voltage is applied to the pixel;
A drive control device for a display device. The display device drive control device according to claim 2, wherein the pixel includes a cathode, a gate, and an anode, and the drive voltage is a cathode-anode voltage or a cathode-gate voltage. The drive control device according to any one of claims 1 to 3,
An image display device comprising: a display device that displays an image according to a modulation signal output from the drive control device. An image display device according to claim 4,
A television apparatus comprising: a receiving circuit that receives a television signal and supplies image data to the image display device.

Images