[go: up one dir, main page]

JP2007036012A - Chip resistor for large electric power - Google Patents

Chip resistor for large electric power Download PDF

Info

Publication number
JP2007036012A
JP2007036012A JP2005218697A JP2005218697A JP2007036012A JP 2007036012 A JP2007036012 A JP 2007036012A JP 2005218697 A JP2005218697 A JP 2005218697A JP 2005218697 A JP2005218697 A JP 2005218697A JP 2007036012 A JP2007036012 A JP 2007036012A
Authority
JP
Japan
Prior art keywords
chip resistor
insulating substrate
terminal electrodes
resistance
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005218697A
Other languages
Japanese (ja)
Inventor
Masaki Yoneda
将記 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2005218697A priority Critical patent/JP2007036012A/en
Priority to US11/922,518 priority patent/US7733211B2/en
Priority to CN2006800222941A priority patent/CN101203922B/en
Priority to EP06766972A priority patent/EP1914760A1/en
Priority to PCT/JP2006/312311 priority patent/WO2006137392A1/en
Priority to KR1020077029737A priority patent/KR20080043268A/en
Priority to TW095122306A priority patent/TW200705469A/en
Publication of JP2007036012A publication Critical patent/JP2007036012A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Details Of Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To plan a large electrification of a chip resistor and an improvement of an anti-surge property in the chip resistor constituted by forming a resistive film and terminal electrodes corresponding to both ends of the resistive film on an insulating substrate. <P>SOLUTION: While forming terminal electrodes 3 for a solder connection at both right and left sides 2' in an insulating substrate 2 made into a rectangular form, at a portion between the both terminal electrodes out of a top face in the insulating substrate, there are arranged in parallel plural resistive films 4 whose both ends conduct to the both terminal electrodes. Each of these resistive films 4 is constituted to be a zigzag form from a terminal electrode at one end toward a terminal electrode at the other end. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は,チップ型にした絶縁基板の表面に抵抗膜を形成して成るチップ抵抗器のうち,大電力に対応できるように構成したチップ抵抗器に関するものである。   The present invention relates to a chip resistor configured to cope with high power among chip resistors formed by forming a resistance film on the surface of a chip-type insulating substrate.

従来,この種のチップ抵抗器Aは,例えば,特許文献1等に記載され,且つ,図4に示すように,長さ寸法がLで,幅寸法がWの長方形にした絶縁基板A1の上面に,抵抗膜A2を絶縁基板A1における長さ方向に延びるように形成する一方,前記絶縁基板A1における長さ方向の両端面A1′に,前記抵抗膜A2の両端に対する端子電極A3を形成して,この両端子電極A3を,プリント基板等に対して半田付けにて実装するという構成にしている。   Conventionally, this type of chip resistor A is described in, for example, Patent Document 1 and the like, and as shown in FIG. 4, the upper surface of an insulating substrate A1 having a rectangular length of L and a width of W is used. Further, the resistance film A2 is formed to extend in the length direction of the insulating substrate A1, while the terminal electrodes A3 for the both ends of the resistance film A2 are formed on both end surfaces A1 ′ in the length direction of the insulating substrate A1. The both terminal electrodes A3 are mounted on a printed circuit board or the like by soldering.

但し,この図3において符号A4は,抵抗値調整用のトリミング溝である。
特開平11−273901号公報
However, in FIG. 3, symbol A4 is a trimming groove for adjusting the resistance value.
JP 11-273901 A

前記図4に示す従来のチップ抵抗器Aにおいては,プリント基板等に対して半田付けされる左右一対の端子電極A3の間に,一つの抵抗膜A2を設けて成るという形態であることにより,両端子電極A3に対する印加電力が,その間の一つに抵抗膜A2に集中し,当該一つの抵抗膜A2における温度上昇が大きくなるから,大電力用に適用することができないという問題があった。   The conventional chip resistor A shown in FIG. 4 has a configuration in which one resistive film A2 is provided between a pair of left and right terminal electrodes A3 soldered to a printed circuit board or the like. The power applied to both terminal electrodes A3 is concentrated on the resistance film A2 in one of them, and the temperature rise in the one resistance film A2 becomes large, so that there is a problem that it cannot be applied for high power.

この場合において,図5に示すように,前記と同じ長方形サイズ(長さ寸法Lを同じにするとともに,幅寸法Wを同じにする)にした絶縁基板B1において,その上面に,当該絶縁基板B1における幅方向に延びる抵抗膜B2の複数個を,長さ方向に並列に形成する一方,前記絶縁基板B1における長さ方向の左右両側面,つまり,左右両長手側面B1′に,前記各抵抗膜B2について共通の端子電極B3を形成するというように多連のチップ抵抗器Bに構成することにより,印加電力を複数の抵抗膜B2に分散できるから,前記図4の図示したチップ抵抗器Aと同じ長方形サイズのままで,大電力化を図ることができる。   In this case, as shown in FIG. 5, in the insulating substrate B1 having the same rectangular size (the same length dimension L and the same width dimension W) as described above, the insulating substrate B1 is formed on the upper surface thereof. A plurality of resistance films B2 extending in the width direction are formed in parallel in the length direction, while the resistance films B2 are formed on both left and right side surfaces in the length direction of the insulating substrate B1, that is, on both left and right long side surfaces B1 '. By configuring the multiple chip resistors B to form a common terminal electrode B3 for B2, the applied power can be distributed to the plurality of resistive films B2, so that the chip resistor A shown in FIG. High power can be achieved with the same rectangular size.

しかし,その反面,この多連のチップ抵抗器Bにおける各抵抗膜B2は,絶縁基板B1における幅方向に延びる長さであることにより,その電流経路の長さが,前記図4のチップ抵抗器Aの場合よりも大幅に短くなるから,静電気や電源ノイズ等の影響で発生するサージ電圧が印加した場合における抵抗値の変化率が大きくて,耐サージ特性が低いという問題がある。   However, on the other hand, each resistive film B2 in this multiple chip resistor B has a length extending in the width direction of the insulating substrate B1, and therefore the length of the current path is the chip resistor of FIG. Since it is much shorter than the case of A, there is a problem that the rate of change in resistance value is large when a surge voltage generated due to the influence of static electricity or power supply noise is applied and the surge resistance is low.

本発明は,大電力に適合し,且つ,耐サージ特性の高いチップ抵抗器を提供することを技術的課題とするものである。   An object of the present invention is to provide a chip resistor that is suitable for high power and has high surge resistance.

この技術的課題を達成するため本発明の請求項1は,
「矩形にした絶縁基板における左右両側面に,半田接続用の端子電極を形成する一方,前記絶縁基板における上面のうち前記両端子電極間の部分に,両端が両端子電極に導通する複数個の抵抗膜を,並列に並べて形成し,この抵抗膜の各々を,その一端における端子電極からその他端における端子電極に向かってつづら折りに構成する。」
ことを特徴としている。
In order to achieve this technical problem, claim 1 of the present invention provides:
“A plurality of terminal electrodes for solder connection are formed on both the left and right side surfaces of the rectangular insulating substrate, while both ends of the upper surface of the insulating substrate are electrically connected to both terminal electrodes. The resistive films are formed side by side, and each of the resistive films is configured to be folded from the terminal electrode at one end to the terminal electrode at the other end.
It is characterized by that.

また,請求項2は,
「前記請求項1の記載において,前記絶縁基板が長方形であり,前記両端子電極が,前記絶縁基板における左右両長手側面に形成されている。」
ことを特徴としている。
Claim 2
“In the first aspect of the present invention, the insulating substrate is rectangular, and the terminal electrodes are formed on both left and right longitudinal sides of the insulating substrate.”
It is characterized by that.

前記請求項1に記載した構成にすることにより,両端子電極に対する印加電力は,複数個の各抵抗膜に分散されることになるから,大電力に適応することができる一方,前記各抵抗膜は,つづら折りで電流経路の長さが長いから,サージ電圧が印加した場合における抵抗値の変化率が小さくなり,耐サージ特性を向上できる。   With the configuration described in claim 1, since the applied power to both terminal electrodes is distributed to a plurality of resistance films, it can be adapted to a large power, while each of the resistance films Since the length of the current path is long due to zigzag folding, the rate of change in resistance when a surge voltage is applied is reduced, and surge resistance can be improved.

特に,請求項2に記載した構成によると,長方形のサイズを変更することなく,大電力化と,耐サージ特性の向上とを図ることができる。   In particular, according to the configuration described in claim 2, it is possible to increase the power and improve the surge resistance without changing the size of the rectangle.

以下,本発明の実施の形態を図面について説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図1〜図3は,本発明の実施の形態によるチップ抵抗器1を示す。   1 to 3 show a chip resistor 1 according to an embodiment of the present invention.

このチップ抵抗器1は,セラミック等の耐熱絶縁体製の絶縁基板2を備え,この絶縁基板2は,長さ寸法がLで,幅寸法がWの長方形に形成されている。   The chip resistor 1 includes an insulating substrate 2 made of a heat-resistant insulator such as ceramic. The insulating substrate 2 is formed in a rectangular shape having a length dimension L and a width dimension W.

前記絶縁基板2におけるその長さ方向の左右両側面,つまり,左右両長手側面2′には,半田接続用の端子電極3を,長手側面2′に沿って延びるように形成している。   Terminal electrodes 3 for solder connection are formed so as to extend along the longitudinal side surface 2 'on the left and right side surfaces in the length direction of the insulating substrate 2, that is, both the left and right longitudinal side surfaces 2'.

一方,前記絶縁基板2における上面のうち前記両端子電極3の間の部分には,抵抗膜4の複数個(図面は,3個にした場合を示す)が,絶縁基板2の長さ方向に適宜間隔で並列状に並べて形成されており,この各抵抗膜4は,その両端が前記両端子電極3に対して電気的に導通されている。   On the other hand, in the upper surface of the insulating substrate 2, a plurality of resistance films 4 (the figure shows the case of three) are provided in the length direction of the insulating substrate 2 between the terminal electrodes 3. The resistance films 4 are formed in parallel at appropriate intervals. Both ends of the resistance films 4 are electrically connected to the terminal electrodes 3.

しかも,前記各抵抗膜4は,当該抵抗膜における一方の側面4′からの複数本(図面では二本)の入り込み溝5と,他方の側面4″からの複数本(図面では二本)の入り込み溝6とを交互に設けることにより,つづら折りに構成されている。   Moreover, each of the resistance films 4 includes a plurality of (two in the drawing) entering grooves 5 from one side surface 4 ′ and a plurality of (two in the drawing) from the other side surface 4 ″. By alternately providing the entering grooves 6, it is configured to be folded in a zigzag manner.

また,前記絶縁基板2の上面には,前記各抵抗膜4の全体を覆うカバーコート7が形成されている。   A cover coat 7 is formed on the upper surface of the insulating substrate 2 to cover the entire resistance film 4.

なお,前記各抵抗膜4は,当該抵抗膜4をスクリーン印刷にて形成するときに同時に入り込み溝5,6を設けることによって,つづら折りに構成しても良いが,前記入り込み溝5,6の一部又は全部を,スクリーン印刷した後でのレーザ光線の照射等の加工によって刻設することによって,つづら折りに構成しても良い。   Each of the resistance films 4 may be formed in a zigzag manner by providing the entry grooves 5 and 6 at the same time when the resistance film 4 is formed by screen printing. A part or the whole may be formed into a zigzag fold by engraving by processing such as laser beam irradiation after screen printing.

前記した構成において,両端子電極3に対する印加電力は,複数個の各抵抗膜4に分散されることになるから,大電力に適応することができる一方,前記各抵抗膜4は,つづら折りでであることにより,電流経路の長さが長いから,サージ電圧が印加した場合における抵抗値の変化率が小さくなり,耐サージ特性を向上できる。   In the above-described configuration, the applied power to both terminal electrodes 3 is dispersed in each of the plurality of resistance films 4, so that it can be adapted to high power, while each of the resistance films 4 is folded in a zigzag manner. As a result, since the length of the current path is long, the rate of change in resistance value when a surge voltage is applied is reduced, and surge resistance can be improved.

図6及び図7は,前記図1〜図3に示す本発明によるチップ抵抗器1,前記図4に示す従来のチップ抵抗器A及び前記図5に示す多連のチップ抵抗器Bを,同じ長方形サイズ(長さ寸法Lを同じにするととにも,幅寸法Wを同じにする)して,その性能比較した実験結果を示す。   6 and 7 are the same as the chip resistor 1 according to the present invention shown in FIGS. 1 to 3 and the conventional chip resistor A shown in FIG. 4 and the multiple chip resistors B shown in FIG. The results of experiments comparing the performance of rectangular sizes (with the same length dimension L and the same width dimension W) are shown.

すなわち,図6は,両端子電極に対して電力を印加した場合に抵抗膜の表面における温度上昇を示すもので,前記従来のチップ抵抗器Aの場合には,温度上昇が,一点鎖線Cで示すように大きいのに対し,前記本発明によるチップ抵抗器1及び前記多連のチップ抵抗器Bの場合には,温度上昇が,実線Dで示すように大幅に低くことができるのであった。   That is, FIG. 6 shows a temperature rise on the surface of the resistance film when power is applied to both terminal electrodes. In the case of the conventional chip resistor A, the temperature rise is indicated by a one-dot chain line C. In contrast, in the case of the chip resistor 1 according to the present invention and the multiple chip resistor B according to the present invention, the temperature rise can be greatly reduced as shown by the solid line D.

次に,図7は,静電破壊試験(耐サージ特性評価)を示すもので,前記多連のチップ抵抗器Bの場合には,抵抗値の変化が,一点鎖線Eで示すように可成り大きいのに対し,前記本発明によるチップ抵抗器1及び前記従来のチップ抵抗器Aの場合には,抵抗値の変化が,実線Fで示すように大幅に小さくできることができるのであった。   Next, FIG. 7 shows an electrostatic breakdown test (evaluation of surge resistance). In the case of the multiple chip resistor B, the change in the resistance value is significant as shown by the alternate long and short dash line E. On the other hand, in the case of the chip resistor 1 according to the present invention and the conventional chip resistor A, the change in the resistance value can be greatly reduced as indicated by the solid line F.

これらの実験により,本発明によると,従来のチップ抵抗器1と同じ長方形サイズにした状態のもとで,大電力化と,耐サージ特性の向上とを図ることができることが明らかになった。   From these experiments, it has been clarified that according to the present invention, the power can be increased and the surge resistance can be improved under the same rectangular size as the conventional chip resistor 1.

なお,本実施の形態の場合,前記絶縁基板2における左右両長手側面2′には,少なくとも一つの凹所8を設けて,この凹所8の内面にも,端子電極3を形成して,プリント基板9等への半田付けに際して半田フレットが,前記凹所8内の部分にまで盛り上がるように構成することにより,半田付け強度の向上を図るようにしている。   In the case of the present embodiment, at least one recess 8 is provided on the left and right longitudinal side surfaces 2 ′ of the insulating substrate 2, and the terminal electrode 3 is formed on the inner surface of the recess 8. When soldering to the printed circuit board 9 or the like, the solder fret is constructed so as to rise up to the portion in the recess 8 so as to improve the soldering strength.

本発明の実施の形態によるチップ抵抗器の平面図である。It is a top view of the chip resistor by an embodiment of the invention. 図1のII−II視断面図である。It is the II-II sectional view taken on the line of FIG. 図1のIII −III 視断面図である。FIG. 3 is a sectional view taken along line III-III in FIG. 1. 従来のチップ抵抗器を示す斜視図である。It is a perspective view which shows the conventional chip resistor. 従来の多連チップ抵抗器を示す斜視図である。It is a perspective view which shows the conventional multiple chip resistor. 抵抗膜の表面における温度上昇を示す図である。It is a figure which shows the temperature rise in the surface of a resistance film. 静電破壊試験の結果を示す図である。It is a figure which shows the result of an electrostatic breakdown test.

符号の説明Explanation of symbols

1 チップ抵抗器
2 絶縁基板
2′ 長手側面
3 端子電極
4 抵抗膜
5,6 入り込み溝
7 カバーコート
DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Insulation board | substrate 2 'Long side surface 3 Terminal electrode 4 Resistive film | membrane 5,6 Entering groove | channel 7 Cover coat

Claims (2)

矩形にした絶縁基板における左右両側面に,半田接続用の端子電極を形成する一方,前記絶縁基板における上面のうち前記両端子電極間の部分に,両端が両端子電極に導通する複数個の抵抗膜を,並列に並べて形成し,この抵抗膜の各々を,その一端における端子電極からその他端における端子電極に向かってつづら折りに構成することを特徴とする大電力用チップ抵抗器。   A terminal electrode for solder connection is formed on both the left and right side surfaces of the rectangular insulating substrate, and a plurality of resistors whose both ends are connected to both terminal electrodes in the portion between the terminal electrodes on the upper surface of the insulating substrate. A high-power chip resistor characterized in that films are formed side by side, and each of the resistive films is formed so as to be folded from a terminal electrode at one end thereof toward a terminal electrode at the other end. 前記請求項1の記載において,前記絶縁基板が長方形であり,前記両端子電極が,前記絶縁基板における左右両長手側面に形成されていることを特徴とする大電力用チップ抵抗器。   2. The high-power chip resistor according to claim 1, wherein the insulating substrate is rectangular and the terminal electrodes are formed on both left and right longitudinal sides of the insulating substrate.
JP2005218697A 2005-06-21 2005-07-28 Chip resistor for large electric power Pending JP2007036012A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2005218697A JP2007036012A (en) 2005-07-28 2005-07-28 Chip resistor for large electric power
US11/922,518 US7733211B2 (en) 2005-06-21 2006-06-20 Chip resistor and its manufacturing process
CN2006800222941A CN101203922B (en) 2005-06-21 2006-06-20 Chip resistor and its manufacturing process
EP06766972A EP1914760A1 (en) 2005-06-21 2006-06-20 Chip resistor and its manufacturing process
PCT/JP2006/312311 WO2006137392A1 (en) 2005-06-21 2006-06-20 Chip resistor and its manufacturing process
KR1020077029737A KR20080043268A (en) 2005-06-21 2006-06-20 Chip Resistor and Manufacturing Method Thereof
TW095122306A TW200705469A (en) 2005-06-21 2006-06-21 Chip resistor and its manufacturing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005218697A JP2007036012A (en) 2005-07-28 2005-07-28 Chip resistor for large electric power

Publications (1)

Publication Number Publication Date
JP2007036012A true JP2007036012A (en) 2007-02-08

Family

ID=37794887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005218697A Pending JP2007036012A (en) 2005-06-21 2005-07-28 Chip resistor for large electric power

Country Status (1)

Country Link
JP (1) JP2007036012A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009194148A (en) * 2008-02-14 2009-08-27 Rohm Co Ltd Chip resistor
JP2010541235A (en) * 2007-09-27 2010-12-24 ヴィシェイ デール エレクトロニクス インコーポレイテッド Power resistor and manufacturing method thereof
JP2013211520A (en) * 2012-01-27 2013-10-10 Rohm Co Ltd Method for manufacturing chip resistor
JP2014060463A (en) * 2008-05-14 2014-04-03 Rohm Co Ltd Chip resistor and method for manufacturing the same
CN114171267A (en) * 2021-11-16 2022-03-11 宁波鼎声微电子科技有限公司 Anti-surge resistor and processing equipment thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010541235A (en) * 2007-09-27 2010-12-24 ヴィシェイ デール エレクトロニクス インコーポレイテッド Power resistor and manufacturing method thereof
JP2009194148A (en) * 2008-02-14 2009-08-27 Rohm Co Ltd Chip resistor
JP2014060463A (en) * 2008-05-14 2014-04-03 Rohm Co Ltd Chip resistor and method for manufacturing the same
JP2013211520A (en) * 2012-01-27 2013-10-10 Rohm Co Ltd Method for manufacturing chip resistor
CN114171267A (en) * 2021-11-16 2022-03-11 宁波鼎声微电子科技有限公司 Anti-surge resistor and processing equipment thereof
CN114171267B (en) * 2021-11-16 2023-05-26 宁波鼎声微电子科技有限公司 Anti-surge resistor and processing equipment thereof

Similar Documents

Publication Publication Date Title
JP6822947B2 (en) Square chip resistor and its manufacturing method
US7049928B2 (en) Resistor and method of manufacturing the same
JP3993852B2 (en) Thermistor with symmetrical structure
JP2010021209A (en) Discharge gap pattern and power source device
JP2007036012A (en) Chip resistor for large electric power
US7733211B2 (en) Chip resistor and its manufacturing process
JP2013179212A (en) Chip resistor
JP7567261B2 (en) Current Detector
US7907046B2 (en) Chip resistor and method for producing the same
JP4212457B2 (en) Resistor
US9668348B2 (en) Multi-terminal electronic component, method of manufacturing the same, and board having the same
JP2007005373A (en) Chip resistor and manufacturing method thereof
EP1950771A1 (en) Chip resistor and its manufacturing method
JP4707329B2 (en) Chip resistor and manufacturing method thereof
JP2005093717A (en) Chip resistor and its manufacturing method
JP4203499B2 (en) Chip resistor and manufacturing method of chip resistor
JP2006278903A (en) Twin chip resistor
JP2013162108A (en) Thick film resistor
JP2007142165A (en) Chip resistor and manufacturing method thereof
WO2019130744A1 (en) Chip resistor
JP4812390B2 (en) Chip resistor and manufacturing method thereof
JP2009194148A (en) Chip resistor
JP2024059518A (en) Chip Resistors
JP2006041557A5 (en)
JP2006041557A (en) Square chip resistor

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080903

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090107