JP2007018299A - Voltage generation circuit and display device - Google Patents

Abstract

A circuit capable of generating a high power supply voltage corresponding to a shift amount of a threshold voltage generated in an amorphous silicon thin film transistor in a gate line driving shift register such as an LCD is provided.
When a control signal SET is at an L level, the gate of a first transistor QM, which is an a-Si TFT, is biased with a power supply voltage VDDA. The control signal SET rises to H level in a period in which the voltage of the node N5 can maintain the voltage VDDA, the first transistor QM is diode-connected, the voltage of the node N2 becomes the threshold voltage Vth of the first transistor QM, and the power supply voltage VDDA is Vth + Vc (Vc is a constant voltage). That is, the threshold voltage Vth of the a-Si TFT is detected. Thereafter, when the threshold voltage Vth increases as a result of the first transistor QM being continuously biased by the power supply voltage VDDA, the power supply voltage VDDA increases by the increase of the threshold voltage Vth due to the rising of the control signal SET to the H level.
[Selection] Figure 7

Description

  The present invention relates to a voltage generating circuit for generating a power supply voltage of a shift register that constitutes a driving circuit of a display device, and is particularly composed of an amorphous silicon thin film transistor (a-Si TFT; hereinafter, also simply referred to as a transistor unless otherwise specified). Related to the power circuit of the shift register.

  As a prior art regarding the shift register and its power supply circuit, there is one described in Patent Document 1. In an N-type amorphous silicon thin film transistor, when a positive voltage is continuously biased between the gate and the source, the threshold voltage (Vth) shifts (increases). In Patent Document 1, since the transistors 17 and 19 in FIG. 2 are continuously positively biased and the threshold voltage Vth shifts, the circuit shown in FIG. 4 is proposed as a countermeasure. .

  In FIG. 4 of Patent Document 1, the transistor 199 is an amorphous silicon thin film transistor, and the transistors other than the transistor 199 are single crystal silicon transistors. The transistor 199 is described as detecting the shift of the threshold voltage Vth of both transistors 17 and 19 in FIG. 2 of Patent Document 1 and shifting the power supply voltage VDD by the shift amount. However, the bias between the gate and the source of the transistors 17 and 19 in FIG. 2 of Patent Document 1 is the voltage VDD, but the transistor 199 in FIG. 4 of Patent Document 1 is diode-connected, and between the gate and source thereof. The voltage (V199) is approximately the threshold voltage Vth.

JP-A-8-263027 (FIGS. 2 and 4) Proceedings of The eleventh International Display Workshops (IDW'04) Integrated Gate Driver Circuit Using a-Si TFT with Dual Pull-down Structure Yong Ho Jang and others

  That is, in Patent Document 1, since the bias between the gate and the source of the transistor 199 is smaller than the bias VDD between the gate and the source of the transistors 17 and 19, the same shift of the threshold voltage Vth as that of the transistors 17 and 19 occurs. As a result, the high voltage VDD corresponding to the shift of the threshold voltage Vth cannot be generated, and the shift register malfunctions.

  The present invention has been made to solve the above problems, and a voltage generation circuit for a shift register capable of generating a high power supply voltage VDDA according to the shift of the threshold voltage Vth, and the voltage generation circuit The object is to provide a display device having

  The subject of the present invention is a unit having an output pull-down transistor whose threshold voltage can be shifted with the continuous application of a bias voltage based on the supply voltage and which sets the output to a non-selected level when in a non-selected state A voltage generation circuit for generating the power supply voltage in a shift register, comprising a first transistor having a threshold voltage that can be shifted in the same manner as the output pull-down transistor, and the first transistor having a predetermined cycle. The threshold voltage of one transistor is detected, an output voltage corresponding to the detected threshold voltage is output from the output node as the power supply voltage, and the first transistor is output during the predetermined period. When the threshold voltage is not detected, a voltage substantially equal to the bias voltage of the output pull-down transistor is set to the first transistor. Wherein the continuously applied as a bias.

  Hereinafter, various embodiments of the subject of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

  According to the subject of the present invention, since the power supply voltage of the unit shift register can be generated in accordance with the threshold voltage shift, the operation life of the unit shift register having a transistor whose threshold voltage is shifted can be extended. There is an effect to say.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol in a figure shall show the same or an equivalent part.

(Embodiment 1)
FIG. 1 is a schematic configuration diagram of a shift register that generates gate line drive signals G1 to G4 of a display device. The shift register uses the output voltage VDDA of the voltage generation circuit according to the present embodiment as its power supply voltage. Use. The shift register of FIG. 1 is a circuit formed by cascading unit shift registers SR1 to SR4 for four stages. FIG. 1 shows an example of a shift register driven by two-phase clock signals (C1, C2) having opposite phases. Of course, it is also possible to drive the shift register with three or more phase clocks.

  FIG. 2 shows a configuration example of a shift register driven by a three-phase clock signal (C1, C2, C3). FIG. 4 is a timing chart showing operation waveforms in the shift register of FIG. 2. The operation is the same as that of the shift register of Patent Document 1.

  In FIG. 1, power supply voltages VDD and VDDA and a ground voltage VSS are supplied to the unit shift registers SR1 to SR4 of each stage, and a clock signal C1 is input to the odd stages and a clock signal C2 is input to the even stages. The

  FIG. 3 is a timing chart showing operation waveforms in the shift register of FIG. The output signal G1 of the first unit shift register SR1 is input to the Gn-1 input terminal of the next unit shift register SR2, and the output signal G2 of the unit shift register SR2 is Gn-1 of the third unit shift register SR3. At the same time as being input to the input terminal, it is also input to the Gn + 1 input terminal of the unit shift register SR1. Output signals G1 to G4 of the unit shift registers SR1 to SR4 are driving signals for the corresponding gate lines on the display device side. Since the output signal G2 of the next stage is not output before the output signal G1 of the first stage is output, actually, one dummy operation that operates up to the final stage of the shift register is performed. A start signal IN is input from the outside to the Gn-1 input terminal of the first stage unit shift register SR1.

  Further, in order to obtain the output signal Gn + 1 at the final stage, N + 1 unit shift registers (not shown) are provided as dummy stages.

  FIG. 5 is a diagram showing a circuit example of a unit shift register using an N-type transistor (a-Si TFT) (based on the circuit used in Patent Document 1). In this application including FIG. 5, for convenience of explanation, the power supply voltage on the low potential side is set to the reference potential (ground voltage) VSS. However, in actual use, the potential of the voltage data written to the pixel is the reference. In FIG. 5, a positive voltage (for example, 17V) is used for the power supply voltage VDD on the high potential side, and a negative potential (for example, −12V) is used for the power supply voltage VSS on the low potential side.

  FIG. 6 is a timing chart showing operation waveforms in the unit shift register of FIG. FIG. 6 shows that the circuit of FIG. 5 changes from the non-selected state (Gn = L) to the selected state (Gn = H) and again enters the non-selected state (Gn = L).

  In the non-selected state, the parasitic capacitance between the gate line (not shown) on the display device side connected to the output node N3 and the data line (not shown) crossing the insulating film (not shown). In order to reduce the capacitive coupling noise caused by the above, it is necessary to maintain the output node N3 at the L level with low impedance. If positive side noise is generated on the gate line, the gate line approaches the selected state, and erroneous data may be written in the pixel selected by the gate line.

  In addition, in the non-selected state, it is necessary to maintain the node N9 at the L level. In the non-selected state, the clock signal CLK is repeatedly input. A relatively large parasitic capacitance (not shown) is generated between the drain (N4) and the gate (N9) of the transistor Q1 due to the overlap of the gate electrode portion and the drain electrode portion. When the level changes to the level, this change is coupled to the gate (N9) via the parasitic capacitance. If the impedance of the node N9 is high, the level of the node N9 becomes high and the transistor Q1 may be turned on. When the transistor Q1 is turned on in the non-selected state, the circuit of FIG. 5 approaches the selected state, and the L level of the output signal (the driving signal for the gate line of the nth row) Gn increases by a certain amount. Even if the level increase is relatively small, this operation is repeatedly performed during one frame, so that the data written in the pixel gradually leaks to the data line and the level decreases. Occur. Therefore, in the non-selected state, the node N9 must also be maintained at the L level.

  5 and 6, the value of the power supply voltage VDDA may be any voltage as long as both transistors Q2 and Q4 are turned on with a predetermined impedance.

  In the circuit of FIG. 5, as an initial state, the node N8 is set to the power supply voltage VDDA, and the node N9 is set to the ground voltage VSS.

  When the gate line drive signal Gn-1 of the previous unit shift register becomes H (VDD) level at time t0, the transistor Q6 is turned on, the node N8 becomes the ground voltage VSS, and the transistor Q4 is turned off. At the same time, the level of the node N9 becomes VDD−Vth when the transistor Q3 is turned ON.

  At time t1, the gate line drive signal Gn-1 becomes L level (VSS) and the transistors Q6 and Q3 are turned off, but the levels of the nodes N8 and N9 are held by parasitic capacitances (not shown) of the respective nodes. The

  When the clock signal CLK becomes H level (VDD) at time t2, the level of the node N3 (Gn) rises because the transistor Q1 is ON. Since the transistor Q1 is ON, the clock signal CLK is capacitively coupled to the node N9 by the capacitance (not shown) between the gate (N9) and the transistor channel, and the level of the node N9 increases with the level of the clock signal CLK. To rise. Since the capacitance value between the gate and the channel of the transistor Q1 is sufficiently larger than the parasitic capacitance value of the node N9, the level of the node N9 rises by almost the change (VDD) of the clock signal CLK. As a result, the level of the node N9 is VDD−Vth + VDD = 2 · VDD−Vth. Since this voltage satisfies the condition for operating the transistor Q1 in the non-saturated region, no threshold voltage drop occurs, and the level of the node N3 (Gn) becomes the same power supply voltage VDD as the H level of the clock signal CLK. (Selected state).

  When the clock signal CLK falls to the reference potential VSS at time t3, the transistor Q1 is turned on, so that the node N3 falls simultaneously with the clock signal CLK, and the level becomes the ground voltage VSS. The level of the node N9 changes in combination with the clock signal CLK similarly to the time t2, but changes in the opposite direction to that at the time t2, and becomes VDD−Vth.

  At time t4, when the gate line drive signal Gn + 1 of the next unit shift register becomes H level (VDD), the transistor Q5 is turned on and the node N8 becomes the power supply voltage VDDA. As a result, the transistor Q4 is turned ON and the node N9 becomes the ground voltage VSS. At the same time, the transistor (output pull-down transistor) Q2 is also turned ON, and the level of the node N3 becomes the VSS level with a low impedance.

  After time t4, the shift register for the gate line drive signal Gn is in a non-selected state, and a positive bias (VDDA) is continuously applied to the gates of the transistors Q2 and Q4. A shift of the voltage Vth occurs.

  The relationship between the shift amount (ΔVth) of the threshold voltage Vth and the gate bias is expressed by the following equation (1).

  In the equation (1), A represents a coefficient, VGS represents a gate-source voltage of the transistor, and Vth represents a threshold voltage.

  It can be understood from the equation (1) that the threshold voltage Vth is more easily shifted as the gate bias voltage is larger. Therefore, in order to reduce the shift amount of the threshold voltage Vth, the bias voltage VGS may be set small.

  On the other hand, as described above, the transistor Q2 is turned on when the gate line connected to the node N3 is not selected, and the level of the gate line is set to the L level (VSS). Can not be reduced, and the level of the gate line rises to the extent that the pixel transistor is turned on, causing a display defect. When the gate line is not selected, the transistor Q2 operates in the non-saturated region, and its ON resistance is expressed by the following equation. The current flowing through the transistor Q2 is expressed by the following equation (2).

  Here, VGS is a gate-source voltage of the transistor Q2, VDS is a drain-source voltage (gate line voltage) of the transistor Q2, and β is a current amplification coefficient of the transistor Q2. From equation (2)

The ON resistance R _ON of transistor Q2 is

  From equation (3)

  Here, B = 1 / β.

  The drain-source voltage VDS corresponds to the voltage of the gate line controlled by the conduction of the transistor Q2 when positive noise is applied to the gate line.

  Usually, since VGS−Vth >> VDS, the equation (4) becomes the following equation (5).

From equation (5), in order to make the ON resistance R _ON constant, VGS−Vth should be made constant.

From the equations (1) and (5), the initial value of the gate-source voltage VGS is reduced, and the gate-source voltage VGS is increased by the shift amount of the threshold voltage Vth to obtain VGS−Vth. if constant, it comes to be the oN resistance R _oN of the transistor Q2 constant for a long time.

  In the present invention, the bias at the initial stage of driving is set to a minimum value necessary for turning on the transistor, and the threshold voltage Vth is hardly shifted. An object of the present invention is to provide a voltage generation circuit that detects the shift amount of the threshold voltage Vth under this condition and increases the bias amount correspondingly to the shift amount of the threshold voltage Vth.

  That is, the term VGS−Vth in the equation (1) is set to the minimum necessary value. When this value is the bias voltage VB, the bias voltage VB is controlled to be constant even when the threshold voltage Vth is shifted, and VGS−Vth (= VB) in the parentheses in the equation (4) is constant. The purpose is to lengthen the time during which the transistor Q2 is ON.

  Now, assuming that the initial gate-source voltage VGS, threshold voltage Vth and bias voltage VB are VGS0, Vth0 and VB0, respectively.

  If the initial value Vth0 of the threshold voltage is shifted to the value Vth, the change ΔVth is

  If the bias voltage at this time is VB,

  That is, the bias voltage VB decreases by the change amount ΔVth.

  If the gate-source voltage VGS is increased by the change ΔVth in the equation (8),

  That is, the bias voltage VB does not change. As a result, since the equation (5) does not change, the ON resistance of the transistor Q2 does not change.

  FIG. 7 shows a VDDA voltage generation circuit according to this embodiment. The output voltage VDDA of the circuit is used as a power supply voltage VDDA for biasing the gates of Q2 and Q4 of the shift register shown in FIG. 5, for example. The circuit of FIG. 7 is a voltage generation circuit that detects the threshold voltage Vth and shifts the output voltage VDDA by a corresponding amount in accordance with the shift amount of the threshold voltage Vth. In FIG. 7, a (first) transistor QM is an amorphous silicon thin film transistor for detecting a shift of the threshold voltage Vth, and is formed on the same insulating substrate (eg, glass) as the shift register.

  The resistor elements (R1, R2), switch elements (SW1, SW2, SW3), constant voltage circuit (Vc), operational amplifier (OPA), and capacitor element (Cs) other than the transistor QM are formed on, for example, a single crystal silicon substrate. Transistors or so-called discrete elements, which are formed separately from the thin film transistor QM.

  In FIG. 7, the first switch SW1 is a switch element provided between the drain and gate of the transistor QM in order to diode-connect the transistor QM. The second switch SW2 is a switch element for cutting off a current flowing between the drain and source of the transistor QM while the transistor QM is biased. If the current can be cut off, the switch element SW2 may be connected between the node N4 and the constant voltage circuit Vc, between the resistance element R2 and the node N4, or between the power supply nodes VCC and R2. good. The third switch SW3 is a switch element for transmitting and holding the voltage output to the node N4 to the non-inverting input node N5 of the operational amplifier. In this example, the switch elements SW1 to SW3 are controlled by the same control signal SET. However, if the operation described below is satisfied, the control signals of the switch elements SW1 to SW3 are signals having different timings. May be.

  If the resistance value of the resistance element R2 is large and the power consumed by the resistance element R2 is small, the second switch SW2 may not be provided.

  The constant voltage circuit Vc is a constant voltage generation circuit for making the voltage of the node N4 higher than the voltage of the node N3 by a certain level, and details thereof will be described later.

  The operational amplifier OPA operates in a voltage follower mode in which the output node and the inverting input node are connected, and outputs the voltage VDDA having the same voltage value as the voltage of the node N5 to the output node N6 with low impedance. The operational amplifier OPA functions as an impedance conversion circuit between the high impedance input node N5 and the low impedance output node N6. If there is a circuit (element) that can realize this function, the operational amplifier OPA may not be used. . For example, as will be described later, a source follower circuit may be used as the impedance conversion circuit.

  The capacitive element Ch is a capacitive element for holding the voltage level taken into the node N5 for a predetermined period. In the case where the voltage level is held by the parasitic capacitance of the node N5 or the like, the capacitive element Ch is not always necessary.

  The capacitive element Cs is a voltage stabilizing capacitive element for preventing an instantaneous voltage drop caused by the output impedance of the operational amplifier OPA when a load current flows through the node N6 (VDDA). However, the capacitive element Cs is not always necessary when the load current is small.

  Resistive element R1 transmits voltage VDDA to the gate of transistor QM, and sets the level of node N2 to threshold voltage Vth when transistor QM is diode-connected. For this reason, the resistance element R1 is set to a sufficiently large resistance value compared to the ON resistance of the transistor QM.

  Resistor element R2, like resistor element R1, sets the level of node N2 to threshold voltage Vth when transistor QM is diode-connected. Therefore, the resistance element R2 is set to a sufficiently large resistance value compared to the ON resistance of the transistor QM. The resistor element R2 only needs to be able to pass a current that generates a predetermined voltage to the node N4, and a current source may be used instead of the resistor element R2.

  The circuit of FIG. 7 operates as follows. The operation will be described with reference to FIG.

  When the control signal SET is at L level, the switch elements SW1, SW2, and SW3 are all in the OFF state. At this time, the gate (N1) voltage of the transistor QM is VDDA, the drain (N2) voltage is 0V, and the source (ground) voltage is 0V. The transistor QM is in the same bias state as the transistors Q2 and Q4 of the shift register of FIG. The threshold voltage Vth of the transistor QM is in a state of shifting. The voltage VDDA is set by the voltage held at the node N5. However, since the voltage at the node N5 is the voltage held at the holding capacitor Ch at the node N5, it is lost with time due to the leakage current, and its level is lowered. As a result, the level of the voltage VDDA also decreases. In order to prevent this, the control signal SET rises to the H level at a constant period T.

  When the control signal SET becomes H level and the switch elements SW1 and SW2 are turned ON, the transistor QM is diode-connected, and a current flows to the transistor QM through the resistance elements R1 and R2, but the resistance elements R1 and R2 Since the resistance value is set sufficiently higher than the ON resistance of the transistor QM, the level of the node N2 (= N3) becomes the threshold voltage Vth of the transistor QM. This level is raised by the voltage Vc of the constant voltage circuit and output to the node N4. That means

  At this time, since the switch element SW3 is also ON, the level of the node N5 becomes Vth + Vc, and the output voltage VDDA of the operational amplifier OPA becomes Vth + Vc. In FIG. 8, the initial value of the threshold voltage Vth of the transistor QM is assumed to be at the voltage Vth1, and the output voltage VDDA at this stage is expressed as being at Vth1 + Vc.

  When the control signal SET becomes L level, a voltage of Vth + Vc level is held at the node N5. On the other hand, since the switch element SW2 is turned off and the current from the power supply node VCC is cut off, the level of the node N4 rises to VCC.

  Hereinafter, the level of the output voltage VDDA can be kept at Vth + Vc by repeatedly setting the control signal SET to the H level in the period T in which the level of the node N5 hardly decreases.

  If the following operation is continued, the threshold voltage Vth rises due to the gate bias of the transistor QM. However, when the control signal SET becomes the H level, the voltage expressed by the equation (10) is input to the node N5. A voltage reflecting the shift of the threshold voltage Vth is output to the output (N6) of the operational amplifier OPA. In this regard, in FIG. 8, the threshold voltage Vth rises from the initial value Vth1 to the value Vth2 (> Vth1), and the output voltage Vth2 + Vc reflecting the shift of the threshold voltage Vth is output to the node N6. The state is shown.

  By using this output voltage VDDA as the power supply voltage of the unit shift register of FIG. 5, even if the threshold voltage Vth is shifted, the transistors Q2 and Q4 can be turned on with a constant bias VB. It can be operated for a long time (extension of operation of the shift register).

(Embodiment 2)
FIG. 9 is a circuit diagram showing a configuration example of the unit shift register voltage generating circuit according to the present embodiment. The voltage generation circuit shown in FIG. 9 is characterized in that a switch element SW4 is used as a fourth switch instead of the resistance element R1 in the voltage generation circuit of FIG. Other points are the same as those in the first embodiment. In the circuit of FIG. 9, the current flowing through the resistance element R1 of FIG. 7 can be eliminated, so that the power consumption can be reduced.

  In addition, since the output voltage VDDA is directly input to the gate of the transistor QM, the output voltage VDDA can be input to the gate of the transistor QM without time delay, so that the bias accuracy can be improved.

  However, the circuit of FIG. 9 requires a control signal / SET having a phase opposite to that of the control signal SET.

  In the circuit of FIG. 9, the switch element SW4 is turned ON while the control signal / SET is at the H level, the output voltage VDDA is input to the gate of the transistor QM, and the transistor QM is biased to the output voltage VDDA (at this time, the control The signal SET is at L level).

  When the control signal / SET becomes L level, the switch element SW4 is turned off, and the gate of the transistor QM and the output voltage VDDA are separated. At this time, the control signal SET becomes H level almost simultaneously, and thereafter, the same operation as in the first embodiment described above is performed, and the constant voltage Vc is added to the threshold voltage Vth of the transistor QM at that time to the node N5. The voltage Vth + Vc is written to the node N5 and output to the node N6 as the output voltage VDDA.

  When the control signal / SET becomes H level again, the switch element SW4 is turned ON, and the gate of the transistor QM is biased again by VDDA (the control signal SET is L level).

(Embodiment 3)
The present embodiment relates to a configuration example of a constant voltage circuit in the voltage generation circuit described above. That is, FIG. 10 shows a specific example of the constant voltage circuit of FIG. 7 or FIG.

  FIG. 10A shows an example in which a constant voltage circuit is configured by connecting a Zener diode D1 between a node N3 and a node N4, and the breakdown voltage is the constant voltage Vc described above.

  FIG. 10B is an example in which a constant voltage circuit is configured by connecting n (arbitrary number) diodes in series between the node N3 and the node N4. The forward voltage drop (Vf) of each diode is shown in FIG. ). Vc≈n · Vf.

  (C) of FIG. 10 is an example in which a constant voltage circuit is configured by serially connecting n (arbitrary number) field effect transistors diode-connected between the node N3 and the node N4. Assuming that the threshold voltage is VT, Vc≈n · VT.

(Embodiment 4)
FIG. 11 is a circuit diagram showing a configuration example of the unit shift register voltage generating circuit according to the present embodiment.

  In the circuit configuration of FIG. 11, in order to reduce the cost of a display device to which the voltage generation circuit according to the present invention is applied, the elements of the voltage generation circuit are placed on the same insulating substrate (glass) as the display elements on the display device side. An example in the case of forming is shown. In FIG. 11, all circuit components other than the resistance elements R1, R2, and R3 and the output voltage stabilization capacitor Cs are formed on the insulating substrate at the same time as the display element.

  In FIG. 11, transistors (a-Si TFTs) QS1, QS2, and QS3 are used as the elements corresponding to the switch elements SW1 to SW3 in FIG. 7, respectively. The constant voltage circuit in FIG. Transistors (a-SiTFT) QC1 and QC2 connected in series between the nodes N4 are used, a transistor (a-SiTFT) Q0 that performs a source follower operation is used as an impedance conversion circuit, and a display capacitor Ch A capacitor having the same structure as the storage capacitor of the pixel in the element is used.

  The circuit of FIG. 11 operates as follows. Referring to the waveform diagram of FIG. 12, when control signal SET (cycle T) is at L level, transistors QS1, QS2 and QS3 are in the OFF state. At this time, the gate (N1) voltage of the transistor QM is VDDA, the drain (N2) voltage is 0V, and the source (ground) voltage is 0V. The transistor QM is in the same bias state as the transistors Q2 and Q4 of the shift register of FIG. It is set and the threshold voltage (Vth1) of transistor QM shifts. Although the value of the output voltage VDDA is set by the voltage held at the node N5, the voltage at the node N5 is the voltage held at the holding capacitor Ch at the node N5. descend. As a result, the level of the output voltage VDDA also decreases. In order to prevent this, the control signal SET becomes H level at a constant period T.

  When the control signal SET becomes H level and the transistors QS1 and QS2 are turned on, a current flows through the transistor QM through the resistance elements R1 and R2, but the resistance values of the resistance elements R1 and R2 are set to the ON resistance of the transistor QM. Since it is set to be sufficiently high, the level of the node N2 (= N3) becomes the threshold voltage Vth1 of the transistor QM. This level is raised by the voltage Vc of the constant voltage circuit composed of the transistors QC1 and QC2 and output to the node N4. The ON resistance values of the transistors QC1 and QC2 of the constant voltage circuit are set sufficiently lower than the resistance value of the resistance element R2, and the drain-source voltage becomes the threshold voltage of the transistors QC1 and QC2, respectively. That is, the gate (drain) -source voltage is the threshold voltage.

  As a result, the threshold voltage shift of the transistors QC1 and QC2 does not occur from the equation (1). Therefore, the threshold voltages of the transistors QC1 and QC2 are not changed from the initial value (Vth0), and the voltage between the node N3 and the node N4 is always 2 · Vth0. As a result, the voltage at the node N4 becomes Vth1 + 2 · Vth0.

  The transistor Q0 performs a source follower operation. In the source follower operation, when a DC load current does not flow, the gate-source voltage of the transistor Q0 is substantially the threshold voltage (Vth0). Therefore, the threshold voltage (Vth0) of the transistor Q0 There is no shift. The resistance element R3 is a resistance element having a resistance value sufficiently higher than the ON resistance value of the transistor Q0, and is for preventing a voltage increase at the node N6 due to a leakage current between the source and drain of the transistor Q0. . Note that the resistance element R3 may be configured by a constant current circuit having the same current value.

  In the circuit of FIG. 11, a DC load current does not flow except for the current of the resistance element R3.

  When the control signal SET becomes L level, the node N5 holds the level of the node N4.

  Since the voltage at the node N5 is equal to the voltage at the node N4, the output voltage VDDA is expressed by the following equation.

  If the following operation is continued, the threshold voltage of the transistor QM rises due to the gate bias of the transistor QM, but when the control signal SET becomes H level, the voltage expressed by the equation (11) is input to the node N5. Therefore, the voltage Vth2 + Vth0 reflecting the shift of the threshold voltage is output to the output (N6).

(Embodiment 5)
It has been reported in Non-Patent Document 1 that the threshold voltage shift is alleviated by repeatedly applying and stopping the gate bias.

  That is, instead of the output pull-down transistor Q2 in FIG. 5, two output pull-down transistors (Q2L, Q2R) are provided in parallel as shown in FIG. 13, and the gate voltages of these transistors Q2L, Q2R are as shown in FIG. By alternately setting a biased (VDDA) and no-biased (VSS) state at time T1 (at this time, the gate line in FIG. 13 is maintained at the ground voltage VSS), the threshold voltage of the output pull-down transistor (The same applies to the transistor Q4).

  FIG. 15 is a block diagram of a shift register that performs the above operation. A control signal CNT having the same timing is input to the shift register.

  FIG. 16 is a diagram illustrating a configuration example of the voltage generation circuit according to the present embodiment when the gate of the transistor QM is biased as described above. In FIG. 16, instead of biasing the node N1 in FIG. 9 with the output voltage VDDA, the level of the control signal CNT is shifted, and the level of the control signal CNT during the period when the control signal / SET of the switch element SW4 is at the H level. Is applied to the gate of the transistor QM to positively bias the transistor QM. On the other hand, when the level of the control signal CNT is L level, the signal of the ground voltage VSS is applied to the gate of the transistor QM. Giving. As a result, the gate of the transistor QM becomes the same bias state as the transistors Q2L and Q2R in FIG. If the H level and L level of the control signal CNT are the same level as the gate bias of the transistors Q2L and Q2R (see FIG. 14), the level shifter is not required in FIG. 16, and the control signal CNT is sent via the switch element SW4. Thus, the signal may be input directly to the gate of the transistor QM. The method for detecting the threshold voltage of the transistor QM and the generation of the output voltage VDDA are as described in the first embodiment, and the description of the operation is omitted.

(Embodiment 6)
FIG. 17 is a diagram illustrating a configuration example of another unit shift register (known). The operation of the unit shift register in FIG. 17 will be described later.

  In the unit shift register of FIG. 17, the gate voltage of the output pull-down transistor Q2 (the voltage at the node N8) is a voltage VDDA−Vth0 that is lowered from the voltage VDDA by the threshold voltage Vth0 of the transistor Q5.

  FIG. 18 is a diagram illustrating a configuration example of a voltage generation circuit corresponding to the unit shift register of FIG. The circuit of FIG. 18 differs from the circuit of FIG. 7 in that a diode-connected transistor Q8 is connected between the output (node 6) of the voltage generation circuit and the resistance element R1. The high-resistance resistance element R4 connected between the node N10 and the ground voltage VSS is for reducing the voltage increase at the node N10 due to the leakage current between the drain and source of the transistor Q8. Since resistance element R4 has a sufficiently high resistance value compared to the ON resistance of transistor Q8, the level of node N10 is approximately VDDA-Vth0.

  As a result, a voltage of VDDA-Vth0 substantially equal to the gate voltage of the transistor Q2 in FIG. 17 is applied to the gate of the transistor QM. When the circuit in FIG. 18 is applied to the circuit in FIG. 1 can be realized.

  For reference, the operation of the unit shift register of FIG. 17 can be briefly described as follows.

  When the level of the signal Gn + 1 changes from 0V to VDD at a certain time t0, the transistor Q7 is turned on and the level of the node N9 is lowered. Then, since the transistor Q6 is turned off, the node N8 is at the level of VDDA-Vth0, whereby the transistor Q4 is turned on and the node N9 becomes VSS. As a result, the transistor Q1 is turned off and the transistor Q2 is turned on, so that the output terminal N3 is VSS, and the gate line is in a low impedance inactive state (non-selected state).

  When the signal Gn + 1 returns to VSS at the next time t1, the transistor Q7 turns off, but the transistor Q4 remains on and the transistor Q6 remains off, so that the node N9 remains at VSS and the node N8 remains unchanged from the level of VDDA-Vth0. .

  At the next time t2, when the signal Gn-1 is input to the input terminal N5 and the level of the input terminal N5 becomes VDD, the transistor Q3 is turned on and the level of the node N9 is increased. Then, the transistor Q6 is turned on and the node N8 is set at VSS, whereby the transistors Q2 and Q4 are turned off, so that the node N9 is at the level of VDD-Vth.

  When the input terminal N5 returns to VSS at the next time t3, the transistor Q3 is turned off. However, since the transistors Q4 and Q7 are also turned off, the node N9 becomes floating. A leak current hardly occurs at the node N9, and the level of the node N9 is reliably maintained at VDD-Vth.

  When the clock signal CLK at the terminal N4 changes from VSS to VDD at the next time t4, the level of the gate rises as the clock signal CLK rises due to capacitive coupling due to the gate-channel capacitance of the transistor Q1, and the node N9 Is boosted to a level of 2 × VDD−Vth. The output terminal N3 follows the rise of the clock signal CLK and goes to the VDD level, whereby the gate line is activated.

  When the clock signal CLK becomes VSS at the next time t5, almost no leakage current is generated at the node N9. Therefore, the level of the node N9 is kept at 2 × VDD−Vth until this time, and the level of the output terminal N3 is Following the clock signal CLK, it falls and becomes VSS. Thereafter, the above operation is repeated.

(Summary)
From the description of each of the embodiments described above, the voltage generation circuit according to the present invention can be shifted when the threshold voltage Vth is continuously applied with a bias voltage based on the power supply voltage VDDA and is in a non-selected state. This is a circuit for generating the power supply voltage VDDA in the unit shift register having an output pull-down transistor Q2 for setting the output N3 of the unit shift register to a non-selection level. The voltage generation circuit according to the present invention includes a first transistor QM having a threshold voltage Vth that can be shifted in the same manner as the output pull-down transistor Q2. The control signal is output during a predetermined period T (that is, during the period T). The threshold voltage Vth of the first transistor QM is detected during a period when SET is at the H level, and an output voltage corresponding to the detected threshold voltage Vth is output from the output node N6 as the power supply voltage VDDA. In addition, the voltage generation circuit according to the present invention outputs the output pull-down transistor during a predetermined period T when the threshold voltage Vth of the first transistor QM is not detected (that is, during the period when the control signal SET is at L level). A voltage substantially equal to the bias voltage (VDDA or VDDA−Vth0) of Q2 is continuously applied as the bias of the first transistor QM. Here, “continuously” means not only a state in which a bias is always applied during a period, but also a case in which a state with a bias and a state without a bias continue during the period (for example, in the case of Embodiment 5). It is a concept that also includes In addition to the resistance element R2, the “current limiting element” includes a constant current transistor instead.

(Appendix)
In each of the above-described embodiments, the case where the voltage VDDA is positive has been described. However, the present invention can be applied even when the voltage VDDA is negative. In this case, the polarity of the transistor is reversed.

  While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

  The voltage generation circuit according to the present invention can be used as a power supply circuit for a shift register for driving a gate line in a display device such as a liquid crystal display device or an organic EL display device.

It is the schematic of a shift register. It is the schematic of a shift register. 2 is a timing chart showing operation waveforms of the shift register of FIG. 1. 3 is a timing chart showing operation waveforms of the shift register of FIG. 2. It is a figure which shows the circuit structural example of a unit shift register. 6 is a timing chart showing operation waveforms of the unit shift register of FIG. 5. It is a figure which shows the structural example of the voltage generation circuit which concerns on Embodiment 1 of this invention. 8 is a timing chart showing operation waveforms of the voltage generation circuit of FIG. It is a figure which shows the structural example of the voltage generation circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the structural example of the constant voltage circuit in the voltage generation circuit based on Embodiment 3 of this invention. It is a figure which shows the structural example of the voltage generation circuit which concerns on Embodiment 4 of this invention. 12 is a timing chart illustrating operation waveforms of the voltage generation circuit of FIG. 11. FIG. 16 is a diagram showing a configuration of a modified example of the output pull-down transistor of FIG. 5 in Embodiment 5 of the present invention. It is a timing chart which shows the voltage waveform applied to the gate of the output pull-down transistor of FIG. 13 in Embodiment 5 of this invention. It is a block diagram which shows the circuit structural example of the shift register in Embodiment 5 of this invention. It is a figure which shows the structural example of the voltage generation circuit which concerns on Embodiment 5 of this invention. It is a figure which shows the circuit structural example of the shift register in Embodiment 6 of this invention. It is a figure which shows the structural example of the voltage generation circuit which concerns on Embodiment 6 of this invention.

Explanation of symbols

QM first transistor (amorphous silicon thin film transistor), SET control signal, SW1, SW2, SW3 switch, Vc constant voltage, OPA operational amplifier, VDDA power supply voltage, Vth, Vth1, Vth2 threshold voltage, Q1-Q7 transistor (amorphous) Silicon thin film transistor), SR1 to SR4 unit shift register.

Claims (6)

The unit shift register having an output pull-down transistor whose threshold voltage can be shifted with continuous application of a bias voltage based on a power supply voltage and which sets an output to a non-selected level when in a non-selected state. A voltage generation circuit for generating a power supply voltage,
A first transistor having a threshold voltage that can be shifted in the same manner as the output pull-down transistor;
Detecting the threshold voltage of the first transistor at a predetermined period, and outputting an output voltage corresponding to the detected threshold voltage from the output node as the power supply voltage;
During the predetermined period, when the threshold voltage of the first transistor is not detected, a voltage substantially equal to the bias voltage of the output pull-down transistor is continuously applied as a bias of the first transistor. To
Voltage generation circuit. The voltage generation circuit according to claim 1,
A value of the bias voltage applied to the first transistor when the threshold voltage is not detected is a voltage substantially equal to the output voltage output from the output node.
Voltage generation circuit. The voltage generation circuit according to claim 1,
A value of the bias voltage applied to the first transistor when the threshold voltage is not detected is a voltage substantially equal to a voltage smaller than the output voltage output from the output node.
Voltage generation circuit. The voltage generation circuit according to claim 1,
The first transistor, the constant voltage circuit, and the current limiting element that are diode-connected when detecting the threshold voltage are connected in series in this order between the low voltage source and the high voltage source. ,
It further includes an impedance conversion circuit that performs impedance conversion of a connection node between the current limiting element and the constant voltage circuit and outputs an output signal to the output node;
All of the first transistor, the transistor constituting the constant voltage circuit, and the transistor constituting the impedance conversion circuit are amorphous silicon thin film transistors and are formed on the same insulating substrate as the display element. Characterized by
Voltage generation circuit. The voltage generation circuit according to claim 1,
When the output pull-down transistor is constituted by two transistors connected in parallel to each other and controlled alternately in a biased state and a biasless state in a certain period in the non-selected state of the unit shift register,
The first transistor has a state in which the voltage substantially equal to the bias voltage of the output pull-down transistor is biased and a state in which the voltage is not biased during the non-detection period of the threshold voltage. Features
Voltage generation circuit. A plurality of pixels including display elements arranged in a matrix;
The voltage generation circuit according to claim 1,
A plurality of the unit shift registers according to claim 1, further comprising a row selection circuit that selects a row of the display element.
Display device.

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