JP2007006464A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an operational defect such as malfunction or no response caused by changing a pulse width in a semiconductor device capable of communicating data through wireless communication. <P>SOLUTION: In a semiconductor device, a level shift circuit is provided between a data demodulation circuit and each circuit block to which a demodulated signal output from the data demodulation circuit is sent. Therefore, a voltage amplitude of a demodulated signal is approximately equalized with a voltage amplitude of an output signal from each circuit block. Thus, a pulse width of the demodulated signal is approximately equalized with that of a signal within each circuit block or the pulse width of the demodulated signal is approximately equalized with that of an output signal from each circuit block, thereby preventing an operational defect such as malfunction or no response caused by changing a pulse width. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of communicating data by wireless communication. The present invention relates to a semiconductor device that performs only data reception or data transmission.

  In recent years, as described in the ubiquitous information society, an environment where an information network can be accessed in any state has been developed. In such an environment, attention has been given to an individual recognition technique in which an ID (individual identification number) is given to each individual object, thereby clarifying the history of the object and making use of it for production, management, and the like. Among them, RFID (Radio Frequency Identification) using a semiconductor device capable of data communication by wireless communication such as an RFID tag (IC tag, IC chip, RF (Radio Frequency) tag, also called a wireless tag, an electronic tag, or a transponder). ) Technology is starting to be used.

  A general structure of a semiconductor device capable of data communication by wireless communication will be described with reference to FIG.

  A semiconductor device 101 capable of data communication by wireless communication includes an antenna 102 and a semiconductor integrated circuit 111. A circuit in the semiconductor device 101 is divided into an analog unit 914 and a digital unit 915. The semiconductor integrated circuit 111 includes circuit blocks such as a high-frequency circuit 103, a power supply circuit 104, a reset circuit 105, a clock generation circuit 106, a data demodulation circuit 107, a data modulation circuit 108, a control circuit 109, and a memory circuit 110. The power supply circuit 104 includes circuit blocks such as a rectifier circuit 112, a storage capacitor 113, and a constant voltage circuit 114.

  Next, the operation of the semiconductor device 101 illustrated in FIG. 2 will be described with reference to the timing chart of FIG.

  A radio signal such as A 'in FIG. 3 is received by the antenna 102 in FIG. The radio signal A ′ is sent to the power supply circuit 104 via the high frequency circuit 103 of FIG. In the power supply circuit 104, the radio signal A ′ is input to the rectifier circuit 112. The radio signal A ′ input to the rectifier circuit 112 is rectified and further smoothed by the storage capacitor 113. Thus, a first high power supply potential (hereinafter referred to as VDDH) is generated by the power supply circuit 104 (B ′ in FIG. 3). The power supply circuit 104 also generates a second high power supply potential (hereinafter referred to as VDD) from VDDH by the constant voltage circuit 114 (C ′ in FIG. 3). VDD is lower than VDDH. Note that a low power supply potential (hereinafter referred to as VSS) is common among a plurality of circuits included in the semiconductor integrated circuit 111 and can be, for example, GND. A first DC power supply voltage corresponding to the potential difference between VDDH and VSS and a second DC power supply voltage corresponding to the potential difference between VDD and VSS are a plurality of circuits (an analog unit and a digital unit) constituting the semiconductor integrated circuit 111. ). The first DC power supply voltage is higher than the second DC power supply voltage. The power supply circuit 104 generates two DC power supply voltages having different voltages (hereinafter also referred to as two types of DC power supply voltages).

  Also, the signal sent to the data demodulation circuit 107 via the high frequency circuit 103 in FIG. 2 is demodulated as D ′ in FIG. 3 (demodulated signal 911). The demodulated signal 911 is input to the clock generation circuit 106, and the clock generation circuit 106 outputs a clock 912. Further, a signal is input to the reset circuit 105 via the high frequency circuit 103, and the reset circuit 105 outputs a reset signal 913. The reset signal 913, the clock 912, and the demodulated signal 911 are sent to the control circuit 109. The signal sent to the control circuit 109 is analyzed by the control circuit 109. Information stored in the memory circuit 110 is output in accordance with the analyzed signal. Information output from the memory circuit 110 is encoded by the control circuit 109. Further, the encoded signal is input to the data modulation circuit 108 and is transmitted on the radio signal by the antenna 102.

A configuration for generating two types of DC power supply voltages using received radio signals is described in Patent Document 1, for example.
JP 2002-319007 A

  In the semiconductor device 101 capable of data communication by the above-described wireless communication, the data demodulation circuit 107 is not supplied with VDD, and the voltage amplitude of the demodulated signal 911 output from the data demodulation circuit 107 is almost equal to the potential difference between VDDH and VSS. The same.

  On the other hand, the clock generation circuit 106 and the control circuit 109 are supplied with VDD as a high power supply potential. In the clock generation circuit 106 and the control circuit 109, one of the input signals is a demodulated signal 911.

  Therefore, in the clock generation circuit 106 and the control circuit 109, the voltage amplitude of the demodulated signal 911, which is one of the input signals, and the supplied power supply voltage (second DC power supply voltage: equivalent to the potential difference between VDD and VSS). Is different). Therefore, in the clock generation circuit 106 and the control circuit 109, the voltage amplitude and pulse width of the input signal and the signal in the circuit (the clock generation circuit 106 and control circuit 109), or the voltage amplitude and pulse of the input signal and the output signal. The width will be different.

  For example, the pulse width of the input signal (corresponding to the demodulated signal 911) to the clock generation circuit 106 and the control circuit 109 is T1 (D ′ in FIG. 3). A signal in the clock generation circuit 106 and the control circuit 109 or an output signal from the clock generation circuit 106 and the control circuit 109 has a voltage amplitude of a potential difference between VDD and VSS as shown by E ′ in FIG. 3 and a pulse width of T1 + α (α is 0). Not a number).

  In the semiconductor device 101 as shown in FIG. 2, the analog circuit is supplied with the first DC power supply voltage (corresponding to the potential difference between VDDH and VSS), and the digital circuit is more voltage than the first DC power supply voltage. A second DC power supply voltage (corresponding to a potential difference between VDD and VSS) having a small amplitude is supplied. A circuit supplied with a small power supply voltage (a circuit using the second DC power supply voltage as the power supply voltage) from a circuit supplied with a large power supply voltage (circuit using the first DC power supply voltage as the power supply voltage) ). In this case, if a signal having a pulse width T1 is input to a circuit to which a small power supply voltage is supplied, the output signal from the circuit delays the falling of the pulse and the pulse width becomes T1 + α (α> 0). End up. On the other hand, the output from the circuit supplied with the small power supply voltage (the circuit using the second DC power supply voltage as the power supply voltage) is changed to the circuit supplied with the large power supply voltage (the first DC power supply voltage as the power supply voltage). Let us consider the case of inputting to a circuit to be used. In this case, if a signal having a pulse width T1 is input to a circuit to which a large power supply voltage is supplied, the output signal from the circuit is delayed in the rise of the pulse and the pulse width becomes T1 + α (α <0). End up.

  The signal in the clock generation circuit 106 and the control circuit 109, or the output of the clock generation circuit 106 and the control circuit 109, as shown by E 'in FIG. 3, with respect to the pulse width T1 of the input signal shown in D' of FIG. The reason why the pulse width of the signal becomes T1 + α will be briefly described. In general, in two signals having different voltage amplitudes, the potential at which “0” and “1” of one signal are switched differs from the potential at which “0” and “1” of the other signal are switched. Therefore, for example, when one of these two signals is used as an input signal and the circuit is operated using the same voltage as the voltage amplitude of the other signal as the power supply voltage, the input signal and the power supply voltage having the same voltage amplitude are operated. The timing at which “0” and “1” of the output signal are switched also changes as compared with the case where the operation is performed using. Accordingly, the pulse width of the output signal also changes. As described above, in the clock generation circuit 106 and the control circuit 109, if the voltage amplitude of the demodulated signal 911 which is one of the input signals and the supplied power supply voltage are different, the input signal and the signal in the circuit The voltage amplitude and pulse width, or the voltage amplitude and pulse width of the input signal and output signal are different.

  For the above reason, the pulse width (T1) of the demodulated signal D ′ in FIG. 3 is different from the pulse width (T1 + α) of the output signal E ′ in FIG. A semiconductor device capable of communicating data by wireless communication has a signal pulse width determined by the standard, and if the pulse width of the signal is greatly different, the semiconductor device 101 malfunctions or the semiconductor device 101 does not respond. Defects may occur.

  In view of the above circumstances, an object of the present invention is to prevent malfunctions such as malfunction and non-response caused by a large difference in pulse width in a semiconductor device capable of data communication by wireless communication.

  In order to solve the above-described problems, the present invention provides a circuit for outputting a signal having substantially the same voltage amplitude as the first DC power supply voltage and a first DC power supply voltage in a semiconductor device that performs data communication by wireless communication. Also, a level shift circuit is provided between the second DC power supply voltage having a small voltage amplitude. The level shift circuit is supplied with both the first DC power supply voltage and the second DC power supply voltage. Note that the semiconductor device is not limited to a semiconductor device that performs data communication by wireless communication, and may be a semiconductor device that performs only data reception by wireless communication or a semiconductor device that performs only data transmission.

  In particular, in a semiconductor device that communicates data by wireless communication, a level shift circuit is provided between a data demodulation circuit and a circuit (hereinafter also referred to as a circuit block) to which a signal (demodulation signal) output from the data demodulation circuit is sent. It is characterized by putting. A circuit block refers to a set of a plurality of circuits having a predetermined function as a whole. Note that the semiconductor device is not limited to a semiconductor device that communicates data by wireless communication, and may be a semiconductor device that only receives data by wireless communication.

  Thus, the voltage amplitude and pulse width of the demodulated signal and the signal in each circuit block to which the demodulated signal is sent are substantially the same, or the voltage amplitude and pulse width of the demodulated signal and the output signal from each circuit block are substantially the same. It is characterized by that.

  For example, when a circuit to which a demodulated signal is sent is a control circuit, the following configuration is characteristic. The semiconductor device includes a data demodulation circuit that demodulates a radio signal, a level shift circuit that receives an output signal of the data demodulation circuit, and a control circuit that receives an output of the level shift circuit. The voltage amplitude of the output signal of the data demodulating circuit is the same as the first DC power supply voltage. The level shift circuit is supplied with a first DC power supply voltage and a second DC power supply voltage having a smaller voltage amplitude than the first DC power supply voltage. A second DC power supply voltage is supplied to the control circuit. Since the input signal input to the level shift circuit is an output signal of the data demodulating circuit, the voltage amplitude thereof is the same as the first DC power supply voltage. The level shift circuit converts the voltage amplitude of the input signal and outputs it. Thus, the voltage amplitude of the signal output from the level shift circuit is the same as the second DC power supply voltage.

  In a semiconductor device that communicates data by wireless communication, the voltage amplitude and pulse width of the demodulated signal and the signal in each circuit block are substantially the same, or the voltage amplitude and pulse width of the demodulated signal and the output signal from each circuit block Are substantially the same. Thus, it is possible to obtain a semiconductor device that can prevent malfunctions such as malfunction and non-response and can transmit information stored in the memory circuit more accurately than conventional semiconductor devices.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in different drawings.

(Embodiment 1)
In Embodiment 1, a structure of a semiconductor device capable of data communication by wireless communication of the present invention and an operation of the semiconductor device will be described.

  First, FIG. 1 shows a structure of a semiconductor device capable of data communication by wireless communication according to the present invention. The semiconductor device 201 includes an antenna 202 and a semiconductor integrated circuit 211. The circuit in the semiconductor device 201 is divided into an analog part and a digital part.

  As the antenna 202, any of a dipole antenna, a patch antenna, a loop antenna, and a Yagi antenna can be used.

  In addition, a method for transmitting and receiving a radio signal in the antenna 202 may be any of an electromagnetic coupling method, an electromagnetic induction method, and a radio wave method.

  The semiconductor integrated circuit 211 includes circuit blocks such as a high frequency circuit 203, a power supply circuit 204, a reset circuit 205, a clock generation circuit 206, a level shift circuit 215, a data demodulation circuit 207, a data modulation circuit 208, a control circuit 209, and a memory circuit 210. Have. The power supply circuit 204 includes circuit blocks such as a rectifier circuit 212, a storage capacitor 213, and a constant voltage circuit 214.

  The analog unit 904 includes an antenna 202, a high frequency circuit 203, a power supply circuit 204, a reset circuit 205, a clock generation circuit 206, a level shift circuit 215, a data demodulation circuit 207, a data modulation circuit 208, and the like, and a digital unit 905 includes A control circuit 209, a memory circuit 210, and the like are included.

  Next, the operation of the semiconductor device 201 will be described. A radio signal received by the antenna 202 is sent to each circuit block via the high frequency circuit 203. A signal sent to the power supply circuit 204 via the high frequency circuit 203 is input to the rectifier circuit 212. The signal is rectified and further smoothed by the storage capacitor 213. Then, a first high power supply potential (VDDH) is generated. VDDH is input to the constant voltage circuit 214 to generate the second high power supply potential (VDD). VDD is lower than VDDH.

  Note that a low power supply potential (hereinafter referred to as VSS) is common in DC power supply voltages of a plurality of circuit blocks constituting the semiconductor integrated circuit 211. VSS can be GND. A first DC power supply voltage corresponding to the potential difference between VDDH and VSS and a second DC power supply voltage corresponding to the potential difference between VDD and VSS are a plurality of circuit blocks (analog unit 904 and Digital section 905). The first DC power supply voltage is higher than the second DC power supply voltage. The power supply circuit 204 generates a plurality of DC power supply voltages (also referred to as a plurality of types of DC power supply voltages) having different voltages.

  Further, the signal sent to the data demodulation circuit 207 via the high frequency circuit 203 is demodulated (demodulated signal 921). Further, the demodulated signal 921 is sent to the level shift circuit 215. Further, a signal is input to the reset circuit 205 via the high frequency circuit 203, and the reset circuit 205 outputs a reset signal 903.

  Here, a second DC power supply voltage (corresponding to a potential difference between VDD and VSS) is supplied to the level shift circuit 215, the clock generation circuit 206, and the control circuit 209. The level shift circuit 215 is also supplied with a first DC power supply voltage (corresponding to a potential difference between VDDH and VSS).

  The voltage amplitude of the demodulated signal 921 is greater than or equal to the voltage amplitude of the output signal of the level shift circuit 215. The demodulated signal 921 is level-shifted by the level shift circuit 215 so that the voltage amplitude becomes small, and is sent to the clock generation circuit 206 and the control circuit 209. In the clock generation circuit 206 and the control circuit 209, a signal (level-shifted demodulated signal 901) having a voltage amplitude substantially equal to the second DC power supply voltage (corresponding to the potential difference between VDD and VSS) by the level shift circuit 215. Is entered. That is, the level shift circuit 215 converts the demodulated signal into a signal (level-shifted demodulated signal 901) having the same voltage amplitude as the second DC power supply voltage (corresponding to the potential difference between VDD and VSS) and outputs the converted signal. To do.

  The level-shifted demodulated signal 901 is input to the clock generation circuit 206, and the clock generation circuit 206 outputs a clock 902. The reset signal 903, the clock 902, and the level-shifted demodulated signal 901 are sent to the control circuit 209.

  The voltage amplitude of the signal in the clock generation circuit 206 and the control circuit 209 or the voltage amplitude of the output signal from the clock generation circuit 206 and the control circuit 209 depends on the supplied power supply voltage (second DC power supply voltage: VDD). The difference with respect to the potential difference with VSS) is almost eliminated. Thus, in the clock generation circuit 206 and the control circuit 209, it is possible to prevent the pulse width of the input signal from being significantly different from the pulse width of the signal in the circuit, and the pulse width of the input signal and the pulse width of the output signal from being greatly different. .

  In a wireless communication system using the semiconductor device of the present invention, a semiconductor device 201 and a reader / writer having a known configuration, an antenna connected to the reader / writer, and a control terminal for controlling the reader / writer can be used. The communication method between the semiconductor device 201 and the antenna connected to the reader / writer is unidirectional communication or bidirectional communication, and is a space division multiplexing method, a polarization plane division multiplexing method, a frequency division multiplexing method, a time division method. Any of a multiplexing scheme, a code division multiplexing scheme, and an orthogonal frequency division multiplexing scheme can be used.

  The radio signal is a signal obtained by modulating a carrier wave. The modulation of the carrier wave is analog modulation or digital modulation, and may be any of amplitude modulation, phase modulation, frequency modulation, and spread spectrum.

  The frequency of the carrier wave is sub-millimeter wave of 300 GHz to 3 THz, millimeter wave of 30 GHz to less than 300 GHz, microwave of 3 GHz to less than 30 GHz, ultra high frequency of 300 MHz to less than 3 GHz, ultra high frequency of 30 MHz to less than 300 MHz, short wave Any frequency of 3 MHz to less than 30 MHz, a medium wave of 300 kHz to less than 3 MHz, a long wave of 30 kHz to less than 300 kHz, and a super long wave of 3 kHz to less than 30 kHz can be used.

  Memory circuit 210, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), FeRAM (Ferroelectric Random Access Memory), mask ROM (Read Only Memory), EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory can be used.

  With the above structure, the semiconductor device capable of communicating data by wireless communication according to the present invention prevents malfunctions such as malfunction and non-response than conventional semiconductor devices, and accurately transmits information stored in the memory circuit. be able to.

(Embodiment 2)
In the second embodiment, the operation of the semiconductor device of the present invention having the configuration shown in FIG. 1 will be described with reference to the timing chart of FIG.

  A radio signal as shown in FIG. 4A is received by the antenna 202 of FIG. The radio signal A is sent to the power supply circuit 204 via the high frequency circuit 203 of FIG. The radio signal transmitted to the power supply circuit 204 is input to the rectifier circuit 212. Thus, the radio signal A is rectified and further smoothed by the storage capacitor 213. Then, a first high power supply potential (VDDH) as shown in FIG. 4B is generated. The first high power supply potential (VDDH) is input to the constant voltage circuit 214, and the second high power supply potential (VDD) as shown in FIG. 4C is generated. Further, the signal sent to the data demodulation circuit 207 via the high frequency circuit 203 in FIG. 1 is demodulated as shown in FIG. 4D (demodulated signal 921). Further, the demodulated signal 921 is sent to the level shift circuit 215.

  Here, the level shift circuit 215, the clock generation circuit 206, and the control circuit 209 are supplied with a power supply voltage (second DC power supply voltage: corresponding to the potential difference between VDD and VSS) as shown in FIG. The level shift circuit 215 is also supplied with a first DC power supply voltage (corresponding to a potential difference between VDDH and VSS). Note that the pulse width of the demodulated signal 921 varies depending on the received signal (wireless signal received by the antenna 202) and is not constant. In FIG. 4, the pulse width of the demodulated signal 921 is T1. Further, the voltage amplitude of the demodulated signal 921 is almost the same as the potential difference between VDDH and VSS as shown in D of FIG.

  Next, a signal obtained by level-shifting the demodulated signal 921 by the level shift circuit 215 so that the voltage amplitude is reduced (E in FIG. 4: equivalent to the demodulated signal 901 level-shifted in FIG. 1) is supplied to the clock generation circuit 206 and the control. Sent to circuit 209. The signal E in FIG. 4 has a voltage amplitude of a potential difference between VDD and VSS and a pulse width of approximately T1.

  The voltage amplitude of the signal in the clock generation circuit 206 and the control circuit 209 or the voltage amplitude of the output signal from the clock generation circuit 206 and the control circuit 209 is the difference from the supplied power supply voltage (potential difference between VDD and VSS). Almost disappears. Thus, in the clock generation circuit 206 and the control circuit 209, it is possible to prevent the pulse width of the input signal and the pulse width of the signal in the circuit from greatly differing, and the pulse width of the input signal and the pulse width of the output signal from greatly differing. .

  With the above structure, the semiconductor device capable of communicating data by wireless communication according to the present invention prevents malfunctions such as malfunction and non-response than conventional semiconductor devices, and accurately transmits information stored in the memory circuit. be able to.

  This embodiment mode can be implemented by being freely combined with Embodiment Mode 1.

(Embodiment 3)
In the third embodiment, a level shift circuit which is a component of the semiconductor device of the present invention will be described.

  An example of the level shift circuit is shown in FIG. 5A, the level shift circuit includes N-channel transistors, ie, a transistor 501, a transistor 502, and a transistor 503, and P-channel transistors that are a transistor 504, a transistor 505, a transistor 506, a transistor 507, A transistor 508. A low power supply potential (VSS) is applied to the sources of the transistors 501 and 502. The drain of the transistor 501 is connected to the drain of the transistor 504 and the gate of the transistor 507. The source of the transistor 504 is connected to the drain of the transistor 506. A second high power supply potential (VDD) is applied to the sources of the transistors 506 and 507. The drain of the transistor 507 is connected to the source of the transistor 505. The drain of the transistor 505 is connected to the gate of the transistor 506 and the drain of the transistor 502. The gates of the transistor 501 and the transistor 504 are connected to each other, and are connected to the drains of the transistor 508 and the transistor 503. The source of the transistor 508 is supplied with the first high power supply potential (VDDH), and the source of the transistor 503 is supplied with the low power supply potential (VSS). The gates of the transistor 502, the transistor 503, the transistor 505, and the transistor 508 are connected to each other and serve as an input of the level shift circuit. In addition, the drain of the transistor 501, the drain of the transistor 504, and the gate of the transistor 507 are the outputs of the level shift circuit.

  Note that the level shift circuit is not limited to the circuit illustrated in FIG. Further, although the circuit name is a level shift circuit, it is not limited to this. The circuit is such that the voltage amplitude of the input signal is different from that of the output signal, and the voltage amplitude of the input signal is level-shifted to the same level as the power supply voltage supplied to the circuit. Any circuit configuration is possible as long as it is present.

  In the level shift circuit of FIG. 5A, the calculation results when the voltage amplitude of the input signal is 5 V, VDDH is 5 V, VDD is 3 V, and VSS is GND (0 V) are shown in FIGS. ).

  In FIG. 5B, the voltage amplitude of the input signal is 5 V, the period is about 5 μs (about 3 μs + about 2 μs), and the frequency is about 20 kHz. In FIG. 5C, the voltage amplitude of the output signal is 3 V, and the period and frequency are substantially the same as those of the input signal. That is, the pulse widths of the input signal and the output signal are hardly changed, and the voltage amplitude of the output signal is almost the same as the power supply voltage supplied to the circuit.

  The demodulated signal output from the data demodulating circuit 207 is converted into a signal having a small voltage amplitude by the level shift circuit 215 as described above, and sent to the clock generating circuit 206 and the control circuit 209. Therefore, the voltage amplitude of the signal in the clock generation circuit 206 and the control circuit 209 or the voltage amplitude of the output signal from the clock generation circuit 206 and the control circuit 209 is equal to the supplied voltage amplitude (the potential difference between VDD and VSS). Equivalent) is almost eliminated. Thus, in the clock generation circuit 206 and the control circuit 209, it is possible to prevent the pulse width of the input signal from being significantly different from the pulse width of the signal in the circuit, and the pulse width of the input signal and the pulse width of the output signal from being greatly different. .

  With the above structure, the semiconductor device capable of communicating data by wireless communication according to the present invention prevents malfunctions such as malfunction and non-response than conventional semiconductor devices, and accurately transmits information stored in the memory circuit. be able to.

  This embodiment mode can be implemented by being freely combined with Embodiment Mode 1 and Embodiment Mode 2.

(Embodiment 4)
In Embodiment Mode 4, a mask drawing for manufacturing a semiconductor device of the present invention will be described.

  A part of a mask drawing for manufacturing a semiconductor device capable of data communication by wireless communication of the present invention is shown in FIG. The mask drawing shown in FIG. 6 corresponds to the circuit diagram of FIG. 5A shown in Embodiment Mode 3. 6, the same portions as those in FIG. 5A are denoted by the same reference numerals. Note that as a mask drawing, a semiconductor layer (semiconductor layer 6601 and semiconductor layer 6602) serving as an active layer of a transistor, a first conductive layer 6603 serving as a gate electrode, and an electrode or wiring connected to a source or a drain are used. The drawing corresponding to the contact hole 6605 connecting the second conductive layer 6604 and the semiconductor layer to the second conductive layer 6604 is shown as a representative. The semiconductor layer 6601 becomes an active layer of a P-channel transistor, and the semiconductor layer 6602 becomes an active layer of an N-channel transistor.

  A feature of the mask drawing shown in FIG. 6 is that corners of electrodes and wiring (in FIG. 6, corners 6001, corners 6002, corners 6003 and corners 6004 are representatively chamfered) are stepped. That is. This stepped chamfer is 10 μm or less, or 1/2 or less of the line width of the wiring and 1/5 or more in length. A mask pattern is prepared using this mask drawing, and the conductive film is etched using the mask pattern to form electrodes and wirings. Thus, the corners of the electrode or wiring pattern can be chamfered. The corners of the electrode and wiring patterns may be further rounded. That is, the wiring pattern shape may be made smoother than the mask drawing by appropriately determining the exposure conditions and the etching conditions. Thus, a wiring with rounded corners is formed.

  In the wiring and the electrode, the following effects can be obtained by making the corners of the bent portion and the portion where the wiring width changes smooth and round. By chamfering the convex portion (corner portion 6002 in FIG. 6), generation of fine powder due to abnormal discharge can be suppressed when dry etching using plasma is performed. Further, by chamfering the concave portions (in FIG. 6, corner portion 6001, corner portion 6003 and corner portion 6004), even if it is fine powder, the fine powder is prevented from collecting at the corners during cleaning, The fine powder can be washed away. Thus, the problem of dust and fine powder in the manufacturing process can be solved and the yield can be improved.

  Although FIG. 6 illustrates a structure in which chamfering is performed on a part of a corner portion of an electrode and a wiring formed using the first conductive layer 6603 and the second conductive layer 6604, the present invention is not limited thereto. It is possible to apply the chamfered configuration at all corners. In addition, the above chamfering configuration can be applied to electrodes and wirings formed using a semiconductor layer. In addition, the above chamfering configuration can be applied to electrodes and wirings formed using other conductive layers.

  Furthermore, not only the level shift circuit but also other circuits of the semiconductor device of the present invention can be applied with the above wiring and electrode configurations.

  This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 3.

(Embodiment 5)
In Embodiment Mode 5, steps for manufacturing a semiconductor device capable of data communication by wireless communication according to the present invention will be described with reference to FIGS.

  7A to 7D illustrate structural examples of the antenna 202 in the semiconductor device 201 illustrated in FIG. There are two ways to provide the antenna 202, and one (hereinafter referred to as a first antenna installation method) is shown in FIGS. 7A and 7C. The other (hereinafter referred to as the second antenna installation method) is shown in FIGS. 7B and 7D. 7C corresponds to a cross-sectional view taken along lines A to A ′ in FIG. 7A, and FIG. 7D corresponds to a cross-sectional view taken along lines B to B ′ in FIG.

  In the first antenna installation method, the antenna 202 is provided over a substrate 600 over which a plurality of elements (hereinafter referred to as an element group 601) is provided (see FIGS. 7A and 7C). The element group 601 forms a circuit other than the antenna of the semiconductor device of the present invention. The element group 601 includes a plurality of thin film transistors. In the structure illustrated, the conductive film functioning as the antenna 202 is provided in the same layer as the wiring connected to the source and drain of the thin film transistor included in the element group 601. However, the conductive film functioning as the antenna 202 may be provided in the same layer as the gate electrode 664 of the thin film transistor included in the element group 601, or an insulating film is provided over the insulating film so as to cover the element group 601. Also good.

  In the second antenna installation method, the terminal portion 602 is provided on the substrate 600 provided with the element group 601. Then, the antenna 202 provided over the substrate 610 different from the substrate 600 is connected so as to be connected to the terminal portion 602 (see FIGS. 7B and 7D). In the structure shown in the drawing, part of the wiring connected to the source and drain of the thin film transistor included in the element group 601 is used as the terminal portion 602. Then, the substrate 600 and the substrate 610 provided with the antenna 202 are attached to be connected to the terminal portion 602. Conductive particles 603 and a resin 604 are provided between the substrate 600 and the substrate 610. The antenna 202 and the terminal portion 602 are electrically connected by the conductive particles 603.

  A structure and a manufacturing method of the element group 601 will be described. If a plurality of element groups 601 are formed on a large-area substrate and then completed by being divided, an inexpensive device can be provided. As the substrate 600, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a semiconductor substrate having an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic may be used. The surface of the substrate may be planarized by polishing such as CMP. Further, a glass substrate, a quartz substrate, or a substrate obtained by polishing and thinning a semiconductor substrate may be used.

  As the base film 661 provided over the substrate 600, an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide can be used. The base film 661 can prevent alkali metal such as Na or alkaline earth metal contained in the substrate 600 from diffusing into the semiconductor layer 662 and adversely affecting the characteristics of the thin film transistor. Although the base film 661 has a single-layer structure in FIG. 7, it may be formed of two or more layers. Note that the base film 661 is not necessarily provided when diffusion of impurities such as a quartz substrate does not cause any problem.

Note that the surface of the substrate 600 may be directly processed by high-density plasma. The high density plasma is generated by using a high frequency (eg, 2.45 GHz). As the high density plasma, one having an electron density of 10 ¹¹ to 10 ¹³ / cm ³ , an electron temperature of 2 eV or less, and an ion energy of 5 eV or less is used. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects than conventional plasma treatment. Plasma can be generated using a high-frequency excitation plasma processing apparatus using a radial slot antenna. The distance from the antenna that generates a high frequency to the substrate 600 is 20 to 80 mm (preferably 20 to 60 mm).

A nitriding atmosphere such as nitrogen (N) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, nitrogen, hydrogen (H), a rare gas atmosphere, or ammonia (NH ₃ ) In the rare gas atmosphere, the surface of the substrate 600 can be nitrided by performing the high-density plasma treatment. When glass, quartz, silicon wafer, or the like is used as the substrate 600, the nitride layer formed on the surface of the substrate 600 contains silicon nitride as a main component, so that it can be used as a blocking layer for impurities diffused from the substrate 600 side. can do. A silicon oxide film or a silicon oxynitride film may be formed over the nitride layer by a plasma CVD method to form the base film 661.

  Further, by performing similar high-density plasma treatment on the surface of the base film 661 made of silicon oxide, silicon oxynitride, or the like, nitriding treatment can be performed at a depth of 1 to 10 nm from the surface and the surface. This extremely thin silicon nitride layer is preferable because it functions as a blocking layer and is less affected by stress on the semiconductor layer 662 formed thereon.

  As the semiconductor layer 662, a crystalline semiconductor film or an amorphous semiconductor film can be used. Further, an organic semiconductor film may be used. The crystalline semiconductor film can be obtained by crystallizing an amorphous semiconductor film. As a crystallization method, a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like can be used. The semiconductor layer 662 includes a channel formation region 662a and a pair of impurity regions 662b to which an impurity element imparting a conductivity type is added. Note that although the structure including the low-concentration impurity region 662c to which the impurity element is added at a lower concentration than the impurity region 662b is shown between the channel formation region 662a and the pair of impurity regions 662b, the invention is not limited thereto. A structure in which the low concentration impurity region 662c is not provided may be employed.

  Note that the semiconductor layer 662 and wirings formed at the same time as these semiconductor layers are preferably led so that corners are rounded when viewed from a direction 3005 perpendicular to the top surface of the substrate 600. The wiring routing method is schematically shown in FIG. A wiring formed at the same time as the semiconductor layer 662 is indicated by a wiring 3011 in the drawing. FIG. 12A shows a conventional wiring routing method. FIG. 12B shows a wiring routing method according to the present invention. The corner 1502a of the wiring 3011 of the present invention is rounded with respect to the corner 1501a of the conventional wiring 3011. In order to round the corner, a mask drawing as shown in Embodiment Mode 4 may be used. By rounding the corner, it is possible to prevent dust and the like from remaining at the corner of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased.

  An impurity element imparting a conductivity type may be added to the channel formation region 662a of the thin film transistor. Thus, the threshold voltage of the thin film transistor can be controlled.

The first insulating layer 663 can be formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like by stacking a single layer or a plurality of films. In this case, the surface of the first insulating layer 663 may be densified by treatment with high-density plasma in an oxidizing atmosphere or a nitriding atmosphere, and oxidizing or nitriding treatment. As described above, the high-density plasma is generated by using a high frequency (for example, 2.45 GHz). As the high density plasma, one having an electron density of 10 ¹¹ to 10 ¹³ / cm ³ , an electron temperature of 2 eV or less, and an ion energy of 5 eV or less is used. Plasma can be generated using a high-frequency excitation plasma processing apparatus using a radial slot antenna. In the apparatus for generating high-density plasma, the distance from the antenna that generates high frequency to the substrate 600 is set to 20 to 80 mm (preferably 20 to 60 mm).

  Note that before the first insulating layer 663 is formed, the surface of the semiconductor layer 662 may be oxidized or nitrided by performing the above high-density plasma treatment. At this time, by performing treatment in an oxidizing atmosphere or a nitriding atmosphere at a temperature of the substrate 600 of 300 to 450 ° C., a favorable interface can be formed with the first insulating layer 663 deposited thereon.

The nitriding atmosphere may be a nitrogen (N) and rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, a nitrogen and hydrogen (H) and rare gas atmosphere, or ammonia (NH ₃ ) And a noble gas atmosphere. As the oxidizing atmosphere, an oxygen (O) and rare gas atmosphere, an oxygen and hydrogen (H) and rare gas atmosphere, or a dinitrogen monoxide (N ₂ O) and rare gas atmosphere can be used.

  As the gate electrode 664, one kind of element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy or compound containing a plurality of such elements can be used. Furthermore, a single layer or a laminated structure composed of these elements, alloys, and compounds can be used. In the figure, a gate electrode 664 having a two-layer structure is shown. Note that the gate electrode 664 and the wiring formed at the same time as the gate electrode 664 are preferably led so that corners are rounded when viewed from a direction 3005 perpendicular to the top surface of the substrate 600. The routing method can be the same as the method shown in FIG. In order to round the corner, a mask drawing as shown in Embodiment Mode 4 may be used. A wiring formed at the same time as the gate electrode 664 and the gate electrode 664 is indicated by a wiring 3012 in the drawing. By rounding the corner as in the corner 1502b of the wiring 3012 of the present invention with respect to the corner 1501b of the conventional wiring 3012, dust or the like can be prevented from remaining in the corner of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased.

  The thin film transistor includes a semiconductor layer 662, a gate electrode 664, and a first insulating layer 663 that functions as a gate insulating film between the semiconductor layer 662 and the gate electrode 664. In this embodiment mode, the thin film transistor is shown as a top gate type transistor. However, a bottom gate type transistor having a gate electrode below a semiconductor layer may be used, or a dual gate having gate electrodes above and below the semiconductor layer. It may be a type transistor.

The second insulating layer 667 is preferably a barrier insulating film that blocks ionic impurities, such as a silicon nitride film. The second insulating layer 667 is formed using silicon nitride or silicon oxynitride. The second insulating layer 667 functions as a protective film that prevents contamination of the semiconductor layer 662. After the second insulating layer 667 is deposited, the second insulating layer 667 may be hydrogenated by introducing hydrogen gas and performing high-density plasma treatment as described above. Alternatively, the second insulating layer 667 may be nitrided and hydrogenated by introducing ammonia (NH ₃ ) gas. Alternatively, oxynitriding treatment and hydrogenation treatment may be performed by introducing oxygen, dinitrogen monoxide (N ₂ O) gas, or the like and hydrogen gas. By this method, the surface of the second insulating layer 667 can be densified by performing nitriding treatment, oxidation treatment, or oxynitridation treatment. Thus, the function of the second insulating layer 667 as a protective film can be enhanced. The hydrogen introduced into the second insulating layer 667 is then released by heat treatment at 400 to 450 ° C., so that the semiconductor layer 662 can be hydrogenated. Note that this hydrogenation treatment may be combined with a hydrogenation treatment using the first insulating layer 663.

  As the third insulating layer 665, a single layer or a stacked structure of an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film formed by an SOG (Spin On Glass) method, or the like can be used. As an organic insulating film, polyimide, polyamide, BCB (benzoic acid) is used. A film such as cyclobutene), acrylic or positive photosensitive organic resin, or negative photosensitive organic resin can be used.

  Alternatively, the third insulating layer 665 can be formed using a material having a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent of this material, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  As the wiring 666, one kind of element selected from Al, Ni, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn or an alloy containing a plurality of such elements can be used. Furthermore, a single layer or a laminated structure made of these elements and alloys can be used. In the figure, an example of a single layer structure is shown. Note that the wiring 666 is preferably led so that corners are rounded when viewed from a direction 3005 perpendicular to the top surface of the substrate 600. The routing method can be the same as the method shown in FIG. In order to round the corner, a mask drawing as shown in Embodiment Mode 4 may be used. A wiring 666 is indicated by a wiring 3013 in the drawing. By rounding the corner as in the corner 1502c of the wiring 3013 of the present invention with respect to the corner 1501c of the conventional wiring 3013, dust or the like can be prevented from remaining in the corner of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased. In the structures illustrated in FIGS. 7A and 7C, the wiring 666 serves as the antenna 202 and the wiring connected to the source and drain of the thin film transistor. In the structures illustrated in FIGS. 7B and 7D, the wiring 666 is a wiring connected to the source and drain of the thin film transistor and the terminal portion 602. In FIG. 12, a contact hole 3014 connecting the wiring 666 and the source and drain of the thin film transistor is shown.

  Note that the antenna 202 can also be formed by a droplet discharge method using a conductive paste containing nanoparticles such as Au, Ag, or Cu. The droplet discharge method is a general term for a method of forming a pattern by discharging droplets, such as an inkjet method or a dispenser method, and has advantages such as improvement in material utilization efficiency.

  In the structure illustrated in FIGS. 7A and 7C, the fourth insulating layer 668 is formed over the wiring 666. As the fourth insulating layer 668, a single layer or a stacked structure of an inorganic insulating film or an organic insulating film can be used. The fourth insulating layer 668 functions as a protective layer for the antenna 202.

  Further, the element group 601 formed over the substrate 600 (see FIG. 10A) may be used as it is, but the element group 601 on the substrate 600 is peeled off (see FIG. 10B), The element group 601 may be attached to the flexible substrate 701 (see FIG. 10C). The flexible substrate 701 has flexibility, and for example, a plastic substrate such as polycarbonate, polyarylate, or polyether sulfone, or a ceramic substrate can be used.

  Peeling of the element group 601 from the substrate 600 can be performed by (A) providing a peeling layer between the substrate 600 and the element group 601 in advance and removing the peeling layer with an etching agent. . Alternatively, (B) a method in which the peeling layer is partially removed using an etchant and then the substrate 600 and the element group 601 are physically peeled off can be used. Alternatively, (C) a method of separating the element group 601 by mechanically removing the substrate 600 with the element group 601 formed or removing the substrate 600 by etching with a solution or a gas can be used. It should be noted that peeling by physical means means peeling by applying stress from the outside, for example, peeling by applying stress from the wind pressure of a gas blown from a nozzle or ultrasonic waves. .

  As a more specific method of the above (A) or (B), a metal oxide film is provided between the substrate 600 having high heat resistance and the element group 601, and the metal oxide film is weakened by crystallization, whereby the element A method for peeling the group 601 can be used. Alternatively, an amorphous silicon film containing hydrogen is provided between the substrate 600 with high heat resistance and the element group 601, and the amorphous silicon film is removed by laser light irradiation or etching, whereby the element group 601 is removed. The method of peeling can be used.

  The peeled element group 601 may be attached to the flexible substrate 701 using a commercially available adhesive, for example, an adhesive such as an epoxy resin adhesive or a resin additive.

  When the element group 601 is attached to a flexible substrate 701 on which an antenna is formed and is electrically connected to the antenna, the semiconductor device is completed which is thin, light, and difficult to break even when dropped (FIG. 10C). reference). When an inexpensive flexible substrate 701 is used, an inexpensive semiconductor device can be provided. Further, since the flexible substrate 701 has flexibility, the flexible substrate 701 can be bonded onto a curved surface or an irregular shape, thereby realizing a wide variety of uses. For example, a wireless tag 720 which is one embodiment of the semiconductor device of the present invention can be attached to a curved surface such as a medicine bottle (see FIG. 10D). Further, when the substrate 600 is reused, a semiconductor device can be manufactured at low cost.

  This embodiment mode can be freely combined with any of Embodiment Modes 1 to 4.

(Embodiment 6)
In this embodiment mode, an example in which the semiconductor device of the present invention has a flexible structure will be described. FIG. 11 is used for the description. 11A, the semiconductor device includes a flexible protective layer 801, a flexible protective layer 803 including an antenna 802, and an element group 804 formed by a peeling process or thinning of a substrate. The element group 804 can have a structure similar to that shown as the element group 601 in Embodiment 5. The antenna 802 formed over the protective layer 803 is electrically connected to the element group 804. In FIG. 11, the antenna 802 is formed only over the protective layer 803; however, the present invention is not limited to this structure, and the antenna 802 may also be formed over the protective layer 801. Note that a barrier film formed of a silicon nitride film or the like is preferably formed between the element group 804 and the protective layer 801 and the protective layer 803. Then, a semiconductor device with improved reliability can be provided without the element group 804 being contaminated.

  The antenna 802 can be formed of Ag, Cu, or a metal plated with them. The element group 804 and the antenna 802 can be connected by using an anisotropic conductive film and performing ultraviolet treatment or ultrasonic treatment. Note that the element group 804 and the antenna 802 may be bonded using a conductive paste or the like.

  A semiconductor device is completed by sandwiching the element group 804 between the protective layer 801 and the protective layer 803 (see arrows in FIG. 11A).

A cross-sectional structure of the semiconductor device thus formed is shown in FIG. The thickness 3003 of the sandwiched element group 804 is 5 μm or less, preferably 0.1 μm to 3 μm. Further, when the thickness when the protective layer 801 and the protective layer 803 are overlapped is d, the thickness of the protective layer 801 and the protective layer 803 is preferably (d / 2) ± 30 μm, more preferably (d / 2) Set to ± 10 μm. The thickness of the protective layer 801 and the protective layer 803 is preferably 10 μm to 200 μm. Further, the area of the element group 804 is 10 mm square (100 mm ² ) or less, and preferably 0.3 mm square to 4 mm square (0.09 mm ^{2 to} 16 mm ² ).

  Since the protective layer 801 and the protective layer 803 are formed of an organic resin material, the protective layer 801 and the protective layer 803 have strong characteristics against bending. In addition, the element group 804 itself formed by a peeling process or thinning of a substrate also has a strong characteristic against bending compared to a single crystal semiconductor. Since the element group 804 and the protective layer 801 and the protective layer 803 can be in close contact with each other so that there is no gap, the completed semiconductor device itself has a strong characteristic against bending. The element group 804 surrounded by the protective layer 801 and the protective layer 803 may be arranged on the surface or inside of another solid object, or may be embedded in paper.

  The case where a semiconductor device including the element group 804 is attached to a substrate having a curved surface will be described. FIG. 11C is used for the description. In the drawing, one transistor 881 selected from the element group 804 is shown. In accordance with the potential of the gate electrode 807, the transistor 881 allows a current to flow from one of the source and drain 805 to the other of the source and drain 806. The transistor 881 is arranged so that the direction in which the current of the transistor 881 flows (carrier movement direction 3004) and the direction in which the substrate 880 draws an arc are orthogonal to each other. With such an arrangement, even when the substrate 880 is bent so as to draw an arc, the influence of stress applied to the transistor 881 is small, and variation in characteristics of the transistor 881 included in the element group 804 can be suppressed.

  This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 5.

(Embodiment 7)
In this embodiment, a structural example of a transistor included in a circuit included in the semiconductor device 201 is described. In addition to a MOS transistor formed on a single crystal substrate, the transistor can be a thin film transistor (TFT). FIG. 13 is a diagram showing a cross-sectional structure of transistors constituting these circuits. FIG. 13 shows an N-channel transistor 2001, an N-channel transistor 2002, a capacitor element 2004, a resistor element 2005, and a P-channel transistor 2003. Each transistor includes a semiconductor layer 305, an insulating layer 308, and a gate electrode 309. The gate electrode 309 is formed with a stacked structure of a first conductive layer 303 and a second conductive layer 302. 14A to 14E are top views corresponding to the transistor, the capacitor, and the resistor illustrated in FIG. 13 and can be referred to.

  In FIG. 13, a pair of impurity regions 307 are formed in the semiconductor layer 305 of the N-channel transistor 2001 so as to be in contact with each other in a channel length direction (carrier flow direction) with a region overlapping with the gate electrode 309 interposed therebetween. As described above, the pair of impurity regions 307 are formed on both sides of the gate electrode 309. The impurity region 306 is a source region and a drain region, and forms a contact with the wiring 304. The impurity region 307 is a low concentration drain (LDD) region doped with an impurity element at a lower concentration than the impurity concentration of the impurity region 306. In the N-channel transistor 2001, phosphorus or the like is added to the impurity region 306 and the impurity region 307 as an impurity imparting N-type conductivity. The LDD region is formed as a means for suppressing hot electron degradation and the short channel effect.

  As shown in FIG. 14A, in the gate electrode 309 of the N-channel transistor 2001, the first conductive layer 303 is formed so as to spread on both sides of the second conductive layer 302. In this case, the first conductive layer 303 is formed thinner than the second conductive layer 302. The first conductive layer 303 is formed to a thickness that allows the ion species accelerated by an electric field of 10 to 100 kV to pass therethrough. The impurity region 307 is formed so as to overlap the first conductive layer 303 of the gate electrode 309. That is, an LDD region overlapping with the gate electrode 309 is formed. In this structure, an impurity region 307 is formed in a self-aligned manner in the gate electrode 309 by adding an impurity of one conductivity type through the first conductive layer 303 using the second conductive layer 302 as a mask. That is, the LDD region overlapping with the gate electrode 309 is formed in a self-aligning manner.

  Transistors having LDD regions on both sides of the gate electrode are rectifier transistors used in the rectifier circuit 212 in the power supply circuit 204 in FIG. 1 and transistors constituting a transmission gate (also referred to as an analog switch) used in a logic circuit. Applied. In these transistors, since both positive and negative voltages are applied to the source electrode and the drain electrode, it is preferable to provide LDD regions on both sides of the gate electrode.

  In FIG. 13, an impurity region 307 is formed on one side of a gate electrode 309 in the semiconductor layer 305 of an N-channel transistor 2002. The impurity region 307 is a low concentration drain (LDD) region doped with an impurity element at a lower concentration than the impurity concentration of the impurity region 306. As shown in FIG. 14B, in the gate electrode 309 of the N-channel transistor 2002, the first conductive layer 303 is formed so as to spread on one side of the second conductive layer 302. In this case as well, an LDD region can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 303 using the second conductive layer 302 as a mask.

  A transistor having an LDD region on one side of a gate electrode may be applied to a transistor in which only a positive voltage or only a negative voltage is applied between a source electrode and a drain electrode. Specifically, if applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO (Voltage Controlled Oscillator). Good.

  In FIG. 13, the capacitor element 2004 is formed by sandwiching an insulating layer 308 between a first conductive layer 303 and a semiconductor layer 305. A semiconductor layer 305 which forms the capacitor 2004 includes an impurity region 310 and an impurity region 311. The impurity region 311 is formed in the semiconductor layer 305 so as to overlap with the first conductive layer 303. Further, the impurity region 310 forms a contact with the wiring 304. Since the impurity region 311 can be doped with one conductivity type impurity through the first conductive layer 303, the impurity concentration contained in the impurity region 310 and the impurity region 311 can be the same or different. It is. In any case, since the semiconductor layer 305 functions as an electrode in the capacitor 2004, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as illustrated in FIG. 14C, the first conductive layer 303 and the second conductive layer 302 can sufficiently function as electrodes of the capacitor element 2004 by using the second conductive layer 302 as an auxiliary electrode. be able to. In this manner, by using a composite electrode structure in which the first conductive layer 303 and the second conductive layer 302 are combined, the capacitor element 2004 can be formed in a self-aligning manner.

  The capacitor element 2004 can be used as a resonance capacitor included in the storage capacitor 213 of the power supply circuit 204 or the high-frequency circuit 203. In particular, since both positive and negative voltages are applied between the two terminals of the capacitor element 2004, the resonant capacitor needs to function as a capacitor regardless of the positive or negative voltage between the two terminals.

  In FIG. 13, the resistance element 2005 is formed of the first conductive layer 303 (see also FIG. 14D). Since the first conductive layer 303 is formed to a thickness of about 30 to 150 nm, the resistance element 2005 can be configured by appropriately setting the width and length thereof.

  The resistance element 2005 can be used as a resistance load included in the data modulation circuit 208. It can also be used as a load when controlling current with a VCO or the like. The resistance element 2005 may be formed using a semiconductor layer containing an impurity element imparting a conductivity type at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

  In FIG. 13, a P-channel transistor 2003 includes an impurity region 312 in the semiconductor layer 305. The impurity region 312 functions as a source region and a drain region that form a contact with the wiring 304. The gate electrode 309 has a structure in which the first conductive layer 303 and the second conductive layer 302 overlap with each other (see also FIG. 14E). The P-channel transistor 2003 is a single drain transistor without an LDD region. In the case of forming the P-channel transistor 2003, boron or the like is added to the impurity region 312 as an impurity imparting P-type conductivity. On the other hand, when phosphorus or the like is added to the impurity region 312 as an impurity imparting N-type conductivity, an N-channel transistor having a single drain structure can be obtained.

  One or both of the semiconductor layer 305 and the gate insulating layer 308 may be oxidized or nitrided by high-density plasma treatment. This process can be performed in the same manner as the method described in the fifth embodiment.

  Through the above treatment, the defect level at the interface between the semiconductor layer 305 and the gate insulating layer 308 can be reduced. By performing this treatment on the gate insulating layer 308, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 308. In the case where the driving voltage of the transistor is 3 V or more, a gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 305 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 308 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor element 2004. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 13 and 14, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 14A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Providing a region where only the first conductive layer is formed on the semiconductor layer is effective in that the LDD region can be formed in a self-aligned manner, but other than on the semiconductor layer (continuous with the gate electrode) In the wiring region, a region where only the first conductive layer is formed is not necessary. By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  13 and 14, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, a TaN film can be used as the first conductive layer, and a tungsten film can be used as the second conductive layer.

  In this embodiment mode, transistors, capacitors, and resistors having different electrode structures are used for the same photomask using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function including a diffraction grating pattern or a semi-transmissive film. Alternatively, a method of making differently by an etching process using a reticle is shown. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 6.

(Embodiment 8)
In this embodiment, an example of a static RAM (SRAM) that can be used as the memory circuit 210 or the like of the semiconductor device 201 is described with reference to FIGS.

  The semiconductor layer 10 and the semiconductor layer 11 illustrated in FIG. 15A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, as the semiconductor layer 10 and the semiconductor layer 11, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

  In any case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. By etching the semiconductor layer using the mask pattern, island-shaped semiconductor layers 10 and 11 having a specific shape including a source region and a drain region of the transistor and a channel formation region are formed.

  A photomask for forming the semiconductor layer 10 and the semiconductor layer 11 shown in FIG. 15A includes a mask pattern 2000 shown in FIG. The mask pattern 2000 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. When a positive resist is used, the mask pattern 2000 shown in FIG. 15B is manufactured as a light shielding portion. The mask pattern 2000 has a shape obtained by deleting the top A of the polygon. Further, the bent portion B has a shape that bends so that the corner portion does not become a right angle. When the bent portion B is enlarged, the bent portion B is bent in a plurality of steps (see the configuration shown in FIG. 6 in Embodiment 5).

  The shape of the mask pattern 2000 shown in FIG. 15B is reflected in the semiconductor layers 10 and 11 shown in FIG. In that case, a shape similar to the mask pattern 2000 may be transferred, but it may be transferred so that the corners of the mask pattern 2000 are further rounded. That is, you may provide the round part which made the pattern shape smoother than the mask pattern 2000 further.

  An insulating layer containing at least part of silicon oxide or silicon nitride is formed over the semiconductor layer 10 and the semiconductor layer 11. One purpose of forming this insulating layer is a gate insulating layer. Then, as illustrated in FIG. 16A, the gate wiring 12, the gate wiring 13, and the gate wiring 14 are formed so as to partially overlap the semiconductor layer. The gate wiring 12 is formed corresponding to the semiconductor layer 10. The gate wiring 13 is formed corresponding to the semiconductor layer 10 and the semiconductor layer 11. The gate wiring 14 is formed corresponding to the semiconductor layer 10 and the semiconductor layer 11. As the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and the shape thereof is formed over the insulating layer by a photolithography technique.

  A photomask for forming this gate wiring is provided with a mask pattern 2100 shown in FIG. This mask pattern 2100 has corner portions bent into an L-shape, and each side of the right triangle is 10 μm or less, or less than 1/2 the line width of the mask pattern 2100 and 1/5 or more of the line width. Delete the part and give the corner part a rounded pattern. That is, the outer periphery of the mask pattern 2100 at the corner portion viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other sandwiching the corner portion, and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the mask pattern 2100 corresponding to the right isosceles triangular portion formed by When removed, two obtuse angle portions are newly formed in the mask pattern 2100. By appropriately setting the mask design and etching conditions, each obtuse angle portion has a curve in contact with both the first line and the second line. The mask pattern 2100 is preferably etched so as to be formed. The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. The shape of the mask pattern 2100 illustrated in FIG. 16B is reflected in the gate wiring 12, the gate wiring 13, and the gate wiring 14 illustrated in FIG. In that case, a shape similar to the mask pattern 2100 may be transferred, or the corner of the mask pattern 2100 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 2100 may be provided. That is, the corners of the gate wiring 12, the gate wiring 13, and the gate wiring 14 may be rounded. The convex part suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and the concave part significantly improves the yield as a result of washing away the fine powder generated at the time of cleaning, which tends to collect at the corner. It has the effect that it can be expected.

  The interlayer insulating layer is a layer formed next to the gate wiring 12, the gate wiring 13, and the gate wiring 14. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material using polyimide, acrylic resin, or the like. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wiring 12, the gate wiring 13, and the gate wiring 14. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities that are not good for the thin film transistor (TFT) such as exogenous metal ions and moisture.

  Openings are formed in predetermined positions in the interlayer insulating layer. For example, the opening is provided corresponding to the gate wiring or the semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 17A, the wiring 15, the wiring 16, the wiring 17, the wiring 18, the wiring 19, and the wiring 20 are formed so as to partially overlap the semiconductor layer 10 and the semiconductor layer 11. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in a contact portion with another wiring or in another region. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

  A photomask for forming the wirings 15 to 20 includes a mask pattern 2200 shown in FIG. Also in this case, the wiring is a corner portion that is bent into an L-shape and one side of the right triangle is 10 μm or less, or 1/2 or less of the line width of the wiring and 1/5 or more of the line width. Remove the corners so that the corners have a rounded pattern. That is, the outer periphery of the wiring at the corner portion viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other sandwiching the corner portion, and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the wiring corresponding to the right isosceles triangular portion formed by is removed. When removed, two obtuse angle parts are newly formed on the wiring. By appropriately setting the mask design and etching conditions, a curve that touches both the first straight line and the second straight line is formed at each obtuse angle part. It is preferable to etch the wiring so that the The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. In such wiring, the convex part suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and the concave part is washed away even if it is fine powder produced at the time of cleaning. As a result, the yield can be expected to be greatly improved. Since the corners of the wiring are rounded, an effect of improving the electrical conduction of the wiring can be expected. Further, in a structure in which a large number of wirings are provided in parallel, it is very convenient to wash out dust by using wirings with rounded corners.

  FIG. 17A shows an N-channel transistor 21, an N-channel transistor 22, an N-channel transistor 23, an N-channel transistor 24, a P-channel transistor 25, and a P-channel transistor 26. Is formed. The N channel type transistor 23 and the P channel type transistor 25 constitute an inverter 27. The N channel type transistor 24 and the P channel type transistor 26 constitute an inverter 28. The circuit including these six transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed over these transistors.

  This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 7.

  In this embodiment, the use of the semiconductor device 201 of the present invention will be described with reference to FIGS. The semiconductor device 201 includes, for example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 9A), packaging containers (wrapping paper, bottles, etc. (See (B)), and can be used by being provided on a recording medium (see FIG. 9C) such as DVD software, CD, or video tape. Also provided for vehicles such as cars, motorcycles and bicycles (see FIG. 9D), personal items such as bags and glasses (see FIG. 9E), foods, clothing, daily necessities, electronic devices, etc. Can be used. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions or television receivers), cellular phones, and the like.

  The semiconductor device 201 can be fixed to the article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing the semiconductor device 201 for bills, coins, securities, bearer bonds, certificates, and the like. Further, by providing the semiconductor device 201 in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. . In addition, forgery and theft can be prevented by providing the semiconductor device 201 in the vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by burying a wireless tag in a living creature such as livestock, it is possible to easily identify the year of birth, sex, type, or the like.

  As described above, the semiconductor device 201 of the present invention can be provided and used for any article (including a living thing).

  The semiconductor device 201 has various advantages such as that it can transmit and receive data by wireless communication, can be processed into various shapes, and has a wide directivity and wide recognition range depending on the selected frequency. .

  Next, one mode of a system using the semiconductor device 201 is described with reference to FIG. A reader / writer 820 is provided on the side surface of the portable terminal including the display portion 821, and a semiconductor device 201 is provided on the side surface of the article 822 (see FIG. 8A). When the reader / writer 820 is held over the semiconductor device 201 included in the article 822, information about the article such as the raw material and origin of the article 822, the inspection result for each production process, the history of the distribution process, and the explanation of the article is displayed on the display unit 821. The As another system, the article 826 can be inspected using the reader / writer 824 and the semiconductor device 201 when the article 826 is conveyed by a belt conveyor (see FIG. 8B). In this manner, by utilizing the semiconductor device 201 of the present invention in the system, information can be easily acquired, and a system that realizes high functionality and high added value can be provided.

  This embodiment can be implemented by being freely combined with Embodiment Modes 1 to 8.

The figure explaining Embodiment 1 and Embodiment 2 of this invention. The figure explaining the conventional structure. The figure explaining the conventional structure. FIG. 6 illustrates Embodiment 2 of the present invention. FIG. 9 illustrates Embodiment 3 of the present invention. FIG. 9 illustrates Embodiment 4 of the present invention. FIG. 6 is a diagram for explaining a fifth embodiment of the present invention. The figure explaining the Example of this invention. The figure explaining the Example of this invention. FIG. 6 is a diagram for explaining a fifth embodiment of the present invention. FIG. 9 is a diagram for explaining Embodiment 6 of the present invention. The figure explaining the routing method of wiring. FIG. 10 illustrates Embodiment 7 of the present invention. FIG. 10 illustrates Embodiment 7 of the present invention. The figure explaining Embodiment 8 of this invention. The figure explaining Embodiment 8 of this invention. The figure explaining Embodiment 8 of this invention.

Explanation of symbols

10 semiconductor layer 11 semiconductor layer 12 gate wiring 13 gate wiring 14 gate wiring 15 wiring 16 wiring 17 wiring 18 wiring 19 wiring 20 wiring 21 transistor 22 transistor 23 transistor 24 transistor 25 transistor 26 transistor 27 inverter 28 inverter 101 semiconductor device 102 antenna 103 high frequency Circuit 104 power supply circuit 105 reset circuit 106 clock generation circuit 107 data demodulation circuit 108 data modulation circuit 109 control circuit 110 memory circuit 111 semiconductor integrated circuit 112 rectifier circuit 113 holding capacitor 114 constant voltage circuit 201 semiconductor device 202 antenna 203 high frequency circuit 204 power supply circuit 205 reset circuit 206 clock generation circuit 207 data demodulation circuit 208 data modulation circuit 209 control circuit 210 memory Circuit 211 semiconductor integrated circuit 212 rectifier circuit 213 holding capacitor 214 constant voltage circuit 215 level shift circuit 302 second conductive layer 303 first conductive layer 304 wiring 305 semiconductor layer 306 impurity region 307 impurity region 308 insulating layer 309 gate electrode 310 impurity region 311 Impurity region 312 Impurity region 501 Transistor 502 Transistor 503 Transistor 504 Transistor 505 Transistor 506 Transistor 507 Transistor 508 Transistor 600 Substrate 601 Element group 602 Conductive particle 604 Resin 610 Substrate 661 Base film 662 Semiconductor layer 662a Channel formation region 662b Impurity region 662c Low-concentration impurity region 663 First insulating layer 664 Gate electrode 665 Third insulating layer 666 Wiring 667 Second insulating layer 668 Fourth insulating layer 701 Flexible substrate 720 Wireless tag 801 Protective layer 802 Antenna 803 Protective layer 804 Element group 805 One of source and drain 806 The other of source and drain 807 Gate electrode 820 Reader / writer 821 Display unit 822 Product 824 Reader / Writer 826 Article 880 Substrate 881 Transistor 901 Level-shifted demodulated signal 902 Clock 903 Reset signal 904 Analog section 905 Digital section 911 Demodulated signal 912 Clock 913 Reset signal 914 Analog section 915 Digital section 921 Demodulated signal 1501a Corner section 1501b Corner section 1501c Corner Part 1502a Corner part 1502b Corner part 1502c Corner part 2000 Mask pattern 2100 Mask pattern 2200 Mask pattern 2001 Transistor 2 02 transistor 2003 transistor 2004 capacitor element 2005 resistor element 3003 thickness 3004 carrier moving direction 3005 direction 3011 wiring 3012 wiring 3013 wiring 3014 contact hole 6001 corner portion 6002 corner portion 6003 corner portion 6004 corner portion 6601 semiconductor layer 6602 semiconductor layer 6603 first Conductive layer 6604 Second conductive layer 6605 Contact hole

Claims (5)

A data demodulation circuit for demodulating a radio signal;
A level shift circuit to which an output signal of the data demodulation circuit is input;
A control circuit to which the output of the level shift circuit is input,
The level shift circuit is supplied with a first DC power supply voltage and a second DC power supply voltage having a smaller voltage amplitude than the first DC power supply voltage,
The control circuit is supplied with the second DC power supply voltage,
The level shift circuit converts an input signal having the same voltage amplitude as the first DC power supply voltage into a signal having the same voltage amplitude as the second DC power supply voltage, and outputs the converted signal. An antenna capable of communicating data by wireless communication;
A data demodulation circuit for demodulating a radio signal;
A level shift circuit to which an output signal of the data demodulation circuit is input;
A control circuit to which the output of the level shift circuit is input,
The level shift circuit is supplied with a first DC power supply voltage and a second DC power supply voltage having a smaller voltage amplitude than the first DC power supply voltage,
The control circuit is supplied with the second DC power supply voltage,
The level shift circuit converts an input signal having the same voltage amplitude as the first DC power supply voltage into a signal having the same voltage amplitude as the second DC power supply voltage, and outputs the converted signal. An antenna capable of communicating data by wireless communication;
A data demodulation circuit for demodulating a radio signal;
A power supply circuit that generates a first DC power supply voltage and a second DC power supply voltage having a smaller voltage amplitude than the first DC power supply voltage from the radio signal;
A level shift circuit to which an output signal of the data demodulation circuit is input;
A control circuit to which the output of the level shift circuit is input,
The level shift circuit is supplied with the first DC power supply voltage and the second DC power supply voltage,
The control circuit is supplied with the second DC power supply voltage,
The level shift circuit converts an input signal having the same voltage amplitude as the first DC power supply voltage into a signal having the same voltage amplitude as the second DC power supply voltage, and outputs the converted signal.   4. The semiconductor device according to claim 1, wherein the control circuit is a circuit that analyzes a signal obtained by demodulating the radio signal.   5. The semiconductor device according to claim 1, wherein a pulse width of an output signal of the data demodulating circuit is the same as a pulse width of an output signal of the level shift circuit. 6.

Images