JP2007005626A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

In a semiconductor device including a film for generating stress in a channel formation region of a field effect transistor formed on a surface of a semiconductor substrate, when the film for generating stress is discontinuously formed on the surface of the substrate, Film peeling occurs from that portion.
The entire surface of the substrate other than the region of the substrate surface where the n-channel conductivity type field effect transistor and the p-channel conductivity type field effect transistor are formed is continuously covered with a film that generates stress.
[Selection] Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor device having a field effect transistor having a MIS structure (Metal Insulator Semiconductor).

  A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using an oxide film as an insulating film among transistors having a MIS structure has been put into practical use. MOSFETs are widely used as LSI devices because they consume less power and can be miniaturized, highly integrated, and operated at high speed.

  In recent years, information communication means have been developed, and the performance required for this type of MOSFET has been increased. Therefore, an operation speed-up technique for intentionally applying stress to the channel formation region of the MOSFET and distorting the crystal of the semiconductor substrate to increase carrier mobility has been studied. Among them, a dual stress liner technology (hereinafter referred to as DSL technology) in which a film for generating a tensile stress in an n channel formation region of an nMOSFET and a film for generating a compressive stress in a p channel formation region of a pMOSFET are formed on each MOSFET. ) Is known (for example, see Patent Document 1).

  FIG. 8 is a schematic cross-sectional view of a semiconductor device using a conventionally known DSL technique. A source region 102 and a drain region 103 are formed in the first region on the semiconductor substrate 101, and a channel formation region 104 is formed in the surface region of the semiconductor substrate 101 between them. A gate insulating film 105 and a gate electrode 106 are formed on the channel formation region 104, and a sidewall 107 is formed on the side wall of the gate electrode 106. A silicide 108 is formed on the source region 102, the drain region 103, and the gate electrode 106 to form an nMOSFET. A first film 109 is formed on the nMOSFET, and stress is generated in the channel formation region 104. The carrier mobility of the channel formation region 104 is affected by the magnitude of the generated stress. Usually, the material, film thickness, and the like of the first film 109 are selected so that tensile stress is generated in the nMOSFET.

  Element isolation regions 110 and 111 are formed on the semiconductor substrate 101, and a scribe region is formed therebetween. In the second region on the semiconductor substrate 101, a source region 112, a drain region 113, a channel formation region 114, a gate insulating film 115, a gate electrode 116, a side wall 117, and a silicide 118 are formed to constitute a pMOSFET. . A second film 119 is formed on the pMOSFET to generate stress in the channel formation region 114. In general, the material, film thickness, and the like of the second film 119 are selected so that compressive stress is generated in the pMOSFET.

  The scribe region between the first region and the second region is a region that is cut by dicing after the semiconductor substrate process is completed. An interlayer insulating film 120 is formed on the first film 109 and the second film 119, a contact hole 121 for electrically connecting the nMOSFET and the pMOSFET is formed, and a plug metal 122 is filled.

In the semiconductor device described above, the first film 109 that generates tensile stress is removed from the region other than the first region after being deposited on the entire surface of the semiconductor substrate 101. Similarly, the second film 119 that generates compressive stress is also removed from the region other than the second region after being deposited on the entire surface of the semiconductor substrate 101.
JP 2003-86708 A

  However, in the semiconductor device described above, the first film 109 that applies stress to the channel formation region 104 has its own stress (this is referred to as intrinsic stress). If the end portion 124 of the second film 119 is discontinuously formed so as to be exposed, it is exposed to subsequent heat treatment or the like, and further thermal strain is applied, and the first film 109 and the second film 119 are exposed. Film peeling easily occurred from the end portions 123 and 124 of the film 119.

  Further, in the above semiconductor device, the first film 109 is deposited and then etched and removed from the scribe region and the second region, and then the second film 119 is deposited and then the scribe region and the first region. The second film 119 is etched away from the region. That is, the end 123 of the first film 109 is once exposed to the etching atmosphere (or etching solution) when the first film 109 is etched away, and then the second film 119 is etched away. Sometimes it was exposed to the etching atmosphere, and the adhesion to the underlying film deteriorated. Therefore, when thermal strain due to the subsequent heat treatment is applied, the film peeling easily occurs especially at the end portion 123.

  Thus, when the end portions 123 and 124 of the first film 109 and the second film 119 having intrinsic stress are discontinuously terminated on the semiconductor substrate 101 with other stress generation films, There was a problem that strain was accumulated by applying stress and the film peeled off. In particular, when the end portion of the first film 109 is not covered with the second film 119, this problem becomes significant. When the film was peeled off during the process, the peeled film was scattered around and turned into dust, which caused a decrease in yield.

  In order to solve the above problems, the present invention has taken the following measures.

  In the present invention according to claim 1, an n-channel conductivity type field effect transistor formed in a first region on a semiconductor substrate and a p-channel conductivity type field effect transistor formed in a second region different from the first region. A first film that is formed on the n-channel conductivity type field effect transistor and generates stress on the n-channel conductivity type field effect transistor, and is formed on the p-channel conductivity type field effect transistor, a p-channel conductivity type field effect transistor having a second film for generating a stress different from that of the first film, wherein the first region and the second region excluding the second region A semiconductor device in which the first film and / or the second film is formed on the entire surface of the third region, which is the first region.

  In this invention which concerns on Claim 2, said 1st film | membrane and said 2nd film | membrane are formed in said 3rd area | region, and the edge part of said 1st film | membrane is covered with said 2nd film | membrane. The semiconductor device according to claim 1.

  In the present invention according to claim 3, the semiconductor device according to claim 1 or 2, wherein the third region includes a scribe region.

  In the present invention according to claim 4, the first film generates a tensile stress in the n-channel conductivity type field effect transistor, and the second film generates a compressive stress in the p-channel conductivity type field effect transistor. A semiconductor device according to any one of claims 1 to 3 is provided.

  In the present invention according to claim 5, the step of forming an n-channel conductivity type field effect transistor in a first region on a semiconductor substrate and a p-channel conductivity type field effect transistor in a second region different from the first region. And a step of selectively forming a first film for generating stress on the n-channel conductivity type field effect transistor on the first region; and the first film on the p-channel conductivity type field effect transistor; Forming a second film for generating different stresses selectively on the second region, and a method of manufacturing a semiconductor device, the semiconductor excluding the first region and the second region A method for manufacturing a semiconductor device is provided in which the first film and / or the second film is selectively formed over the entire surface of the third region, which is another region on the substrate.

  In this invention which concerns on Claim 6, depositing said 2nd film | membrane on said 1st film | membrane, and then excluding the vicinity of the edge part of 1st film | membrane, said 2nd film | membrane is 1st film | membrane. The semiconductor device according to claim 5 is selectively removed from above.

  In the present invention according to claim 7, the first film generates a tensile stress in the n-channel conductivity type field effect transistor, and the second film generates a compressive stress in the p-channel conductivity type field effect transistor. A method for manufacturing a semiconductor device according to claim 5 or 6 is provided.

  According to the present invention, the first film or the second film is formed on the entire surface of the third region which is another region on the semiconductor substrate excluding the first region and the second region, or the first film Since both the first film and the second film are continuously formed, the film is peeled off from the third region, which is the peripheral region, by heat treatment after forming the first film and the second film. Occurrence can be prevented.

  Furthermore, according to the present invention, the end of the first film is covered with the second film, and the end of the first film is exposed to the etching atmosphere of the second film in the etching process of the second film. Therefore, without deteriorating the adhesion of the first film, the resistance to thermal strain caused by the subsequent heat treatment is improved, and the film peeling can be prevented.

  Embodiments of the present invention will be described below. In the following description, the term “on the semiconductor substrate” refers to the surface or the surface on which the elements of the semiconductor substrate are formed, and does not refer to the back surface of the semiconductor substrate unless otherwise specified.

  According to the embodiment of the present invention, the nFET is formed in the first region on the semiconductor substrate, and the pFET is formed in the second region different from the first region. A first film that generates stress in the nFET is selectively formed in the first region including the nFET, and a second film that generates stress different from the first film in the pFET includes the second film including the pFET. It is selectively formed in the region. For the first film, a material that generates a tensile stress in the nFET is selected. For example, a silicon nitride film by a thermal CVD (thermal chemical vapor deposition) method is used. For the second film, a material that generates compressive stress in the pFET is selected. For example, a silicon nitride film formed by a thermal CVD method formed under conditions different from those of the first film is used.

  The first film or the second film, or the other area on the semiconductor substrate excluding the first area and the second area so that the first film and the second film are continuous. Is formed on the entire surface of the third region.

  Since the first film and the second film are usually deposited by different film forming processes, the terminal portion of the first film or the second film is necessarily formed on the surface of the semiconductor substrate. In this case, the second film is formed so as to overlap the terminal portion of the first film. For example, since the first film has a tensile stress and the second film has a compressive stress, the overall stress on the substrate can be reduced by laminating the first film and the second film. Can do. Thereby, film peeling can be prevented also in this laminated portion.

  In the embodiment of the present invention, the third region may include a scribe region. This is because the scribe region is cut and removed in the final stage of the semiconductor substrate process, but it is necessary to prevent film peeling also in this region during the substrate process. The third region can include a field region in which a wiring layer is formed and a pad region formed in the peripheral portion of the semiconductor chip. That is, in the semiconductor chip, all the surfaces on the semiconductor substrate other than the first region and the second region where the nFET and the pFET are formed are covered with the first film or the second film.

  The first film and the second film are deposited by a plasma CVD (plasma chemical vapor deposition) method or a low pressure CVD (low pressure chemical vapor deposition) method in addition to the thermal CVD method with different film formation conditions. A silicon nitride film can be used. In addition to the silicon nitride film, a silicon oxide film or other materials can be used, and a composite film composed of a plurality of layers may be used in addition to a single layer film.

  Embodiments according to the present invention will be described in detail below. In addition, in each figure, the same code | symbol was attached | subjected to the same element.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device in which an nFET and a pFET are formed in the present embodiment. First, element isolation regions 2 and 3 are formed on the surface of the semiconductor substrate 1, and a first region for forming an nFET, a second region for forming a pFET, and a third region formed therebetween are defined. Hereinafter, in the present embodiment, the third region will be described as a scribe region.

  The element isolation regions 2 and 3 are formed as follows. First, a silicon nitride film is deposited on the entire surface of the semiconductor substrate 1 by low pressure CVD (low pressure chemical vapor deposition). Next, the silicon nitride film and the semiconductor substrate 1 in the regions to be the element isolation regions 2 and 3 are selectively removed sequentially by photolithography and etching techniques to form shallow trenches. Next, a silicon oxide film is deposited and buried in this trench by a low pressure CVD method. Thereafter, chemical mechanical polishing (CMP) is performed and planarized, and then an oxidation treatment is performed in an oxygen atmosphere to densify the oxide film, thereby forming element isolation regions 2 and 3.

  Next, the gate insulating film 4 and the gate electrode 5 are formed. The gate insulating film 4 is formed by thermally oxidizing the semiconductor substrate 1, and then polysilicon is deposited by low pressure CVD. The gate electrode 5 is formed by selectively removing the polysilicon by photolithography and etching techniques. Next, ion implantation is performed using the gate electrode 5 as a mask to form an LDD (lightly doped drain) region. Arsenic or phosphorus is ion-implanted into the nFET, and boron is ion-implanted into the pFET. Next, a silicon nitride film and a silicon oxide film are deposited by plasma CVD, and anisotropic etching is performed to form side walls 6 on the gate electrode 5. Next, ion implantation is performed using the gate electrode 5 and the sidewall 6 as a mask to form the source region / drain region 7. Arsenic or phosphorus is ion-implanted into the nFET and boron is ion-implanted into the pFET. At this time, the impurity region 7 ′ is formed by simultaneously implanting ions into the scribe region between the element isolation regions 2 and 3. However, if necessary, the ion implantation may not be performed by masking.

  Next, cobalt is deposited on the entire surface of the semiconductor substrate 1 by sputtering, is subjected to rapid thermal annealing (RTA) to be silicided (CoSi), and then the cobalt is removed to form the source region / drain region 7. The conductive layer 8 is selectively formed in the gate electrode 5 and the third region. In this manner, an nFET is formed in the first region and a pFET is formed in the second region, and a scribe region is formed between the two element isolation regions 2 and 3. An n-channel formation region 9 is formed in a surface region on the semiconductor substrate 1 immediately below the gate insulating film 4 of the nFET, and a p-channel formation region 10 is formed in a surface region on the semiconductor substrate 1 immediately below the gate insulating film 4 of the pFET. The

  FIG. 2 is a schematic cross-sectional view of a semiconductor device in which the first film 11 is selectively formed in the present embodiment. A silicon nitride film was used as the first film 11. The silicon nitride film is formed by a thermal CVD (thermal chemical vapor deposition) method using an organic source gas. Next, the silicon nitride film which is the first film 11 is left in the first region including the nFET and removed from the scribe region and the second region including the pFET by photolithography and etching techniques. In this way, a tensile stress can be generated for the n channel forming region 9 of the nFET.

  FIG. 3 is a schematic cross-sectional view of a semiconductor device in which the second film 12 is selectively formed in the present embodiment. A silicon nitride film was used as the second film 12. The silicon nitride film was formed under conditions different from those of the first film 11 by a thermal CVD method using an organic source gas. Next, the second film 12 is removed from the first film 11 on the nFET, leaving the second film 12 including the pFET and the scribe region by photolithography and etching techniques. At this time, the element isolation region 2 is selectively removed from the first film 11 while leaving a part of the second film 12 so as to overlap the first film 11. By forming a silicon nitride film as the second film 12 on the pFET, a compressive stress can be generated in the p-channel formation region 10 of the pFET.

  In this way, the second film 12 is formed without a break on the entire surface of the third region including the scribe region. The first film 11 and the second film 12 are continuously formed on the element isolation region 2, and the end of the first film 11 is covered with the second film 12. . As a result, the end portion of the first film 11 is not exposed to the etching atmosphere during the etching process of the second film 12.

  FIG. 4 is a schematic cross-sectional view of a semiconductor device in which the interlayer insulating film 13 and the plug metal 15 are formed in the present embodiment. An interlayer insulating film 13 made of a silicon oxide film is deposited on the first film 11 and the second film 12 on the semiconductor substrate 1. Next, contact holes 14 are formed in the interlayer insulating film 13. The contact hole 14 is subjected to anisotropic etching of the interlayer insulating film 13 until the conductive layer 8 is exposed by using photolithography and reactive ion etching (RIE) technology. Next, a plug metal 15 is deposited in the contact hole 14, and then CMP is performed to planarize the surface so that it can be electrically connected to the source / drain regions 7 of the nFET and pFET.

  In the description of the above embodiment, the overlapping portion of the first film 11 and the second film 12 is formed on the element isolation region 2, but this is applied to the entire surface of the third region. 11 and the overlapping portion of the first film 11 and the second film 12 can be formed on the element isolation region 3.

  FIG. 5 is a schematic cross-sectional view of a semiconductor device showing another embodiment of the present invention, in which an nFET and a pFET are formed separately in a first region and a second region on the semiconductor substrate 1, respectively. A state in which one film 11 is selectively formed is shown.

  An nFET is formed in the first region on the semiconductor substrate 1, a pFET is formed in the second region, and a third region is formed between the first region and the second region. Hereinafter, the third area will be described as a field area.

  First, a silicon nitride film is deposited on the entire surface of the semiconductor substrate 1 by a low pressure CVD method, and then the silicon nitride film and the semiconductor substrate 1 in a region to be a field region are selectively removed sequentially by photolithography and etching techniques. A shallow trench is formed. Next, a silicon oxide film is deposited by low pressure CVD to fill the trench. Next, planarization is performed by CMP, and then an oxidation treatment is performed in an oxygen atmosphere to densify the oxide film, thereby forming a field oxide film 20. The field oxide film 20 also has an element isolation function.

  Next, the semiconductor substrate 1 is thermally oxidized to form the gate insulating film 4, and polysilicon is deposited thereon by low pressure CVD, and selectively removed by photolithography and etching techniques to form the gate electrode 5. . Next, ion implantation is performed using the gate electrode 5 as a mask to form an LDD region. Thereafter, a sidewall 6 is formed on the gate electrode 5, and ion implantation is performed using the gate electrode 5 and the sidewall 6 as a mask to form a source region / drain region 7. Next, cobalt is deposited on the entire surface of the semiconductor substrate 1 by sputtering, and after RTA treatment is performed for silicidation, the cobalt is removed and the conductive layer 8 is selectively formed.

  As described above, the nFET is formed in the first region, the pFET is formed in the second region, and the n-channel formation region 9 and the p-channel formation region 10 are formed immediately below the gate insulating film 4 of the nFET and the pFET.

  Next, the first film 11 is deposited on the entire surface of the semiconductor substrate 1. A silicon nitride film is deposited as the first film 11 by a thermal CVD method. Next, the first film 11 is selectively formed on part of the first region nFET and the third region field oxide film 20 by photolithography and etching techniques. The first film 11 generates stress in the n-channel formation region 9 of the nFET. In general, tensile stress is generated for nFETs.

  FIG. 6 is a schematic cross-sectional view of the semiconductor device showing a state in which the second film 12 is selectively formed in the present embodiment. A second film 12 is deposited on the entire surface of the semiconductor substrate 1. A silicon nitride film is formed as the second film 12 by a thermal CVD method under conditions different from those of the first film 11. Next, the second film 12 is removed from the first film 11 except for a part on the end region of the first film 11 by photolithography and etching techniques. Therefore, the end portion 21 of the first film 11 is not exposed to the etching atmosphere when the second film 12 is etched.

  The second film 12 generates stress in the p channel formation region 10 of the pFET. Usually, a compressive stress is generated for the pFET. If the first film 11 is set to have a tensile stress and the second film 12 has a compressive stress, the intrinsic stress cancels out at the overlapping portion of the first film 11 and the second film 12. Therefore, even if thermal strain due to heat treatment is applied in the subsequent process, film peeling does not occur.

  FIG. 7 is a schematic cross-sectional view of the semiconductor device showing a state in which the interlayer insulating film 13 and the wiring layer 22 are formed in the present embodiment. A silicon oxide film is deposited on the first film 11 and the second film 12 to form an interlayer insulating film 13. Next, a contact hole 14 is formed in order to make contact with the source / drain region 7, and then a barrier metal (not shown) and a plug metal 15 are sequentially deposited to fill the contact hole 14, and then interlayer insulation The surface of the film 13 is flattened by CMP. Next, a wiring layer 22 is selectively formed on the surface of the interlayer insulating film 13.

  In the present embodiment, the overlapping region of the first film 11 and the second film 12 is provided on the field oxide film 20, but it may be a region where other elements are formed.

  In the above description, the stress of the first film 11 and the second film 12 is a film having tensile stress and compressive stress, but both the first film 11 and the second film 12 have compressive stress. Even in this case, the first film 11 can be applied to the present embodiment even when the compressive stress is smaller than that of the second film 12.

It is typical sectional drawing of the semiconductor device in this Embodiment. It is typical sectional drawing of the semiconductor device in this Embodiment. It is typical sectional drawing of the semiconductor device in this Embodiment. It is typical sectional drawing of the semiconductor device in this Embodiment. It is typical sectional drawing of the semiconductor device in other this Embodiment. It is typical sectional drawing of the semiconductor device in other this Embodiment. It is typical sectional drawing of the semiconductor device in other this Embodiment. It is a typical sectional view of a conventionally well-known semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1, 2 Element isolation region 4 Gate insulating film 5 Gate electrode 6 Side wall 7 Source region / drain region 8 Conductive layer 9 N channel formation region 10 P channel formation region 11 First film 12 Second film 13 Interlayer Insulating film 14 Contact hole 15 Plug metal 20 Field oxide film 21 End 22 Wiring layer

Claims (7)

An n-channel conductivity type field effect transistor formed in a first region on a semiconductor substrate and a p-channel conductivity type field effect transistor formed in a second region different from the first region;
A first film formed on the n-channel conductivity type field effect transistor and generating stress in the n-channel conductivity type field effect transistor;
A semiconductor device having a second film formed on the p-channel conductivity type field effect transistor and generating stress different from the first film in the p-channel conductivity type field effect transistor,
A semiconductor device in which the first film and / or the second film are formed on the entire surface of a third region which is another region on the semiconductor substrate excluding the first region and the second region.   2. The semiconductor device according to claim 1, wherein the first film and the second film are formed in the third region, and an end portion of the first film is covered with the second film.   The semiconductor device according to claim 1, wherein the third region includes a scribe region.   4. The method according to claim 1, wherein the first film generates a tensile stress in the n-channel conductivity type field effect transistor, and the second film generates a compressive stress in the p-channel conductivity type field effect transistor. The semiconductor device according to item. Forming an n-channel conductivity type field effect transistor in a first region on a semiconductor substrate and a p-channel conductivity type field effect transistor in a second region different from the first region;
Selectively forming a first film on the first region for generating stress in the n-channel conductivity type field effect transistor;
And a step of selectively forming a second film on the p-channel conductivity type field effect transistor that generates a stress different from that of the first film on the second region. ,
A semiconductor device that selectively forms the first film and / or the second film on the entire surface of a third region, which is another region on the semiconductor substrate, excluding the first region and the second region. Production method.   Depositing the second film on the first film, and then selectively removing the second film from above the first film except near the edges of the first film. 5. The semiconductor device according to 5. The said 1st film | membrane produces | generates a tensile stress in the said n channel conductivity type field effect transistor, and a said 2nd film | membrane produces a compressive stress in the said p channel conductivity type field effect transistor. Semiconductor device manufacturing method.

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