JP2006294942A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of forming a hole pattern at a high density even when the diameter of a via plug or a contact plug is reduced, and a method for manufacturing the same.
In a semiconductor device provided with a via hole that communicates in a vertical direction with at least one wiring formed at a predetermined interval on an insulating film, an elliptical shape is formed at a first lithography position 13A so that one end overlaps the wiring 11. By exposing the first hole pattern and exposing an elliptical second hole pattern at the second lithography position 13B so that one end overlaps the one end of the first hole pattern, the two hole patterns are formed. A via hole 12 is formed in the overlapping portion.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a via hole communicating with a wiring on a wafer from a vertical direction, and a method for manufacturing the same, and in particular, a hole pattern can be formed at a high density even when the diameter of a via plug or a contact plug is reduced. The present invention relates to a possible semiconductor device and a manufacturing method thereof.

  In recent years, in semiconductor devices, with miniaturization of elements, via plugs that electrically connect multilayer wirings and contact plugs that connect wirings and transistor electrodes formed on a Si substrate It is required to form with an ultrafine diameter of 100 nm or less.

  Conventionally, for via plugs and contact plugs, a hole pattern with an ultrafine diameter is formed with a photoresist using a lithography technique. However, in a fine hole pattern with a hole diameter of 100 nm or less, the hole pattern is increased due to the optical limit of lithography. It has become difficult to arrange with density.

  That is, when a desired hole diameter is formed by lithography, the minimum pitch p between holes is generally p> 1 (much larger than 1). As a solution to this problem, it is conceivable to secure an exposure margin during lithography by forming the hole pattern in an elliptical shape. If the hole pattern is elliptical, the pitch in the minor axis direction of the hole pattern can be reduced, so that via plugs and contact plugs can be arranged at the minimum pitch.

  In order to form an elliptical hole pattern, a mask having an elliptical shape whose short axis is equal to or less than the wavelength of the irradiation light is used, and the mask and the resist on the substrate are moved relative to each other in the long axis direction. A resist pattern forming method is known in which a resist pattern is formed by superimposing a part of two elliptical optical images (see, for example, Patent Document 1).

  According to the resist pattern forming method of Patent Document 1, a first optical image is formed by irradiating light onto a resist surface on a substrate through an elliptical mask, and then the substrate and the mask are formed into an elliptical long axis. A second elliptical optical image is formed by irradiating light with a mask arranged so that the first optical image partially overlaps with relative movement in the direction. Thereby, an elongated resist pattern having a size sufficiently larger than the wavelength of light used for exposure in the major axis direction is formed by a combination of the first optical image and the second optical image that are partially overlapped. .

However, according to Patent Document 1, since the size in the major axis direction of the resist pattern becomes large, the major axis size of the resist pattern is larger than the wiring pitch in the substrate in which the upper layer wiring and the lower layer wiring are arranged to intersect each other. There is a problem that it becomes difficult to form a high-density hole pattern and the layout of the wiring is restricted, and the degree of integration cannot be improved in accordance with the miniaturization of the semiconductor device.
JP 2000-208394 A ([0076] to [0088], FIG. 3, FIG. 5, FIG. 6)

  An object of the present invention is to provide a semiconductor device capable of forming a hole pattern at a high density even when the diameter of a via plug or a contact plug is reduced, and a method for manufacturing the same.

  According to one embodiment of the present invention, there is provided a connection member having a cross-sectional shape defined by a conductive layer and a region of an overlapping portion of a pattern having two major axes and a minor axis arranged so as to partially overlap each other. A semiconductor device is provided.

  According to another aspect of the present invention, a first connection hole having a major axis and a minor axis having a predetermined depth that does not reach the conductive layer is formed in an insulating film formed on the conductive layer. And a second connecting hole having a pattern of a major axis and a minor axis that partially overlaps the first connecting hole and has a depth reaching the conductive layer. And a third step of forming a connection member connected to the conductive layer by filling the first and second connection holes with a conductive material. provide.

  According to the semiconductor device and the manufacturing method thereof of the present invention, the hole pattern can be formed at a high density even if the diameter of the via plug or the contact plug is reduced.

  The present invention relates to a connection member for connecting a conductive layer and wiring thereon and a method for manufacturing the connection member. Here, in the embodiment described below, the conductive layer represents a wiring or an impurity region on the semiconductor substrate, and the connection member represents a via plug or a contact plug. However, the present invention is not limited to the embodiment and the gist thereof is not changed. Various modifications are possible within the range.

[First embodiment]
(Configuration of semiconductor device)
FIG. 1 is a plan view showing a semiconductor device according to the first embodiment of the present invention. This semiconductor device 1 is formed by opening a wiring 11 made of Cu formed at a predetermined interval on an insulating layer provided with a predetermined thickness on a semiconductor substrate and an insulating layer formed on the wiring 11. Via hole 12. In the figure, three via holes 12 are shown, but the number of via holes 12 may be other than the number shown.

  The wiring 11 is formed by using a damascene method in a lower insulating film and is composed of a barrier metal and Cu. The barrier metal is provided so as to cover the bottom surface and the side surface of Cu, and a refractory metal such as Ta or Ti, a nitride thereof, or a nitrided nitride thereof can be used as the material thereof.

  The via hole 12 is formed by two times of lithography. That is, an elliptical first hole pattern indicated by a one-dot chain line is exposed to the first lithography position 13A, and then an elliptical second hole indicated by a one-dot chain line having the same size and shape as the first lithography. By exposing the pattern to the second lithography position 13B, the first and second hole patterns are overlapped and formed to have a size smaller than that of the first and second hole patterns. In other words, the via hole does not reach the wiring 11 in the first lithography, and the region where the first lithography position 13A and the second lithography position 13B overlap by the second lithography reaches the wiring 11 and becomes the via hole 12. Contact plugs or via plugs are embedded in the via holes 12.

  As the contact plug or via plug, a metal plug whose main material is any one of W, Al, Cu, Ti, TiN, Ta, and TaN can be used.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device according to the first embodiment will be described below with reference to the process diagrams of FIGS.

  FIG. 2A is a plan view showing a wiring formation process, and FIG. 2B is a cross-sectional view taken along the line AA in FIG. In this wiring formation step, first, the wiring 11 made of the barrier metal 21 and Cu 22 is formed on the first interlayer insulating film 20 based on the damascene method, and Cu is formed on the wiring 11 and the first interlayer insulating film 20. A barrier insulating film 23 having a diffusion preventing capability, a second interlayer insulating film 24, and a hard mask 25 are sequentially formed. Note that Cu diffusion can be suppressed by a top barrier metal made of TiN or the like on the Cu 22 instead of the barrier insulating film 23.

  As the barrier insulating film 23, any of SiN, SiCN, SiC film, or a laminated film of these insulating films can be used.

The first interlayer insulating film 20 and the second interlayer insulating film 24 are respectively a low-k film made of SiO ₂ , F-added SiO ₂ , SiOC, or an organic material, or a porous low- A k film and a laminated film in which a plurality of these films are combined can be used. Here, the low-k film means a low dielectric constant.

The hard mask 25 can be selected from a material that serves as an etching mask when the second interlayer insulating film 24 is etched, that is, a material having a high etching selectivity with the second interlayer insulating film 24. . For example, when the second interlayer insulating film 24 is SiO ₂ , fluorine-added SiO ₂ , or SiOC, SiN, SiCN, or SiC can be used as the hard mask 25, and the second interlayer insulating film 24 In the case of an organic material, SiO ₂ or the like can be used in addition to the hard mask material described above.

  FIG. 2C is a plan view showing the first hole pattern process, and FIG. 2D is a cross-sectional view taken along the line BB in FIG. In this first hole patterning process, a first photoresist film 26 is applied on the hard mask 25 shown in FIG. 2B, and the first photoresist pattern 26 is formed by lithography as shown in FIG. 2C. An elliptical first opening 27 having a major axis and a minor axis is formed as a hole pattern. The first photoresist film 26 is a single layer here, but may be a multilayer. For example, an antireflection film may be provided immediately below or directly above the first photoresist film 26, or a multilayer photoresist structure may be employed.

  FIG. 2E is a plan view showing the hard mask removing process, and FIG. 2F is a cross-sectional view taken along the line CC in FIG. In this hard mask removing step, the hard mask 25 is removed by RIE (Reactive Ion Etching) using the first photoresist film 26 as an etching mask.

  FIG. 3A is a plan view showing the first photoresist film removing step, and FIG. 3B is a cross-sectional view taken along the line DD in FIG. In the first photoresist film removing step, the first hole pattern is transferred to the hard mask 25 by removing the first photoresist film 26 by any one of ashing, dry etching, and wet etching.

  FIG. 3C is a plan view showing a second hole pattern process, and FIG. 3D is a cross-sectional view taken along line EE in FIG. In this second hole pattern process, a second photoresist film 28 is applied on the hard mask 25 from which a part of the second interlayer insulating film 24 shown in FIG. 2), an elliptical second opening 29 having a major axis and a minor axis is formed as a second hole pattern by lithography.

  The opening 29 is formed at a position shifted in the long axis direction with respect to the first opening 27, and between the first opening 27 and the second opening 29, the first opening 27 is formed. And an overlapping region 30 where the second opening 29 overlaps is formed. The second photoresist film 28 may also have a laminated structure with an antireflection film as in the first photoresist film 26, or may have a multilayer photoresist structure.

  FIG. 3E is a plan view showing the via hole forming step, and FIG. 3F is a cross-sectional view taken along the line F-F in FIG. In this via hole forming step, the second photoresist film 28 and the hard mask 25 in which a part of the second interlayer insulating film 24 shown in FIG. To open. The sectional shape in the planar direction of the contact hole 12 thus opened is the same as that of the overlapping region 30 shown in FIG.

  FIG. 4A is a plan view showing a second photoresist film removing step, and FIG. 4B is a cross-sectional view taken along the line GG in FIG. In this second photoresist film removing step, the second photoresist film 28 shown in FIG. 3F is removed by any one of ashing, dry etching, and wet etching, and the barrier insulating film 23 is removed by the RIE method. Then, the exposed surface of the hard mask 25 is also removed, and the via hole 12 is opened up to the wiring 11 as shown in FIG. A via plug can be embedded in the via hole 12 thus opened.

(Effects of the first embodiment)
According to the first embodiment described above, the via hole 12 is formed so that the first opening 27 and the second opening 29, which are elliptical hole patterns having a major axis and a minor axis, overlap each other. Bypassing optical limits in exposure, it is possible to form via holes 12 having a size smaller than the long axis and the short axis as compared with the hole pattern, while ensuring a lithography margin for fine holes and relaxing design restrictions in the long axis direction. be able to. As a result, a fine via plug can be formed, and the semiconductor device can be highly integrated.

[Second Embodiment]
(Configuration of semiconductor device)
5A and 5B show a semiconductor device showing only wiring and via plugs according to the second embodiment of the present invention, where FIG. 5A is a plan view of the semiconductor device, and FIG. 5B is an HH line of FIG. Sectional drawing, (c) is a sectional view taken along line II in (a). In FIGS. 5A to 5C, illustration of the interlayer insulating film is omitted. In the following description, common reference numerals are given to portions having the same configuration and function as those of the first embodiment.

  The semiconductor device 1 includes a lower layer wiring 14 made of Cu formed at a predetermined interval on an interlayer insulating film (not shown) formed of SiN on a semiconductor substrate, and an interlayer insulating (not shown) formed of SiN on the lower layer wiring 14. An upper layer wiring 15 made of Cu is provided so as to intersect the lower layer wiring 14 through a film, and a via plug 16 made of Cu is provided so that one of the upper layer wirings 15 communicates with the lower layer wiring 14 directly below.

  As shown in FIGS. 5B and 5C, the via plug 16 has, for example, a major axis direction larger than the width of the lower layer wiring 14 and a minor axis direction substantially equal to the width of the upper layer wiring 15. It is configured.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device according to the second embodiment will be described below with reference to the process diagrams of FIGS.

  FIG. 6A is a plan view showing a lower layer wiring forming step, and FIG. 6B is a cross-sectional view taken along the line JJ in FIG. In this lower layer wiring formation step, first, as shown in FIG. 6B, a lower layer wiring 14 made of a barrier metal 21 and Cu 22 is formed on the first interlayer insulating film 20 by using a damascene method. A barrier insulating film 23 having an ability to prevent Cu diffusion is formed on the surface of the lower wiring 14 and the first interlayer insulating film 20.

  The barrier metal 21 may be made of a high melting point metal such as Ta or Ti, or a nitride thereof or a nitrided nitride thereof.

  As the barrier insulating film 23, any one of SiN, SiCN, SiC film, or a laminated film of these insulating films can be used.

  Further, as shown in FIG. 6B, a second interlayer insulating film 24 and a first hard mask 25 are sequentially formed on the barrier insulating film 23.

The first interlayer insulating film 20 and the second interlayer insulating film 24 have so-called low-k films such as SiO ₂ films, F-added SiO ₂ films, SiOC films, and organic films, and holes in these low-k films, respectively. An introduced porous low-k film or a laminated film of these films can be used.

The first hard mask 25 can be selected from a material that serves as an etching mask when the second interlayer insulating film 24 is etched, that is, a material having a high etching selectivity with the second interlayer insulating film 24. For example, when the second interlayer insulating film 24 is SiO ₂ , F-added SiO _2, or SiOC, SiN, SiCN, or SiC can be used as the first hard mask 25. When the second interlayer insulating film 24 is an organic film, an SiO ₂ film or the like can be used as the material in addition to the hard mask material.

  FIG. 6C is a plan view showing the first hole pattern process, and FIG. 6D is a cross-sectional view taken along the line KK in FIG. In the first hole pattern process, a first photoresist film 26 is applied on the first hard mask 25 shown in FIG. 6B, and the first photoresist film 26 is formed by lithography as shown in FIG. 6C. An elliptical first opening 27 having a major axis and a minor axis is formed as one hole pattern. The first photoresist film 26 is a single layer here, but may be a multilayer. For example, an antireflection film may be provided directly below or directly above the first photoresist film 26, or a multilayer resist structure may be used.

  FIG. 6E is a plan view showing the first hard mask removing step, and FIG. 6F is a cross-sectional view taken along line LL in FIG. In the first hard mask removing step, the first hard mask 25 is removed by the RIE method using the first photoresist film 26 as an etching mask.

  After the first hard mask 25 is removed, the first photoresist film 26 is removed by any one of ashing, dry etching, and wet etching to transfer the first hole pattern to the first hard mask 25. To do.

(Process for forming third interlayer insulating film and second hard mask)
FIG. 7A is a plan view showing a step of forming a third interlayer insulating film and a second hard mask, and FIG. 7B is a cross-sectional view taken along line MM in FIG. In the step of forming the third interlayer insulating film and the second hard mask, as shown in FIG. 7B, the third interlayer insulating film 32 and the second hard mask 33 are sequentially formed.

The third interlayer insulating film 32 is a low-k film made of SiO ₂ , F-added SiO ₂ , SiOC, or an organic material, a porous low-k film in which holes are introduced into these low-k films, or a laminated film of these films Can be used.

The second hard mask 33 can be selected from a material that serves as an etching mask when the third interlayer insulating film 32 is etched, that is, a material having a high etching selectivity with the third interlayer insulating film 32. . For example, when the third interlayer insulating film 32 is SiO ₂ , F-added SiO ₂ , or SiOC, SiN, SiCN, or SiC can be used as the second hard mask 33, and the third interlayer insulating film When 32 is an organic film, SiO ₂ or the like can be used as the hard mask material in addition to the hard mask material described above.

  FIG. 7C is a plan view showing the second hole pattern process, and FIG. 7D is a cross-sectional view taken along line NN in FIG. In the second hole pattern process, as shown in FIG. 7D, a second photoresist film 34 is applied on the second hard mask 33, and as shown in FIG. 7C, lithography is performed. By the technique, an elliptical second opening 35 having a major axis and a minor axis is formed as a second hole pattern. For example, the second opening 35 is formed at a position shifted in the major axis direction by at least the length of the minor axis of the ellipse with respect to the first opening 27, and the second opening 35 and the first opening 27 The second opening 35 is formed with an overlapping region 36 where the first opening 27 and the second opening 35 overlap. Similar to the photoresist film 26, the photoresist film 34 may have a laminated structure with an antireflection film or a multilayer resist structure.

  FIG. 7E is a plan view showing a third hole pattern process, and FIG. 7F is a cross-sectional view taken along the line OO in FIG. In this third hole pattern process, as shown in FIG. 7E, the third interlayer insulating film is used by using the second photoresist film 34 and the second hard mask 33 as an etching mask. An elliptical third opening 37 is formed as a third hole pattern in 32.

  FIG. 8A is a plan view showing a via hole forming step, and FIG. 8B is a cross-sectional view taken along the line P-P in FIG. In this via hole forming step, as shown in FIG. 8B, the via hole 38 is formed by the RIE method up to just above the barrier insulating film 23 using the first hard mask 25 and the second hard mask 33 as an etching mask. . As a result, as shown in FIG. 8A, the cross-sectional shape of the via hole 38 in the plane direction is an overlapping region where the first opening 27 and the second opening 35 shown in FIG. It will be the same as 36.

  FIG. 8C is a plan view showing the patterning process, and FIG. 8D is a cross-sectional view taken along the line Q-Q in FIG. In this patterning step, patterning for forming a groove for the upper layer wiring 15 is performed. At this time, as shown in FIG. 8D, the opening 37 and the via hole 38 are filled with the embedding material 39 having the antireflection function, and the periphery of the embedding material 39, that is, the upper wiring 15 should be formed. In the region, a fourth opening 47 is formed in the third photoresist film 40 by lithography.

  FIG. 8E is a plan view showing the removal process of the embedding material 39, and FIG. 8F is a cross-sectional view taken along the line RR in FIG. In this etching step, as shown in FIG. 8F, the filling material 39 is etched using the third photoresist film 40 as an etching mask.

  FIG. 9A is a plan view showing a wiring groove forming step, and FIG. 9B is a cross-sectional view taken along the line SS of FIG. 9A. In the wiring groove forming step, as shown in FIGS. 9A and 9B, the second hard mask 33 and the second hard mask 33 are formed by the RIE method using the third photoresist film 40 as an etching mask. An upper wiring trench 41 is formed in the interlayer insulating film 32.

  FIG. 9C is a plan view illustrating the etching process of the barrier insulating film, and FIG. 9D is a cross-sectional view taken along the line TT in FIG. In the etching process of the barrier insulating film 23, as shown in FIGS. 9C and 9D, the barrier insulating film 23 on the bottom surface of the via hole is removed by RIE. As a result, a dual damascene structure including the via hole 38 in the second interlayer insulating film 24 and the wiring groove 41 for the upper wiring 15 in the third interlayer insulating film 32 can be formed.

  FIG. 9E is a plan view showing a via plug and wiring formation process, and FIG. 9F is a cross-sectional view taken along the line U-U in FIG. In this via plug and wiring formation process, the barrier metal 42 and Cu 43 are embedded and further planarized by a CMP method. As a result, as shown in FIGS. 9E and 9F, the Cu via plug 44 and the upper wiring 15 are formed simultaneously.

  According to the second embodiment, in addition to the effects of the first embodiment, in the semiconductor device 1 composed of two layers of the lower layer wiring 14 and the upper layer wiring 15, while ensuring a lithography margin of fine holes, Since the design constraint in the major axis direction can be relaxed, the semiconductor device can be highly integrated.

(Third embodiment)
FIG. 10 shows a semiconductor device according to the third embodiment of the present invention. Here, since the same parts as those of the semiconductor device in the second embodiment are indicated by the same reference numerals, overlapping description is omitted, but the P-type or N-type formed in the first interlayer insulating film 20 is omitted. The impurity region 100 is connected to a wiring (not shown) located thereon by a contact plug (not shown) filled in the groove 41. The groove 41 is formed in an overlapping region where the opening of the hard mask 25 and the opening of the photoresist film 32 overlap.

(Other embodiments)
FIG. 11 is a plan view showing another shape of the hole pattern, in which (a) is based on a rectangular hole pattern, and (b) is based on a rhombus-shaped hole pattern. Instead of the elliptical hole pattern described in the above embodiment, a rectangular or rhomboid hole pattern is formed by irradiating the resist surface on the substrate with light through a rectangular or rhombus mask. The same effect can be obtained.

  The first to third embodiments described above are merely examples, and various modifications can be made in each embodiment, and the embodiments can be used as they are or after being modified. Can be combined.

  In the above embodiment, the ellipse, the rectangle, and the rhombus having the same shape are shown as the first and second hole patterns. However, the present invention is not limited to these, and the shapes of the first hole pattern and the second hole pattern may be changed. For example, a combination of ovals with different ellipticities, a combination of ovals and circles, a combination of ovals and rectangles, and the like may be used.

  The characteristics of the present invention are summarized as follows.

(1) In a semiconductor device including a via hole communicating with at least one wiring formed on an insulating film from a vertical direction,
The via hole is a semiconductor device in which an elliptical end portion having two major axes and a minor axis is overlapped.

(2) The wiring is composed of a lower layer wiring and an upper layer wiring arranged so as to intersect with each other via a second insulating film, and the lower layer wiring and the upper layer wiring are connected by a metal plug embedded in the via hole. The semiconductor device of (1) above.

(3) The semiconductor device according to (2), wherein the metal plug is made mainly of any one of Cu, Ti, TiN, W, Ta, TaN, and Al.

(4) a first step of forming a wiring on the insulating film and forming a barrier insulating film on the surfaces of the insulating film and the conductor wiring;
After performing processing for photolithography on the barrier insulating film, an elliptical first hole pattern having a major axis and a minor axis is transferred to the wiring, and then an ellipse having a major axis and a minor axis The second hole pattern is transferred onto the wiring so as to partially overlap the first hole pattern, and a via hole reaching the surface of the wiring by lithography in a region where the first and second hole patterns overlap A method for manufacturing a semiconductor device, which includes a second step of forming a semiconductor device.

(5) In the second step, the minor diameters of the first and second hole patterns are made the same, and the length of the overlapping region in the major axis direction is made substantially the same as the minor axis (4) ) Semiconductor device manufacturing method.

(6) The method for manufacturing a semiconductor device according to (5), wherein the first and second hole patterns have respective major axes substantially on the same line in the width direction of the wiring.

(7) In the second step, after the first photoresist film and the mask are formed on the barrier insulating film, the first hole pattern is transferred, and then the second photoresist film is transferred to the barrier. (4) The method for manufacturing a semiconductor device according to (4), further including a step of transferring the second hole pattern after being formed on the insulating film.

(8) In the second step, after the first photoresist film and the mask are formed on the barrier insulating film, the first hole pattern is transferred, and then the second photoresist film is transferred to the barrier. A transfer step of transferring the second hole pattern after being formed on the insulating film;
A wiring forming step of forming a via plug that connects the upper layer wiring and the wiring at the same time after forming the second hole pattern and simultaneously forming an upper wiring above the wiring by insulating the wiring from the wiring; (4) A method of manufacturing a semiconductor device.

(9) The transfer step includes a step of transferring the first hole pattern to a mask formed on the barrier insulating film,
The method of manufacturing a semiconductor device according to (8), wherein the wiring forming step includes a step of forming the upper layer wiring on the mask.

1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. (A) is a top view which shows a wiring formation process, (b) is sectional drawing in the AA part of (a). (C) is a top view which shows a 1st hole pattern process, (d) is sectional drawing in the BB part of (c). (E) is a top view which shows a hard mask removal process, (f) is sectional drawing in CC section of (e). (A) is a top view which shows a 1st photoresist film removal process, (b) is sectional drawing in the DD section of (a). (C) is a top view which shows a 2nd hole pattern process, (d) is sectional drawing in the EE part of (c). (E) is a top view which shows a contact hole formation process, (f) is sectional drawing in the FF part of (e). (A) is a top view which shows a 2nd photoresist film removal process, (b) is sectional drawing in the GG part of (a). 2A shows a semiconductor device according to a second embodiment of the present invention, where FIG. 1A is a plan view of the semiconductor device, FIG. 2B is a cross-sectional view taken along the line H-H in FIG. 1A, and FIG. It is sectional drawing of the II line. (A) is a top view which shows a lower layer wiring formation process, (b) is sectional drawing in the JJ part of (a). (C) is a top view which shows a 1st hole pattern process, (d) is sectional drawing in the KK part of (c). (E) is a top view which shows a 1st hard mask removal process, (f) is sectional drawing in the LL part of (e). (A) is a top view which shows the formation process of an interlayer insulation film and a 2nd hard mask, (b) is sectional drawing in the MM part of (a). (C) is a top view which shows a 2nd hole pattern process, (d) is sectional drawing in the NN part of (c). (E) is a top view which shows a 3rd hole pattern process, (f) is sectional drawing in the OO part of (e). (A) is a top view which shows a via hole formation process, (b) is sectional drawing in the PP part of (a). (C) is a top view which shows a patterning process, (d) is sectional drawing in the QQ part of (c). (E) is a top view which shows the etching process of the photoresist film 40, (f) is sectional drawing in the RR part of (e). (A) is a top view which shows the formation process of the groove | channel for wiring, (b) is sectional drawing in SS part of (a). (C) is a top view which shows the etch process of a barrier insulating film, (d) is sectional drawing in the TT part of (c). (E) is a top view which shows a via plug formation process, (f) is sectional drawing in the UU part of (e). It is sectional drawing which shows the semiconductor device of the 3rd Embodiment of this invention. It is a top view which shows the other shape of a hole pattern, (a) is based on a rectangular hole pattern, (b) is based on a rhombus-shaped hole pattern,

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Wiring, 12, 38 ... Via hole, 14 ... Lower layer wiring, 15 ... Upper layer wiring, 16 ... Via plug hole, 20 ... 1st interlayer insulation film, 24 ... 2nd interlayer insulation film, 27 , 29, 35, 37 ... opening, 30, 36 ... overlap region, 38 ... via hole, 39 ... filling material, 44 ... via plug

Claims (5)

A conductive layer;
A connecting member having a cross-sectional shape defined by a region of an overlapping portion of a pattern having two major axes and a minor axis, which are formed on the conductive layer and arranged so as to partially overlap each other; A featured semiconductor device.   The semiconductor device according to claim 1, wherein the pattern having the two major axes and the minor axis has an elliptical shape.   The semiconductor device according to claim 1, wherein the pattern having the two major axes and the minor axis is provided on a line having substantially the same major axis direction. A first step of forming, in an insulating film formed on the conductive layer, a first connection hole having a pattern having a major axis and a minor axis having a predetermined depth that does not reach the conductive layer;
A second step of forming, in the insulating film, a second connection hole having a pattern having a major axis and a minor axis that partially overlaps the first connection hole and has a depth reaching the conductive layer. When,
A method of manufacturing a semiconductor device, comprising a third step of filling the first and second connection holes with a conductive material to form a connection member connected to the conductive layer.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the third step, the connection member is formed of a metal material containing Cu, Ti, TiN, W, Ta, TaN, or Al as a main component.

Images