JP2006128284A

JP2006128284A - Capacitor, semiconductor device, decoupling circuit and high frequency circuit

Info

Publication number: JP2006128284A
Application number: JP2004312455A
Authority: JP
Inventors: Yoshihiro Takeshita; 良博竹下
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2004-10-27
Filing date: 2004-10-27
Publication date: 2006-05-18
Anticipated expiration: 2024-10-27
Also published as: JP4565964B2

Abstract

【課題】低ＥＳＬであり、且つ適切なＥＳＲを有するコンデンサを提供すること、および、上述したようなコンデンサを用いて構成される、半導体装置、デカップリング回路及び高周波回路を提供する。
【解決手段】誘電体層２の一方主面に第１導体層３が、前記誘電体層２の他方主面に、前記第1導体層３と該誘電体層２を介して一部重畳する第２導体層４が配設されるとともに、前記第２導体層４内の非導体形成領域１４を前記誘電体層２の厚み方向に貫通し、かつ前記第１導体層５に接続される複数の第１貫通導体５と、前記第１導体層３内の非導体形成領域１３を前記誘電体層２の厚み方向に貫通し、かつ前記第２導体層４に接続される複数の第２貫通導体４とを有し、前記第１導体層３、第２導体層４、第１貫通導体５および第２貫通導体６の少なくとも１つの導体に、他の領域よりも導電率の低い部分Ｌを有することを特徴とする。
【選択図】図１To provide a capacitor having low ESL and appropriate ESR, and to provide a semiconductor device, a decoupling circuit, and a high-frequency circuit configured using the above-described capacitor.
A first conductor layer 3 partially overlaps one main surface of a dielectric layer 2 and the other main surface of the dielectric layer 2 with the first conductor layer 3 and the dielectric layer 2 interposed therebetween. The second conductor layer 4 is disposed, and a plurality of non-conductor forming regions 14 in the second conductor layer 4 are penetrated in the thickness direction of the dielectric layer 2 and connected to the first conductor layer 5. A plurality of second through-holes that penetrate through the first conductor 5 and the non-conductor-forming region 13 in the first conductor layer 3 in the thickness direction of the dielectric layer 2 and are connected to the second conductor layer 4. A portion L having a conductivity lower than that of the other region is provided on at least one of the first conductor layer 3, the second conductor layer 4, the first through conductor 5, and the second through conductor 6. It is characterized by having.
[Selection] Figure 1

Description

本発明は、コンデンサ、配線基板、デカップリング回路及び高周波回路に関するもので、特に、高周波領域において有利に適用され得るコンデンサ、ならびに、このコンデンサを用いて構成される、半導体装置、デカップリング回路及び高周波回路に関するものである。 The present invention relates to a capacitor, a wiring board, a decoupling circuit, and a high frequency circuit, and in particular, a capacitor that can be advantageously applied in a high frequency region, and a semiconductor device, a decoupling circuit, and a high frequency that are configured using the capacitor. It relates to the circuit.

代表的なコンデンサとして、積層コンデンサを例にとって説明する。積層コンデンサを用いた等価回路では、コンデンサの静電容量をＣ、等価直列インダクタンス（ＥＳＬ）をＬとしたとき、共振周波数（ｆ_０）は、ｆ_０＝１／〔２π×（Ｌ×Ｃ）^１／２〕の関係で表され、共振周波数（ｆ_０）より高い周波数領域では、コンデンサの機能が消失してしまうことが知られている。すなわち、一定値以上の静電容量（Ｃ）を維持するためには、できるだけＥＳＬ（Ｌ）を低くする必要がある。つまり、ＥＳＬが低ければ、共振周波数（ｆ_０）は高くなり、より高周波領域で使用できることになる。このことから、積層コンデンサをマイクロ波領域で使うためには、より低ＥＳＬ化が図られたものが必要となる。 As a typical capacitor, a multilayer capacitor will be described as an example. In an equivalent circuit using multilayer capacitors, when the capacitance of the capacitor is C and the equivalent series inductance (ESL) is L, the resonance frequency (f ₀ ) is f ₀ = 1 / [2π × (L × C). expressed in relation ^1/2], in the frequency region higher than the resonance frequency (f _0), it is known that the function of the capacitor is lost. That is, in order to maintain an electrostatic capacity (C) of a certain value or more, it is necessary to make ESL (L) as low as possible. That is, if the ESL is low, the resonance frequency (f ₀ ) is high and can be used in a higher frequency region. For this reason, in order to use the multilayer capacitor in the microwave region, it is necessary to further reduce the ESL.

また、ワークステーションやパーソナルコンピュータ等のマイクロプロセッシングユニット（ＭＰＵ）のＭＰＵチップに電源を供給するために用いられ、通常デカップリングコンデンサとして配線基板上に接続されている積層コンデンサも、近年のＭＰＵの高速、高周波化に伴って、低ＥＳＬ化が求められている。 In addition, multilayer capacitors that are used to supply power to the MPU chip of a microprocessing unit (MPU) such as a workstation or personal computer and are usually connected on a wiring board as a decoupling capacitor are also used in recent MPU high speeds. As the frequency increases, there is a demand for lower ESL.

ここで、従来の積層コンデンサについて、図７（ａ）（ｂ）をもとに説明する。（ａ）は第１及び第２導体層の投影平面図、（ｂ）は（ａ）のＸ−Ｘ線断面図である。 Here, a conventional multilayer capacitor will be described with reference to FIGS. (A) is a projection top view of the 1st and 2nd conductor layer, (b) is XX sectional drawing of (a).

図７に示す従来の積層コンデンサ５０は、誘電体層５２の一方主面に第１導体層５３が、他方主面に第２導体層５４が夫々形成され、これらの誘電体層５２が複数積層されており、また、これらの誘電体層５２の厚み方向には第１及び第２導体層５３、５４同士を夫々接続する第１及び第２貫通導体５５、５６が形成され、積層体５１が構成されている。ここでは、第１及び第２貫通導体５５、５６が、積層体５１の一方の最表面に露出し、夫々第１及び第２接続端子５７、５８に接続され、積層コンデンサ５０が構成されている。さらに、第１及び第２導体層５３、５４内に、第２及び第１貫通導体５６、５５とは夫々接続しない第１及び第２非導体形成領域６３、６４が形成されている。 In the conventional multilayer capacitor 50 shown in FIG. 7, a first conductor layer 53 is formed on one main surface of a dielectric layer 52, and a second conductor layer 54 is formed on the other main surface, and a plurality of these dielectric layers 52 are stacked. In addition, in the thickness direction of these dielectric layers 52, first and second through conductors 55 and 56 are formed to connect the first and second conductor layers 53 and 54, respectively. It is configured. Here, the first and second through conductors 55 and 56 are exposed on one outermost surface of the multilayer body 51 and connected to the first and second connection terminals 57 and 58, respectively, so that the multilayer capacitor 50 is configured. . Further, first and second non-conductor forming regions 63 and 64 that are not connected to the second and first through conductors 56 and 55 are formed in the first and second conductor layers 53 and 54, respectively.

この積層コンデンサにおいて、第１及び第２貫通導体５５、５６は、第１及び第２導体層５３、５４の全域にわたって、交互に格子状に分散して配置されている。上記積層コンデンサ５０によれば、静電容量は、第１及び第２導体層５３、５４の内、主に第１及び第２貫通導体５５、５６に囲まれた部分に発生する（特許文献１乃至４参照）。 In this multilayer capacitor, the first and second through conductors 55 and 56 are alternately distributed in a grid pattern over the entire area of the first and second conductor layers 53 and 54. According to the multilayer capacitor 50, the capacitance is generated mainly in the portion surrounded by the first and second through conductors 55 and 56 in the first and second conductor layers 53 and 54 (Patent Document 1). To 4).

上記した積層コンデンサ５０によれば、低ＥＳＬ化を図るためには、第1及び第２貫通導体５５、５６の数を増加するとともに、これらの中心間の距離を小さくする方法が考えられるが、第1及び第２貫通導体５５、５６の数を増加するとコンデンサ５０全体の等価直流抵抗（ESR）もまた大幅に低下することになる。 According to the multilayer capacitor 50 described above, in order to reduce the ESL, a method of increasing the number of the first and second through conductors 55 and 56 and reducing the distance between these centers can be considered. When the number of the first and second through conductors 55 and 56 is increased, the equivalent direct current resistance (ESR) of the entire capacitor 50 is also greatly reduced.

この様な大幅な低ESL化を実現したコンデンサは図５に示すような半導体装置の一部として用いられる。図５（ａ）は（ｂ）図のＡ−Ａ線断面図、（ｂ）は半導体装置の平面図である。この半導体装置は基板上に半導体素子収納用のパッケージが実装され、そのパッケージ上にはMPUなどの半導体素子が搭載されている。また、このMPUの周辺には低インダクタンスコンデンサ６１が配置され、一方、基板上の周縁部にもコンデンサが備えられている。これらコンデンサや低インダクタンスコンデンサの役割は、MPUなどの半導体素子からパッケージ側の電源配線回路を見たときのインピーダンスを広い周波数範囲に渡って低くすることにある。
特開平７−２０１６５１号公報（３−５頁、図１−５）特開平１１−２０４３７２号公報（４−６頁、図１−４）特開２００１−１４８３２４号公報（４−７頁、図１−６）特開２００１−１４８３２５号公報（５−７頁、図１−９） Such a capacitor realizing a significant reduction in ESL is used as a part of a semiconductor device as shown in FIG. 5A is a cross-sectional view taken along line AA in FIG. 5B, and FIG. 5B is a plan view of the semiconductor device. In this semiconductor device, a package for housing a semiconductor element is mounted on a substrate, and a semiconductor element such as an MPU is mounted on the package. Further, a low inductance capacitor 61 is disposed around the MPU, and a capacitor is also provided on the peripheral portion of the substrate. The role of these capacitors and low-inductance capacitors is to reduce the impedance over a wide frequency range when the power supply wiring circuit on the package side is viewed from a semiconductor element such as an MPU.
Japanese Patent Laid-Open No. 7-201651 (page 3-5, FIG. 1-5) Japanese Patent Laid-Open No. 11-204372 (page 4-6, FIG. 1-4) JP 2001-148324 A (page 4-7, FIG. 1-6) JP 2001-148325 A (page 5-7, FIG. 1-9)

しかしながら、従来の等価回路では、低インダクタンスコンデンサを用いた場合でも、図４（Ａ）に見られるように、依然として７ＭＨｚ付近に現れるようなインピーダンスのピークが発生するという問題があった。このピークは、図５の低インダクタンスコンデンサ６１と基板上に実装されたチップコンデンサ９との共振によって発生し、そのピークの大きさは、共振回路の損失の大きさによって決まる。この様な配線回路において共振回路の損失は配線の抵抗成分が支配的であるが、前述のように低インダクタンスコンデンサ６１のＥＳＲは低インダクタンス化を実現する多端子構造のために極めて小さい値となっている。更に、低インダクタンスコンデンサ６１は図５の様に複数個搭載される場合が殆どで有り、装置全体の抵抗は図５の場合で低インダクタンスコンデンサ１個のＥＳＲの１／８となってしまう。このため、前述のインピーダンスピークが大きくなり、広範な周波数範囲全体のインピーダンスを下げるという要求が満足できないという問題となっている。 However, the conventional equivalent circuit has a problem that even when a low-inductance capacitor is used, an impedance peak still appears in the vicinity of 7 MHz as seen in FIG. This peak occurs due to resonance between the low-inductance capacitor 61 of FIG. 5 and the chip capacitor 9 mounted on the substrate, and the magnitude of the peak is determined by the loss of the resonance circuit. In such a wiring circuit, the resonance circuit loss is dominated by the resistance component of the wiring, but as described above, the ESR of the low-inductance capacitor 61 is extremely small due to the multi-terminal structure that achieves a low inductance. ing. Further, in most cases, a plurality of low-inductance capacitors 61 are mounted as shown in FIG. 5, and the resistance of the entire device is 1/8 of the ESR of one low-inductance capacitor in the case of FIG. For this reason, the above-mentioned impedance peak becomes large, and there is a problem that the requirement to reduce the impedance of the entire wide frequency range cannot be satisfied.

因みに、低インダクタンスコンデンサのＥＳＲを制御する方法としては、導体パターンの一部を狭くする方法（特開２００３−１６８６２０）や貫通導体の数を減らす方法があるが、これらの手法ではＥＳＲを大きくすることができるが、一方のインダクタンスも同時に大きくなってしまい、低インダクタンスコンデンサ６１には採用できないという問題がある。 Incidentally, as a method of controlling the ESR of the low-inductance capacitor, there are a method of narrowing a part of the conductor pattern (Japanese Patent Laid-Open No. 2003-168620) and a method of reducing the number of through conductors, but these methods increase the ESR. However, there is a problem that one of the inductances becomes large at the same time and cannot be adopted for the low inductance capacitor 61.

従って本発明は、上述の問題点に鑑みて案出されたものであり、その目的は、低ＥＳＬであり、且つ適切なＥＳＲを有するコンデンサを提供することである。 Accordingly, the present invention has been devised in view of the above-described problems, and an object thereof is to provide a capacitor having a low ESL and an appropriate ESR.

本発明の他の目的は、上述したようなコンデンサを用いて構成される、半導体装置、デカップリング回路及び高周波回路を提供することである。 Another object of the present invention is to provide a semiconductor device, a decoupling circuit, and a high-frequency circuit that are configured using a capacitor as described above.

本発明のコンデンサは、（１）誘電体層の一方主面に第１導体層が、前記誘電体層の他方主面に、前記第1導体層と該誘電体層を介して一部重畳する第２導体層が配設されるとともに、前記第２導体層内の非導体形成領域を前記誘電体層の厚み方向に貫通し、かつ前記第１導体層に接続される複数の第１貫通導体と、前記第１導体層内の非導体形成領域を前記誘電体層の厚み方向に貫通し、かつ前記第２導体層に接続される複数の第２貫通導体とを有し、前記第１導体層、第２導体層、第１貫通導体および第２貫通導体の少なくとも１つの導体に、他の領域よりも導電率の低い部分を有することを特徴とする。 In the capacitor of the present invention, (1) the first conductor layer is partially overlapped with the first principal surface of the dielectric layer, and the first conductor layer and the dielectric layer are partially overlapped with the other principal surface of the dielectric layer. A plurality of first through conductors that are provided with a second conductor layer, penetrate a non-conductor forming region in the second conductor layer in the thickness direction of the dielectric layer, and are connected to the first conductor layer And a plurality of second through conductors that penetrate through the non-conductor forming region in the first conductor layer in the thickness direction of the dielectric layer and are connected to the second conductor layer, and the first conductor At least one of the layer, the second conductor layer, the first through conductor, and the second through conductor has a portion having a lower conductivity than the other regions.

また上記コンデンサでは、（２）低い導電率を示す導体が第１貫通導体および第２貫通導体であることが望ましい。 In the above capacitor, it is desirable that (2) conductors exhibiting low conductivity are the first through conductor and the second through conductor.

また本発明のコンデンサは、（３）複数の誘電体層を積層してなる積層体と、該積層体内部の少なくとも１層の誘電体層の一方主面に設けられた第１導体層と、該第１導体層に対向する前記誘電体層の他方主面に前記第１導体層が前記誘電体層を介して一部重畳する第２導体層と、前記第１導体層内の第１非導体形成領域を前記誘電体層の厚み方向に貫通し、かつ前記第２導体層に接続される第２貫通導体と、該第２貫通導体に対して平行に形成されるとともに、前記第２導体層内の第２非導体形成領域を貫通し、かつ前記第１導体層に接続される第１貫通導体とを具備し、前記第１および第２貫通導体の端部が前記積層体の少なくとも一方表面に導出され、かつ前記表面に最も近い前記第１導体層または前記表面に最も近い前記第２導体層を、他の導体層よりも低い導電率としたことを特徴とする。 The capacitor of the present invention includes (3) a laminate formed by laminating a plurality of dielectric layers, a first conductor layer provided on one main surface of at least one dielectric layer in the laminate, A second conductor layer in which the first conductor layer partially overlaps the other main surface of the dielectric layer facing the first conductor layer via the dielectric layer; and a first non-layer in the first conductor layer A second through conductor that penetrates the conductor forming region in the thickness direction of the dielectric layer and is connected to the second conductor layer, and is formed in parallel to the second through conductor, and the second conductor A first penetrating conductor penetrating through a second non-conductor forming region in the layer and connected to the first conductor layer, and an end portion of the first and second penetrating conductors is at least one of the multilayer body The first conductor layer that is led to the surface and is closest to the surface or the second conductor layer that is closest to the surface , Characterized in that a lower conductivity than the other conductor layers.

本発明のコンデンサは、（４）半導体装置に備えられること、（５）デカップリング回路に用いられること、（６）高周波回路に用いられること、を特徴とするものである。つまり、本発明は、上述のコンデンサを備えた配線基板にも適用でき、また、ＭＰＵに備えるＭＰＵチップのための電源回路に接続されるデカップリングコンデンサとしても有利に用いられるものであり、さらには高周波回路にも適用できる。 The capacitor of the present invention is characterized by (4) being provided in a semiconductor device, (5) being used in a decoupling circuit, and (6) being used in a high-frequency circuit. That is, the present invention can be applied to a wiring board provided with the above-described capacitor, and is also advantageously used as a decoupling capacitor connected to a power supply circuit for an MPU chip provided in the MPU. It can also be applied to high frequency circuits.

本発明においては、第１導体層、第２導体層、第１貫通導体および第２貫通導体のうちの少なくとも一つの導体層または貫通導体が他の導体層または貫通導体よりも低い導電率を示すように形成している。これによって、ＥＳＬを増加させること無くＥＳＲを増加させることができる。 In the present invention, at least one of the first conductor layer, the second conductor layer, the first through conductor, and the second through conductor has a lower conductivity than the other conductor layers or the through conductor. It is formed as follows. As a result, ESR can be increased without increasing ESL.

また、複数の誘電体層を重畳してなる積層体で、前記第1および第２貫通導体の端部が前記積層体の少なくとも一方表面に導出されており、少なくとも第１表面に最も近い前記第１導体層、あるいは第１表面に最も近い前記第２導体層を低導電率領域とすることによって、前記第１表面に導出された貫通導体から入った電流は、低導電率領域を通ってコンデンサの容量系形成部に至ることになり、ＥＳＲを増加させることができる。 Further, in the multilayer body formed by superimposing a plurality of dielectric layers, end portions of the first and second through conductors are led out to at least one surface of the multilayer body, and at least the first layer closest to the first surface is formed. By making the first conductor layer, or the second conductor layer closest to the first surface, a low conductivity region, a current flowing from the through conductor led to the first surface passes through the low conductivity region and becomes a capacitor. Thus, the ESR can be increased.

以下、本発明のコンデンサ、半導体装置、デカップリング回路及び高周波回路を図面に基づいて詳説する。なお、図１〜３において低導電率部分は色を薄くして表している。 Hereinafter, a capacitor, a semiconductor device, a decoupling circuit, and a high frequency circuit of the present invention will be described in detail with reference to the drawings. In FIGS. 1 to 3, the low conductivity portion is shown with a lighter color.

図１は本発明のコンデンサの一例である積層コンデンサを示す図であり、（ａ）は第１及び第２導体層の投影平面図、（ｂ）は（ａ）のＸ−Ｘ線断面図である。 1A and 1B are diagrams showing a multilayer capacitor as an example of the capacitor of the present invention, wherein FIG. 1A is a projected plan view of first and second conductor layers, and FIG. 1B is a sectional view taken along line XX in FIG. is there.

図１において、１０は積層コンデンサ、２は誘電体層、３、４は第１及び第２導体層（内部電極層）、５、６は第１及び第２貫通導体（ビアホール導体）、７、８は第１及び第２接続端子である。 In FIG. 1, 10 is a multilayer capacitor, 2 is a dielectric layer, 3 is first and second conductor layers (internal electrode layers), 5 and 6 are first and second through conductors (via-hole conductors), 7, Reference numeral 8 denotes first and second connection terminals.

図１に示すように、積層コンデンサ１０は、誘電体層２の一方主面に第１導体層３が、他方主面に第２導体層４が夫々形成され、これらの誘電体層２が複数積層されており、また、これらの誘電体層２の厚み方向には、第1および第２非導体形成領域１３、１４によってそれぞれ隔てられた第１及び第２導体層３、４同士を夫々接続する複数の第１及び第２貫通導体５、６が形成され積層体１が構成されている。ここでは、複数の第１及び第２貫通導体５、６が、積層体１の一方の最表面に露出し、夫々第１及び第２接続端子７、８に接続され積層コンデンサ１０が構成されている。 As shown in FIG. 1, in the multilayer capacitor 10, a first conductor layer 3 is formed on one main surface of a dielectric layer 2, and a second conductor layer 4 is formed on the other main surface, and a plurality of these dielectric layers 2 are formed. The first and second conductor layers 3 and 4 separated from each other by the first and second non-conductor forming regions 13 and 14 are connected in the thickness direction of the dielectric layer 2. A plurality of first and second through conductors 5 and 6 are formed to form a multilayer body 1. Here, a plurality of first and second through conductors 5 and 6 are exposed on one outermost surface of the multilayer body 1 and connected to the first and second connection terminals 7 and 8, respectively, thereby forming the multilayer capacitor 10. Yes.

本発明のコンデンサでは、第１導体層３、第２導体層４、第１貫通導体５および第２貫通導体６のうちの少なくとも一つの導体層または貫通導体が他の導体層または貫通導体よりも低い導電率を示すことを特徴とする。つまり、第１及び第２導体層（内部電極層）、３、４及び第１及び第２貫通導体（ビアホール導体）５、６の一部に、低導電率の領域Ｌが形成されていることが重要である。こうした構成により、第１表面に導出された貫通導体から入った電流は、低導電率の領域を通ってコンデンサの容量系形成部に至ることになりＥＳＲを増加させることができる。なお、本発明では、上記のように導体層もしくは貫通導体の一部に低導電率の部分を形成することによって本発明の効果を得ることができるが、同一面内の導体層および同一誘電体層内の貫通導体は共に高くすることがより望ましい。 In the capacitor of the present invention, at least one of the first conductor layer 3, the second conductor layer 4, the first through conductor 5, and the second through conductor 6 is more than the other conductor layer or the through conductor. It is characterized by exhibiting low conductivity. That is, the low-conductivity region L is formed in a part of the first and second conductor layers (internal electrode layers) 3, 4, and the first and second through conductors (via hole conductors) 5, 6. is important. With such a configuration, the current entering from the through conductor led to the first surface reaches the capacitance system forming portion of the capacitor through the low conductivity region, and can increase the ESR. In the present invention, the effect of the present invention can be obtained by forming a portion of low conductivity in part of the conductor layer or the through conductor as described above. However, the conductor layer and the same dielectric in the same plane can be obtained. It is more desirable that both the through conductors in the layer are made high.

一方、上記本発明の構成に対して、第１導体層、第２導体層、第１貫通導体および第２貫通導体のいずれの箇所にも余分な抵抗成分を挿入しないと、依然として７ＭＨｚ付近に現れるようなインピーダンスのピークが発生する。 On the other hand, if an extra resistance component is not inserted in any part of the first conductor layer, the second conductor layer, the first through conductor, and the second through conductor in the configuration of the present invention, it still appears in the vicinity of 7 MHz. Such an impedance peak occurs.

なお本発明において、誘電体層２は、チタン酸バリウムを主成分とする非還元性誘電体材料、及びガラス成分を含む誘電体材料からなり、この誘電体層２が図上、上方向に積層して積層体１が構成される。なお、誘電体層２の形状、厚み、積層数は容量値によって任意に変更することができる。 In the present invention, the dielectric layer 2 is made of a non-reducing dielectric material mainly composed of barium titanate and a dielectric material containing a glass component, and the dielectric layer 2 is laminated in the upward direction in the figure. Thus, the laminate 1 is configured. The shape, thickness, and number of layers of the dielectric layer 2 can be arbitrarily changed depending on the capacitance value.

また本発明によれば、第１及び第２導体層３、４の低導電率領域Ｌは、Ｎｉ（８０ｗｔ％）―Ｃｏ（２０ｗｔ％）合金を主成分とする材料から構成され、その厚みは１〜２μｍであることが好ましい。第１及び第２導体層３、４の低導電率領域Ｌ以外の領域は、Ｎｉを主成分とする材料から構成され、その厚みは１〜２μｍとしている。さらには、第１及び第２接続端子７、８は、半田バンプ、半田ボールなどが用いられる。 According to the present invention, the low conductivity region L of the first and second conductor layers 3 and 4 is made of a material mainly composed of a Ni (80 wt%)-Co (20 wt%) alloy, and its thickness is It is preferable that it is 1-2 micrometers. Regions other than the low conductivity region L of the first and second conductor layers 3 and 4 are made of a material containing Ni as a main component and have a thickness of 1 to 2 μm. Furthermore, solder bumps, solder balls, or the like are used for the first and second connection terminals 7 and 8.

図２は、本発明の積層コンデンサ１０の他の実施の形態を示す概略図である。図のように、第１貫通導体および第２貫通導体の全体を低導電率の領域ＬとすることによりコンデンサのＥＳＲを高めることができる。この場合、形成した貫通孔の一部に他の部分に比較して導電率の低い導体を適用することにより形成される。コンデンサに供給される電流は必ず接続端子から貫通導体を通じてコンデンサ内部に流れる。そこで接続端子に直接接続された導体である貫通導体を低い導電率とすることによりコンデンサのＥＳＲを効果的に高めることができる。この場合、より望ましくは、接続端子に近い側を低い導電率とすることがより望ましい。 FIG. 2 is a schematic view showing another embodiment of the multilayer capacitor 10 of the present invention. As shown in the figure, the ESR of the capacitor can be increased by setting the entire first through conductor and second through conductor as a low-conductivity region L. In this case, it is formed by applying a conductor having a lower conductivity than other portions to a part of the formed through hole. The current supplied to the capacitor always flows from the connection terminal into the capacitor through the through conductor. Therefore, the ESR of the capacitor can be effectively increased by setting the through conductor, which is a conductor directly connected to the connection terminal, to a low conductivity. In this case, it is more desirable that the side close to the connection terminal has a low conductivity.

図３は、本発明の積層コンデンサ１０のさらに他の実施の形態を示す断面図である。複数の誘電体層２を重畳してなる積層体において、第１表面に最も近い前記第１導体層および第１表面に最も近い前記第２導体層を低い導電率としたものである。この場合には、前記第１導体層および第２導体層のみの導体成分を他の導体層よりも導電率の低い成分を適用することにより得られる。つまり、積層したコンデンサにおいては、接続端子に最も近い導体であるコンデンサの表面側の導体により多くの電流が流れようとする。このため多くの電流の流れる部分に低い導電率の部分を設けることによりコンデンサのＥＳＲを効果的に高めることができる。 FIG. 3 is a cross-sectional view showing still another embodiment of the multilayer capacitor 10 of the present invention. In the laminated body formed by superposing a plurality of dielectric layers 2, the first conductor layer closest to the first surface and the second conductor layer closest to the first surface have low conductivity. In this case, the conductive component of only the first conductive layer and the second conductive layer is obtained by applying a component having lower conductivity than the other conductive layers. That is, in the laminated capacitor, a larger amount of current tends to flow through the conductor on the surface side of the capacitor, which is the conductor closest to the connection terminal. For this reason, the ESR of the capacitor can be effectively increased by providing a portion having a low conductivity in a portion where a large amount of current flows.

そして本発明者らは、図１に示す本発明の積層コンデンサ１０と、図７に示す従来の積層コンデンサ５０を作成し、静電容量Ｃ及び等価直列インダクタンスＬを測定した。ここで、積層コンデンサ１０、５０の両方とも、寸法は３．２ｍｍ×３．２ｍｍ×０．８５ｍｍ、積層数は１２０層、第１及び第２貫通導体３、４の数は両方合わせて３６個、第１及び第２貫通導体３、４の半径は０．０７ｍｍ、第１及び第２非導体形成領域１３、１４の半径は０．１７ｍｍとした。測定の結果、図７に示す従来の積層コンデンサ５０はＣ＝７．８μＦ、Ｌ＝２０ｐＨ、ESR=１０ｍΩとなったのに対し、図１に示す本発明の積層コンデンサ１０はＣ＝７．８μＦ、Ｌ＝２０ｐＨ、ESR=１００ｍΩであった。 The inventors made the multilayer capacitor 10 of the present invention shown in FIG. 1 and the conventional multilayer capacitor 50 shown in FIG. 7, and measured the capacitance C and the equivalent series inductance L. Here, both of the multilayer capacitors 10 and 50 have dimensions of 3.2 mm × 3.2 mm × 0.85 mm, the number of layers is 120, and the number of first and second through conductors 3 and 4 is 36 in total. The radius of the first and second through conductors 3 and 4 is 0.07 mm, and the radius of the first and second non-conductor forming regions 13 and 14 is 0.17 mm. As a result of the measurement, the conventional multilayer capacitor 50 shown in FIG. 7 has C = 7.8 μF, L = 20 pH, ESR = 10 mΩ, whereas the multilayer capacitor 10 of the present invention shown in FIG. 1 has C = 7.8 μF. L = 20 pH, ESR = 100 mΩ.

図１と図７のコンデンサを図５の半導体装置に実装した場合に相当する回路解析を行った結果を図４に示す。本発明の積層コンデンサ１０は図４の曲線C、従来のコンデンサ５０は図４の曲線Aとなり、インピーダンスピークが抑制されることがわかった。 FIG. 4 shows the result of circuit analysis corresponding to the case where the capacitors of FIGS. 1 and 7 are mounted on the semiconductor device of FIG. The multilayer capacitor 10 of the present invention has the curve C in FIG. 4, and the conventional capacitor 50 has the curve A in FIG.

このように本発明は、図５に示すようなコンデンサをデカップリングコンデンサとして用い高周波帯で用いられる半導体装置に好適に用いることができる。なお、本発明のコンデンサをデカップリングコンデンサとして用い高周波帯で用いられる半導体装置の電気回路図を図６に示した。本発明では容量成分とインダクタンス成分との間に抵抗成分を有するものである。 As described above, the present invention can be suitably used for a semiconductor device used in a high frequency band using a capacitor as shown in FIG. 5 as a decoupling capacitor. An electrical circuit diagram of a semiconductor device used in a high frequency band using the capacitor of the present invention as a decoupling capacitor is shown in FIG. In the present invention, there is a resistance component between the capacitance component and the inductance component.

本発明のコンデンサを示す図であり、（ａ）は第１、第２導体層の投影平面図、（ｂ）は図１（ａ）のＸ−Ｘ線断面図である。It is a figure which shows the capacitor | condenser of this invention, (a) is a projection top view of a 1st, 2nd conductor layer, (b) is the XX sectional view taken on the line of Fig.1 (a). 本発明のコンデンサの他の実施の形態を示す概略図である。It is the schematic which shows other embodiment of the capacitor | condenser of this invention. 本発明のコンデンサのさらに他の実施の形態を示す断面図である。It is sectional drawing which shows other embodiment of the capacitor | condenser of this invention. 本発明のコンデンサと従来のコンデンサを半導体装置に実装した場合のインピーダンスの周波数特性である。It is the frequency characteristic of the impedance at the time of mounting the capacitor | condenser of this invention and the conventional capacitor | condenser in a semiconductor device. 本発明のコンデンサをデカップリングコンデンサとして用いた半導体装置の構造例であり、図５（ａ）は（ｂ）図のＡ−Ａ線断面図、（ｂ）は半導体装置の平面図である。FIG. 5A is a structural example of a semiconductor device using the capacitor of the present invention as a decoupling capacitor, FIG. 5A is a cross-sectional view taken along line AA of FIG. 5B, and FIG. 5B is a plan view of the semiconductor device. 本発明のコンデンサをデカップリングコンデンサとして用い高周波帯で用いられる半導体装置の電気回路図である。It is an electric circuit diagram of a semiconductor device used in a high frequency band using the capacitor of the present invention as a decoupling capacitor. 従来のコンデンサを示す図であり、（ａ）は第１、第２導体層の重なり状態を示す概略図、（ｂ）は図７（ａ）のＸ−Ｘ線断面図である。It is a figure which shows the conventional capacitor | condenser, (a) is the schematic which shows the overlapping state of a 1st, 2nd conductor layer, (b) is XX sectional drawing of Fig.7 (a).

Explanation of symbols

１０積層コンデンサ
２誘電体層
３第１導体層
４第２導体層
５第１貫通導体
６第２貫通導体
７第１接続端子
８第２接続端子
１３第１非導体形成領域
１４第２非導体形成領域 DESCRIPTION OF SYMBOLS 10 Multilayer capacitor 2 Dielectric layer 3 1st conductor layer 4 2nd conductor layer 5 1st penetration conductor 6 2nd penetration conductor 7 1st connection terminal 8 2nd connection terminal 13 1st nonconductor formation area 14 2nd nonconductor formation region

Claims

A first conductor layer is disposed on one principal surface of the dielectric layer, and a second conductor layer partially overlapping the first conductor layer via the dielectric layer is disposed on the other principal surface of the dielectric layer. And a plurality of first through conductors that penetrate through the non-conductor forming region in the second conductor layer in the thickness direction of the dielectric layer and are connected to the first conductor layer, and in the first conductor layer A plurality of second through conductors penetrating through the non-conductor forming region in the thickness direction of the dielectric layer and connected to the second conductor layer, the first conductor layer, the second conductor layer, the first A capacitor characterized in that at least one of the through conductor and the second through conductor has a portion having lower conductivity than the other region.

The capacitor according to claim 1, wherein the conductor having a low conductivity portion is a first through conductor and a second through conductor.

A laminate formed by laminating a plurality of dielectric layers; a first conductor layer provided on one main surface of at least one dielectric layer in the laminate; and the dielectric facing the first conductor layer A second conductor layer in which the first conductor layer partially overlaps the other main surface of the body layer via the dielectric layer, and a first non-conductor formation region in the first conductor layer as a thickness of the dielectric layer. A second penetrating conductor penetrating in a direction and connected to the second conductor layer, and a second non-conductor forming region in the second conductor layer formed in parallel to the second penetrating conductor. A first through conductor that penetrates and is connected to the first conductor layer, and ends of the first and second through conductors are led out to at least one surface of the multilayer body, and The first conductor layer that is close or the second conductor layer that is closest to the surface has a lower conductivity than the other conductor layers. Capacitor characterized in that was.

A semiconductor device comprising the capacitor according to claim 1.

A decoupling circuit comprising the capacitor according to claim 1.

A high-frequency circuit comprising the capacitor according to claim 1.