JP2006101072A - High frequency power amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect accuracy of an output power of an output power detection circuit which is used in a radio communication system which performs feedback control by detecting output power of a high frequency power amplifier circuit and amplifies a difference between a reference voltage and a detection output. To improve.
A detection circuit (221) for detecting an AC signal extracted from an output of a high-frequency power amplifier circuit, a bias generation circuit (222) for generating a voltage for providing an operating point of the detection circuit, An output power detection circuit (220) including a subtraction circuit (225) for outputting a voltage proportional to the difference between the output and the voltage generated by the bias generation circuit is provided, and two inverting amplifiers (261, 261) are provided as the subtraction circuit. 262) is used as a subordinate connection, and an inverting amplifier (264) for feedback is provided, which inputs the output of the subsequent inverting amplifier and a predetermined voltage as input and supplies the difference voltage as a reference voltage to the preceding inverting amplifier, An on / off switch (SW0) and a capacitive element (C0) capable of holding the output of the inverting amplifier are provided on the output side of the inverting amplifier.
[Selection] Figure 2

Description

  The present invention relates to a technique that is effective in a high-frequency power amplifier circuit that is used in a radio communication system such as a cellular phone and amplifies and outputs a high-frequency transmission signal, and particularly detects output power necessary for feedback control of output power. The present invention relates to a technology that is effective for use in circuits.

  In general, a transmission-side output unit in a wireless communication device (mobile communication device) such as a mobile phone is provided with a high-frequency power amplification circuit that amplifies a modulated transmission signal. In conventional wireless communication devices, the output power of a high-frequency power amplifier circuit or antenna is detected in order to control the amplification factor of the high-frequency power amplifier circuit according to the transmission request level from a control circuit such as a baseband circuit or a microprocessor. Thus, a feedback is performed (see, for example, Patent Document 1). The output power is generally detected using a coupler, a diode detection circuit, or the like, and the diode detection circuit is composed of a semiconductor integrated circuit or a discrete component separate from the high-frequency power amplification circuit. There are many.

  In the conventional output power detection method of a high frequency power amplifier circuit using a coupler, a diode is required to detect the detection output in addition to the size of the coupler itself. Since many semiconductor integrated circuits and electronic parts are used, it has been difficult to reduce the size of the module. Further, when a coupler is used, there is a problem that power loss is relatively large.

  Furthermore, in recent mobile phones, in addition to a method called GSM (Global System for Mobile Communication) using a frequency of 880 to 915 MHz, for example, a DCS (Digital Cellular System) using a frequency of 1710 to 1785 MHz is used. Dual-band mobile phones that can handle various types of signals have been proposed. In the high-frequency power amplification module used in such a cellular phone, an output power amplifier is also provided for each band. Therefore, a coupler and a detection circuit for detecting the output power are also required for each band. Therefore, it becomes difficult to further downsize the module.

Therefore, the present applicant, as shown in FIG. 5, detects the output power of the high-frequency power amplifier circuit that does not use a coupler from the middle of the impedance matching circuit connected to the subsequent stage of the final amplifier stage of the high-frequency power amplifier circuit. An invention was made in which an AC component of output power was extracted through a capacitive element and detected by an output power detection circuit, and was filed earlier (Japanese Patent Application No. 2003-123040).
JP 2000-151310 A

  The output power detection circuit according to the prior invention of FIG. 5 is for output detection in which an AC signal taken out from the output portion of the high-frequency power amplifier circuit 210 via the coupling capacitor Ci is received at the control terminal and a current proportional to the output power is passed. A transistor Q1, a bias generation circuit 223 for giving an operating point to the control terminal of the transistor, current mirror circuits Q2 and Q3 for transferring a current flowing through the output detection transistor, and a current − for converting the transferred current into a voltage − This comprises a voltage conversion transistor Q4, impedance conversion buffer amplifiers 222 and 224, a subtraction circuit 225 for subtracting the voltage of the bias generation circuit 223 from the voltage converted by the transistor Q4, and the like. The output of the subtraction circuit 225 is the DC component applied by the bias generation circuit 223. The detection voltage Vdet proportional to the AC component of the pure output power without the.

  The output power detection circuit (FIG. 5) according to the invention of the prior application has a problem that the input impedance is low and the buffer amplifiers 222 and 224 are indispensable, and the detection voltage Vdet varies due to variations in resistance. Therefore, the use of a subtracting circuit in which three operational amplifiers (operational amplifiers) AMP1 to AMP3 are cascade-connected as shown in FIG. 6 was examined. The subtraction circuit shown in FIG. 6 is a known circuit described in, for example, CQ Publishing Co., Ltd., published in January 1990, “Analog IC Utilization Handbook” p65, p66.

  The output Vdet of the subtracting circuit shown in FIG. 6 has a resistance ratio of the input resistance Rin and the feedback resistance Rf of each inverting amplifier to 1: (N−1), and the difference between the two input voltages Vin1 and Vin2 is ΔVin (= Vin2−Vin1). ), Vdet≈Vdc + N · ΔVin. When the AC signal is no signal, Vdet≈Vdc, but although not actually shown in this equation, the operational amplifiers AMP1, AMP2, and AMP3 have input offsets Voff1, Voff2, and Voff3, respectively. The subtracting circuit shown in FIG. 6 has a problem that its output Vdet is shifted due to the input offset of the operational amplifiers AMP1 to AMP3.

  In the subtracting circuit shown in FIG. 6, when the reference voltage Vdc is generated by dividing a constant voltage by resistance division by the resistance voltage dividing circuit, it is necessary to adjust the value of the resistor constituting the resistance voltage dividing circuit. As a result, it takes a relatively long time to detect and adjust the resistance value in the manufacturing process, which may increase the chip cost.

An object of the present invention is to detect an output power detection circuit that is used in a radio communication system that performs feedback control by detecting output power of a high-frequency power amplifier circuit and amplifies and outputs a difference between a reference voltage and a detection output. It is to improve the accuracy of output.
Another object of the present invention is to incorporate an output power detection circuit with high detection accuracy, which is used in a radio communication system that performs feedback control by detecting output power and amplifies and outputs a difference between a reference voltage and a detection output. Another object of the present invention is to provide an inexpensive semiconductor integrated circuit for high-frequency power amplification.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a detection circuit that detects an AC signal extracted from the output of the high-frequency power amplifier circuit, a bias generation circuit that generates a voltage that gives an operating point of the detection circuit, and an output of the detection circuit and the bias generation circuit And an output power detection circuit including a subtraction circuit that outputs a voltage proportional to the difference from the measured voltage. The subtraction circuit includes two inverting amplifiers connected in cascade. An inverting amplifier for feedback is provided that takes the DC voltage of the input as an input and the difference voltage as a reference voltage to the inverting amplifier in the previous stage. In addition, a capacitive element is provided, and the feedback loop is closed by turning on the switch in the absence of the operation value input to the two inverting amplifiers. After taking the output of the feedback inverting amplifier into the capacitive element, the operation value is input to the two inverting amplifiers with the switch turned off, and a voltage corresponding to the potential difference between them is output. It is a thing.

  According to the above means, the voltage including the offset of the three inverting amplifiers constituting the subtracting circuit is held in the capacitive element by the feedback loop, and then the feedback loop is opened and the voltage held in the capacitive element is used as a reference. Thus, the potential difference between the two inputs is amplified. In other words, since the voltage obtained by correcting the original reference DC voltage according to the offsets of the three inverting amplifiers is used as the reference voltage, a highly accurate output power detection signal can be obtained. For this reason, it is not necessary to provide a trimming circuit for adjusting a reference voltage, and trimming work in the manufacturing process is not required, so that the manufacturing cost of the high-frequency power amplifier circuit incorporating the output power detection circuit can be reduced.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, an output power detection circuit that is used in a radio communication system that performs feedback control by detecting output power of a high-frequency power amplifier circuit and amplifies and outputs a difference between a reference voltage and a detection output. The accuracy of detection output can be improved. In addition, according to the present invention, a built-in output power detection circuit with high detection accuracy for amplifying and outputting a difference between a reference voltage and a detection output, which is used in a radio communication system that performs output control by detecting output power, is built-in. An inexpensive high-frequency power amplifier circuit can be realized.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of a high frequency power amplifier (hereinafter referred to as a power module) to which the output power detection circuit of the present invention is applied. In this specification, a plurality of semiconductor chips and discrete components are mounted on an insulating substrate such as a ceramic substrate with printed wiring on the surface or inside, and each component has a predetermined role in the printed wiring or bonding wire. A module that can be handled as a single electronic component is called a module.

  The power module 200 of this embodiment includes a high frequency power amplification unit 210 including an amplification FET that amplifies an input high frequency signal RFin, an output power detection circuit 220 that detects output power of the high frequency power amplification unit 210, and the high frequency power. It comprises a bias circuit 230 that applies a bias voltage to the amplifying FETs at each stage of the amplifying unit 210 and controls an idle current that flows through each FET.

  Although not particularly limited, the high-frequency power amplifying unit 210 of this embodiment includes three power amplifying FETs 211, 212, and 213, and the latter FETs 212 and 213 are the drain terminals of the preceding FETs 211 and 212, respectively. The gate terminal is connected to the first and second amplifier circuits as a whole. Further, gate bias voltages Vb1, Vb2, and Vb3 supplied from the bias circuit 230 are applied to the gate terminals of the FETs 211, 212, and 213 in each stage, and an idle current corresponding to these voltages is applied to each FET 211, 212, and 213. It is made to be shed by each.

  The bias circuit 230 includes a diode-connected MOS transistor Q10 that converts a constant current Icont supplied from the outside into a voltage, MOS transistors Q11, Q12, and Q13 that are connected in common to the transistor Q10 and form a current mirror circuit. These transistors Q11, Q12, Q13 are respectively composed of diode-connected MOS transistors Qb1, Qb2Qb3 connected in series, and the current transferred to Q11, Q12, Q13 is converted into a voltage by Qb1, Qb2, Qb3, This is applied as a bias voltage to the gates of the amplifying FETs 211, 212, and 213 through resistors R1, R2, and R3, respectively.

  The MOS transistors Q10, Q11, Q12, and Q13 are set to have a predetermined size ratio in accordance with the amplification FETs 211 to 213, respectively, so that an idle current proportional to the constant current Iton supplied from the outside can be obtained. 213. The resistors R1 to R3 function to suppress the current of the bias transistors Qb1 to Qb3 from being changed by leakage of a high frequency signal from the input terminal. A power supply voltage Vdd is applied to the drain terminals of the FETs 211, 212, and 213 at each stage. A direct current cut capacitive element C1 is provided between the gate terminal of the first stage FET 211 and the input terminal Pin, and a high frequency signal RFin is input to the gate terminal of the FET 211 via these circuits and elements.

  A DC-cut capacitive element C2 is provided between the drain terminal of the first stage FET 211 and the gate terminal of the second stage FET 212, and between the drain terminal of the second stage FET 212 and the gate terminal of the last stage FET 213. Is connected to a DC-cut capacitive element C3. The drain terminal of the FET 213 at the final stage is connected to the output terminal OUT via the impedance matching circuit 241 and the capacitive element C4, and a signal RFout obtained by cutting the DC component of the high-frequency input signal RFin and amplifying the AC component is output. .

  The output power detection circuit 220 of this embodiment has one terminal connected to a microstrip line constituting a coupler 242 provided in the middle of an output line connecting the drain terminal of the amplification FET 213 at the final stage and the output terminal OUT of the module. Connected to the capacitor C5, the resistor R4 and the capacitor C6 connected in series with the capacitor C5, the detection MOS transistor Q1 whose other terminal is connected to the gate, and the transistor Q1 connected in series. A detection circuit 221 comprising a P-channel MOS transistor Q2, a MOS transistor Q3 connected to the transistor Q2 in a current mirror connection, a current-voltage conversion MOS transistor Q4 connected in series with the transistor Q3, and the MOS transistor Q1 Bias generation giving gate bias voltage as a point A road 223, and a differential amplifier (subtracter circuit) 225 for amplifying and outputting the potential difference generated bias voltage at the output and the bias generating circuit 223 of the detection circuit 221.

  In the embodiment of FIG. 1, the coupler 242 is configured to extract the AC component of the output of the high-frequency power amplifier 210. However, as in the above-mentioned output power detection circuit (see FIG. 5) of the prior application, You may comprise so that an alternating current component may be taken out from the impedance matching circuit 241 provided on the output line of the power amplification part 210. FIG. In that case, the capacitor C5 in FIG. 1 is omitted, and one terminal of the resistor R4 is connected to the microstrip line constituting the impedance matching circuit 241 so as to extract the AC component of the output of the high frequency power amplifier 210. can do.

  In the output power detection circuit 220 of this embodiment, the bias generation circuit 223 includes a constant current source CS0, a diode-connected MOS transistor Q9 that converts the constant current Ic from the constant current source CS0 into a voltage, and a resistor R6. It is composed of The constant current source CS0 that supplies the constant current Ic includes a constant voltage circuit that generates a constant voltage having a low temperature dependency, such as a band gap reference circuit, a transistor that converts the generated constant voltage into a current, It can be constituted by a current mirror circuit for supplying a current proportional to the flowing current. Instead of configuring the constant current source CS0 as an internal circuit, the constant current source CS0 may be configured to be supplied from the outside of the chip. Further, instead of the constant current, the constant voltage may be applied from the outside of the chip. In the case where the voltage is applied as a constant voltage, a resistor may be connected in series with the transistor Q9 instead of the constant current source CS0 in FIG. 1, as in the output power detection circuit of the previous application (see FIG. 5).

  In this embodiment, a voltage value close to the threshold voltage of Q1 is set as the value of the gate bias voltage of the detection MOS transistor Q1 of the detection circuit 221 so that the transistor Q1 can be operated in class B amplification. ing. As a result, a current that is proportional to the AC signal input through the capacitor C6 and half-wave rectified flows through the MOS transistor Q1, and the drain current of Q1 is a DC component that is proportional to the amplitude of the input AC signal. To be included.

  The drain current of the transistor Q1 is transferred to the Q3 side by a current mirror circuit of Q2 and Q3, and is converted into a voltage by a diode-connected transistor Q4. Here, the MOS transistors Q1 and Q4 and Q2 and Q3 are set to have a predetermined size ratio. Thus, for example, if the characteristics (particularly the threshold voltage) of the MOS transistors Q1 and Q2 vary due to manufacturing variations, the characteristics of the MOS transistors Q4 and Q3 that form a pair with the MOS transistors Q1 and Q2 also vary in the same way. As a result, the influence due to the characteristic variation is offset, and a detection voltage that is not affected by the variation of the MOS transistor appears at the drain terminal of the MOS transistor Q4.

  In this embodiment, the same voltage as the bias voltage generated by the bias generation circuit 223 and applied to the gate terminal of the detection MOS transistor Q1 is supplied to the differential amplifier (subtraction circuit) 225, and the detection circuit 221 is supplied. A voltage obtained by amplifying the potential difference from the output of is output as the detection voltage Vdet. As a result, the output of the differential amplifier 225 becomes a detection voltage Vdet proportional to the AC component of pure output power that does not include the DC component applied by the bias generation circuit 223.

  The power module 200 of this embodiment includes each element of the power amplifying unit 210 (except for the DC cut capacitive elements C1 to C3), each element of the bias circuit 230, and each element (capacitance C5 of the output power detection circuit 220). Is configured as a semiconductor integrated circuit on one semiconductor chip such as single crystal silicon. The semiconductor integrated circuit, the capacitors C1 to C3 of the power amplifier 210, the impedance matching circuit 241, the DC-cut capacitor C4, the coupler 242, and the capacitor C5 of the output power detection circuit 220 are combined into one ceramic. It is mounted on a substrate and configured as a power module. The inductor constituting the impedance matching circuit 241 can be formed by a bonding wire connected between pads of a semiconductor chip or a microstrip line formed on a module substrate.

  Thus, in the power module to which the output power detection circuit of the present embodiment is applied, the output power detection circuit 220 can be easily integrated into a semiconductor integrated circuit together with the power amplification unit 210 and its bias circuit 230. This makes it possible to reduce the size of the module. Although not shown, the semiconductor integrated circuit of this embodiment compares the detection voltage Vdet detected by the output power detection circuit 220 with the output level instruction signal Vramp from the baseband circuit, and a control signal corresponding to the potential difference. An error amplifier (APC circuit) that generates Vramp is provided, and the control signal Vramp generated by the error amplifier is supplied to the bias circuit 230 to generate the bias voltages Vb1 to Vb3 of the high-frequency power amplifier 210. Is also possible.

FIG. 2 shows a specific circuit example of the differential amplifier section (subtraction circuit) 225 of the output power detection circuit 220 of the above embodiment.
The differential amplifying unit (subtracting circuit) 225 of the present embodiment includes two non-inverting amplifier circuits 261 and 262 connected in cascade, a voltage follower 263 for impedance conversion provided in the subsequent stage, and a DC voltage as a reference An inverting amplifier circuit 264 that receives Vdc0 and the output voltage of the non-inverting amplifier circuit 262 in the subsequent stage of the non-inverting amplifier circuits 261 and 262, and impedance conversion of the output of the inverting amplifier circuit 264 to convert the non-inverting amplifier circuit. A voltage follower 265 that feeds back to the non-inverting amplifier circuit 261 in the previous stage as a reference potential is included.

  The non-inverting amplifier circuit 261 includes an operational amplifier AMP1, an input resistor R11, and a feedback resistor R12. The non-inverting amplifier circuit 262 includes an operational amplifier AMP2, an input resistor R21, and a feedback resistor R22. The bias voltage from the bias circuit 223 is input to the non-inverting input terminal of the operational amplifier AMP1 of the circuit 261 as the input voltage Vin1, and the output voltage from the detection circuit 221 is input to the non-inverting input terminal of the operational amplifier AMP2 of the non-inverting amplifier circuit 262. It is input as the input voltage Vin2. The resistance ratio between the input resistance R11 and the feedback resistance R12 and the resistance ratio between the input resistance R21 and the feedback resistance R22 are set to 1: (N−1), respectively.

  Further, between the inverting amplifier circuit 264 and the voltage follower 265, an on / off switch SW0 for transmitting or blocking the output of the inverting amplifier circuit 264 to the voltage follower 265, and an inverting amplifier circuit when the switch is turned on. H.264 detecting the rising of the power supply voltage Vpd of the operational amplifiers AMP3, AMP5, and AMP4 constituting the capacitive amplifier C0, the operational amplifiers AMP1, AMP2 and the voltage followers 263, 265, and the inverting amplifier circuit 264 A power supply voltage detection circuit 267 that generates an ON / OFF signal ON / OFF is provided. In the present embodiment, the operational amplifiers AMP1 to AMP5 are composed of MOS transistors having a higher input impedance than bipolar transistors.

  FIG. 3 shows the operation timing of the differential amplifier section (subtraction circuit) 225 of this embodiment. When the power supply voltage Vpd rises, the ON / OFF signal ON / OFF is changed to a high level, the switch SW0 is turned on, and the loop of the amplifiers AMP1-AMP2-AMP4-AMP5-AMP1 is closed. At this time, since the input voltages Vin1 and Vin2 of the non-inverting amplifier circuits 261 and 262 are at the same level, feedback is applied so that the output of the amplifier AMP2 coincides with the reference voltage Vdc0 by the imaginary short action of the amplifier AMP4.

  At this time, if the amplifiers AMP1, AMP2, AMP4, and AMP5 each have an input offset, the output of the amplifier AMP4 becomes a voltage Vdc1 corresponding to the sum of the input offsets and the reference voltage Vdc0, and the capacitance is determined by the voltage. Element C0 is charged. In a communication system such as a GSM mobile phone, the reception mode and the transmission mode are executed in a relatively short time unit such as 577 μsec called a time slot. In the transmission mode, the power supply voltage Vpd is set every time transmission is started. Since the start-up is performed, even if the capacitance value of the capacitive element C0 is not set to a very large value, there is no possibility that the charge of the capacitive element C0 leaks during transmission and the output of the subtraction circuit changes.

  The ON / OFF signal ON / OFF output from the power supply voltage detection circuit 267 is configured to change to a low level after a predetermined time. When the ON / OFF signal ON / OFF becomes a low level, the switch SW0 is turned off. Thus, the voltage Vdc1 of the immediately previous capacitive element C0 is held as it is. Thereafter, voltages Vin1 and Vin2 that change due to the operation of the detection circuit 221 are input to the non-inverting amplifier circuits 261 and 262, and the potential difference is amplified and output as the detection voltage Vdet. According to the differential amplifier section (subtraction circuit) of this embodiment, the output voltage Vdet at this time includes only the input offset of the amplifier AMP3, and does not include the input offsets of the amplifiers AMP1, AMP2, AMP4, and AMP5. become. Therefore, the error of the detection voltage due to the input offset of the operational amplifier is significantly reduced as compared with the circuit of FIG. As a result, the output power detection circuit of the embodiment improves the detection accuracy of the output power.

  As a result, the output power detection circuit according to the embodiment does not need a trimming circuit for adjusting a reference voltage supplied to the subtraction circuit and does not require a trimming operation in the manufacturing process. Thus, the cost of the high frequency power amplifier circuit can be reduced.

FIG. 4 shows a schematic configuration of a system capable of wireless communication using two communication systems, GSM and DCS, as an example of an effective wireless communication system to which the power module of the embodiment is applied.
In FIG. 4, ANT is an antenna for transmitting and receiving signal radio waves, 100 is a modulation / demodulation circuit capable of performing GMSK modulation and demodulation in GSM and DCS systems, and I and Q signals are generated based on transmission data (baseband signals). A high-frequency signal processing circuit (baseband circuit) 110 having a circuit for processing I and Q signals extracted from received signals, low noise amplifiers LNA1 and LNA2 for amplifying received signals, and the like are formed on one semiconductor chip. A high-frequency signal processing semiconductor integrated circuit (baseband IC), bandpass filters BPF1 and BPF2 for removing harmonic components from a transmission signal, bandpass filters BPF3 and BPF4 for removing unnecessary waves from a reception signal, etc. in one package A mounted electronic device (hereinafter referred to as an RF device) Tx-MIX1 and Tx-MIX2 are mixers for up-converting GSM and DCS transmission signals, and Rx-MIX1 and Rx-MIX2 are mixers for down-converting GSM and DCS reception signals.

  The baseband circuit 110 includes mixers Tx-MIX1, Tx-MIX2 for up-converting GSM and DCS transmission signals, mixers Rx-MIX1, Rx-MIX2, for down-converting GSM and DCS reception signals, respectively. Oscillators VCO1 to VCO4 that generate oscillation signals that are mixed with transmission signals and reception signals by a mixer, variable gain amplifiers GCA1 and GAC2 that amplify transmission signals of GSM and DCS, respectively, and a desired amplitude by controlling the gain of these amplifiers A gain control circuit 111 is provided for outputting the above signal.

  In FIG. 4, reference numeral 200 denotes the power module of the above-described embodiment that amplifies the high-frequency transmission signal supplied from the baseband circuit 110, and 300 denotes filters LPF <b> 1 and LPF <b> 2 that remove noise such as harmonics included in the transmission signal. This is a front-end module including demultiplexers DPX1 and DPX2 for synthesizing and separating GSM signals and DCS signals, a transmission / reception changeover switch T / R-SW, and the like. The power module 200 is provided with a high frequency power amplifier circuit (power amplifier) 210a for GSM and a high frequency power amplifier circuit 210b for DCS.

  As shown in FIG. 4, in this embodiment, a mode selection signal VBAND indicating GSM or DCS from the baseband circuit 110 to the bias circuit 230 of the high frequency power amplifier circuits 210a and 210b and a constant current Itont are The bias circuit 230 generates a bias current corresponding to the mode based on the control signal VBAND and the constant current Itont and supplies it to one of the power amplifiers 210a and 210b. The bias circuit 230 includes a current mirror circuit including the transistors Q10 to Q13 and bias transistors Qb1 to Qb3 in FIG. 1 for GSM and DCS, respectively, and a selection circuit and the like are added.

  In this embodiment, the detection voltage Vdet output from the output power detection circuit 220 in the power module 200 is supplied to the gain control circuit 111 of the baseband circuit 110, and the gain control circuit 111 is connected to the output detection voltage Vdet. The output level instruction signal Vramp is compared to generate a power control signal PCS for the variable gain amplifiers GCA1 and GCA2, and their gains are controlled, and the amplitude of the high frequency signal input to the power amplifiers 210a and 210b according to this is controlled. To be controlled.

  In the GSM and DCS dual-band communication system as described above, the maximum levels of the output power of the GSM-side power amplifier 210a and the output power of the DCS-side power amplifier 210b are defined by different standards. . Therefore, although not shown in FIG. 4, the output power detection circuit 220 of FIG. 4 is provided with detection circuits having configurations as shown in FIGS. 1 and 2 for GSM and DCS, respectively. In accordance with the control signal VBAND, one of them can be selectively activated.

  In the embodiment of FIG. 4, the detection voltage Vdet output from the output power detection circuit 220 is supplied to the gain control circuit 111 of the baseband circuit 110 to control the gains of the variable gain amplifiers GCA1 and GCA2. An error amplifier (APC circuit) that compares the detection voltage Vdet detected by the output power detection circuit 220 with the output level instruction signal Vramp from the baseband circuit and generates a control signal Vramp corresponding to the potential difference in the module 200. When provided, the output level instruction signal Vramp is supplied from the baseband circuit 110 to the APC circuit (error amplifier) in the power module 200, and the APC circuit (error amplifier) outputs the output level instruction signal Vramp and the output power detection circuit 220. The output control signal Vapc for the bias circuit 230 is generated by comparing with the detection voltage Vdet from The circuit 230 can be configured to control the gains of the power amplifiers 210a and 210b in accordance with the output control signal Vapc.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, FETs are used for the amplifying transistors 211 to 213 of the high-frequency power amplifier, but the amplifying transistors 211 to 213 are bipolar transistors, GaAs MESFETs, heterojunction bipolar transistors (HBT), HEMT ( It is also possible to use other transistors such as High Electron Mobility Transistor). In the above-described embodiment, the case where the number of amplification stages of the high-frequency power amplification unit is three, but the number of amplification stages may be one or two. The current-voltage conversion transistor Q4 constituting the detection circuit 221 may be a resistance element.

  Furthermore, in the above-described embodiment, the operational amplifiers AMP1 to AMP5 constituting the subtraction circuit 225 are constituted by MOS transistors. However, operational amplifiers constituted by bipolar transistors may be used. However, in this case, each amplifier has an input impedance lower than that of an amplifier composed of a MOS transistor. Therefore, it is necessary to provide one corresponding to the buffer amplifiers 222 and 224 in the embodiment of the prior application (see FIG. 5). desirable.

  In the above-described embodiment, as the bias circuit 230 for generating the gate bias of the amplification FETs 211 to 213 constituting the high frequency power amplification unit 210, the amplification FETs 211 to 213 are received by the current mirror circuit in response to an external control current Icont. The bias circuit 230 is configured to flow an idle current. However, the bias circuit 230 may be configured by a resistance dividing circuit that generates a gate bias of the FETs 211 to 213 by dividing a control voltage supplied from the outside with a resistor. good.

  In the above description, the case where the invention made mainly by the present inventor is applied to a high frequency power amplifier circuit and a power module used in a mobile phone which is a field of use behind the present invention has been described, but the present invention is not limited thereto. It can be used for a high-frequency power amplifier circuit and a power module that constitute a wireless LAN.

1 is a circuit configuration diagram showing an embodiment of an output power detection circuit according to the present invention and a high-frequency power amplifier (power module) to which the output power detection circuit is applied. It is a circuit block diagram which shows the specific circuit example of the differential amplifier (subtraction circuit) which comprises an output electric power detection circuit. FIG. 3 is a timing chart showing operation timings of the differential amplification unit (subtraction circuit) of FIG. 2. 1 is a block diagram showing a schematic configuration of a system capable of wireless communication of two communication systems, GSM and DCS, to which a high-frequency power amplifier circuit of the present invention is applied. It is a circuit block diagram which shows an example of the conventional output power detection circuit. It is a circuit block diagram which shows the structural example of the subtraction circuit of the output electric power detection circuit examined prior to this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 RF device 110 Baseband circuit 200 Power module 210 High frequency power amplification part 210a, 210b High frequency power amplification circuit (power amplifier)
211, 212, 213 Power amplification FET
220 output power detection circuit 221 detection unit 222, 224 buffer circuit 223 bias generation circuit 225 subtraction circuit 230 bias circuit 241 to 244 impedance matching circuit 250 error amplifier (APC circuit)
300 Front-end module

Claims (5)

A power amplification circuit for amplifying a high-frequency transmission signal; and an output power detection circuit for detecting a level of output power of the power amplification circuit;
The output power detection circuit includes: a detection circuit that detects an AC signal extracted from the output of the power amplification circuit; a bias generation circuit that generates a voltage that provides an operating point of the detection circuit; an output of the detection circuit; A subtraction circuit that outputs a voltage proportional to the difference from the voltage generated by the bias generation circuit,
The subtracting circuit includes two subordinately connected inverting amplifiers, a third inverting amplifier that inputs an output of a subsequent inverting amplifier and a predetermined voltage and supplies a difference voltage as a reference voltage to the preceding inverting amplifier, A feedback loop can be formed by including an on / off switch provided on the output side of the third inverting amplifier and a capacitive element capable of holding the output of the third inverting amplifier. In the absence of input, the switch is turned on, the loop is closed and the output of the third inverting amplifier is taken into the capacitive element, and then the detection is made to the two inverting amplifiers with the switch turned off. A high-frequency power amplifier circuit, wherein a circuit output and a voltage generated by the bias generation circuit are input to output a voltage corresponding to a potential difference between them.   2. The high frequency device according to claim 1, wherein the subtracting circuit includes a buffer amplifier for impedance conversion provided between an output terminal of the third inverting amplifier and an input terminal of the preceding inverting amplifier. Power amplifier circuit.   3. The high frequency power amplifier circuit according to claim 1, wherein the subtraction circuit includes a second buffer amplifier that impedance-converts and outputs an output of the subsequent inverting amplifier.   The inverting amplifier at the preceding stage and the inverting amplifier at the succeeding stage are each composed of an operational amplifier, an input resistor connected to the inverting input terminal of the operational amplifier, and a feedback resistor connected between the output terminal and the inverting input terminal of the operational amplifier. The resistance value of the input resistance of the inverting amplifier in the preceding stage and the input resistance of the inverting amplifier in the succeeding stage are the same, the resistance ratio of the input resistance and the feedback resistor in the preceding inverting amplifier, and the input resistance of the inverting amplifier in the succeeding stage The high-frequency power amplifier circuit according to claim 1, wherein a resistance ratio of the feedback resistor and the feedback resistor is the same.   The detection circuit includes: a first transistor to which an AC signal extracted from an output unit of the power amplifier circuit is applied to a control terminal; a second transistor connected in series with the first transistor; and the second transistor And a third transistor connected in a current mirror connection and current-voltage conversion means connected in series with the third transistor, and the voltage generated by the bias generation circuit is applied to the control terminal of the first transistor. The high frequency power amplifier circuit according to claim 1, wherein the high frequency power amplifier circuit is provided.

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