JP2006019765A - Semiconductor device and semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a mounting effective area ratio and to suppress a distortion generated due to a difference in thermal expansion coefficient and a semiconductor device.
In the present invention, a semiconductor substrate 110 made of Si is prepared as a mounting substrate, so that the thermal expansion coefficient α is made equal to that of a semiconductor chip 60. Therefore, even if the radial wiring is provided so as to overlap with the semiconductor chip 60, the semiconductor substrate 110 and the semiconductor chip 60 are repeatedly expanded and contracted in the same manner, and a structure in which the distortion generated between them is difficult to occur can be realized.
60 and the thermal expansion coefficient α are made equal. Therefore, even if the radial wiring is provided so as to overlap with the semiconductor chip 60, the semiconductor substrate 110 and the semiconductor chip 60 are repeatedly expanded and contracted in the same manner, and a structure in which the distortion generated between them is difficult to occur can be realized.
[Selection] Figure 1

Description

      The present invention relates to a semiconductor device.

  A general semiconductor device in which elements such as a bipolar IC and a MOS LSI are formed on a silicon substrate mainly has a configuration as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

  As described above, the silicon substrate 1 on which the bipolar IC is formed is fixedly mounted on the island 2 such as a copper-based heat sink via the brazing material 5 such as solder, as shown in FIG. The lead terminal 3 arranged in the periphery and each electrode such as a bipolar IC are electrically connected by wire bonding, and then transferred to the silicon substrate and the lead terminal by thermosetting resin 4 such as epoxy resin. A part of the resin is completely covered and protected, and a resin mold type semiconductor device is provided.

  A resin-molded semiconductor device is usually mounted on a wiring substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate to perform a predetermined circuit operation. Treated as a part.

  As shown in FIG. 30, the mounting area where the semiconductor device 20 is mounted on the mounting substrate 30 is represented by a region surrounded by each lead terminal 21, 22, 23 and a conductive pad connected to the lead terminal. . The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, but most of the mounting area is due to mold resin and lead terminals. The proportion of the area of the semiconductor chip is very small.

  Considering the ratio between the area where the semiconductor chip is formed and the mounting area as the effective area ratio, it has been confirmed that the effective area ratio is extremely low in a resin-molded semiconductor device. The low effective area ratio means that when the semiconductor device 20 is used by being connected to other circuit elements on the wiring board 30, most of the mounting area becomes a dead space that is not directly related to a functioning semiconductor chip. . If the effective area ratio is small, the dead space is increased on the mounting substrate 30 as described above, which hinders high-density downsizing of the mounting substrate 30.

This problem is particularly noticeable in a semiconductor device having a small package size. For example, it is assumed that the semiconductor chip is a package as shown in FIG. 31 and the minimum size is 3.4 mm × 2.4 mm. When this semiconductor chip is connected to a metal lead terminal with a wire and resin-molded, the overall size of the semiconductor device is about 6.0 mm × 5.0 mm.
Since the chip area of this semiconductor device is 8.16 mm 2 and the mounting area for mounting the semiconductor device is 30.0 mm 2, the effective area ratio of this semiconductor device is about 27.2% even if the lead is ignored. (In practice, this value is further reduced when the lead is taken into account.) Most of the mounting area is a dead space that is not directly related to the area of the functioning semiconductor chip.

  Wiring boards used in recent electronic devices, for example, portable information processing devices such as personal computers and electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. The mounting substrate used is also in the trend of high density and miniaturization.

  However, in the above-described prior art resin-encapsulated semiconductor device, as described above, since the mounting area for mounting the semiconductor device has a large dead space, there is a limit to downsizing of the mounting substrate, and downsizing of the mounting substrate. Was one of the obstacles.

  By the way, there is JP-A-3-248551 as a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, in order to minimize the mounting area when the resin mold type semiconductor device is mounted on a mounting substrate or the like, lead terminals 41, 42, 43 connected to the base, emitter, and collector electrodes of the semiconductor chip 40 are provided. The lead terminals 41, 42, and 43 are formed so as to be flush with the side surface of the resin mold 44 without protruding outward from the side surface of the resin mold 44.

  According to this configuration, the mounting area can be reduced by the amount that the tip portions of the lead terminals 41, 42, and 43 do not come out, and the effective area ratio can be slightly improved, but the size of the dead space is Not much improvement.

  In order to improve the effective area ratio, it is necessary to make the semiconductor chip area and the mounting area of the semiconductor device substantially the same, and in the resin mold type semiconductor device, as in this prior art, the tip of the lead terminal Even if the part is not derived, it is difficult to improve the effective area ratio due to the presence of the mold resin.

  Further, in the above-described semiconductor device, a lead terminal connected to the semiconductor chip and a mold resin are indispensable. Therefore, a wire connection process between the semiconductor chip and the lead terminal, a molding resin injection molding process, and a manufacturing process are required. However, there is a problem that the manufacturing cost cannot be reduced.

  In order to maximize the effective area ratio, as described above, the semiconductor chip area and the mounting area are almost the same by mounting the semiconductor chip directly on the mounting substrate, so that the effective area ratio can be maximized. .

  As described above, as one prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-6-338504, a flip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 A technique for face-down bonding a chip to a mounting substrate 47 is known (see FIG. 33). In such a semiconductor device joined by face-down bonding, when the bump electrode is subjected to stress due to thermal stress or the like, problems such as separation of the bump electrode from the semiconductor chip appear remarkably.

  As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in Japanese Patent Laid-Open No. 7-38334, a semiconductor chip 53 is formed on a conductive pattern 52 formed on a mounting substrate 51. A technique of bonding and connecting electrodes of the conductive pattern 52 and the semiconductor chip 53 arranged around the semiconductor chip 53 with a wire 54 is known (see FIG. 34).

  As the wire 54 that connects the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53, a gold fine wire is usually used. Further, in order to increase the peel strength (tensile force) of the bonding joint portion bonded to the gold wire, it is preferable to perform bonding in a heated atmosphere of about 200 to 300 degrees.

  However, when die bonding a semiconductor chip on an insulating resin-based mounting substrate, the wiring substrate is distorted when heated to the above-described temperature. Also, in order to melt solder for fixing other circuit elements such as chip capacitors and chip resistors mounted on the mounting substrate, wire bonding connection is realized at a heating temperature of about 100 to 150 degrees. However, there is a problem that the peel strength of the bonding joint is lowered.

  In this prior art, the die-bonded semiconductor chip is usually covered and protected with a thermosetting resin such as an epoxy resin. However, as described above, when wire bonding is performed at a low temperature, the adhesive strength is lowered, and thus there is a problem that the bonded portion of the bonding portion is peeled off due to shrinkage or the like of the epoxy resin during thermosetting.

The present invention has been made in view of the aforementioned problems,
First, a semiconductor substrate made of silicon to be a wiring substrate, an insulating layer formed on a surface of the semiconductor substrate made of silicon, a plurality of wires provided on the insulating layer, and the plurality of wires In a semiconductor device having a semiconductor chip provided on a semiconductor substrate made of silicon and electrically connected,
The problem is solved by providing the plurality of wirings at least between the semiconductor substrate and the semiconductor chip and forming them radially.
Since the semiconductor substrate and the semiconductor chip use the same silicon and have the same thermal expansion coefficient α, even if heat is generated or heat is applied, distortion is unlikely to occur.

Second, a semiconductor substrate made of silicon to be a wiring substrate, a first insulating layer formed on the semiconductor substrate made of silicon, a plurality of radial wirings provided on the first insulating layer, A semiconductor IC chip provided on the semiconductor substrate made of the second insulating layer provided excluding the contact hole region of the radial wiring and the silicon electrically connected to the radial wiring through the contact hole To solve the problem. Thirdly, the semiconductor IC chip is a bipolar IC or MOS LSI.
Fourth, the semiconductor IC chip is solved by being provided face-down with respect to the semiconductor substrate.
Fifth, a semiconductor substrate made of silicon to be a wiring substrate, a first insulating layer formed on the semiconductor substrate made of silicon, and a plurality of radial wirings provided on the first insulating layer, A semiconductor IC provided on a semiconductor substrate made of silicon, which is electrically connected to the radial wiring via the contact hole, a second insulating layer provided excluding the contact hole region of the radial wiring; A semiconductor device comprising a chip;
The semiconductor device is mounted by a mounting substrate made of a ceramic substrate, a glass epoxy substrate, a phenol substrate, or a metal substrate subjected to insulation treatment.
Sixth, the semiconductor IC chip is a bipolar IC or MOS LSI.

In the present invention, since the semiconductor substrate and the semiconductor chip are made of the same silicon, the thermal expansion coefficient α is equal, and even when the semiconductor chip is provided on the semiconductor substrate on which the radial wiring is provided, a structure in which distortion is not easily generated. Can be realized.

(1) First Embodiment Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the semiconductor device includes a semiconductor chip 60, a plurality of block-like external connection electrodes 70, a second semiconductor substrate 110 serving as a wiring substrate, and first and first examples of connection means. The second bump electrodes 90 and 100 are configured.

  As shown in FIG. 1, the external connection electrode 70 is connected to the connection electrode of the semiconductor chip 60, is arranged adjacent to at least one periphery of the semiconductor chip 60 and spaced apart by a predetermined distance, and is a semiconductor different from the semiconductor chip 60. It is formed from a substrate.

  In addition, the second semiconductor substrate 110 serving as a wiring substrate has a wiring pattern 81 electrically connected to each electrode of the semiconductor chip 60 and the external connection electrode 70 on the upper surface thereof. It is arranged to face the external connection electrode 70.

  Furthermore, the connection means 90 and 100 are for connecting the electrode of the semiconductor chip 60 and the external connection electrode 70 to form a predetermined space.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes the second semiconductor substrate 110 serving as a wiring substrate and the wiring pattern 81 provided on the upper surface thereof. In addition, a metal lead terminal connected to the external electrode and a protective sealing mold are unnecessary, and the external dimensions of the semiconductor device can be significantly reduced. The details will be described in the manufacturing method shown below.

  First, as shown in FIGS. 2 and 3, for example, an N− type epitaxial layer 70b is formed on a wafer-like first semiconductor substrate 70a made of an N + type single crystal silicon substrate by an epitaxial growth technique. A first bump electrode 90 is formed in a region 70x (shaded region) serving as an external connection electrode on the first semiconductor substrate 70a on which the epitaxial layer 70b is formed. Here, since the epitaxial layer is adopted as the wafer of the semiconductor chip 60 of FIG. 1 and the high-concentration diffusion region 71 (usually used as a vertical separation region) is adopted, the epitaxial layer is formed by 70b. Although used, it is not particularly limited. Impurities may be diffused on the entire surface of the substrate 70a by deposition, and the entire surface may be diffused to the back surface with a high concentration.

  Here, an N epitaxial layer is formed on an N substrate and a diffusion region 71 such as an N + type vertical separation region is formed. However, a reverse conductivity type may also be used. That is, a P type epitaxial layer may be formed on a P + type substrate to form a P + type high concentration diffusion region.

  The region 70x to be the external connection electrode is formed on the first semiconductor substrate 70a so as to regularly arrange predetermined pattern shapes that are annular or opposed to each other. More specifically, the external connection electrode region 70x is arranged at a predetermined interval on the outer periphery of the semiconductor device size region 70y (one-dot chain line region), and the first bump electrode 90 is disposed on the external connection electrode region 70x. Form.

  Here, a method of forming the first bump electrode 90 will be briefly described with reference to FIGS. FIG. 4 is a partially enlarged view of the first bump electrode 90 in FIG.

  N-type high concentration impurities such as phosphorus (P) and antimony (Sb) are implanted and diffused into the epitaxial layer 70b in the external connection electrode region 70x where the first bump electrode 90 is formed, and the high concentration diffusion region 71. Is formed. The high concentration diffusion layer 71 is formed to suppress the internal resistance in the external connection electrode region 70x. After the high concentration diffusion region 71 is formed, an insulating film such as a silicon oxide film or a silicon nitride film is formed on the epitaxial layer 70b, and an insulating film 71A having a contact hole in the external connection electrode region 70x is selectively formed. Form.

  A connection electrode 72 is formed by selectively depositing a metal material such as aluminum on the external connection electrode 70x exposed through the contact hole. A passivation film made of an insulator such as a PSG film, SiN, or SiNx is formed on the connection electrode 72, and a passivation film 73 that selectively exposes the connection electrode 72 to the external connection electrode region 70x is formed. After the passivation film 73 is formed, chromium, copper, titanium, or the like is selectively deposited by plating or vapor deposition on the exposed external connection electrode region 70x to form the first barrier metal film 74, and the connection electrode 72 is formed. Prevent failures due to corrosion. After forming the first barrier metal film 74, a first bump electrode 90 serving as a first connection means is formed.

  The first bump electrode 90 is formed on the first barrier metal film 74 formed on each external connection electrode region with a height of about 30 to 50 μm. The first bump electrode 90 is formed by a gold plating process. On the surface of the bump electrode, chromium, copper, titanium or the like is selectively attached by plating or vapor deposition to form a second barrier metal film 91 of several thousand angstroms. Form.

  Further, as shown in FIG. 4, a bonding metal is vapor-deposited on the second barrier metal 91 to form a bonding layer 92 in order to electrically bond to another substrate described later. The metal material used for the bonding layer 92 has a melting point lower than the melting point of the bump electrode made of gold (Au) and higher than the melting point of the solder material used when mounting on the mounting substrate described later. Material is used.

  Specifically, the melting point of gold (Au) is usually about 1064 degrees, and the melting point of the solder material used for mounting on the mounting substrate is about 170 degrees to 190 degrees. Any material can be used as long as it has a melting point within the temperature range of the two. For example, gold (Au) and tin (Sn) are alternately deposited and laminated, and the melting point is about 370 degrees. AuSn) is used.

  The above-described bonding layer is formed so as to spread outward from the center portion of the second barrier metal 91, but is separately formed on the second barrier metal 91 as shown in FIGS. May be.

  Further, only one first bump electrode 90 described above is formed on each external connection electrode 70 region, but the first bump electrode 90 is not limited to this. For example, as shown in FIG. A plurality of electrode regions 70x may be formed.

  Next, as shown in FIGS. 8 and 9, for example, a wafer-like second semiconductor substrate 110 made of an N + type single crystal silicon substrate is prepared, and the semiconductor is formed on the second semiconductor substrate 110. In the region corresponding to the device size region 70y, a plurality of wiring patterns 81 having one end extending to the external connection electrode region 70x of the first semiconductor substrate 70a and the other end extending into the semiconductor device size region 70y are formed. .

  The wiring pattern 81 is formed, for example, by forming an insulating layer 111 such as SiO 2 or SiN × on the surface of the second semiconductor substrate 110 and selectively depositing a metal such as aluminum on the insulating layer 111 in a predetermined shape. can do. As will be described later, the wiring pattern 81 is a wiring for connecting the external connection electrode region 70x and the semiconductor chip 60, and the pattern can be arbitrarily formed depending on the arrangement of the external connection electrodes 70. Then, as shown in FIG.

  After the wiring pattern 81 is formed on the second semiconductor substrate 110, an insulating film such as a silicon oxide film or a silicon nitride film is formed on the second semiconductor substrate 110, and both end portions of each wiring pattern 81 are selectively formed. Alternatively, a contact hole is formed in the central portion as necessary.

  On the wiring pattern 81 exposed by the contact hole, a metal material such as aluminum is selectively deposited to form the connection electrode 112. A passivation film made of an insulator such as a PSG film, SiN, or SiNx is formed on the connection electrode 112, and the connection electrode 112 is selectively exposed at both ends of the wiring pattern 81. After the passivation film 113 is formed, chromium, copper, titanium, or the like is selectively deposited by plating or vapor deposition on the exposed connection electrode 112 region to form the first barrier metal film 114, and the connection electrode 112 is formed. Prevent failures due to corrosion. After the formation of the first barrier metal film 114, the second bump electrode 100 serving as the second connection means is formed.

  The second bump electrode 100 is formed in the same manner as the first bump electrode 90. That is, the second bump electrode 100 is formed on the first barrier metal film 114 formed on each wiring pattern 81 at a height of about 30 to 50 μm. The second bump electrode 100 is also formed by a gold plating process. On the bump electrode surface, chromium, copper, titanium, or the like is selectively attached by plating or vapor deposition to form a second barrier metal film 101 of several thousand angstroms. Form.

  Further, a bonding metal is vapor-deposited on the second barrier metal 101 so as to be electrically bonded to the first bump electrode 90 formed on the external connection electrode region 70x described above. 102 is formed. Similar to the bonding layer 92 formed on the first bump electrode 90, the metal material used for the bonding layer 102 has a melting point lower than the melting point of the second bump electrode 102 formed of gold (Au). A material having a melting point higher than that of a solder material used when mounting on a mounting substrate described later is used. Specifically, when the melting point of gold (Au) is normally about 1064 degrees and the melting point of the solder material used for mounting on the mounting substrate is about 170 to 190 degrees, it is used for the bonding layer 102. Any material can be used as long as it has a melting point within the temperature range of the two. For example, gold (Au) and tin (Sn) are alternately deposited and laminated, and the melting point is about 370 degrees. AuSn) is used.

  The above-described bonding layer 102 is formed so as to spread outward from the center portion of the second barrier metal 101, but is formed separately on the second barrier metal 101 as shown in FIGS. May be. Further, similar to FIG. 6B, a cross shape may be used.

  As will be described later, the bumps supporting the external connection electrodes are supported at a plurality of points as shown in FIG. Moreover, it has the merit which can prevent the rotation at the time of melting of solder.

  Next, as shown in FIG. 10, the bump electrodes 90 and 100 formed on the first and second substrates 70 a and 110 are bonded together, and a resin layer 120 is formed between the substrates 70 a and 110. A plurality of bump electrodes 90 and 100 formed on both substrates 70 and 110 are brought into contact with each other, and bonding layers 92 and 102 formed on the bump electrodes 90 and 100 are melted to form gold bumps as shown in FIG. The bonding is performed by the bonding layers 92 and 102 without using the bump electrodes 90 and 100 as the bonding material. Specifically, the outer edge of the wiring pattern 81 formed radially on the first bump electrode 90 and the second semiconductor substrate 110 formed in the external connection electrode region 70x of the first semiconductor substrate 70a. The second bump electrode 100 formed on the substrate is joined, and a resin layer 120 is formed by filling a resin between both substrates.

  For example, the bump electrodes 90 and 100 formed on both the substrates 70a and 110 are aligned and placed in a heated atmosphere, and only the bonding layers 92 and 102 formed on the bump electrodes 90 and 100 are melted to perform electrical bonding. Do. As described above, since the second barrier metal films 91 and 101 are interposed between the bonding layers 92 and 102 and the bump electrodes 90 and 100, the molten metal material of the bonding layers 92 and 102. And the gold (Au) of the bump electrodes 90 and 100 are not eutectic. What is important here is that the bump electrodes 90 and 100 remain in the composition state immediately after plating, and the external connection of the first substrate 70 is performed by the bonding layers 92 and 102 formed on both the barrier metals 91 and 101. The electrical connection between the electrode region 70a and the wiring pattern 81 of the second substrate 110 is performed.

  By the way, when the bonding layers 92 and 102 formed on the bump electrodes 90 and 100 are formed as shown in FIG. 5, as shown in FIG. Book).

  The bonding layers 92 and 102 formed on the bump electrodes 90 and 100 are melted and electrically bonded to bond (bond) the first substrate 70a and the second substrate 110, and then both the substrates 70a and 110 are bonded. While applying a predetermined pressure, an impregnating material made of a liquid epoxy-based thermosetting resin is poured between the substrates 70a and 110, and heat treatment is performed. The impregnating material is cured, and the above-described resin layer 120 is formed. Then, both substrates 70 and 110 are temporarily fixed.

  At this time, if the heights of the bump electrodes 90 and 100 formed on both the substrates 70a and 110 are too low, the distance between the substrates 70a and 110, that is, the film thickness of the resin layer 120 becomes thin. When formed, the tip end portion of the slit hole may reach the surface of the second substrate 110, and the wiring pattern 81 may be cut, and it is necessary to maintain a sufficient distance between the substrates 70a and 110. For this reason, it is necessary to adjust the height of each bump electrode 90,100.

  Next, as shown in FIGS. 13 and 14, the external connection electrode regions 70x of the first substrate 70a are individually electrically separated from the opposite main surface (back) side of the first substrate 70a. The first substrate 70a is cut to form a plurality of slit holes 130 in a lattice shape. The slit hole 130 is formed by using a dicing blade by a dicing apparatus.

  The reason why the slit hole 130 is formed by using the dicing apparatus is that the width and depth of dicing can be controlled with high accuracy, and that the existing equipment is not required to be newly purchased. The dicing width is set according to the width of the dicing blade, and the dicing depth varies depending on the manufacturer of the dicing machine. However, the current technology has an accuracy error of about 2 μm to 5 μm, and cuts the wiring pattern 81 on the second substrate 110 Without this, it is possible to reliably cut only the first substrate 70a and to electrically isolate the external connection electrode region 70x reliably and accurately.

  Below, the process of forming the slit hole 130 will be described.

  As shown in FIG. 15, it arrange | positions and hold | maintains so that the 1st board | substrate 70a may be on the table 151 of a dicing apparatus. Thereafter, as shown in FIG. 16, the infrared light emitted from the infrared lamp device 154 and transmitted to the inside of the first substrate 70a is irradiated to the surface of the first substrate 70a, and the reflected light is detected by a detection device 153 such as an infrared monitor. Detecting and aligning the position of the slit hole forming region, as shown in FIG. 17, a dicing blade 155 forms a grid-like slit hole 130 as shown in FIG. If a dicing apparatus with an infrared detection function is used, it is possible to form the slit hole 130 that accurately cuts only the first substrate 70a even from the back side of the first substrate 70a. In a dicing apparatus having no infrared detection function, it is difficult to accurately form the slit hole 130 because alignment cannot be performed accurately. The dicing width of the slit hole 130 formed in this step is, for example, about 0.1 mm because it is necessary to maintain sufficient insulation between the adjacent external connection electrodes 70 after separation.

  As described above, the depth of the dicing (slit hole 130) is required to cut the first substrate 70a reliably in order to electrically separate the external connection electrode regions 70x. About 2 μm to 5 μm.

  As described above, the plurality of external connection electrode regions 70x formed on the first substrate 70a are electrically separated from each other by the lattice-shaped slit holes 130 formed from the back surface side of the first substrate 70a, It becomes the electrode 70 for external connection of each semiconductor device.

  In this embodiment, before forming the slit hole 130, the first substrate 70a is diced with a trapezoidal dicing blade to a predetermined depth on the region to be the slit hole 130 using the above-described dicing apparatus ( The surface of the first substrate 70a is shaved). In this dicing process, a tapered portion is formed at the edge portion of each external connection electrode 70. The angle of the tapered portion is determined by the shape of the dicing blade, but is arbitrarily set depending on the size of the solder joint portion and the amount of solder.

  After removing a part of the first substrate 70a and forming a tapered portion at the edge portion of each external connection electrode 70, a plated layer of a metal such as solder is formed on the surface of the first substrate 70a. The plating layer is formed on the entire surface of the first substrate 70a using a plating process such as electroplating or electroless plating. After forming the plating layer, the slit hole 130 is formed as shown in FIG.

  As described above, a high-concentration diffusion layer is formed in the external connection electrode region 70x of the first semiconductor substrate 70a to reduce loss due to wiring resistance.

  Next, as shown in FIGS. 18 and 19, at least the first semiconductor substrate 70 a in the region surrounded by the external connection electrode 70 is removed to form a storage space 140 for storing the semiconductor chip 60. As described above, the external connection electrode 70 formed from the first semiconductor substrate 70 a is electrically bonded to the wiring pattern 81 on the second semiconductor substrate 110 via the first and second bump electrodes 90 and 100. Has been made. On the other hand, since the first semiconductor substrate 70a other than the external connection electrode 70 is only temporarily fixed to the second semiconductor substrate 110 by the resin layer 120, the resin layer 120 is removed by etching. As shown in FIG. 19, the other first substrate 70 a is removed leaving only the external connection electrodes 70 fixed by the bonding layers 92, 102 on the bump electrodes 90, 100. As a result, the storage space 140 for storing the semiconductor chip 60 of a predetermined size can be formed in the region surrounded by the external connection electrodes 70.

  Next, as shown in FIG. 20, the semiconductor chip 60 is accommodated in the accommodation space 140, and the semiconductor chip 60 and another second bump electrode 100 formed on the wiring pattern 81 on the second semiconductor substrate 110. The electrical connection is performed.

  For example, as shown in FIG. 20, the semiconductor chip 60 forms a photomask having a predetermined shape on a P-type semiconductor substrate 61 and diffuses N-type high-concentration impurities such as antimony to form an island-like N + -type buried layer. A collector region 62 is formed, and an N − type epitaxial layer 63 is formed on the substrate 61 by an epitaxial growth technique.

  Here, an epitaxial layer is employed because a bipolar element is taken up as a semiconductor chip. However, some MOSs employ an epitaxial layer and others do not employ an epitaxial layer. Therefore, it is not essential for the present invention to employ an epitaxial layer.

  An isolation diffusion region 64 is formed by diffusing P + type impurities such as boron in the isolation diffusion region of the epitaxial layer 63. By this isolation diffusion region 64, the N-type region which becomes the active region of the transistor is surrounded by the P-type isolation diffusion region. An island-like base region 65 having a predetermined depth is formed by selectively diffusing P-type impurities such as boron (B) in a predetermined region of the epitaxial layer 63.

  N-type impurities such as phosphorus (P) and antimony (Sb) are selectively thermally diffused in the base region 65 and the collector region, thereby forming an emitter region 66 and a collector contact diffusion region 67 of the transistor. .

  An insulating film 68 such as a silicon oxide film or a silicon nitride film having an emitter contact hole and a collector contact hole is formed on the surface of the semiconductor chip 60.

  In a region exposed by the base contact hole, the emitter contact hole, and the collector contact hole, a base electrode 65a, an emitter electrode 66a, and a collector electrode 67a selectively deposited with a metal material such as aluminum are formed.

  When aluminum is used for the base electrode 65a, the emitter electrode 66a, and the collector electrode 67a, a passivation film 69 made of an insulator such as a PSG film, SiN, or SiNx is formed on the substrate 61, and the base electrode 65a, the emitter electrode The passivation film 69 on the predetermined position of 66a, collector electrode 67a and / or other electrodes as required is selectively removed to expose the surfaces of the electrodes 65a, 66a, 67a. Further, chromium, copper, titanium, or the like is selectively plated or deposited in the exposed region to form a first barrier metal film to prevent problems due to corrosion of each electrode or the like.

  A bump electrode 150 is formed on each electrode of the semiconductor chip 60 as shown in FIGS. 4 and 5 described above. Here, since the description of the bump electrode 150 has already been described, the description thereof is omitted. When the back surface side of the semiconductor chip 60 is used as an electrode, the four sides on the back surface side of the semiconductor chip 60 are tapered to form such solder fillets.

After the semiconductor chip 60 is stored in each storage space 140 surrounded by the external connection electrodes 70, the semiconductor chip 60 is disposed in a heating atmosphere of about 370 degrees, and the second bump electrode formed on the second semiconductor substrate 110 is formed. The bonding layer 102 of 100 and the bonding layer (not shown) of the bump electrode 150 formed on the semiconductor chip 60 are bonded to perform electrical bonding.
Here, there is no need to explain, but the back surface of the accommodated semiconductor chip 60 is designed to be the same as or slightly lower than the surface of the external connection electrode 70.

  By the way, as described above, each external connection electrode 70 has already been formed separately and independently. Therefore, in this heat treatment step, the first bump electrode 90 of each external connection electrode 70 and the second semiconductor substrate are formed. The bonding layers 92 and 102 that are bonded to the second bump electrode 100 may be remelted and rotated as indicated by solid arrows in FIG. 20 to cause a problem that the external connection electrode 70 is displaced. . However, by forming the bonding layers 92 and 102 formed on the bump electrodes 90 and 100 as shown in FIGS. 5 and 6, for example, the external connection electrode 70 when the semiconductor chip 60 is fixed. It is possible to prevent slipping and to prevent a problem that causes a positional shift or the like.

  In addition, the structure of FIG. 4 is an unstable baby with a large head, and when the structure shown in FIG. 18 is used, a crack occurs immediately at the neck, but the structure shown in FIGS. Its strength can be increased.

  Next, as shown in FIG. 21, the external connection electrodes 70 formed from the first semiconductor substrate 70 a and the spaces formed between the semiconductor chip 60 and the second semiconductor substrate 110 and the slit holes 130. Again, an impregnation resin made of an epoxy resin is filled to form a resin layer 160, and each external connection electrode 70 and the semiconductor chip 60 are fixed. Then, dicing is performed at the above-described semiconductor device size region, that is, the substantially central portion of the slit hole 130 surrounding the external connection electrode 70 arranged in an annular shape, and divided into individual semiconductor devices as shown in FIG. In this dividing step, the second substrate 110 is arranged on the table of the dicing apparatus so that the second substrate 110 is on the lower side, and the slit holes 130 surrounding the semiconductor device size region 70y are aligned and dicing is performed to individually divide the substrate. To do.

  A part of the resin layer 160 can remain on the side surface of the divided semiconductor device, and leakage current from the external connection electrode 70 can be suppressed. Individually divided semiconductor devices are individually taped and wound into a reel after predetermined measurement and label printing.

  The semiconductor device manufactured by the manufacturing method described above is fixedly mounted on a pad of a conductive pattern formed on a wiring substrate such as a ceramic substrate, a glass epoxy substrate, a phenol substrate, or a metal substrate subjected to insulation treatment. A solder layer in which solder cream is pre-printed is formed on the pad, and the semiconductor device can be fixedly mounted on the pad of the wiring board by melting the solder and mounting the semiconductor device of the present invention. .

  At this time, as described above, the taper portion is formed at the edge portion of each external connection electrode 70, so that the solder fillet at the solder joint portion with the conductive pad (land) of the mounting substrate can be optimized. As a result, the bonding strength of the solder joint portion can be improved and the connection reliability can be improved. Although not shown in the drawing, this fixed mounting process can be performed in the same process as the mounting process of other circuit elements mounted by solder such as a chip capacitor and a chip resistor mounted on the mounting substrate.

  Furthermore, when the semiconductor device is mounted on the mounting substrate, the external connection electrodes 70 are separated by the interval of the slit holes 130, so that the solder that is fixed to the mounting substrate is adjacent to the external connection electrodes 70. There is no short circuit.

  The semiconductor device manufactured by the manufacturing method of the present invention can be formed in a size as shown in FIG. 22, for example. In the semiconductor device of this embodiment, the semiconductor chip 60 having substantially the same function as that of the semiconductor device described in the conventional example is 3.4 mm × 2.4 mm in size, and each external connection electrode 70 is 0.3 mm × 0.3 mm in size. In the semiconductor device in which the width of the slit hole 130 and the clearance between the semiconductor chip 60 and each external connection electrode 70 are 0.3 mm, the effective area ratio is as follows. That is, since the element area is 8.16 mm 2 and the area of the semiconductor device as the mounting area is 16.56 mm 2, the effective area ratio is about 49.3%.

  Since the effective area ratio of the semiconductor device having a chip size of 3.4 mm × 2.4 mm described in the conventional example is 27.2% as described above, the effective area ratio of the semiconductor device of the present invention is about 1. It is 81 times larger, the dead space of the mounting area to be mounted on the mounting board can be reduced, and it can contribute to the downsizing of the mounting board.

  In this embodiment, the semiconductor chip 60 made of a bipolar IC is housed in the housing space 140. However, the present invention is not limited to this, and a single semiconductor such as a MOS LSI, a vertical power MOSFET, an IGBT, or an HBT is used. Needless to say, the present invention can be applied to a device or a semiconductor device that combines them.

(2) Second Embodiment Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In addition, about the matter which is common in 1st Embodiment, description is abbreviate | omitted in order to avoid duplication.

  First, the semiconductor device of this embodiment will be described with reference to FIG.

  In the semiconductor device according to the first embodiment shown in FIG. 1, a semiconductor substrate in which high-concentration impurities are diffused to reduce resistance is used as the external connection electrode 70. However, in this embodiment, the external connection electrode is used. Only a metal plate, for example, a copper plate, is used as 270, and the structure and function are almost the same as those of the first embodiment, and thus detailed description thereof is omitted.

  According to the semiconductor device of this embodiment, since a copper plate is used as the external connection electrode 270, the resistance is much lower than that of a semiconductor substrate in which impurities are diffused to reduce resistance.

    Hereinafter, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

  First, as shown in FIG. 24, the first bump electrode 290 is formed on the upper surface of the copper plate 200 by the same process as described in the first embodiment.

  That is, an insulating film such as a silicon oxide film, a silicon nitride film, or an insulating resin is formed on the copper plate 200, a contact hole is formed in a region corresponding to the external connection electrode, and an external connection electrode exposed thereby is formed. A connection electrode 272 is formed by selectively depositing a metal material such as aluminum, a metal alloy, or the like on the region to be formed, or by other methods. A passivation film is formed on the connection electrode 272, a contact hole is formed, and the connection electrode 272 is exposed.

  Next, chromium, copper, titanium, or the like is selectively deposited by plating or vapor deposition to form the first barrier metal film 274 on the connection electrode 272 to prevent the connection electrode 272 from being corroded. Thereafter, a first bump electrode 290 serving as a first connection means is formed on the first barrier metal film 274.

  Thereafter, a barrier metal film (not shown) is formed on the first bump electrode 290, and a bonding layer (not shown) is formed on the barrier metal film. Note that the material, film thickness, film forming conditions, and the like formed in the above steps are the same as those in the first embodiment, and thus description thereof is omitted.

  Next, a second semiconductor substrate 110 that is formed in the process described in the first embodiment and becomes a wiring substrate as shown in FIG. 9 is prepared, and the first bump electrode 290 and the second semiconductor substrate 110 are prepared. The bump electrodes 100 are aligned so that they come into contact with each other, and these are connected. After the connection, a resin 160 is sealed in a space formed between the second semiconductor substrate 110 and the copper plate 200 as shown in FIG. The details of the above steps are the same as the steps described in the first embodiment, and a description thereof will be omitted.

  Next, as shown in FIG. 26, the copper plate 200 other than the region where the external connection electrode is formed is cut out and removed by dicing to form a storage space 140 for storing the semiconductor chip, and the copper plate 200 is formed from the copper plate. An external connection electrode 270 is formed. Since the details of this process are the same as those in the first embodiment, description thereof will be omitted.

  Next, as shown in FIG. 27, the semiconductor chip 60 described in the first embodiment is stored in the storage space 140 after being aligned. The details of this step are the same as those in the first embodiment.

  Next, as shown in FIG. 28, after the bump electrode 150 which is the connection electrode of the semiconductor chip 60 and the second bump electrode 100 provided on the second semiconductor substrate 110 are electrically connected and fixed. The resin 160 is sealed in a space formed between the semiconductor chip 60 and the second semiconductor substrate 110.

  Thereafter, each semiconductor device size region is cut out by dicing or the like to complete the semiconductor device according to the present embodiment as shown in FIG.

  As described above, when using a metal material such as a copper plate to reduce the resistance of the external connection electrode, in addition to the above manufacturing method, a fine copper plate matching the size of the external connection electrode is first used. In this method, it is necessary to align and connect the fine copper plate to the semiconductor substrate in the corresponding region.

  For example, if 10 external connection electrodes are required for one semiconductor device, it is necessary to align and connect the fine copper plate 10 times, and it takes a lot of time for alignment and connection, so work efficiency is increased. Decreases, leading to a decrease in yield.

  However, in the manufacturing method of the present embodiment, the copper plate 200 that will be the material of the external connection electrode is aligned with the second semiconductor substrate 110 that will be the wiring substrate, and the first bump electrode 290 and the second bump are later aligned. After the electrode 100 is connected and fixed, the copper plate 200 in an unnecessary region is cut out and removed, and the removed space is used as a semiconductor chip storage space 140. Therefore, an external connection electrode is provided for one semiconductor device. No matter how many, there is only one electrode alignment step.

  Therefore, since it is not necessary to align and affix a fine copper plate one by one, the burden required for the alignment can be greatly reduced as compared with the above method, which contributes to an improvement in yield.

  Moreover, when employ | adopting the copper plate 200, it can form also with the following method.

  First, as shown in FIG. 35, a copper plate 200 is prepared, and nickel 300 and Au 301 are laminated on the entire surface. This is formed of two layers, but any number of layers may be used, and the uppermost layer is a material that can be bonded to the bonding layer 92 (see FIG. 4) used in the bump electrode 100 shown in FIG. A material having good adhesiveness with copper is selected, and various layers are sequentially selected in order to prevent film peeling and the like between the layers.

  Subsequently, the second semiconductor substrate 110 on which the solder bumps 100 are formed is formed in the same manner as described in FIG. Reference numeral 120 denotes a resin layer, which is used for the purpose of temporary fixing when the copper plate is diced thereafter. Further, if the bump electrodes 100 and 100A have the same size, the bump of 100A is also fixed at the same time, and the subsequent copper plate cannot be penetrated, so that the size of 100A is made small.

  However, if it is desired to form 100 and 100A in the same size, the cutout portion shown in FIG. 37 may be pressed to form a recess, and the bump 100A may be formed with a height lower than 100.

  Subsequently, as shown in FIG. 37, a storage space 140 in which the semiconductor chip 60 can be grounded is formed by dicing from the back surface of the copper plate, the semiconductor chip is stored as shown by arrows, and 100A and 150 are connected. Here, the solder bumps 100A are formed small, but since the bumps 150 are formed on the semiconductor chip, the back surface of the substrate pops out conversely, but it is sufficient to make the copper plate thicker by this amount.

  The same applies to the formation of the recess, and the back surfaces of the copper plate and the semiconductor chip are made flush by adjusting the thicknesses of the semiconductor chip and the copper plate.

  As described above, the point of the present invention is that surface mounting is possible using the back surface of the semiconductor substrate and the back surface of the external connection electrode as electrodes.

  After this, since it is the same as the explanation of FIG. 21, the explanation is omitted.

  In the present invention, the external connection electrode was initially considered as a semiconductor substrate, but a Cu substrate was adopted because the resistance value may become a problem even if impurities are diffused.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. 1 is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the bump electrode of this invention. Sectional drawing which shows the bump electrode of this invention. The top view which shows the bump electrode of this invention. The cross section and top view which show the bump electrode of this invention. 1 is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the junction part of a bump electrode. Sectional drawing which shows the junction part of a bump electrode. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 1 is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 1 is a plan view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which shows the back surface of the semiconductor device of this invention. Sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the conventional semiconductor device. Sectional drawing which shows the state which mounted the conventional semiconductor device on the wiring board. The top view which shows the conventional semiconductor device. The top view which shows the conventional semiconductor device. Sectional drawing explaining the conventional semiconductor device. Sectional drawing explaining the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention.

Claims (6)

A semiconductor substrate made of silicon to be a wiring substrate, an insulating layer formed on the surface of the semiconductor substrate made of silicon, a plurality of wirings provided on the insulating layer, and electrically connected to the plurality of wirings In a semiconductor device having a semiconductor chip provided on the semiconductor substrate made of silicon,
The semiconductor device, wherein the plurality of wirings are provided at least between the semiconductor substrate and the semiconductor chip and are formed in a radial pattern. A semiconductor substrate made of silicon to be a wiring substrate, a first insulating layer formed on the semiconductor substrate made of silicon, a plurality of radial wires provided on the first insulating layer, and the radial wires A second insulating layer provided excluding a contact hole region of the wiring; and a semiconductor IC chip provided on the semiconductor substrate made of silicon and electrically connected to the radial wiring through the contact hole. A semiconductor device characterized by that. The semiconductor device according to claim 2, wherein the semiconductor IC chip is a bipolar IC or a MOS LSI. The semiconductor device according to claim 2, wherein the semiconductor IC chip is provided face down with respect to the semiconductor substrate. A semiconductor substrate made of silicon to be a wiring substrate, a first insulating layer formed on the semiconductor substrate made of silicon, a plurality of radial wires provided on the first insulating layer, and the radial wires A second insulating layer provided except for a contact hole region of the wiring, and a semiconductor IC chip provided on the semiconductor substrate made of silicon and electrically connected to the radial wiring through the contact hole. A semiconductor device;
A semiconductor module comprising a ceramic substrate, a glass epoxy substrate, a phenol substrate, or a mounting substrate made of a metal substrate subjected to insulation treatment, on which the semiconductor device is mounted. 6. The semiconductor module according to claim 5, wherein the semiconductor IC chip is a bipolar IC or a MOS LSI.