JP2006049948A - Data transfer control device, electronic device, and data transfer control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer control device, an electronic device, and a data transfer control method for realizing reliable time management of transfer data, reducing the processing load accompanying data transfer and reducing the cost.
A data transfer control device includes a cycle timer that counts a cycle time that is updated every transfer cycle, and a transfer controller that controls transfer of packet data. When the transfer controller 140 outputs the packet data to which the time stamp information is not added to the transfer destination when it is input to the data transfer control device 100, the cycle that precedes the current cycle time of the cycle timer 150 by the offset value. Output time stamp information corresponding to the time is added to the packet data.
[Selection] FIG.

Description

  The present invention relates to a data transfer control device, an electronic device, and a data transfer control method.

  In recent years, digital broadcasting such as BS digital broadcasting that distributes MPEG (Moving Picture Experts Group, more specifically MPEG2) streams has attracted attention, and electronic devices such as digital broadcast tuners and digital broadcast content recording / playback devices have become popular. The spread is remarkable. The digital broadcast tuner and the recording / reproducing apparatus are connected via a general-purpose high-speed serial interface represented by, for example, IEEE (Institute of Electrical and Electronics Engineers) 1394.

  In IEEE 1394, isochronous transfer (synchronous transfer in a broad sense) realized by packetizing the above-described stream is performed. Isochronous transfer is always performed within approximately 125 μs (microseconds), and is preferentially performed over asynchronous transfer (asynchronous transfer in a broad sense), and is therefore suitable for real-time data transfer. .

  When transmitting and receiving such a stream, it is necessary to maintain time consistency between the transmission side and the reception side. For this reason, time management is performed by adding time stamp information to packetized data. Therefore, it is necessary to secure a transfer rate above a certain level for isochronous transfer while performing this time management.

  However, the transfer rate cannot be unconditionally increased due to the limitation of the capacity of the buffer memory of the receiving apparatus. Therefore, the transmission side apparatus controls data transfer by software so as to transfer several packets for each transfer cycle called an isochronous cycle while referring to time stamp information included in the data.

Such control of data transfer is disclosed in, for example, Patent Document 1. In Patent Document 1, time stamp information generated by adding a transmission delay value and a transmission delay value to the arrival time of packet data is added to the packet data, and the packet data is output after being delayed by the transmission delay value. Technology is disclosed.
JP 2002-84288 A

  However, if processing for determining packet data to be transferred with reference to time stamp information within an isochronous cycle is performed by software, the processing load is heavy. Therefore, the processing capability of the central processing unit (CPU) that controls the control cannot be assigned to other advanced processing. For this reason, a high-performance CPU and other additional circuits are used to maintain the processing capability of the entire system, resulting in high costs. In particular, as described in Cited Document 1, when packet data added with output time stamp information is buffered when a stream arrives, time management of packet data to be transmitted may not be accurately controlled. For example, an unexpected delay may occur when adding time stamp information, or an extra delay time must be set in consideration of this type of delay.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to realize reliable time management of transfer data, reduce processing load associated with data transfer, and reduce costs. An object of the present invention is to provide a data transfer control device, an electronic device, and a data transfer control method for achieving the above-mentioned.

  In order to solve the above problems, the present invention provides a data transfer control device for controlling data transfer, a cycle timer for counting a cycle time updated for each transfer cycle, and a transfer for controlling transfer of packet data. A controller, and when the transfer controller is input to the data transfer control device, when the packet data to which time stamp information is not added is output to the transfer destination, an offset is made based on the current cycle time of the cycle timer. The present invention relates to a data transfer control device that adds output time stamp information corresponding to the cycle time preceding the value to the packet data.

  According to the present invention, when outputting packet data to the transfer destination, output time stamp information is added to the packet data, so that the packet data is transferred at a timing suitable for buffering on the transfer destination side. It can be sent out. For example, when the playback time is specified by the time stamp information, after the cycle time specified as the playback time has passed on the transfer destination side, for example, depending on the transfer status of another node, for example, due to buffering once A situation in which packet data is transmitted can be avoided. For this reason, the margin of the time stamp information added to the packet data can be reduced, and the processing load can be reduced. Accordingly, the time management of the packet data to be transmitted can be accurately controlled with a simple configuration.

  In the data transfer control device according to the present invention, input time stamp information corresponding to a cycle time of the cycle timer when the packet data is input to the data transfer control device is added to the packet data, and the transfer controller The first time stamp information corresponding to the cycle time preceded by the offset value based on the cycle time added as the input time stamp information is used as the output time stamp information, and the packet data is sent to the transfer destination. When outputting, it can be set instead of the input time stamp information.

  In the data transfer control device according to the present invention, the transfer controller adds a second time stamp to be added in a current transfer cycle based on the first time stamp information and a current cycle time of the cycle timer. Information is obtained, and the second time stamp information can be set as the output time stamp information in place of the input time stamp information.

  According to the present invention, time stamp information can be set more accurately than in the case of adding time stamp information preceded by an offset value based on the current cycle time. Therefore, finer time management can be realized.

  In the data transfer control device according to the present invention, the transfer controller creates header information to be added to packet data based on a remaining amount of data in a packet memory in which packet data to which the input time stamp information is added is stored. Generating the output packet data that combines the header information generated by the header generation circuit and the packet data stored in the packet memory, and outputs the output packet data to the transfer destination And the packet generation circuit can set the output time stamp information instead of the input time stamp information.

  In the data transfer control device according to the present invention, when the transfer controller has less than one packet of data remaining in the packet memory in which the packet data to which the input time stamp information is added is stored in the current transfer cycle. An empty packet can be output to the transfer destination.

  Further, the data transfer control device according to the present invention includes the packet memory, and the packet memory is created by the data area in which the packet data to which the input time stamp information is added is stored, and the header creation circuit. A header area in which header information is stored, and the packet generation circuit sets the output timestamp information instead of the input timestamp information included in the packet data from the data area, and the packet data The header information from the header area can be combined.

  In the data transfer control device according to the present invention, the header creation circuit reads basic information of the header stored in the header area, generates the header information using the basic information, and writes the header information in the header area. Can be returned.

  According to the present invention, it is possible to reduce the load of packet data generation processing and header addition processing.

  The data transfer control device according to the present invention includes a transfer mode setting register for switching between the first and second modes, and when the transfer controller is switched to the first mode by the transfer mode setting register, the transfer controller Generating the output time stamp information corresponding to the cycle time preceding the offset value on the basis of the current cycle time of the cycle timer, and generating the packet data set when the packet data is output to the transfer destination. When the transfer mode setting register switches to the second mode, the transfer controller stores the time stamp information and the comparison value included in the packet data accumulated in the packet memory and added with the input time stamp information. Time stamps that match the comparison value For the packet data group including information, in place of the input time stamp information, output time stamp information corresponding to the cycle time preceding the offset value based on the current cycle time of the cycle timer is set, Output packet data to the destination in the current transfer cycle, update the comparison value when time stamp information that does not match the comparison value is detected, and at the next cycle time of the current cycle time, The updated comparison value can be compared with the time stamp information included in the data stored in the packet memory.

  According to the present invention, even when time stamp information is already added to packet data, transmission can be performed at a timing suitable for buffering on the transfer destination side. Even in this case, for example, when the playback time is specified by the time stamp information, it is specified as the playback time on the transfer destination side, for example, depending on the transfer status of other nodes, for reasons such as buffering once. It is possible to avoid a situation in which packet data is transmitted after the cycle time passed. For this reason, the margin of the time stamp information added to the packet data can be reduced, and the processing load can be reduced. Accordingly, the time management of the packet data to be transmitted can be accurately controlled with a simple configuration.

  In the data transfer control device according to the present invention, when the mode is switched to the second mode, the transfer controller compares the comparison value with the time stamp information included in the packet data and matches the comparison value. When packet data including time stamp information to be detected is not detected, an empty packet can be output to the transfer destination.

  In the data transfer control device according to the present invention, when the transfer controller is switched to the second mode, the transfer controller reads the time stamp information included in the packet data, and sets the time stamp information that matches the comparison value. Generating header information for the data group including the data, and performing update processing of the comparison value on condition that packet data including time stamp information that does not match the comparison value is detected, and time stamp information of the packet data Instead, the packet data can be generated by setting output time stamp information corresponding to the cycle time preceding the offset value based on the current cycle time of the cycle timer, and output to the transfer destination .

  In the data transfer control device according to the present invention, data transfer conforming to the IEEE 1394 standard can be performed.

  The present invention also includes a receiving circuit that receives packet data, and the data transfer control device according to any one of the above that is provided between the receiving circuit and a bus through which packet data is transmitted. An apparatus relates to an electronic device that transfers the packet data to a recording medium connected via the bus.

  ADVANTAGE OF THE INVENTION According to this invention, the electronic device which can implement | achieve accurate time management of the packet data received by the receiving circuit with a small processing load can be provided.

  Further, the present invention includes any one of the data transfer control devices described above and a recording medium connected to a bus via the data transfer control device, and the data transfer control device is input via the bus. The present invention relates to an electronic device that outputs the recorded data to the recording medium and records the data on the recording medium, or outputs the data read from the recording medium via the bus.

  ADVANTAGE OF THE INVENTION According to this invention, the electronic device which can implement | achieve accurate time management of the packet data of the packet data for recording on the recording medium or the packet data for reproducing | regenerating from a recording medium with a small processing load can be provided.

  The present invention also provides a data transfer control method for controlling data transfer, which counts the cycle time updated for each transfer cycle, and transfers packet data to which no time stamp information is added when it is input. This is related to a data transfer control method in which output time stamp information corresponding to a cycle time preceded by an offset value based on the current cycle time is added to the packet data and output to the transfer destination.

  In the data transfer control method according to the present invention, input time stamp information corresponding to a cycle time when the packet data is input is added to the packet data, and the cycle time added as the input time stamp information is used as a reference. The first time stamp information corresponding to the cycle time preceding the offset value is used as the output time stamp information, and the packet data is output to the transfer destination when the packet data is output to the transfer destination instead of the input time stamp information. Can be set.

  In the data transfer control method according to the present invention, second time stamp information to be added at the current cycle time is obtained based on the first time stamp information and the current cycle time, and the second time is determined. Stamp information can be set as the output time stamp information in place of the input time stamp information.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Packet Data FIG. 1 shows a configuration example of a system to which the data transfer control device of this embodiment is applied.

  This system includes an antenna 10, a digital broadcast tuner 20, and a recording / playback device 30. The antenna 10 receives an MPEG2 stream distributed as BS digital broadcast. The digital broadcast tuner 20 includes a data transfer control device 22, and from an MPEG2TS multi-stream in which TS (Transport Stream) packets for a plurality of channels received by the antenna 10 are continuous, an MPEG2TS in which TS packets for one channel are continuous. Extract a partial stream. Then, the data transfer control device 22 transfers the TS packet of the extracted stream to the recording / reproducing device 30 connected via the IEEE 1394 bus. The recording / reproducing apparatus 30 includes a recording medium 32 and records TS packets transferred via the IEEE 1394 bus on the recording medium 32. The recording / reproducing apparatus 30 can also read and reproduce the TS packet recorded on the recording medium 32.

  FIG. 2 is an explanatory diagram of a data structure in the BS digital broadcast, the data transfer control device, and the IEEE 1394 bus.

  In BS digital broadcasting, MPEG2 TS packets are distributed. The TS packet is 188-byte fixed-length packet data. This TS packet includes I picture (intra-frame encoded data in a broad sense), B picture and P picture (inter-frame encoded data or predictive encoded data in a broad sense), audio data (audio data, non-video data). Data) and the like are multiplexed into one bit stream and packetized (packet multiplexing). This TS packet is composed of a TS header (TSH) and a TS payload.

  The data transfer control device 22 adds a 4-byte SP (Source Packet) header (SPH) to the TS packet received by the antenna 10, and then creates an isochronous packet (ISO packet) constructed using the SP header and the TS packet. Output to the IEEE 1394 bus. The ISO packet can include one or a plurality of sets of SP header and TS packet, with the SP header and TS packet as one set. An 8-byte isochronous header (ISOH) and an 8-byte CIP (Common Isochronous Packet) header (CIPH) are added to each ISO packet. A CIP header and one or a plurality of sets of SP headers and TS packets can be referred to as a 1394 payload. One or a plurality of sets of SP headers and TS packets can be referred to as SP (Source Packet).

  In the case of a null packet as an empty packet, only the ISO header and the CIP header are included. That is, the Null packet has only the ISO header and the CIP header without including the SP.

  FIG. 3 shows an example of the format of the TS packet.

  A TS packet is composed of a TS header and a TS payload. The TS header includes a sync byte, a transport error indicator, a payload unit start indicator (PUSI), a transport priority, a PID (Packet identification), and a transport. It has scramble control (transport scrambling control), adaptation field control (adaptation field control), continuity counter (continuity counter), adaptation field (adaptation field), etc.

  By using the PID included in the TS header, about 8000 types of TS packets can be identified. For example, as shown in FIG. 4, a PES (Packetized Elementary Stream) configured in an MPEG stream is divided into TS packets having the same PID. This PES is divided into TS packets having the same PID. On the receiving side, the original PES can be restored by connecting the payload portions of TS packets having the same PID.

  Note that the PES is divided and transferred in the payload portion of the TS packet with the same PID, but the head of the PES is arranged to start from the head of the TS payload. The TS payload in which the head of the PES is arranged is identified by a payload part start indicator (PUSI).

  5A to 5D show an example of the format of the ISO packet and the SP header, CIP header, and ISO header included in the ISO packet.

  FIG. 5A shows a configuration example of an ISO packet output to the IEEE 1394 bus by isochronous transfer. FIG. 5B shows an example of the format of the SP header. FIG. 5C shows an example of the format of the CIP header. FIG. 5D shows an example of the format of the ISO header.

  The SP header and CIP header shown in FIGS. 5B and 5C are defined by the IEC (International Electrotechnical Commission) 61883 standard that defines a protocol for transferring an MPEG2 stream on the IEEE 1394 bus. The SP header includes a cycle count of isochronous transfer as time stamp information. The cycle count is a count value of cycle time. The SP header includes a cycle offset. The cycle offset is a count value for counting up the cycle count. The SP header cycle count may be treated as time stamp information, or the SP header cycle count and cycle offset may be treated as time stamp information. In the following description, for convenience of explanation, it is assumed that the time stamp information indicates the cycle count of the SP header.

  The CIP header shown in FIG. 5C declares that the data to be transferred is MPEG data, and specifies a method for dividing an MPEG TS packet. Source node ID (SID), data block size (DBS), format ID (FMT), etc.

  The ISO header shown in FIG. 5D includes a data length (Data_length) indicating a data length, an isochronous data format tag (tag), an isochronous channel number (Channel) acquired from an isochronous resource manager, a transaction code (tcode), and a synchronization code. (Sy) includes a header CRC (Header_CRC). In the case of a null packet, the data length of the CIP header is set in the data length.

  In IEEE 1394, a bus reset is performed when the connection state of a port changes due to power-on or device insertion / removal. When a bus reset is performed, tree identification is performed, and a parent-child relationship between nodes and a root node are determined. Thereafter, self-identification is performed, and the address of each node is automatically assigned by transmitting and receiving self-ID packets.

  When the node connection state can be managed in this way, the management node selected as the isochronous resource manager among all the nodes provides the necessary resources to the node that performs isochronous transfer, and allocates a band for isochronous transfer. Furthermore, the node selected as the cycle master among all the nodes transmits a cycle start packet every 125 microseconds on average. A node performing isochronous transfer starts an isochronous cycle (ISO cycle) (transfer cycle in a broad sense) based on a cycle start packet from the cycle master.

  FIG. 6 is an explanatory diagram of isochronous transfer.

  The node that performs isochronous transfer starts the ISO cycle based on the cycle start packets 50, 52, and 54 from the cycle master. In principle, the cycle master transmits a cycle start packet every 125 microseconds. Each time the node performing isochronous transfer receives a cycle start packet, it increments the cycle count of the SP header of FIG. Therefore, the cycle count is updated every ISO cycle. The cycle count is sequentially incremented from 0, and when it becomes 1F3Fh in hexadecimal notation (the last “h” indicates that it is hexadecimal notation, the same applies hereinafter), it returns to 0 again. That is, the cycle count is from 0h to 1F3Fh (from decimal 0 to 7999). Thereby, it is possible to measure 1 second (= 125 microseconds × 8000) by a cycle count updated every 125 microseconds. The count value in seconds can be managed by holding it by software or firmware. The cycle offset is a count value for counting 125 microseconds, and the cycle count is incremented when an overflow of the incremented cycle offset occurs.

  After receiving a cycle start packet, a node that performs isochronous transfer starts arbitration after a bus idle time called an isochronous gap has elapsed and transmits an ISO packet. In FIG. 6, in the ISO cycle started by receiving the cycle start packet 50, the node A transfers the ISO packet ISOA and the node B transfers the ISO packet ISOB. In the ISO cycle started by receiving the next cycle start packet 52, the node A transfers the ISO packet ISOA and the node B transfers the ISO packet ISOB. The asynchronous packet is transferred after the ISO packet is transferred in the ISO cycle. This is because the priority of each transfer can be made different by setting the bus idle time before the start of arbitration of asynchronous transfer called a subaction gap to be longer than the isochronous gap.

  Thus, the ISO packet transferred by isochronous transfer and the cycle count of the SP header have the following relationship.

  FIG. 7 is an explanatory diagram showing the relationship between the ISO packet and the SP header cycle count.

  In isochronous transfer, ISO packet transfer is performed. Usually, an ISO packet includes one or more TS packets as described above. In FIG. 7, it is assumed that Null packets are not transferred, and for simplification, the ISO header and the CIP header are omitted, and only the SP header of the TS packet is shown.

  The cycle time corresponding to the ISO cycle is specified by the cycle count. Since the cycle count is incremented every time a cycle start packet is received from the cycle master, the cycle time is similarly incremented every time a cycle start packet is received. A node that performs isochronous transfer transmits an ISO packet including a TS packet in which a cycle time (cycle count) that designates a reproduction time on the reception side is set in the SP header. In FIG. 7, when the cycle time is 1000, an ISO packet including two TS packets in which 1003 is set as the cycle count in the SP header is transmitted. In other words, the current cycle time is transmitted with an offset of +3. Thus, on the receiving side, when the cycle time reaches 1003, the received TS packet is input to the decode, decompressed, and reproduced. As described above, the TS packet stored in the buffer memory on the receiving side is transmitted by designating the preceding cycle time.

  However, the transfer rate cannot be unconditionally increased due to the limitation of the capacity of the buffer memory on the receiving side. Therefore, it is necessary to control the data transfer so that several packets are transferred every ISO cycle while referring to the SP header on the transmission side. However, if the processing for discriminating a packet to be transferred within the ISO cycle with reference to the SP header is performed by software, the processing load becomes heavy. In addition, when a packet is transmitted after buffering once on the transmission side, if an SP header is added when the packet arrives, time management of the packet to be transmitted may not be accurately controlled. For example, depending on the transfer status from another node, if a packet is transmitted after the cycle time (eg, 1003) designated as the playback time on the receiving side has passed, the cycle time reaches 7999 and becomes 1003 again. It will not be possible to play until. In order to avoid such a situation, it is necessary to specify a time with a margin added, and fine time management becomes impossible.

  Therefore, in the present embodiment, by adopting the following configuration, it is possible to realize the reliable time management of the packets into which the stream is divided, and to reduce the processing load accompanying the data transfer and reduce the cost.

2. Data Transfer Control Device FIG. 8 shows a block diagram of a configuration example of the data transfer control device in this embodiment.

  Note that the data transfer control device of this embodiment does not have to include all the circuits and units (units) in FIG. 8, and may be configured to omit some of them.

  The data transfer control device 100 in this embodiment includes a stream interface (InterFace: I / F) circuit 110, an IDE (Integrated Drive Electronics) I / F circuit (I / F for recording medium in a broad sense) 120, an SDRAM (Synchronous Dynamic). Random Access Memory) I / F circuit (DRAM I / F in a broad sense) 130 can be included.

  The stream I / F circuit 110 is a circuit that realizes an interface between the MPEG2 stream receiving device (antenna, demodulator) or decoder and the data transfer control device 100. The receiving device or decoder is provided outside the data transfer control device 100. The receiving apparatus supplies the data transfer control apparatus 100 with a stream that is received and demodulated as an MPEG2 stream distributed as a digital broadcast. The decoder decodes the MPEG2 stream output from the data transfer control device 100 and supplies it to a display device (not shown) as image data for displaying an image corresponding to the decoding result. The stream I / F circuit 110 includes an SPH comparison output circuit 112, and based on the SP header included in the packet data as the time stamp information, the stream I / F circuit 110 performs timing so that the time interval between the packet data is as specified by the SP header. Packet data can be output to the decoder while adjusting. The IDE I / F circuit 120 is a circuit that realizes an interface between a data transfer control device 100 and a recording / reproducing device of a hard disk drive (HDD) or a DVD (Digital Versatile Disk) as a recording medium. The hard disk drive and DVD recording / reproducing device are provided outside the data transfer control device 100. The SDRAM I / F circuit 130 is a circuit that realizes an interface between the SDRAM and the data transfer control device 100, which is faster in sequential access than an SRAM (Static Random Access Memory). The SDRAM is provided outside the data transfer control device 100.

  The data transfer control device 100 in this embodiment includes a link controller (transfer controller in a broad sense) 140 and a cycle timer 150. The data transfer control device 100 is connected to the IEEE 1394 bus via, for example, a 1394 PHY chip. The 1394 PHY chip implements the IEEE 1394 physical layer protocol and is connected to the IEEE 1394 bus. In FIG. 8, the PHY I / F circuit (not shown) is included without including the 1394 PHY chip, but the data transfer control device 100 may include the 1394 PHY chip.

  In the data transfer control device 100, the cycle timer 150 counts a cycle time that is updated every ISO cycle (transfer cycle in a broad sense). More specifically, the cycle time is counted each time a cycle start packet sent by the selected cycle master is received after the bus reset. When the cycle timer 150 updates the cycle time, the cycle time may be incremented or the cycle time may be decremented. The SPH comparison output circuit 112 compares the cycle count included in the SP header with the cycle time of the cycle timer 150, and outputs packet data.

  In the recording medium, an inexpensive hard disk drive having IDE (ATA) I / F widely used for personal computers is used. On the other hand, IEEE1394 is widely used as an I / F of digital data (digital video data, digital audio data). As shown in FIG. 8, by providing the IDE I / F circuit 120 and the link controller 140, the data transfer control device 100 can realize the conversion bridge function of IEEE 1394 and IDE.

  In FIG. 8, the link controller 140 controls the transfer of packet data via the IEEE 1394 bus. The link controller 140 is a circuit for realizing an IEEE 1394 link layer or a link layer and a protocol higher than the link layer. The link controller 140 creates a header (ISO header, CIP header, SP header) and outputs a packet with the header added to the IEEE 1394 bus.

  The data transfer control device 100 can include an SRAM 160 as a packet memory. The SRAM 160 can be provided outside the data transfer control device 100. The SRAM 160 temporarily stores TS packets input via the stream I / F circuit 110, the IDE I / F circuit 120, or the SDRAM I / F circuit 130 for transfer via the IEEE 1394 bus. The SRAM 160 also has a function of temporarily storing packets received via the IEEE 1394 bus. The SRAM 160 is configured to be randomly accessible by firmware or the like.

  The data transfer control device 100 can include a pointer controller 170. The pointer controller 170 controls a write pointer for designating a write area of the SRAM 160 and a read pointer for designating a read area of the SRAM 160. An area for writing packet data to the SRAM 160 is designated by a write pointer that identifies the storage area of the SRAM 160. Each time packet data is written, the pointer controller 170 updates the write pointer (increment or decrement). The read area for packet data from the SRAM 160 is designated by a read pointer that identifies the storage area of the SRAM 160. Each time packet data is read, the pointer controller 170 updates the read pointer (by decrementing or incrementing).

  The data transfer control device 100 can further include a PID filter 180. The PID filter 180 extracts a partial stream having a predetermined PID from the multi-stream of MPEG2TS input via the stream I / F circuit 110, the IDE I / F circuit 120, or the SDRAM I / F circuit 130, and supplies the partial stream to the SRAM 160. .

  The data transfer control device 100 includes a processing unit 190. The processing unit 190 controls each circuit and each unit (unit) in the apparatus and controls the entire apparatus. The function of the processing unit 190 is realized by hardware such as a CPU or a system controller or firmware (program). The processing unit 190 may be provided outside the data transfer control device 100.

  In this embodiment, when the link controller 140 outputs a TS packet (packet data) to which no time stamp information is added to the bus (transfer destination) when it is input to the data transfer control device 100, the output time stamp information is set. It can be added to the TS packet. Therefore, the link controller 140 can include a header creation circuit 142 and a transmission control circuit (packet generation circuit in a broad sense) 144.

  The header creation circuit 142 creates a header to be added to the packet output to the IEEE 1394 bus. The header creation circuit 142 generates an ISO header, a CIP header, and an SP header. More specifically, the header generation circuit 142 outputs information obtained by rewriting only predetermined information with respect to basic information of a header generated in advance as a header (information).

  The transmission control circuit 144 generates an ISO packet to which the header created by the header creation circuit 122 is added, and performs control to output the ISO packet to the IEEE 1394 bus. Thus, the transmission control circuit 144 adds time stamp information (output time stamp information) to the TS packet when outputting to the IEEE 1394 bus (transfer destination in a broad sense) via the 1394 PHY chip.

  As described above, when the link controller 140 outputs the TS packet to which the time stamp information is not added to the IEEE 1394 bus (transfer destination in a broad sense) via the 1394 PHY chip when the data is input to the data transfer control device 100, Stamp information (output time stamp information) is added to the TS packet. This time stamp information is time stamp information corresponding to a cycle time that precedes the current cycle time of the cycle timer 150 by an offset value. For example, when the count direction of the cycle timer 150 is the increment direction, a value obtained by offsetting the current cycle time in the increment direction is set as the time stamp information. For example, when the count direction of the cycle timer 150 is the decrement direction, a value obtained by offsetting the current cycle time in the decrement direction is set as the time stamp information.

  In this way, for example, TS packets can be transmitted at a timing suitable for buffering on the decoder side. Furthermore, a situation in which a packet is transmitted after a cycle time designated as a reproduction time on the receiving side, for example, depending on the transfer status of another node, can be avoided because of buffering. At this time, it is not necessary to add extra time, and the processing load can be reduced. Accordingly, it is possible to accurately control time management of transmitted packets with a simple configuration.

  The data transfer control device 100 can also include a transfer mode setting register 200, a maximum connected packet number setting register 202, an SPH load setting register 204, a transfer start SPH setting register 206, and a transmission offset value setting register 208. Further, the processing unit 190 can control each circuit and each unit (unit) in the data transfer control device and perform overall control of the device in accordance with the set values of these setting registers (control registers).

  In the transfer mode setting register 200, a setting value for setting the transfer mode of the data transfer control device 100 is set. The data transfer control device 100 controls isochronous transfer in one of the transfer modes of the data remaining amount comparison mode (first mode in a broad sense) or the SP header comparison mode (second mode in a broad sense).

  When there is a TS packet to be transferred to the SRAM 160, the data transfer control device 100 set to the remaining data comparison mode performs control to output the TS packet to the transfer destination via the IEEE 1394 bus. This data remaining amount comparison mode is a transfer mode that is effective for transferring real-time data continuously input via the stream I / F circuit 110. In the present embodiment, isochronous transfer is performed when one or more TS packets to be transferred are stored in the SRAM 160, and isochronous transfer is performed for each packet number corresponding to the set value set in the maximum connected packet number setting register 202 at the maximum. I do. At this time, an SP header including a value obtained by adding the set value of the transmission offset value setting register 208 to the cycle time of the cycle timer 150 is added to the TS packet. When the TS packet stored in the SRAM 160 and to be transferred is less than one packet, a null packet is transferred as an empty packet.

  On the other hand, the data transfer control device 100 set in the SP header comparison mode refers to the SP header added to the TS packet stored in the SRAM 160 and corresponds to the cycle count updated by the cycle timer 150. Control to output TS packets. This SP header comparison mode is an effective transfer mode for transferring TS packets from a recording medium input via the IDE I / F circuit 120. In this embodiment, isochronous transfer is performed using a TS packet in which the time stamp information included in the SP header matches the setting value of the transfer start SPH setting register 206, and the setting set in the maximum connected packet number setting register 202 at the maximum. Isochronous transfer is performed for each number of packets corresponding to the value. At this time, the SP header including the setting value of the SPH load setting register 204, the setting value of the transmission offset value setting register 208, and the value generated based on the cycle time of the cycle timer 150 is replaced with the original SP header to create a TS packet. Is sent out. When the TS packet stored in the SRAM 160 and to be transferred is less than one packet, a null packet is transferred as an empty packet.

  FIG. 9 shows a block diagram of a configuration example of the link controller 140.

  The link controller 140 generates an ISO packet and outputs it to the IEEE 1394 bus in either the data remaining amount comparison mode or the SP header comparison mode.

  The link controller 140 can access the SRAM 160 via the access arbitration unit 250 included in the processing unit 190. That is, the link controller 140 outputs an access control signal for creating the header, an access control signal for reading the created header, and an access control signal for reading the data of the ISO packet to the access arbitration unit 250. The access arbitration unit 250 arbitrates these access control signals and accesses the SRAM 160 based on the access control signal after the arbitration.

  The header creation circuit 142 of the link controller 140 includes a memory access control unit 300 and a header generation controller 310. The memory access control unit 300 generates an access control signal for creating a header and an access control signal for reading the created header. The header generation controller 310 generates a control signal for controlling the memory access control unit 300.

  The transmission control circuit 144 of the link controller 140 includes a RAM control signal generation unit 320, an ISO transmission sequencer 330, an ISO transmission FIFO (First-In First-Out) 340, and a replacement SPH holding register 350. The RAM control signal generation unit 320 generates an access control signal for reading data such as TS packets constituting the ISO packet from the SRAM 160. The ISO transmission sequencer 330 performs timing control for transmitting an ISO packet. The ISO transmission FIFO 340 functions as a transmission buffer for ISO packets. The replacement SPH holding register 350 holds an addition value between the cycle time of the cycle timer 150 and the setting value of the transmission offset value setting register 208. The value held in the replacement SPH holding register 350 is set as the cycle count of the SP header of the ISO packet in synchronization with the SPH replacement enable from the ISO transmission sequencer 330.

  Hereinafter, the operation of each transfer mode in the above configuration will be described.

2.1 Data Remaining Comparison Mode FIG. 10 shows a general flow of an operation example of the data transfer control device 100 set in the data remaining amount comparison mode.

  The data transfer control device 100 has a transfer enable setting register (not shown), and is set to an enable state or a disable state according to a set value of the transfer enable setting register.

  First, the data transfer control device 100 is enabled by the transfer enable setting register (step S10). Thereafter, TS packets are received via the stream I / F circuit 110 and stored in the SRAM 160.

  Then, the link controller 140 determines the remaining amount of data in the SRAM 160 (step S11). When it is determined that the remaining amount of data in the SRAM 160 is 1 packet or more (step S11: Y), an ISO header is created (step S12), and an ISO packet is generated (step S13).

  In step S11, when it is determined that the remaining amount of data in the SRAM 160 is less than one packet (step S11: N), a null packet is generated (step S14).

  After step S13 or step S14, when the next ISO cycle is reached (step S15: Y), the ISO packet generated in step S13 or the null packet in step S14 is transmitted (step S16).

  Thereafter, when a predetermined end condition is satisfied (step S17: Y), a series of processing ends (end). When the predetermined end condition is not satisfied (step S17: N), the process returns to step S11.

  Each circuit or each unit (unit) of the data transfer control device 100 operates as described above independently or under the control of the processing unit 190.

  FIG. 11 is an explanatory diagram of processing timing of the data transfer control device.

  Of the processes shown in FIG. 10, the remaining data confirmation process for determining whether or not to transfer data by obtaining the remaining data in the SRAM 160 is performed by the isochronous transfer 64 in the ISO cycle period started with the cycle start packet 60 as a reference. To do later. Then, after the data remaining amount confirmation processing within the ISO cycle period, the ISO packet header generation processing is performed.

  FIG. 12 is an explanatory diagram of the remaining data comparison mode. In FIG. 12, the same parts as those of FIG.

  In this embodiment, when performing isochronous transfer that requires real-time performance, when outputting a TS packet to a transfer destination, the link controller 140 uses a cycle that precedes the current cycle time of the cycle timer 150 by an offset value. Output time stamp information corresponding to the time is added to the packet data. At this time, when packet data to which time stamp information is not added is input to the data transfer control device 100, input time stamp information corresponding to the cycle time of the cycle timer 150 may be temporarily added to the TS packet. it can. Then, when outputting the TS packet to the transfer destination, the link controller 140 outputs the first time stamp information corresponding to the cycle time preceding by the offset value based on the cycle time added as the input time stamp information. The time stamp information may be set by the transmission control circuit 144 instead of the input time stamp information.

  In this case, the stream I / F circuit 110 includes the SPH adding circuit 114, and the SPH adding circuit 114 can add the input time stamp information to the TS packet. In this case, the SRAM 160 stores the TS packet with the SP header added.

  The SPH addition circuit 114 refers to the cycle time updated by the cycle timer 150 and adds the arrival time of the TS packet to the SP header as input time stamp information, for example, to the TS packet of the MPEG2TS multi-stream from the receiving device. . The arrival time is added as information for specifying when the arrival time stamp information is received. TS packets input via the stream I / F circuit 110 are supplied to the PID filter 180.

  FIG. 13A shows an operation explanatory diagram of the SPH addition circuit 114. FIG. 13B shows an explanatory diagram of a TS packet after the PID filter. In FIGS. 13A and 13B, only the SP header of the TS packet is shown, and the ISO header and the CIP header are not shown.

  Time stamp information is not added to TS packets distributed by BS digital broadcasting. Therefore, the time stamp information is not added to the TS packet received by the receiving apparatus and input to the stream I / F circuit 110. Therefore, the SPH addition circuit 114 sets the cycle time of the cycle timer 150 as the cycle count of the SP header as time stamp information at the time when the TS packet is input. In FIG. 13A, an SP header with a cycle count set to 3000 is added to a TS packet input when the cycle time is 3000. Similarly, an SP header with the cycle count set to 3001 is added to the TS packet input when the cycle time is 3001.

  The PID filter 180 deletes unnecessary channel packets and supplies each packet shown in FIG.

  The storage area of the SRAM 260 is desirably separated into a header area and a data area, or a transmission area and a reception area. The data area may be divided into an asynchronous area and an isochronous area.

  FIG. 14 shows an example of the memory map of the SRAM 160.

  In FIG. 14, the SRAM 160 is divided into a header area (transmission header area, reception header area) and a data area (asynchronous transmission data area, asynchronous reception data area, isochronous transmission data area, isochronous reception data area). The packet header (control information) is stored in the header area, and the packet data (asynchronous data, isochronous data) is stored in the data area.

  In FIG. 14, the data area is divided into an asynchronous (asynchronous) area (asynchronous transmission data area and asynchronous reception data area) and an isochronous area (isochronous transmission data area and isochronous reception data area). Further, in FIG. 14, the SRAM 160 is divided into a transmission area (asynchronous transmission data area and isochronous transmission data area) and a reception area (asynchronous reception data area and isochronous reception data area).

  Furthermore, in FIG. 14, the transmission header area includes an automatic transfer header area, a null packet header area, and an isochronous header area. In the automatic transfer header area, basic information of headers (ISO header, CIP header, SP header) created in advance for transferring the ISO packet in the data remaining amount comparison mode or the SP header comparison mode is stored. The Null packet header area stores basic information of a header (ISO header, CIP header) created in advance for transferring a null packet in the remaining data comparison mode or the SP header comparison mode. Then, when transferring the ISO packet or the null packet, the header creation circuit 142 of the link controller 140 reads the basic information of the header from the header area for automatic transfer or the header area for the null packet, rewrites the predetermined information, and the SRAM 160 Write back to the isochronous header area. Then, the transmission control circuit 144 reads the rewritten header information from the isochronous header area, and reads isochronous data from the isochronous transmission data area to construct an ISO packet.

  In this way, the storage area of the SRAM 160 is managed by separating the header area and the data area, separating the transmission area and the reception area, and separating the isochronous transfer area and the asynchronous transfer area. It becomes easy. Therefore, access to the SRAM 160 is simplified when packets are transmitted and received.

  Therefore, as in the present embodiment, as a packet memory, for example, a data area in which a TS packet to which input time stamp information is added by the SPH addition circuit 114 and a header information created by the header creation circuit 142 are stored. It is desirable to include an SRAM 160 having a header area. In this case, the transmission control circuit 144 (link controller 140) as a packet generation circuit sets the output time stamp information included in the packet data from the data area of the SRAM 160 instead of the input time stamp information, and the packet data and the SRAM 160 are set. Packet data combined with header information from the header area (output packet data in a broad sense) is transmitted. When a header is created in advance and a header is added to a packet by hardware, packet data combining processing and header addition processing can be easily realized by separating the header area and the data area.

  Each region in FIG. 14 has a so-called ring buffer structure. That is, the header or data of the packet is stored from one boundary (start address) to the other boundary (end address) of these areas. When the other boundary is reached, the packet returns to one boundary and returns to the packet boundary. A header or data is stored. By doing so, the storage capacity of the SRAM 160 can be used efficiently. Also, as shown in FIG. 14, each region is separated for each application, so that a ring buffer structure can be easily realized.

  In FIG. 12, packet data from which unnecessary channels are deleted by the PID filter 180 is stored in the isochronous transmission data area of the SRAM 160 shown in FIG.

  FIG. 15 is an explanatory diagram of the transmission operation of the packet data stored in the SRAM 160.

  When isochronous transfer is performed in the remaining data comparison mode, when TS packets are accumulated in the SRAM 160 in a certain ISO cycle, all the TS packets are constructed into ISO packets and output to the IEEE 1394 bus. At this time, if the input time stamp information added to the TS packet is transferred as it is, a future time is designated when it is input to the decoder. For example, when a TS packet is transmitted at a time when the current cycle time is 3000, the cycle time advances when reaching the receiving side, and the cycle time at the time of arrival is larger than, for example, 3000. Therefore, when a TS packet in which 3000 is specified as time stamp information is decoded, the TS packet is not reproduced until the cycle count reaches one cycle and the cycle time reaches 3000 again.

  Therefore, in the present embodiment, when the TS packet read from the SRAM 160 is transferred, the value obtained by adding the offset value to the cycle count of the current SP header is set again in the SP header and transmitted. More specifically, the cycle count added as time stamp information to the SP header of the TS packet read from the SRAM 160 is referred to, and a value obtained by adding the set value of the transmission offset value setting register 208 to the cycle count is used as the SP header. Re-set as the cycle count and send.

  FIG. 15 shows a case where the setting value of the transmission offset value setting register 208 is 5. For this reason, in FIG. 15, a value obtained by adding 5 to the cycle count added as time stamp information to the SP header of the TS packet read from the SRAM 160 is reset and transmitted as the cycle count of the SP header. For example, the TS packet stored in the SRAM 160 is constructed into an ISO packet and transmitted in the next ISO cycle.

  More specifically, the link controller 140 constructs the TS packet stored in the SRAM 160 as an ISO packet and transmits it as follows.

  In FIG. 12, the pointer controller 170 obtains data remaining in the SRAM information for determining the amount of TS packets stored in the SRAM 160. More specifically, the pointer controller 170 obtains data remaining in the SRAM information corresponding to the difference between the stream side pointer that is the write pointer of the SRAM 160 and the link side pointer that is the read pointer of the SRAM 160. The remaining data amount information in the SRAM obtained by the pointer controller 170 is supplied to the header creation circuit 142 of the link controller 140.

  The header creation circuit 142 determines whether there are one or more TS packets in the SRAM 160 based on the remaining data amount information in the SRAM from the pointer controller 170. When it is determined that there are one or more TS packets in the SRAM 160, an ISO header for generating an ISO packet is created. The ISO header created by the header creation circuit 142 is stored in the isochronous header area of the SRAM 160.

  The transmission control circuit 144 detects whether or not there is an ISO header created by the header creation circuit 142 in the isochronous header area of the SRAM 160. When it is detected that there is an ISO header in the isochronous header area in the SRAM 160, the transmission control circuit 144 reads the ISO header from the isochronous area and reads data (TS packets) from the isochronous transmission data area. Then, the transmission control circuit 144 outputs the SP header added to the data in place of the SP header having a value obtained by adding the setting value of the transmission offset value setting register 208 to the current cycle time.

  When it is detected that there is no ISO header in the isochronous area in the SRAM 160, the transmission control circuit 144 reads the Null packet header from the Null packet header area. Then, the transmission control circuit 144 outputs this Null packet header as a Null packet.

  Hereinafter, the operation of the link controller 140 will be described with reference to FIG.

  FIG. 16 shows a timing diagram of an operation example of the link controller 140 when a null packet is transmitted.

  First, when an automatic transfer enable is received from the processing unit 190, the header creation circuit 142 starts its operation. In FIG. 16, it is assumed that the enable state is set by the automatic transfer enable.

  In this state, when the header creation circuit 142 receives the ISO packet transfer completion signal, generation of an isochronous header is started. The ISO packet transfer completion signal becomes active when the transfer of the ISO packet is completed based on the timing control of the ISO transmission sequencer 330 in the ISO cycle.

  The sequencer 312 of the header generation controller 310 that has received the ISO packet transfer completion signal determines whether one or more TS packets are stored in the SRAM 160 based on the remaining data information in the SRAM from the pointer controller 170. Determine (E1).

  When the TS packet stored in the SRAM 160 is less than one packet, the sequencer 312 enables NextNull and activates the header read start signal (E2). As a result, the header access controller 302 of the memory access control unit 300 reads the header from the Null packet header area of the SRAM 160 as described with reference to FIG. 14 (E3).

  Next, the header access controller 302 writes the read Null packet header area in the isochronous header area of the SRAM 160 (E4). The header access controller 302 activates the end of writing the header and notifies the sequencer 312.

  When the cycle start packet is received and the isocycle start signal becomes active (E5), the next ISO cycle is started. The ISO transmission sequencer 330 reads the header from the isochronous header area of the SRAM 160 via the RAM control signal generation unit 320, rewrites the data length as necessary, and transmits it as a null packet (E6). Since it is a null packet, it does not contain data.

  FIG. 17 shows a timing diagram of an operation example of the link controller 140 when transmitting an ISO packet. Also in FIG. 17, it is assumed that the enable state is set by the automatic transfer enable.

  For example, when transmission of a null packet is completed in the ISO cycle, the ISO transmission sequencer 330 activates an ISO packet transfer completion signal. The sequencer 312 of the header generation controller 310 that has received the ISO packet transfer completion signal determines whether one or more TS packets are stored in the SRAM 160 based on the remaining data information in the SRAM from the pointer controller 170. Discriminate (E10).

  When the number of TS packets stored in the SRAM 160 is one or more, the sequencer 312 invalidates NextNull and activates the header read start signal (E11). As a result, the header access controller 302 of the memory access control unit 300 reads the basic information of the header from the automatic transfer header area of the SRAM 160 as described with reference to FIG. 14 (E12).

  The transfer data length calculation unit 314 of the header generation controller 310 obtains the data length of the ISO packet that can be transferred in the next ISO cycle using the remaining data amount information in the SRAM. The header rewriting unit 304 of the memory access control unit 300 rewrites the basic information of the header read from the automatic transfer header using the transfer data length from the transfer data length calculation unit 314. Then, the header access controller 302 writes the rewritten header in the isochronous header area of the SRAM 160 (E13). The header access controller 302 activates the end of writing the header and notifies the sequencer 312.

  When the cycle start packet is received and the isocycle start signal becomes active (E14), the next ISO cycle is started. The ISO transmission sequencer 330 reads the header from the isochronous header area of the SRAM 160 via the RAM control signal generator 320, reads the data from the isochronous transmission data area of the SRAM 160, generates an ISO packet, and transmits it as an ISO packet (E15). ).

  As described above, in this embodiment, the cycle time matches the value of the SP header immediately after the packet arrives at the receiving side, so that reliable time management of the transfer data is realized, and the processing load accompanying data transfer Can be reduced and the cost can be reduced.

  As described above, a predetermined transmission offset value may be added to the current cycle time, but more precisely, it is desirable to replace the SP header as follows. That is, based on the time stamp information (first time stamp information) added to the SPH addition circuit 114 and the current cycle time of the cycle timer 150, the second time stamp information to be added at the current cycle time is obtained. Then, the second time stamp information is set as output time stamp information instead of the input time stamp information. As a result, finer time management can be realized as compared with the case where the transmission offset value has a constant offset value with respect to the current cycle time.

2.2 SP Header Comparison Mode FIG. 18 shows a general flow of an operation example of the data transfer control device 100 set in the SP header comparison mode.

  First, the data transfer control device 100 is set to an enable state by the transfer enable setting register (step S20). Here, it is determined by the SPH load setting register 204 whether the SPH load setting is set to the enable state or the disable state (step S21).

  When the SPH load setting is enabled (step S21: Y), the SP header cycle count of the first packet in the SRAM 160 is set as a comparison value (step S22). This comparison value is set in the transfer start SPH setting register 206.

  On the other hand, when the SPH load setting is disabled (step S21: N), the value designated by the firmware is set as a comparison value (step S23). This comparison value is also set in the transfer start SPH setting register 206.

  After the transfer enable setting, TS packets are accepted via the stream I / F circuit 110 and stored in the SRAM 160.

  After step S22 or step S23, the link controller 140 determines whether or not the remaining data amount of the SRAM 160 is equal to or greater than the maximum number of connected packets (step S24). The maximum concatenated packet number is set in the maximum concatenated packet number setting register 202.

  When the remaining amount of data in the SRAM 160 is equal to or greater than the maximum number of concatenated packets (step S24: Y), the SP header added to each TS packet stored in the isochronous data area of the SRAM 160 is referred to and the cycle count that matches the comparison value is It is detected whether there is a TS packet to which the SP header is added (step S25).

  When the remaining data amount is less than the maximum number of concatenated packets in step S24 (step S24: N), null packet data is generated (step S26).

  When it is detected in step S25 that there is no TS packet with an SP header having a cycle count that matches the comparison value in the isochronous data area of the SRAM 160 (step S25: N), after incrementing the comparison value (step S27) Null packet data is generated (step S26).

  In step S25, when it is detected that there is a TS packet to which an SP header having a cycle count matching the comparison value is added in the isochronous data area of the SRAM 160 (step S25: Y), the cycle count does not match the comparison value. On the condition that there is a TS packet with an SP header added (step S28: Y), the comparison value is incremented (step S29).

  After step S29 or when there is no TS packet with an SP header having a cycle count that does not match the comparison value in step S28 (step S28: N), a header for the ISO packet is created (step S30). A set ISO packet is generated in place of the SP header having a cycle count that precedes the cycle time by an offset value (step S31).

  After step S26 or step S31, when the next ISO cycle is reached (step S32: Y), the ISO packet generated in step S31 or the null packet in step S26 is transmitted (step S33).

  Thereafter, when a predetermined end condition is satisfied (step S34: Y), a series of processing ends (end). When the predetermined end condition is not satisfied (step S34: N), the process returns to step S24.

  Each circuit or each unit (unit) of the data transfer control device 100 operates as described above independently or under the control of the processing unit 190.

  Even in the SP header comparison mode, the remaining data check process for determining whether or not to transfer data by obtaining the remaining data in the SRAM 160 is performed after isochronous transfer in the ISO cycle period. Then, after the data remaining amount confirmation processing in the ISO cycle period, the ISO packet header creation processing is performed.

  FIG. 19 shows an explanatory diagram of the SP header comparison mode. In FIG. 19, the same parts as those in FIG. 8 or FIG.

  The data transfer control device 100 set to the SP header comparison mode is provided between the IEEE 1394 bus and the recording medium. Therefore, when recording MPEG2 TS on a recording / reproducing apparatus for HDD or DVD as a recording medium, a packet transferred via an IEEE1394 bus connected to the data transfer control apparatus 100 or a stream I / F circuit 110 is used. It is one of the packets of the received stream. A packet transferred via the IEEE 1394 bus has an SP header already added in accordance with the IEC61883 standard. The SPH addition circuit 114 adds an SP header to the stream packet received via the stream I / F circuit 110. Therefore, when recording MPEG2TS on a recording medium, the data transfer control device 100 outputs it as it is via the IDE I / F circuit 120. At this time, packet data to be written to the SDRAM 380 (buffer memory in a broad sense) connected to the outside of the data transfer control device 100 via the SDRAM I / F circuit 130 is accumulated and recorded from the SDRAM 380 via the IDE / IF circuit 120. It is desirable to write to the medium. For example, when the recording medium is an HDD, if the data is not written in bursts, the write time becomes longer due to an increase in seek time or the like.

  On the other hand, when MPEG2TS is read out and reproduced from a recording / reproducing apparatus for an HDD or DVD as a recording medium, it is performed as follows. In this case, the MPEG2TS read from the recording medium is buffered in the SDRAM 380 connected to the outside via the SDRAM I / F circuit 130.

  FIG. 20 shows an operation explanatory diagram when data read from the HDD as a recording medium is transferred to the SDRAM 380 in the data transfer control device 100.

  When the MPEG2TS read from the HDD is reproduced, data is written to the SDRAM 380 in a somewhat large data unit as in recording. By doing so, TS packets that are not interrupted as isochronous data can be supplied to the SRAM 160 according to the length of the seek time.

  In FIG. 20, when the cycle time is 5000, data having SP, 2500, 2501, 2502, and 2503 in the SP header cycle count of data read from the HDD is read. Thus, the SP header of data read from the HDD and the cycle time counted by the cycle timer 150 are completely irrelevant. This is because there is no relationship between the cycle count of the SP header added at the time of recording or the like and the cycle time at the time of reproduction. In addition, since the time for reading data from the HDD is much faster than the MPEG2TS bandwidth, the cycle count of the SP header added during recording or the like cannot be associated with the cycle time during playback.

  The MPEG2TS written in the SDRAM 380 in this way is transferred to the SRAM 160. This transfer is preferably a DMA transfer controlled by a DMA (Direct Memory Access) control circuit included in the SDRAM I / F circuit 130, for example.

  FIG. 21 shows an operation explanatory diagram when data is transferred from the SDRAM 380 to the SRAM 160 in the data transfer control device 100.

  Here, when the cycle time is 6500, the data of the SP header cycle count 2500, 2501, 2502, 2503 is read from the SDRAM 380 and written to the SRAM 160. As described above, even when the data accumulated in the SDRAM 380 is written into the SRAM 160 by DMA transfer, the cycle time of the cycle timer 150 is not related to the cycle count of the SP header added to the TS packet.

  The data stored in the SRAM 160 is referred to by its SP header, and a data group to which an SP header having a cycle count that matches the comparison value is read out, constructed into an ISO packet, and transmitted.

  FIG. 22 is an operation explanatory diagram when data is transferred from the SRAM 160 to the IEEE 1394 bus in the data transfer control device 100.

  For example, when transfer is started when the cycle time of the cycle timer 150 is 6500, two TS packets to which an SP header having a cycle count matching the comparison value 2500 is added are connected and output. At this time, the SP header is replaced with an SP header having a cycle count of 6506 obtained by adding an offset value 4006 to 2500. This can be replaced with an SP header having a cycle count preceded by an offset value of 5 based on the current cycle time. The two TS packets are output to the IEEE1394 bus at a cycle time of 6501.

  In the next ISO cycle, the comparison value is incremented and updated to 2501. Accordingly, two TS packets to which an SP header having a cycle count matching the comparison value 2501 is added are connected and output. At this time, the cycle count of the SP header can be a value incremented with 6501 as an initial value. The SP header cycle count may be a value obtained by adding an offset value 4006 to the original SP header cycle count. In short, the cycle count of the SP header may be a value that precedes the current cycle time by 5.

  By changing the maximum number of concatenated packets, even if there are two or more TS packets with an SP header having a cycle count that matches the comparison value in one ISO cycle, only one is transmitted, It is also possible to transfer the rest in the next ISO cycle.

  Hereinafter, the operation of the link controller 140 in the SP header comparison mode will be described with reference to FIG.

  FIG. 23 shows a timing chart of an operation example of the link controller 140 in the SP header comparison mode.

  Also in FIG. 23, it is assumed that the automatic transfer enable is set to the enable state. In this state, when an ISO packet transfer completion signal is received, generation of an isochronous header is started.

  For example, when transmission of a null packet is completed in the ISO cycle, the ISO transmission sequencer 330 activates an ISO packet transfer completion signal. The sequencer 312 of the header generation controller 310 that has received the ISO packet transfer completion signal determines whether one or more TS packets are stored in the SRAM 160 based on the remaining data information in the SRAM from the pointer controller 170. It discriminate | determines (E20).

  When the number of TS packets stored in the SRAM 160 is one or more, the sequencer 312 activates the SPH read start signal and outputs it to the memory access control unit 300 (E21).

  Upon receiving the SPH read start signal, the header access controller 302 of the memory access control unit 300 reads the SP header added to the TS packet stored in the isochronous transmission data area of the SRAM 160 (E22). The SPH comparison unit 316 of the header generation controller 310 determines whether or not the read SP header (its cycle count) matches the comparison value CompaCount set in the transfer start SPH setting register 206.

  When it is determined that the read SP header (its cycle count) matches the comparison value CompaCount, the SPHOK signal is activated and output to the sequencer 312 (E23), and the SPH match count supplied to the transfer data length calculation unit 314 Increment the signal.

  The sequencer 312 determines whether or not the SRAM 160 has the next readable SP header based on the remaining data information in the SRAM. When it is determined that there is a next readable SP header, the sequencer 312 activates the SPH read start signal again (E24). Similarly, the header access controller 302 reads the SP header of the packet stored in the isochronous transmission data area of the SRAM 160 (E25). Further, when the SPH comparison unit 316 determines that the read SP header matches the comparison value CompaCount, it activates the SPHOK signal and outputs it to the sequencer 312 (E26), and the SPH match supplied to the transfer data length calculation unit 314 Increment the count signal.

  The sequencer 312 determines whether or not the SRAM 160 has the next readable SP header based on the remaining data amount information in the SRAM. When it is determined that there is the next readable SP header, the sequencer 312 activates the SPH read start signal again (E27). Then, the header access controller 302 reads the SP header of the packet stored in the isochronous transmission data area of the SRAM 160 (E28).

  The same processing is repeated until it is determined that there is no readable SP header in the SRAM 160 or until the SPH comparison unit 316 determines that the read SP header does not match the comparison value CompaCount.

  For example, when the SPH comparison unit 316 determines that the read SP header does not match the comparison value CompaCount, the transfer data length calculation unit 314 determines the number of data that can be transferred in the next ISO cycle based on the value of the SPH match count signal. calculate. That is, the transfer data length calculation unit 314 obtains the number of 192 bytes × SPH coincidence as the transfer data length.

  Thereafter, the sequencer 312 disables NextNull and activates the header read start signal (E29). As a result, the header access controller 302 of the memory access control unit 300 reads the basic information of the header from the automatic transfer header area of the SRAM 160 as described with reference to FIG. 14 (E30).

  The header rewriting unit 304 rewrites the basic information of the automatic transfer header using the transfer data length from the transfer data length calculation unit 314. Then, the header access controller 302 writes the rewritten header in the isochronous header area of the SRAM 160 (E31). The header access controller 302 activates the end of writing the header and notifies the sequencer 312.

  When the cycle start packet is received and the isocycle start signal becomes active (E32), the next ISO cycle is started. The ISO transmission sequencer 330 reads the header from the isochronous header area of the SRAM 160 via the RAM control signal generator 320, reads the data from the isochronous transmission data area of the SRAM 160, generates an ISO packet, and transmits it as an ISO packet (E33). ).

  When the first SP header does not match the comparison value CompaCount, the transfer data length is 0, it is determined that there is no data that can be transferred in the next ISO cycle, and the Null packet is transferred as described above. That is, the comparison value is compared with the time stamp information included in the data stored in the SRAM 160, and when no data including time stamp information matching the comparison value is detected, an empty packet is output to the transfer destination.

  As described above, the data transfer control device 100 in this embodiment includes the transfer mode setting register 200. When the link controller 140 outputs the TS packet (packet data) to the bus (transfer destination) when the transfer mode setting register 200 switches to the data remaining amount comparison mode (first mode), the cycle timer Output time stamp information corresponding to the cycle time preceding the offset value by the current cycle time of 150 can be added to the TS packet.

  Alternatively, in the data remaining amount comparison mode, for example, input time stamp information corresponding to the cycle time of the cycle timer 150 when the TS packet is input to the data transfer control device 100 is added to the TS packet. After that, the link controller 140 outputs the TS packet to the bus using the first time stamp information corresponding to the cycle time preceding the offset value based on the cycle time added as the input time stamp information as the output time stamp information. Can be set instead of the input time stamp information.

  When the transfer mode setting register 200 switches to the SP header comparison mode (second mode), the link controller 140 stores the time stamp information added to the TS packet added to the input time stamp information accumulated in the SRAM 160. Compare with the comparison value. A TS packet is generated by adding output time stamp information corresponding to the cycle time preceding the offset value with respect to the current cycle time of the cycle timer 150 to the data group including the time stamp information that matches the comparison value. At the same time, the packet data is output to the bus (transfer destination) at the current cycle time. Here, when time stamp information that does not match the comparison value is detected, the comparison value is updated. Then, at the cycle time next to the current cycle time, the updated comparison value can be compared with the time stamp information included in the data stored in the SRAM 160.

  Thus, even when packet data is transferred from a recording medium to which time stamp information is added from the beginning, it can be transmitted at a timing suitable for buffering on the transfer destination side. Become.

  Here, also in the SP header comparison mode, it is desirable to create header information for a data group including time stamp information that matches the comparison value, as in the remaining data comparison mode. The comparison value update process is preferably performed on the condition that data including time stamp information that does not match the comparison value is detected. Further, the time stamp information of the data stored in the SRAM 160 is replaced with output time stamp information corresponding to the cycle time that precedes the current cycle time of the cycle timer 150 by the offset value, and a TS packet is generated to generate an IEEE 1394 bus. It is desirable to output to

3. Next, an example of an electronic device including the data transfer control device of this embodiment will be described.

  FIG. 24 is a block diagram showing a configuration example of a digital broadcast receiving apparatus as an electronic apparatus to which the data transfer control apparatus according to this embodiment is applied. In FIG. 24, the same parts as those of the data transfer control device 100 shown in FIG.

  The digital broadcast receiving apparatus 400 receives the MPEG2 stream distributed as BS digital broadcast via the antenna 420. The MPEG2 stream can be decoded and output to the display device 430, a partial stream of the MPEG2 stream can be output to the HDD 432 incorporated in the display device 430, or the partial stream can be transferred to the HDD recorder 440.

  The digital broadcast receiving apparatus 400 can include the data transfer control apparatus 100 of this embodiment, an RF / demodulation unit (receiving circuit) 402, a decoder 404, and a 1394 PHY chip 406. The digital broadcast receiving apparatus 400 does not need to include all the circuits and units (units) in FIG. 24, and may be configured to omit some of them.

  The data transfer control device 100 applied to the digital broadcast receiving device 400 controls data transfer in the data remaining amount comparison mode. Therefore, in FIG. 24, only a part of the data transfer control device 100 of FIG. 8 is illustrated.

  The MPEG2 stream received via the antenna 420 is demodulated by the RF / demodulator 402 and supplied to the data transfer control device 100 and the decoder 404 as an MPEG2TS multistream.

  When displaying a real-time image of the MPEG2 stream on the display device 430, the result of decoding by the decoder 404 is output to the display device 430.

  When recording in the HDD 432 built in the display device 430, the data transfer control device 100 takes in the MPEG2TS multi-stream via the stream I / F circuit 110, extracts the MPEG2TS partial stream with the PID filter 180, and the IDE I / F circuit. The data is output to the HDD 432 via 120.

  When recording to the HDD recorder 440, the data transfer control device 100 buffers the MPEG2TS partial stream extracted by the PID filter 180 in the SRAM 160 and outputs the buffered data to the 1394 PHY chip 406 via the link controller 140. The 1394 PHY chip transfers the TS packet to the HDD recorder 440 via the IEEE 1394 bus. Therefore, the packet data stream received by the RF / demodulator 402 is transferred by the data transfer control device 100 to the HDD recorder 440 having a recording medium via the IEEE 1394 bus.

  In FIG. 24, when the digital broadcast receiving device 400 includes the display device 430, it can be said that the data transfer control device 100 in this embodiment can be applied to the digital broadcast display device.

  According to such a digital broadcast receiving apparatus, it is possible to reduce the processing load and reduce the cost under reliable TS packet time management.

  FIG. 25 is a block diagram showing a configuration example of a recording / reproducing apparatus as an electronic apparatus to which the data transfer control device according to this embodiment is applied. In FIG. 25, the same parts as those of the data transfer control device 100 shown in FIG.

  The recording / reproducing apparatus 500 realizes recording / reproducing of AV data. That is, it is possible to record the MPEG2 stream received via the antenna 520 on the HDD 510 containing the MPEG2 stream or to reproduce the MPEG2 stream recorded on the HDD 510.

  The recording / reproducing apparatus 500 can include the data transfer control apparatus 100, the HDD 510, the SDRAM (buffer memory in a broad sense) 380, and the 1394 PHY chip 406 of this embodiment. Note that the recording / reproducing apparatus 500 does not have to include all the circuits and units (units) in FIG. 25, and may be configured to omit some of them.

  The data transfer control device 100 applied to the recording / reproducing device 500 controls data transfer in the SP header comparison mode. Therefore, in FIG. 25, only a part of the data transfer control device 100 of FIG. 8 is illustrated.

  The MPEG2 stream received via the antenna 520 is decoded by a display device (for example, a digital TV device) 530, and an image corresponding to the decoding result is displayed as a digital broadcast. The MPEG2 stream supplied to the display device 530 is transferred to the recording / reproducing device 500 via the IEEE1394 bus.

  In the recording / reproducing apparatus 500, TS packets on the IEEE 1394 bus are supplied to the data transfer control apparatus 100 via the 1394 PHY chip 406.

  When an MPEG2 stream is recorded on an HDD (recording medium in a broad sense) 510, the data transfer control device 100 temporarily stores TS packets in the SRAM 160. Then, after buffering in the SDRAM 380 via the SDRAM I / F circuit 130, DMA transfer is again performed to the HDD 510 via the SDRAM I / F circuit 130 and the IDE I / F circuit 120.

  When reproducing the MPEG2 stream stored in the HDD 510, the data transfer control device 100 once DMA-transfers the MPEG2 stream read from the HDD 510 to the SDRAM 380 via the IDE / F circuit 120 and the SDRAM I / F circuit 130. Buffered. Thereafter, the data transfer control device 100 stores the data read from the SDRAM 380 in the SRAM 160 via the SDRAM I / F circuit 130. Then, the ISO packets are sequentially transferred via the IEEE 1394 bus while referring to the SP header of the data stored in the SRAM 160. The display device 530 receives and decodes the ISO packet, and displays an image corresponding to the decoding result.

  As described above, the HDD 510 is connected to the IEEE 1394 bus via the data transfer control device 100. Then, the data transfer control device 100 can output and record the data input via the IEEE 1394 bus to the HDD 510 or output the data read from the HDD 510 via the IEEE 1394 bus.

  According to such a recording / reproducing apparatus, transmission can be performed at a timing suitable for the decoding side under reliable TS packet time management, and the processing load can be reduced to realize cost reduction.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

  In addition, terms (header generation circuit or packet generation circuit, TS packet, etc.) cited as broad terms (transfer controller, packet data, etc.) in the description in the specification or drawings are other descriptions in the specification or drawings. Can be replaced with broad terms.

  In the present embodiment, the case of performing isochronous transfer has been described, but the present invention is not limited to this. For example, the present invention can be applied to asynchronous transfer.

  In this embodiment, the cycle count of the SP header is described as an example of the time stamp information, but the present invention is not limited to this. For example, the time stamp information may be added, set, or replaced by including a cycle offset in addition to the SP header cycle count.

  Furthermore, in the present embodiment, the TS packet has been described as an example, but the present invention is not limited to this.

  Furthermore, in the present embodiment, the case where the data of the MPEG standard (MPEG2, MPEG4) is transferred by the IEEE 1394 standard bus (interface) has been described, but the present invention is not limited to this. For example, the present invention is also applied to a case where data of a standard based on the same idea as MPEG (MPEG2, MPEG4) or a standard developed from MPEG is transferred by a bus based on a standard based on the same idea as IEEE 1394 or a standard developed from IEEE 1394. Can be applied. The present invention can also be applied to the case where encoded data such as MPEG is transferred by USB (Universal Serial Bus) isochronous transfer.

  Furthermore, in the present embodiment, the general-purpose high-speed serial interface such as IEEE1394 has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a data transfer control device that controls data transfer via a wireless transmission path.

The figure which shows the structural example of the system to which the data transfer control apparatus of this embodiment was applied. Explanatory drawing of the data structure in BS digital broadcasting, a data transfer control apparatus, and IEEE1394 bus | bath. The figure which shows an example of the format of TS packet. Explanatory drawing of the structure of an MPEG stream. FIGS. 5A to 5D are diagrams showing examples of formats of an SP header, a CIP header, and an ISO header. Explanatory drawing of ISO transfer. Explanatory drawing of the relationship between an ISO packet and the cycle count of SP header. 1 is a block diagram of a configuration example of a data transfer control device according to an embodiment. The block diagram of the structural example of the link controller of FIG. The flowchart of the operation example of the data transfer control apparatus set to the data remaining amount comparison mode. Explanatory drawing of the process timing of the data transfer control apparatus in this embodiment. Explanatory drawing of the data remaining amount comparison mode in this embodiment. FIG. 13A is an operation explanatory diagram of the SPH addition circuit. FIG. 13B is an explanatory diagram of a TS packet after the PID filter. The figure which shows an example of the memory map of SRAM. Explanatory drawing of transmission operation | movement of the packet data stored in SRAM in data remaining amount comparison mode. The timing diagram of the operation example of a link controller in the case of transmitting a Null packet in data remaining amount comparison mode. The timing diagram of the example of operation | movement of a link controller in the case of transmitting an ISO packet in data remaining amount comparison mode. The flowchart of the operation example of the data transfer control apparatus set to SP header comparison mode. Explanatory drawing of SP header comparison mode in this embodiment. Explanatory drawing when data read from HDD is transferred to SDRAM in SP header comparison mode. Operation | movement explanatory drawing when it transfers from SDRAM to SRAM in SP header comparison mode. Explanatory drawing when it transfers to the IEEE1394 bus | bath from SRAM in SP header comparison mode. The timing diagram of the operation example of the link controller in SP header comparison mode. The block diagram of the example of a structure of the digital broadcast receiver as an electronic device to which the data transfer control apparatus in this embodiment was applied. 1 is a block diagram of a configuration example of a recording / reproducing apparatus as an electronic apparatus to which a data transfer control device according to an embodiment is applied.

Explanation of symbols

10, 420, 520 antenna, 20 digital broadcast tuner,
22, 100 Data transfer control device, 30 recording / reproducing device, 32 recording medium,
110 stream I / F circuit, 112 SPH comparison output circuit,
114 SPH addition circuit, 120 IDEI / F circuit,
130 SDRAM I / F circuit, 140 link controller,
142 header creation circuit, 144 transmission control circuit, 150 cycle timer,
160 SRAM, 170 pointer controller, 180 PID filter,
190 processing unit, 200 transfer mode setting register,
202 Maximum concatenated packet number setting register, 204 SPH load setting register,
206 Transfer start SPH setting register, 208 Transmission offset value setting register,
250 access arbitration unit, 300 memory access control unit,
302 header access controller, 304 header rewrite unit,
310 header generation controller, 312 sequencer,
314 Transfer data calculation unit, 316 SPH comparison unit,
320 RAM control signal generator, 330 ISO transmission sequencer,
340 ISO transmission FIFO, 350 re-storing SPH holding register,
380 SDRAM, 400 digital broadcast receiver, 402 RF / demodulator,
404 decoder, 406 1394 PHY chip, 430, 530 display device,
432, 510 HDD, 440 HDD recorder

Claims (16)

A data transfer control device for controlling data transfer,
A cycle timer that counts the cycle time updated every transfer cycle;
A transfer controller for controlling the transfer of packet data,
The transfer controller is
When input to the data transfer control device, when outputting packet data to which no time stamp information is added to the transfer destination, an output corresponding to the cycle time preceding the cycle time by the offset value based on the current cycle time of the cycle timer A data transfer control device, wherein time stamp information is added to the packet data. In claim 1,
Input time stamp information corresponding to the cycle time of the cycle timer when the packet data is input to the data transfer control device is added to the packet data,
The transfer controller is
The packet data is output to the transfer destination using the first time stamp information corresponding to the cycle time preceding the offset value based on the cycle time added as the input time stamp information as the output time stamp information. The data transfer control device is characterized in that it is set instead of the input time stamp information. In claim 2,
The transfer controller is
Based on the first time stamp information and the current cycle time of the cycle timer, second time stamp information to be added in the current transfer cycle is obtained, and the second time stamp information is obtained as the output time. A data transfer control device, wherein the stamp information is set in place of the input time stamp information. In claim 2 or 3,
The transfer controller is
A header creation circuit for creating header information to be added to packet data based on a remaining amount of data in a packet memory in which packet data to which the input time stamp information is added is stored;
A packet generation circuit that generates output packet data by combining the header information generated by the header generation circuit and the packet data stored in the packet memory, and outputs the output packet data to the transfer destination; Including
The packet generation circuit comprises:
The data transfer control device, wherein the output time stamp information is set instead of the input time stamp information. In any of claims 2 to 4,
The transfer controller is
Data that outputs an empty packet to the transfer destination when the remaining amount of data in the packet memory in which the packet data to which the input time stamp information is added is stored in the current transfer cycle is less than one packet Transfer control device. In claim 5,
Including the packet memory;
The packet memory is
A data area in which packet data to which the input time stamp information is added is stored; and a header area in which the header information created by the header creation circuit is stored;
The packet generation circuit comprises:
Data transfer control characterized in that the output time stamp information is set instead of the input time stamp information included in the packet data from the data area, and the packet data and the header information from the header area are combined. apparatus. In claim 6,
The header creation circuit is
A data transfer control device, comprising: reading basic information of a header stored in the header area, generating the header information using the basic information, and writing back the header information in the header area. In claim 6 or 7,
A transfer mode setting register for switching between the first and second modes;
When switched to the first mode by the transfer mode setting register,
The transfer controller is
Output time stamp information corresponding to the cycle time preceding the offset value based on the current cycle time of the cycle timer, and generating the packet data set when outputting the packet data to the transfer destination,
When switched to the second mode by the transfer mode setting register,
The transfer controller is
Comparing the time stamp information included in the packet data stored in the packet memory and having the input time stamp information added thereto with a comparison value;
An output time corresponding to a cycle time preceding the offset value based on the current cycle time of the cycle timer instead of the input time stamp information for a packet data group including time stamp information that matches the comparison value Set stamp information and output the packet data to the transfer destination in the current transfer cycle;
When the time stamp information that does not match the comparison value is detected, the comparison value is updated, and at the cycle time next to the current cycle time, the updated comparison value and the data stored in the packet memory are updated. A data transfer control device for comparing time stamp information included therein. In claim 8,
When switched to the second mode,
The transfer controller is
The comparison value is compared with time stamp information included in the packet data, and an empty packet is output to the transfer destination when packet data including time stamp information that matches the comparison value is not detected. A data transfer control device. In claim 8 or 9,
When switched to the second mode,
The transfer controller is
Reading the time stamp information included in the packet data, creating header information for a data group including time stamp information that matches the comparison value, and packet data including time stamp information that does not match the comparison value The comparison value is updated on the condition that it is detected,
In place of the time stamp information of the packet data, the packet data is generated by setting output time stamp information corresponding to the cycle time preceding the offset value based on the current cycle time of the cycle timer, and the transfer A data transfer control device that outputs the data first. In any one of Claims 1 thru | or 10.
A data transfer control device that performs data transfer conforming to the IEEE 1394 standard. A receiving circuit for receiving packet data;
A data transfer control device according to any one of claims 1 to 7, provided between the receiving circuit and a bus through which packet data is transmitted.
The data transfer control device is
An electronic apparatus that transfers the packet data to a recording medium connected via the bus. A data transfer control device according to any one of claims 8 to 10,
Including a recording medium connected to a bus via the data transfer control device,
The data transfer control device is
An electronic apparatus, wherein data input via the bus is output to the recording medium and recorded on the recording medium, or data read from the recording medium is output via the bus. A data transfer control method for controlling data transfer,
Count the cycle time that is updated every transfer cycle,
When outputting packet data to which the time stamp information is not added to the transfer destination when it is input, output time stamp information corresponding to the cycle time that precedes the current cycle time by an offset value is added to the packet data. A data transfer control method comprising adding and outputting to the transfer destination. In claim 14,
Adding input time stamp information corresponding to a cycle time when the packet data is input to the packet data;
The first time stamp information corresponding to the cycle time preceded by the offset value based on the cycle time added as the input time stamp information is replaced with the input time stamp information as the output time stamp information. A data transfer control method comprising: setting data in the packet data when outputting the data to a transfer destination. In claim 15,
Based on the first time stamp information and the current cycle time, second time stamp information to be added at the current cycle time is obtained, and the second time stamp information is used as the output time stamp information. A data transfer control method characterized in that it is set in place of input time stamp information.

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