JP2005229218A - Image decoding apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a conventional arithmetic decode processing that takes much time for the decode processing since a context is presumed while updating peripheral information on the basis of a decoding result. <P>SOLUTION: A stream analysis section 10 inputs coded data CD to an entropy decoding section 12. A peripheral information register group 20 stores the peripheral information with respect to a target pixel for presuming the context used for arithmetic decoding of the coded data CD. A context presuming section 22 presumes the context on the basis of the peripheral information stored in the peripheral information register group 20 and gives a context label CX to an arithmetic decoding section 24. The arithmetic decoding section 24 decodes the coded data CD on the basis of the context label CX to obtain a decision D and gives it to an inverse quantization section 14. The peripheral information stored in the peripheral information register group 20 is updated by the same cycle as that required for decoding depending on a decoding result by the arithmetic decoding section 24. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image decoding apparatus.

  In ISO / ITU-T, standardization of JPEG2000 using discrete wavelet transform (DWT) is performed as a successor of JPEG (Joint Photographic Expert Group), which is a standard technology for compression coding of still images. JPEG2000 can encode a wide range of image quality from low bit rate encoding to lossless compression with high performance, and it is easy to realize a scalability function that gradually increases image quality.

  In the encoding process in JPEG2000, a block division process, a coefficient bit modeling process, and an arithmetic encoding process are performed. In the block division process, each subband generated by subjecting the original image to discrete wavelet transform is divided into small regions called code blocks. In the coefficient bit modeling process, the quantized value of the wavelet transform coefficient is decomposed into bit planes from the most significant bit (MSB) to the least significant bit (LSB), and 2 for arithmetic coding. Generate value symbols and contexts. The arithmetic encoding process performs entropy encoding based on the appearance probability of a symbol sequence based on the generated symbol and context.

As described above, in the arithmetic encoding process, it is necessary to input a context in addition to the data to be encoded. Patent Document 1 discloses an arithmetic encoding device and an arithmetic decoding device configured to prepare a plurality of possible context candidates and switch them by a selector according to the arithmetic encoding operation result.
Japanese Patent No. 3406550

  In order to execute encoding and decoding in JPEG2000 at high speed, parallel processing is required. In arithmetic coding in JPEG2000, pixel peripheral information is required to determine the context. In encoding, since data of all pixels is known in advance, necessary peripheral information can be prepared, and parallelization and high-speed processing are easy. However, in decoding, since pixel peripheral information is not known unless it is actually decoded, parallelization is difficult and must be a sequential process.

  In the arithmetic decoding device disclosed in Patent Literature 1, context candidates are prepared in advance, but the control for switching the context candidates is complicated. In addition, when processing is performed in parallel with this apparatus, the number of context candidates increases exponentially, resulting in an increase in circuit scale and complicated control.

  The present invention has been made in view of these problems, and an object thereof is to provide an image decoding technique capable of performing decoding at high speed. Another object is to provide an image decoding technique that can be easily parallelized.

  One embodiment of the present invention relates to an image decoding apparatus. This apparatus, when decoding a pixel, a peripheral information register that holds peripheral information of the pixel, and context estimation that generates the context information for reading the peripheral information from the peripheral information register and predicting the decoding result of the pixel And a decoding unit that decodes the pixel from the generated context information and the encoded data of the pixel, and the decoding unit decodes one pixel for each unit decoding period and ends each unit decoding period. Sometimes, the peripheral information is updated with the decoding result of the pixels decoded in the unit decoding period and written back to the peripheral information register. For example, the decoding unit may perform arithmetic decoding on the pixels.

  Another aspect of the present invention also relates to an image decoding apparatus. This apparatus includes an entropy decoding block that entropy-decodes an encoded image, an inverse quantization unit that inversely quantizes entropy-decoded data, and an inverse conversion unit that performs spatial frequency inverse transformation on the inversely quantized data. Prepare. The entropy decoding block generates a context information for predicting a decoding result of a pixel by reading the peripheral information from the peripheral information register and a peripheral information register that holds the peripheral information of the pixel when decoding the pixel A context estimation unit, and a decoding unit that decodes the pixel from the generated context information and encoded data of the pixel. The decoding unit decodes one pixel for each unit decoding period, and each unit decoding period At the end, the peripheral information is updated with the decoding result of the pixels decoded in the unit decoding period and written back to the peripheral information register.

  The peripheral information register holds peripheral information of the entire pixel block to be processed, has an output bus width smaller than the number of bits of the peripheral information to be stored, and reads out necessary peripheral information sequentially. The peripheral information may be held by a ring buffer method.

  The context generation unit may generate and retain in advance a piece of context information necessary for the next unit decoding period in a certain unit decoding period. A decoding position calculation unit for specifying a pixel to be decoded may be further provided based on the peripheral information, and a decoding process for a pixel that does not need to be decoded may be skipped.

  A plurality of the context estimation units and the decoding units are provided for parallel processing, the peripheral information register is shared by a plurality of the context estimation units, and the held peripheral information is decoded by a plurality of the decoding units. It may be updated in each unit decoding period according to the result.

  The peripheral information register is provided with a shifter that holds a part of peripheral information held at a storage position other than a position read by a ring buffer method, and the context estimation unit gives an instruction of a shift amount to the shifter Thus, the partial peripheral information may be read out.

  Each of the plurality of context estimation units and the decoding unit executes a decoding process in units of paths corresponding to a plurality of encoding passes of the encoded image, and the position of the peripheral information register referred to in the decoding process by each pass is A control unit that controls the operation timing of the decoding process of each pass may be further included so as to be separated by a predetermined number of pixels.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a computer program, a recording medium, and the like are also effective as an aspect of the present invention.

  According to the present invention, it is possible to decode an encoded image at high speed. Also, decoding of the encoded image can be executed in parallel.

Embodiment 1
FIG. 1 is a configuration diagram of an image decoding apparatus 100 according to the first embodiment. The configuration of the image decoding apparatus 100 can be realized in hardware by a CPU, memory, or other LSI of an arbitrary computer, and is realized in software by a program having a decoding function loaded in the memory. Here, the functional blocks realized by the cooperation are depicted. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  The image decoding apparatus 100 receives an input of a compression encoded image, decodes the input encoded image, and outputs the decoded image. An encoded image is an image obtained by recursively dividing an original image into four frequency subbands, wavelet transforming, and quantizing and then arithmetically encoding. The encoded image conforms to the JPEG2000 standard as an example.

  The encoded image input to the image decoding device 100 may be an encoded frame of a moving image. The image decoding apparatus 100 can reproduce a moving image by continuously decoding each encoded frame of a moving image input as an encoded stream.

  The stream analysis unit 10 analyzes the input encoded image stream, extracts the encoded data, and provides the extracted data to the entropy decoding unit 12. The entropy decoding unit 12 entropy-decodes the encoded data for each bit plane, and gives the quantized wavelet transform coefficient obtained as a result of the decoding to the inverse quantization unit 14.

  The inverse quantization unit 14 inversely quantizes the quantized value of the wavelet transform coefficient and provides the quantized value to the wavelet inverse transform unit 16. The wavelet inverse transform unit 16 inversely transforms the inversely quantized wavelet transform coefficients and outputs the obtained decoded image.

  FIG. 2 is a configuration diagram of the entropy decoding unit 12. The encoded data CD is input from the stream analysis unit 10 to the entropy decoding unit 12. The peripheral information register group 20 is a register that holds peripheral information for a pixel of interest for estimating a context used for arithmetic decoding of the encoded data CD. The context estimation unit 22 estimates the context for predicting the decoding result of the encoded data CD based on the peripheral information held in the peripheral information register group 20 and provides the context label CX to the arithmetic decoding unit 24.

  The arithmetic decoding unit 24 receives the encoded data CD from the stream analysis unit 10 and the context label CX from the context estimation unit 22 as input, obtains a decision D that is a binary decision value by arithmetic decoding, and performs inverse quantum To the conversion unit 14. The decision D output from the arithmetic decoding unit 24 is input to the peripheral information register group 20 at the end of the unit decoding period, that is, in the same cycle as the decoding, and the peripheral information held in the peripheral information register group 20 is arithmetic decoded. Updated by the calculation result by the unit 24.

  The context estimation unit 22 performs a coefficient bit modeling process at the time of decoding in JPEG2000. The coefficient bit modeling process at the time of decoding is a process of determining the context required for the arithmetic decoding while updating the peripheral information using the decoding result by the arithmetic decoding unit 24. Hereinafter, the coefficient bit modeling process at the time of decoding will be described with reference to FIGS.

  The subband image extracted from the encoded stream by the stream analysis unit 10 is divided into small regions called code blocks, and the code block is a decoding processing unit. The subband image has an LL subband having a low frequency component in both the x and y directions of the original image, a low frequency component in one of the x and y directions, and a high frequency component in the other direction. The HL and LH subbands are either HH subbands having high frequency components in both the x and y directions.

The size of the code block is an integer value of a power of ² in which the height and width are in the range of 2 ² to 2 ¹⁰ , and the standard defines that the sum of the height and width indices is 12 or less. In the present embodiment, the code block is described as 32 pixels in length and width.

  FIG. 3 is a diagram for explaining a bit plane formed by slicing a code block for each bit. The bit plane of the code block is composed of a Sign plane that stores the sign of the quantized value of the wavelet transform coefficient, and a plurality of planes from MSB to LSB that give the absolute value of the quantized value of the wavelet transform coefficient. . The entropy decoding unit 12 selects bit planes in order from the higher order bits, and performs decoding processing of each coefficient on the bit plane in units of bit planes.

  FIG. 4 is a diagram for explaining the scanning order when the coefficients on the bit plane are decoded. The bit plane is divided into stripes of 4 pixels in length, and is scanned and decoded in units of stripes. The width of each stripe is the width of the code block, which is 32 pixels in this example. The total number of stripes is 8.

  In each stripe, as indicated by the arrows, the vertical four pixels in the first column are scanned in order from the top, and the decoding process proceeds one pixel at a time, and then the vertical four pixels in the second column are scanned in the same direction. Repeat until the last column. When the decoding process is completed up to the end of the stripe, scanning is performed in the same manner from the leading coefficient of the next stripe, the decoding process is performed, and the process is repeated until the last line of the code block. Note that the decoding of the Sign plane storing the positive and negative signs of the coefficients is appropriately performed when decoding the plane corresponding to the absolute value portion of the coefficients.

  Each coefficient in the code block is identified in two states: significant or insignificant. 1 is assigned if significant, 0 is assigned if not significant, and the significance state of each coefficient is identified by a binary value. At the start of decoding, all coefficients in the code block are not significant.

  Here, the coefficient is significant means a state in which the quantized value of the focused wavelet transform coefficient is known to be not “0” from the results of the decoding processing so far. In other words, it means the state of the wavelet transform coefficient in which a bit of “1” is found while decoding while scanning in units of stripes sequentially from the upper bit plane. Also, the coefficient is not significant means a state where the quantized value of the focused wavelet transform coefficient is “0” or remains “0”. In other words, it means the state of the wavelet transform coefficient in which the bit of “1” has not yet been found during the sequential decoding from the upper bit plane.

  In the coefficient bit modeling process, the context is determined for each coefficient bit based on the significance state of the coefficients around the coefficients on the bit plane. FIG. 5 is a diagram illustrating eight neighboring coefficients adjacent to the periphery of the coefficient X to be decoded on the bit plane (hereinafter referred to as the current coefficient X). The eight neighboring coefficients are two coefficients h0 and h1 adjacent to the current coefficient X in the horizontal direction, two coefficients v0 and v1 adjacent in the vertical direction, and four coefficients d0 to d3 adjacent in the oblique direction. It consists of.

  Since each of the eight neighboring coefficients in FIG. 5 can take two states, which are significant or not significant, there can be 256 contexts as a combination with respect to the current coefficient X. It is collected into 19 kinds of contexts using the sex etc., and these contexts are identified with labels of 0-18. If any neighborhood coefficient is located outside the code block being processed, the neighborhood coefficient is regarded as insignificant and processed.

  Each coefficient bit in the bit plane is decoded based on one of three types of processing paths, that is, an S pass (significance propagation pass), an R pass (magnitude refinement pass), and a C pass (cleanup pass). In the S pass, a non-significant coefficient around which a significant coefficient exists is decoded, in the R pass, a significant coefficient is decoded, and in the C pass, the remaining coefficients are decoded.

  Each processing pass of the S pass, R pass, and C pass has a large contribution to the image quality in this order. Each processing pass is executed in this order, and the context of each coefficient is determined in consideration of information on neighboring coefficients. Hereinafter, a specific processing procedure in each processing path will be described. First, the S pass process will be described.

  When the current coefficient X is insignificant in scanning in each stripe of the bit plane, and at least one of the eight neighboring coefficients adjacent to the current coefficient X is significant, the current coefficient X is It is selected as an S pass processing target. In other cases, it is not an S pass processing target. A coefficient to be decoded in the S pass is a coefficient that is most likely to be significant in the bit plane.

  The context estimation unit 22 Σhi (= h0 + h1) that gives the number of significant coefficients among the two neighboring coefficients h0 and h1 in the horizontal direction, and the two neighboring coefficients v0, Σvi (= v1 + v2) that gives the number of significant coefficients in v1, and Σdi (= d1 + d2 + d3 + d4) that gives the number of significant coefficients among the four neighboring coefficients d0, d1, d2, and d3 in the diagonal direction Ask for.

  FIG. 6 is a diagram for explaining a context classification table in the S pass. This context table shows the number of neighborhood coefficients Σhi, Σvi that are significant in the horizontal, vertical, and diagonal directions depending on whether the code block being processed belongs to the LH / LL subband, HL subband, or HH subband. , Σdi and nine kinds of context labels CX identified by labels 0 to 8 are associated with each other. The context estimation unit 22 refers to the context classification table, and determines nine types of coefficients to be processed in the S path according to the combination of the directionality of subband frequency components and the number of neighboring coefficients Σhi, Σvi, Σdi that are significant. And the corresponding context label CX is output.

  In the S pass, when the value of the bit of the current coefficient X is “1”, the significance state of the current coefficient X is changed from “not significant” to “significant”. When the current coefficient X becomes significant, the polarity bit indicating the sign of the current coefficient X is subsequently decoded.

  The context for the polarity bit is determined in the following two steps based on the significance state and the positive and negative polarity values of the two neighboring coefficients v0, v1 in the vertical direction and the two neighboring coefficients h0, h1 in the horizontal direction.

  FIG. 7 is a diagram for explaining a vertical index and a horizontal index table for determining the context of the polarity bit. The context estimation unit 22 first determines whether each of the two vertical neighborhood coefficients v0 and v1 is a positive significant coefficient, a negative significant coefficient, or a nonsignificant coefficient. Referring to the table of FIG. 7, any value of “0”, “1”, “−1” is assigned to the vertical index v. Similarly, any one of “0”, “1”, and “−1” is assigned to the horizontal index h with reference to the table of FIG. 7 for the horizontal neighborhood coefficients h0 and h1.

  FIG. 8 is a table in which combinations of horizontal indices h and vertical indices v are associated with context labels CX for five types of polarity bits identified by labels 9 to 13. The context estimation unit 22 refers to the table of FIG. 8 and classifies the polarity bits into one of five types of contexts according to the combination of the obtained horizontal index h and vertical index v values, and outputs the corresponding context label CX. To do.

  Next, R path processing will be described. When it is determined that the current coefficient X is already significant, the current coefficient X becomes an R path processing target in the bit plane being processed. However, a coefficient that has changed to a significant state in the immediately preceding S pass in the bit plane is not processed. The R-pass decoding process has a role of increasing the accuracy of the coefficients decoded in the S-pass.

  FIG. 9 is a diagram showing a context classification table in the R path. In the R path, the context estimation unit 22 obtains a value of Σhi + Σvi + Σdi indicating the number of significant coefficients among the eight neighboring coefficients for the current coefficient X, and further, the current coefficient X is significantly higher in the bit plane one level higher. In other words, it is determined whether or not the current R path is the first path after the current coefficient X has changed from a non-significant state to a significant state. As shown, it is classified into three types of contexts identified by labels 14 to 16, and the corresponding context label CX is output.

  Finally, the C pass process will be described. The C path is used when the current coefficient X does not correspond to either the S path or the R path. In the C pass, run length decoding or decoding processing referring to the values of eight neighboring coefficients as in the S pass is performed. In the C pass, the process proceeds while determining whether to perform run-length decoding.

  FIG. 10 is a diagram illustrating a context classification table in the C path. In the C path, all four consecutive coefficients in the vertical direction are not significant, that is, all the vertical columns in the stripe belong to the C path, and the eight neighboring coefficients for all the four coefficients are also significant. It is determined whether or not the condition that there is no coefficient is. When this condition is satisfied, the decoding process is performed in the run length mode, and the context label CX is 17. If this condition is not met, there is at least one significant coefficient among the four consecutive coefficient values in the vertical direction. Therefore, the position of the first significant coefficient is determined using the UNIFORM context, and the context label at this time CX is 18. The same processing as in the S pass is performed for all remaining coefficients.

  As described above, in the coefficient bit modeling process by the context estimation unit 22, the context label CX of each coefficient on the bit plane is determined using any one of the three processing paths.

  The peripheral information register group 20 is provided with five types of 32-bit vertical and horizontal registers corresponding to the size of one bit plane of the code block, and holds peripheral information of the entire code block. The first to fifth registers constituting the peripheral information register group 20 store information necessary for the context estimation unit 22 to obtain the context label CX in each processing path in the bit plane.

  The first register of the peripheral information register group 20 stores information indicating whether each coefficient is significant or not significant. The second register stores information indicating whether each coefficient has become significant in the bit plane one level above, and is used in the R path processing. The third register stores information indicating whether each coefficient has become significant in the current bit plane. This is necessary to generate the information in the second register. The fourth register stores information indicating whether or not each coefficient has already been decoded, and is used in the C pass process. The information in the fourth register can be calculated from the information in the first register and the third register, but the information is held separately for convenience of processing. The fifth register stores polarity information indicating the sign of each coefficient.

  The contents of the first and fifth registers are reset to zero when the code block processing starts or ends. The contents of the second register are initialized by copying the contents of the third register at the start or end of processing of the bit plane. The contents of the third and fourth registers are reset to zero when the bit plane processing starts or ends.

  FIG. 11 is a diagram for explaining the configuration of each register of the peripheral information register group 20. Each of the five types of registers included in the peripheral information register group 20 has a configuration in which registers corresponding to the stripe size are arranged by the number of stripes in accordance with the code block being scanned and decoded in units of stripes. Take. Each register row has 4 bits in length corresponding to 4 pixels in the vertical direction of the stripe, and 32 bits in width corresponding to 32 pixels in the width of the code block.

  Each register row is divided into four bits in the horizontal direction, such as R00 to R07, R10 to R17,..., R70 to R77, and R00, R10, and R00, R10, which are hatched at the left end for speeding up and downsizing ..., a shift register that can read and write only to the four bits of R70. Hereinafter, a 4-bit segment is called a register block.

  Note that only in the case of the first and fifth registers, it is necessary to refer to the neighborhood coefficient in the S pass process, and therefore it is possible to read one pixel on the left and right of the leftmost register block. That is, the leftmost register blocks R01, R11,..., R71 and the left one bit of each register block R00, R10,. It is assumed that the right one bit of each register block R07, R17,.

  12A and 12B are diagrams for explaining the operation of each register row in FIG. FIG. 12A shows a register string of stripe 0 as an example, which is divided into register blocks R00 to R07 by 4 bits, and can be read from and written to the leftmost register block R00. This register functions like a ring buffer or barrel shifter. As shown in FIG. 12B, the R00 at the left end is moved to the right end, and the remaining R01 to R07 are sequentially shifted to the left by 4 bits. Thus, the register location that can be read and written can be shifted by 4 bits.

  In this embodiment, for each plane, the processing path is sequentially executed in the order of the S path, the R path, and the C path, so the decoding operation is as follows. First, the C pass process is executed for each stripe of the MSB plane, and each register string is shifted 7 times by 4 bits, whereby each stripe is processed to the end, and returns to the beginning by the eighth shift. Next, the S pass processing is executed for each stripe in the plane immediately below the MSB, and each stripe is processed 7 times by shifting 4 bits by 7 times. Return. In this state, the R pass processing is executed for each stripe of the same plane, and similarly, by shifting 7 times by 4 bits, each stripe is processed to the end, and the first shift returns. Thereafter, the C pass process is similarly executed. By repeating this up to the LSB plane, the decoding process for the code block ends.

  During the decoding process of the code block, the content of the peripheral information held in the peripheral information register group 20 is determined in the decoding cycle every time the arithmetic decoding unit 24 decodes one bit plane coefficient and determines the decision D. Updated.

  As described above, according to the present embodiment, since the peripheral information necessary for estimating the context of each coefficient is held in the register, the peripheral information is read at high speed, the context is estimated, and the arithmetic decoding unit Can be given to. Further, the peripheral information held in the register can be updated in the same cycle as the arithmetic decoding by using the calculation result by the arithmetic decoding. When peripheral information is held in a memory such as SRAM, addressing is required, and it takes several cycles to read and write, which slows down processing. However, by holding peripheral information in a register, a series of processes necessary for decoding is performed. That is, reading of peripheral information, estimation of context, decoding of arithmetic code, and updating of peripheral information can be performed in the same cycle, and decoding of one pixel can be processed in one cycle, thereby speeding up decoding processing. Can be achieved.

Embodiment 2
FIG. 13 is a configuration diagram of the entropy decoding unit 12 in the image decoding apparatus according to Embodiment 2. The image decoding apparatus according to the present embodiment is different from the image decoding apparatus 100 according to the first embodiment only in the configuration of the entropy decoding unit 12, and the other configurations are the same.

  In the entropy decoding unit 12 of the present embodiment, a context register 23 for holding the context label CX calculated in advance by the context estimation unit 22 is provided in the subsequent stage of the context estimation unit 22.

  A decision D obtained as a result of decoding the encoded data CD by the arithmetic decoding unit 24 is fed back to the peripheral information register group 20, and the contents held in each register are updated as appropriate. In order to estimate the context, the updated peripheral information register group 20 is referred to. In the present embodiment, the context estimation unit 22 further receives the value of the decision D from the arithmetic decoding unit 24 directly without passing through the peripheral information register group 20, thereby requiring a context label required in the next cycle. CX is obtained first, and the context register 23 latches the context label CX. The arithmetic decoding unit 24 receives the context label CX latched in the context register 23 and advances decoding of the encoded data CD.

  According to the present embodiment, in parallel with the calculation of the normal context label CX using the peripheral information register group 20, the context label CX can be calculated by bypassing the peripheral information register group 20, and the arithmetic decoding unit By using the context label CX in which 24 is latched, the speed of the decoding process can be further increased.

Embodiment 3
FIG. 14 is a configuration diagram of the entropy decoding unit 12 in the image decoding device according to Embodiment 3. The image decoding apparatus according to the present embodiment also differs from the image decoding apparatus 100 according to the first embodiment only in the configuration of the entropy decoding unit 12, and the other configurations are the same.

  The entropy decoding unit 12 according to the present embodiment proceeds the decoding process while specifying the location of the coefficient to be decoded instead of scanning all the coefficients when decoding while scanning the stripe of the bit plane.

  The decoding position calculation unit 27 refers to the peripheral information held in the peripheral information register group 20 and calculates the position of the coefficient to be decoded in each processing pass.

  FIGS. 15A to 15C are diagrams illustrating the decoding position calculation procedure by the decoding position calculation unit 27. FIG. FIG. 15 (a) shows the order of decoding by scanning the minimum processing unit 60 of 4 pixels vertically and horizontally by 4 pixels in the vertical direction, and usually the peripheral information is displayed pixel by pixel in this scanning order. Inspect and decrypt.

  In the S pass, if any significant coefficient exists around a non-significant coefficient, decoding is performed. Information on eight neighboring coefficients for a certain coefficient can be used in part as peripheral information for other coefficients. Therefore, the next information can be obtained from the peripheral information obtained so far without checking the peripheral information for all pixels. The coefficient to be decoded can be specified. For example, as shown in FIG. 15B, it is assumed that the coefficient indicated by reference numeral 51 is significant among the neighboring coefficients 52 surrounded by eight dotted lines with respect to the coefficient 50 indicated by the diagonal line at the upper left corner. At this time, for example, it can be seen that at least one of the eight neighboring coefficients 54 is significant with respect to the second coefficient 53 indicated by hatching, so that the second coefficient 53 is determined as a coefficient to be decoded. can do. FIG. 15 (c) shows a state in which the coefficients 50, 53, 55 determined to be decoded in this way are sequentially traced.

  The peripheral information reading unit 28 reads the peripheral information for the position specified by the decoding position calculation unit 27 from the peripheral information register group 20 and supplies the information to the context estimation unit 22. The decision D by the arithmetic decoding unit 24 is stored in the image buffer 26 based on the position L determined by the decoding position calculation unit 27. The decoded wavelet transform coefficients written in the image buffer 26 are output to the inverse quantization unit 14. When the decoding of a predetermined unit such as a code block unit or a stripe unit is completed, the image buffer 26 is reset before storing the result of the next decoding unit.

  According to the present embodiment, by referring to the contents of the peripheral information register group 20, it is possible to specify a coefficient to be decoded next in each processing pass and skip processing of a coefficient that does not need to be decoded. Further, it is possible to further speed up the decoding process.

Embodiment 4
FIG. 16 is a configuration diagram of the entropy decoding unit 12 in the image decoding apparatus according to the fourth embodiment. The image decoding apparatus according to the present embodiment also differs from the image decoding apparatus 100 according to the first embodiment only in the configuration of the entropy decoding unit 12, and the other configurations are the same.

  In the present embodiment, two context estimation units 22a and 22b and two arithmetic decoding units 24a and 24b are provided to decode two pixels in parallel. The first context estimation unit 22a estimates the context label CX1 for the first pixel, and based on the context label CX1, the first arithmetic decoding unit 24a performs the decoding process for the first pixel, and the first decision D1 is output. On the other hand, the second context estimation unit 22b estimates the context label CX2 for the second pixel, and based on the context label CX2, the second arithmetic decoding unit 24b performs the decoding process for the second pixel, and the second The decision D2 is output.

  The update determination unit 25 needs to update the information input to the second arithmetic decoding unit 24b by the decoding result of the first arithmetic decoding unit 24a with the value of the first decision D1 of the first arithmetic decoding unit 24a. If it is necessary, the result of decoding by the first arithmetic decoding unit 24a is given to the second arithmetic decoding unit 24b. The first and second arithmetic decoding units 24a and 24b exchange probability estimates with each other to improve the accuracy of arithmetic decoding.

  Both the first and second decisions D1 and D2 by the first and second arithmetic decoding units 24a and 24b are fed back to the peripheral information register group 20, and the information held in each register is updated.

  In the present embodiment, context registers 23a and 23b are further provided in the subsequent stage of the first and second context estimation units 22a and 22b, as in the second embodiment, and the context labels CX1 and CX2 are latched. You may comprise.

Embodiment 5
FIG. 17 is a configuration diagram of the entropy decoding unit 12 in the image decoding apparatus according to Embodiment 5. The image decoding apparatus according to the present embodiment also differs from the image decoding apparatus 100 according to the first embodiment only in the configuration of the entropy decoding unit 12, and the other configurations are the same.

  In the present embodiment, the entropy decoding unit 12 of the third embodiment shown in FIG. 14 has a configuration changed so that parallel decoding of two pixels is possible. Two peripheral information reading units 28a, 28b, two context estimation units 22a and 22b, and two arithmetic decoding units 24a and 24b are provided.

  The decoding position calculation unit 27 refers to the peripheral information held in the peripheral information register group 20 by the method described in the third embodiment, and calculates the position of the coefficient to be decoded in each processing path. In the embodiment, for parallelization, two coefficients to be decoded are obtained, and the positions L1 and L2 are given to the first and second peripheral information reading units 28a and 28b, respectively. The first and second peripheral information reading units 28a and 28b respectively read the peripheral information for the positions L1 and L2 designated by the decoding position calculation unit 27 from the peripheral information register group 20, and the first and second context estimation units 22a and 22b.

  Thereafter, the parallel decoding operation of two pixels by the first and second context estimation units 22a and 22b, the first and second arithmetic decoding units 24a and 24b, and the update determination unit 25 is the same as in the fourth embodiment. is there.

  The image buffer 26 stores the first and second decisions D1 and D2 output from the first and second arithmetic decoding units 24a and 24b based on the positions L1 and L2 given from the decoding position calculation unit 27. The

  Note that, in the present embodiment, context registers 23a and 23b are further provided in the subsequent stage of the first and second context estimation units 22a and 22b, as in the second embodiment, and the context label CX is latched. May be.

Embodiment 6
FIG. 18 is a configuration diagram of the entropy decoding unit 40 in the image decoding apparatus according to the sixth embodiment. The image decoding apparatus according to the present embodiment is obtained by replacing the configuration of the entropy decoding unit 12 of the image decoding apparatus 100 according to the first embodiment with the entropy decoding unit 40 shown in FIG. This is the same as the image decoding device 100.

  The entropy decoding unit 40 according to the present embodiment performs parallel processing in units of bit planes and processing paths. For the parallel processing in units of bit planes, the first bit plane decoding unit 30a and the second bit plane decoding are performed. A portion 30b is provided. Further, in order to parallelize each processing path unit of the S path, the R path, and the C path, the first bit plane decoding unit 30a and the second bit plane decoding unit 30b include an S, R, and C path decoding unit. 12S, R path decoding unit 12R, and C path decoding unit 12C are included.

  When the input encoded image has a format in which the number of bytes of the encoded stream of each pass is specified in the header, the stream analysis unit 10 extracts the encoded stream for each pass and performs parallel processing in units of passes. Is possible. In this case, the encoded streams of the S pass, the R pass, and the C pass are provided from the stream analysis unit 10 to the S, R, C pass decoding unit 12S, the R pass decoding unit 12R, and the C pass decoding unit 12C, respectively, and decoded. It is processed. The S, R, and C path decoding unit 12S performs a dedicated decoding process on the S path, and in parallel, the R path decoding unit 12R performs a dedicated decoding process on the R path and the C path decoding unit 12C. Each path is decoded in parallel.

  If the number of bytes of the encoded stream of each pass is not specified in the header of the encoded image, the path delimiter cannot be known, so that parallel processing in units of passes cannot be performed. When parallel processing in units of paths cannot be performed, the stream analysis unit 10 sequentially provides each of the S-pass, R-pass, and C-pass encoded streams to the S, R, and C-pass decoding units 12S, and the S, R, and C-pass decoding units 12S sequentially decodes each path in the order of S path, R path, and C path. At this time, the R path decoding unit 12R and the C path decoding unit 12C do not operate.

  Each of the decoding units 12S, 12R, and 12C for each path may have the configuration of any of the entropy decoding units 12 of the first to fifth embodiments. A mode including a plurality of configurations of one entropy decoding unit 12 will be described.

  The decoding units 12S, 12R, and 12C for each path of the first bit plane decoding unit 30a include a context estimation unit 22 and an arithmetic decoding unit 24, respectively, and the context estimation unit 22 reads peripheral information from the peripheral information register group 20 The context label is calculated and given to the arithmetic decoding unit 24. The arithmetic decoding unit 24 decodes the encoded data of each pass based on the context label and writes the decoded data to the first data register 32a.

  The same applies to the second bit plane decoding unit 30b. The same peripheral information register group 20 is shared, the paths of the second bit plane are decoded in parallel, and the result is output to the second data register 32b. . For the first bit plane decoding unit 30a, the data flow is illustrated by a solid line, and for the second bit plane decoding unit 30b, the data flow is illustrated by a dotted line.

  Of the five types of registers in the peripheral information register group 20, the fifth register is a Sign plane indicating the sign of the coefficient in the code block. The data output unit 34 reads the decoding result of the first bit plane by the first bit plane decoding unit 30a from the first data register 32a, and the decoding result of the second bit plane by the second bit plane decoding unit 30b is the second Read from the data register 32b, and further read polarity data indicating the sign of the coefficient from the Sign plane of the peripheral information register group 20, and finally a decoded code block 36 consisting of the Sign plane and the plane from the MSB to the LSB. The decryption result is output in the form of

  In this embodiment, the peripheral information register group 20 is shared by two bit planes, and further shared by each processing path in each bit plane. Therefore, the configuration of the peripheral information register group 20 is partially different from that of the first to fifth embodiments. Hereinafter, the configuration and parallel operation of the peripheral information register group 20 will be described in detail.

  FIG. 19 is a diagram showing a minimum processing unit 60 of 4 pixels in the vertical and horizontal directions in each stripe of the bit plane, a total of 16 pixels, and a neighboring pixel group in the vicinity thereof. The minimum processing unit 60 is a unit for reading peripheral information from each register of the peripheral information register group 20, and corresponds to a register block of each register row. As already described in the first embodiment, in the S pass, information on the significance state of eight neighboring coefficients is necessary for the coefficient to be processed. For this reason, when decoding processing is performed for each pixel in an area of 4 pixels in the vertical and horizontal directions, peripheral information is necessary for adjacent pixels indicated by hatching.

  The adjacent pixel groups 62 and 64 each having 6 pixels on the upper and lower sides are not located on the stripe, but are located on the upper and lower stripes. Further, the adjacent pixel groups 61 and 63 each having four pixels on the left and right are located at the position of the adjacent register block in the same stripe.

  FIG. 20 is a diagram illustrating the corresponding positions on the register of the adjacent pixel groups 61 to 64 around the minimum processing unit 60 of FIG. It is assumed that at a certain time, the stripe 2 is an R path processing target, the stripe 3 is an S path processing target, and the stripe 4 is a C path processing target of the previous bit plane.

  In the R path, the peripheral information is read from the register block R22 currently located at the left end and the decoding process is performed on the stripe 2. In the S pass, the peripheral information is read from the register block R34 currently positioned at the left end and the decoding process is performed on the stripe 3. In the C path, the peripheral information is read from the register block R46 currently located at the left end and the decoding process is performed on the stripe 4. As described above, in parallel processing in units of processing paths, the decoding location of each processing path is controlled so as to be shifted by at least two blocks in the horizontal direction in order to avoid the influence of the update of the peripheral information.

  When attention is paid to the register block R34 that the S path refers to in the decoding process of the stripe 3, the minimum processing unit 60 is at the position of the register block R34. On the other hand, the adjacent pixel groups 62 and 64 of the upper and lower 6 pixels are at the positions of the register block R24 of the stripe 2 and the register block R44 of the stripe 4, respectively. Further, the adjacent pixel groups 61 and 63 of the four pixels on the left and right are respectively at the positions of the register blocks R33 and R35 of the stripe 3. In order to perform the S pass process, it is necessary to extract the peripheral information of these adjacent pixel groups 61 to 64 from the register blocks at the respective positions.

  FIG. 21 is a diagram for explaining the configuration of the first and fifth registers of the peripheral information register group 20. Similar to each register of the peripheral information register group 20 of the first embodiment, register strings corresponding to the stripes of the bit plane are arranged, and each register string is shifted on the ring independently by 4 bits each like a ring buffer. Thus, reading and writing are possible from the left end. In the present embodiment, the leftmost register blocks R00, R10,..., R70, the right adjacent register blocks R01, R11,. Thus, a total of 6 bits are output, including 1 bit on the right side of each register block R07, R17,.

  Further, only in the first and fifth registers, the upper-end 1 bit string traversing all the register blocks in each register string corresponding to the stripes 1 to 7 is input to and held in the shifters 71 to 77, respectively. The lower end 1-bit string traversing all the register blocks in each register string corresponding to the stripes 0 to 6 is input to and held in the shifters 80 to 86, respectively. Each of the shifters 71 to 77 and 80 to 86 has an input of 32 bits and an output of 6 bits. By giving a shift amount instruction, the adjacent pixels of the upper and lower 6 pixels described in FIG. 20 are output. . As described above, in the first and fifth registers, a total of 14 shifters 71 to 77 and 80 to 86 are provided for reading upper and lower adjacent pixels.

  Note that the second, third, and fourth registers in the peripheral information register group 20 do not need to read information on adjacent pixels, and therefore may have the same configuration as the register of the first embodiment. In the first embodiment, since the path unit is not parallelized, it is not necessary to shift the path processing in each stripe. In the first embodiment, the first and fifth registers are also configured as shifters. Note that was not required.

  Referring to FIG. 20 again, the shift amount given to the shifter in order to extract the upper and lower adjacent pixels with the shifter will be described. The shift amount for extracting the lower adjacent pixel 44 is obtained by subtracting the horizontal position of the register block R34 currently referenced by the S path, that is, 4 from the horizontal position of the register block R46 currently referenced by the C path, that is, 6. The shift amount is 2. The context estimation unit 22 shifts the 32-bit information held by the shifter to the right by two blocks by giving a shift amount 2 to the upper shifter 74 of the register row corresponding to the stripe 4 in FIG. The peripheral information of the adjacent pixel 44 can be extracted.

  Similarly, the shift amount for extracting the upper adjacent pixel 42 is changed from the horizontal position of the register block R22 currently referred to by the R path, that is, 2 to the horizontal position of the register block R34 currently referred to by the S path, that is, 4. The shift amount is -2. The context estimation unit 22 shifts the 32-bit information held by the shifter by two blocks to the left by giving a shift amount −2 to the lower shifter 82 of the stripe 2 in FIG. The peripheral information of the pixel 42 can be taken out.

  FIG. 22 is a diagram illustrating a state in which the peripheral information register group 20 is shared and parallel processing is performed in units of bit planes and paths. In the figure, at a certain time, the stripe 7 processes the C path of the previous bit plane, and the stripes 6, 5, and 4 process the S path, R path, and C path of the current bit plane, respectively. In 3, 2, and 1, the S path, R path, and C path of the next bit plane (here, the least significant bit plane) are respectively processed, and in stripe 0, the first C path of the next code block is processed. Indicates the state being processed. The register blocks referred to in the respective processing paths are indicated by hatching. Actually, the hatched register block is located at the left end, but here, for convenience of explanation, the register block of each register column is not shifted, and the position of the referenced register block is shifted for illustration. ing.

  When parallelization is performed in units of paths, adjacent pixels may overlap in the first and fifth registers. If adjacent pixels overlap, there is an influence by updating peripheral information. Therefore, control is performed so that the register block referred to by each processing path is shifted by 2 in the horizontal direction in the upper and lower stripes so that adjacent pixels do not overlap.

  For example, the horizontal position of the register block R66 referenced by the S path in the stripe 6 and the horizontal position of the register block R54 referenced by the R path in the stripe 5 are shifted by two blocks. If the two blocks are shifted in this way, the adjacent pixels on the upper and lower sides do not overlap, so that even if the peripheral information is updated, there is no influence.

  In parallel processing in units of paths, control is performed so that the decoding position of its own processing path is shifted by at least two blocks in the horizontal direction from the decoding position of the previous path. For this reason, when the difference between the decoding positions in the upper and lower stripes is smaller than two blocks, a timing control unit is provided for controlling the processing path to stop and restart the operation at a timing shifted by at least two blocks. .

  FIG. 23 is a timing chart illustrating decoding start timing control for each processing path. The stripe processing timing of each processing path by the first bit plane decoding unit 30a (hereinafter abbreviated as BP0) and the stripe processing timing of each processing path by the second bit plane decoding unit 30b (hereinafter abbreviated as BP1). It is shown.

  At time t1, C path processing by BP0 is started for the MSB brain. st0 to st7 illustrate the processing timing of the stripes 0 to 7, respectively. At time t2, S path processing by BP1 is started in the second plane. Here, the time t2 when the S pass process by the BP1 starts to decode the stripe 0 is when the C pass process by the BP0 proceeds to the stripe 1 and the position of the register block to be referenced is separated by 2 blocks. This timing control will be described with reference to FIG.

  FIG. 24 is a timing chart for explaining in detail the decoding start timing control of FIG. In the upper part, the timing of decoding processing of stripe 0 and stripe 1 of the C path by BP0 is shown in units of processing of register blocks R00 to R07 and R10 to R17. In the lower part, the timing of decoding processing of S-path stripe 0 by BP1 is shown in units of processing of register blocks R00 to R07.

  At the time point t2 when the C pass processing by BP0 has advanced to the position of the third register block R12 of the stripe 1, the S pass processing by BP1 starts at the position of the first register block R00 of the stripe 0. At this time, since the decoding position of each pass is shifted by 2 blocks between the stripe 1 and the stripe 0, the overlapping of adjacent pixels does not occur. Thereafter, the C-pass process using BP0 is performed for the stripe 1 and the S-pass process using BP1 is performed for the stripe 0 with a shift of 2 blocks.

  At time t7, the decoding process of the position of the second register block R01 in stripe 0 is completed in the S pass process by BP1, but the decoding of the position of the fourth register block R13 in stripe 1 is completed in the C pass process by BP0. Processing takes time and is not finished yet. At this time, the S pass processing of stripe 0 by BP1 is temporarily stopped.

  At time t8, when the decoding process of the position of the fourth register block R13 of stripe 1 is completed by the C path process of BP0, the S path process of stripe 0 by BP1 is resumed and the decoding of the position of the third register block R02 is resumed. Start processing. At this time, the C-pass process of stripe 1 by BP0 starts the decoding process of the position of the fifth register block R14. By this operation timing control, the C path process for stripe 1 and the S path process for stripe 0 are held in a state shifted by two blocks.

  Returning to FIG. 23 again, at time t3, the R path by BP1 starts decoding the stripe 0 of the second plane. Here, the time t3 when the R-pass processing by BP1 starts to decode the stripe 0 is when the S-pass processing by BP1 proceeds to the stripe 1 and the position of the register block to be referenced is separated by 2 blocks. This timing control is the same as in FIG. Thereafter, similarly, at time t4, the C-pass process by BP1 starts decoding stripe 0.

  Further, at time t5 when the C path processing by BP1 advances to stripe 1 and the position of the register block to be referred advances by two blocks, the S pass processing by BP0 starts decoding stripe 0 of the third plane. Similarly, at time t6, the R path processing by BP0 starts to decode stripe 0.

  In this way, processing of each path of the two bit planes is executed in parallel while sharing the peripheral information register group 20.

  FIG. 25 is a timing chart illustrating code block decoding start timing control. The upper part shows the decoding timing of each stripe in the S pass, R pass, and C pass by BP0. The lower part shows the decoding timing of each stripe in the S pass, R pass, and C pass by BP1. The process of the current code block is hatched, and the process of the next code block is not hatched.

  In BP0, the LSB plane of the current code block is processed in the order of the S pass, the R pass, and the C pass, and the process of the last C pass of the code block is completed at time t11. On the other hand, in BP1, processing proceeds in the order of the S pass, R pass, and C pass for the plane immediately above the LSB of the current code block, and the plane at time t10 earlier than the decoding end time t11 of the code block of BP0. The C path processing has been completed. Therefore, without waiting for the time t11 when the last pass of the code block is finished by BP0, at the time t10 when the C pass of the plane immediately before LSB is finished by BP1, the first C pass of the next code block by BP1. Start processing. By this operation control, the C path processing of the MSB plane of the next code block can be executed continuously at an early stage.

  Thereafter, after the C path processing by BP1 proceeds to stripe 1 of the MSB plane, the S path processing by BP0 starts from stripe 0 of the next plane. Thereafter, an R path process and a C path process by BP0, and an S path process and an R path process by BP1 are started in order. The processing start timing control of each path is as already described with reference to FIGS.

  As described above, according to the present embodiment, using the fact that the decoding units 12S, 12R, and 12C of each path share the peripheral information register group 20 and can complete a series of decoding processes in one cycle, Arithmetic decoding can be performed in parallel in bit plane units and path units. Since arithmetic decoding is performed while updating peripheral information, it is generally difficult to parallelize decoding processing. However, in this embodiment, the peripheral information register group 20 can be updated in the same cycle as arithmetic decoding. In addition to parallelization in units of planes, fine parallelization in units of paths is also possible. Further, if the header of the encoded image does not include information on the number of bytes of each pass, parallelization can be performed at least in bit plane units.

  The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. . Such a modification is shown below.

  The image decoding apparatus according to any of the above embodiments may be integrated with an image encoding apparatus that compresses and encodes an input original image by the JPEG2000 method. In this case, the image decoding apparatus and the image encoding apparatus The peripheral information register may be shared, and the image encoding apparatus may be provided with an arithmetic encoding unit that uses the same peripheral information register as that used for decoding. However, in the case of encoding, since the contents of the peripheral information register can be created in advance from the original image data, it is not necessary to update the contents of the peripheral information register with the calculation results as in decoding.

  The image decoding apparatus according to the above embodiment is incorporated in a digital camera including an image capturing block and an image encoding unit that arithmetically encodes a captured image, and is used to decode and reproduce the arithmetically encoded image. May be. Further, the image decoding apparatus according to the above-described embodiment may be incorporated in a signal processing unit of a surveillance camera and used for decoding and reproduction of a surveillance image encoded by the JPEG2000 system. The image data captured and encoded by the surveillance camera may be transmitted via the network, and the image decoding apparatus connected to the network may decode and reproduce the encoded image data received from the network.

1 is a configuration diagram of an image decoding device according to Embodiment 1. FIG. It is a block diagram of the entropy decoding part of FIG. FIG. 3 is a diagram illustrating a bit plane of a code block that is decoded by an entropy decoding unit in FIG. 2. It is a figure explaining the scanning order at the time of decoding the coefficient on a bit plane. It is a figure explaining the neighborhood coefficient adjacent to the circumference | surroundings of the coefficient of the decoding object on a bit plane. It is a figure explaining the context classification table in S pass processing. It is a figure explaining the vertical parameter | index for determining the context of a polarity bit, and a horizontal parameter | index table. It is a figure which shows the classification table of the context with respect to a polarity bit. It is a figure which shows the classification table of the context in R path | pass process. It is a figure which shows the classification table of the context in C path | pass processing. It is a figure explaining the structure of each register | resistor of a peripheral information register group. It is a figure explaining operation | movement of each register row | line | column of FIG. 6 is a configuration diagram of an entropy decoding unit in an image decoding apparatus according to Embodiment 2. FIG. FIG. 10 is a configuration diagram of an entropy decoding unit in an image decoding device according to Embodiment 3. It is a figure explaining the calculation procedure of the decoding position by the decoding position calculation part of FIG. FIG. 10 is a configuration diagram of an entropy decoding unit in an image decoding device according to Embodiment 4. FIG. 10 is a configuration diagram of an entropy decoding unit in an image decoding device according to Embodiment 5. FIG. 10 is a configuration diagram of an entropy decoding unit in an image decoding device according to a sixth embodiment. It is a figure which shows the minimum process unit in each stripe of a bit plane, and the adjacent pixel group of the circumference | surroundings. It is a figure explaining the corresponding position on the register | resistor of the adjacent pixel group around the minimum processing unit of FIG. It is a figure explaining the structure of the 1st, 5th register of a peripheral information register group. It is a figure explaining a mode that a peripheral information register group is shared and parallel processing is performed per bit plane and path. It is a figure explaining the decoding start timing control of each process path. It is a figure explaining the decoding start timing control of FIG. 23 in detail. It is a figure explaining the decoding start timing control of a code block.

Explanation of symbols

  10 stream analysis unit, 12 entropy decoding unit, 14 inverse quantization unit, 16 wavelet inverse transformation unit, 20 peripheral information register group, 22 context estimation unit, 23 context register, 24 arithmetic decoding unit, 25 update determination unit, 26 image buffer 27 decoding position calculation unit, 28 peripheral information reading unit, 30a first bit plane decoding unit, 30b second bit plane decoding unit, 12S S, R, C path decoding unit, 12R R path decoding unit, 12C C path decoding unit 40 Entropy decoding unit, 100 Image decoding device.

Claims (8)

When decoding a pixel, a peripheral information register that holds peripheral information of the pixel;
A context estimation unit that reads out the peripheral information from the peripheral information register and generates context information for predicting a pixel decoding result;
A decoding unit for decoding the pixel from the generated context information and the encoded data of the pixel,
The decoding unit decodes one pixel every unit decoding period, and at the end of each unit decoding period, updates the peripheral information with the decoding result of the pixels decoded in the unit decoding period, and stores it in the peripheral information register. An image decoding apparatus characterized by writing back. An entropy decoding block for entropy decoding the encoded image;
An inverse quantization unit for inversely quantizing the entropy decoded data;
An inverse transform unit that performs inverse spatial frequency transform on the inversely quantized data;
The entropy decoding block is:
When decoding a pixel, a peripheral information register that holds peripheral information of the pixel;
A context estimation unit that reads out the peripheral information from the peripheral information register and generates context information for predicting a pixel decoding result;
A decoding unit for decoding the pixel from the generated context information and the encoded data of the pixel,
The decoding unit decodes one pixel every unit decoding period, and at the end of each unit decoding period, updates the peripheral information with the decoding result of the pixels decoded in the unit decoding period, and stores it in the peripheral information register. An image decoding apparatus characterized by writing back.   The peripheral information register holds peripheral information of the entire pixel block to be processed, has an output bus width smaller than the number of bits of the peripheral information to be stored, and reads necessary peripheral information sequentially. The image decoding apparatus according to claim 1 or 2, wherein the peripheral information is held by a ring buffer method.   4. The image decoding device according to claim 1, wherein the context generation unit previously generates and holds context information required in a next unit decoding period in a certain unit decoding period. 5. .   5. The method according to claim 1, further comprising a decoding position calculation unit that specifies a pixel to be decoded based on the peripheral information, and skipping a decoding process of a pixel that does not need to be decoded. Image decoding apparatus. A plurality of the context estimation unit and the decoding unit are provided for parallel processing,
2. The peripheral information register is shared by a plurality of the context estimation units, and the held peripheral information is updated in each unit decoding period by a decoding result of the plurality of decoding units. 6. The image decoding device according to any one of 1 to 5.   The peripheral information register is provided with a shifter that holds a part of peripheral information held at a storage position other than a position read by a ring buffer method, and the context estimation unit gives an instruction of a shift amount to the shifter The image decoding apparatus according to claim 6, wherein the partial peripheral information is read out.   Each of the plurality of context estimation units and the decoding unit performs a decoding process in units of paths corresponding to a plurality of encoding passes of the encoded image, and the position of the peripheral information register referred to in the decoding process by each pass is The image decoding apparatus according to claim 6, further comprising a control unit that controls an operation timing of decoding processing of each pass so as to be separated by a predetermined number of pixels.

Images