JP2005268319A - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a high breakdown voltage switching element of 500 V or higher and a control IC for driving the switching element are integrated on the same semiconductor chip.

FIG. 6 is a main part circuit diagram of a conventional switching power supply. This conventional switching power supply is described in Patent Document 1.
A rectifier 133 is connected to a power supply 131 of AC100V to 240V via a fuse 132, and an output of the rectifier 133 is connected to a power supply capacitor 134. The power supply capacitor 134 is connected to the primary winding 136 of the transformer 135 having two outputs. One end is connected to the starting power input terminal 114 of the switching power supply control semiconductor device 120, and the other end is connected to the drain terminal 113 of the MOSFET 102 that is a high voltage switching transistor constituting the switching power supply control semiconductor device 120. In addition, one secondary winding 137 a of each of the secondary windings of the transformer 135 is connected to the output capacitor 139 via the diode 138, and the output capacitor 139 is connected to the output terminal 150. The secondary winding 137 b is connected to the smoothing capacitor 142 via the diode 141, and the smoothing capacitor 142 is connected to the VCC terminal 116 of the switching power supply control semiconductor device 120. The switching power source control semiconductor device 120 includes a MOSFET 102 used as a high voltage switching transistor, a JFET 105 which is a normally-on lateral high voltage junction transistor used as a starting power supply element, a power circuit unit 121 and a control circuit. The unit 122 is configured to be integrated on the same semiconductor chip or incorporated in the same module. The source S of the JFET 105 is connected to the power supply circuit unit 121, and the power supply circuit unit 121 supplies power to the control circuit unit 122. The control circuit unit 122 is connected to the gate G of the MOSFET 102 to control the switching of the MOSFET. The drain terminal 113 is connected to the drain pad 103 of the MOSFET 102 shown in FIG. 7 and the starting power input terminal 114 is connected to the JFET 105. Connected to the drain pad 104, the VCC terminal 116 is connected to the power supply circuit unit 121 via the VCC pad 108 a of the control IC 107.

Conventionally, in the switching power source control semiconductor device 120, the JFET 105, the control IC 107 composed of the power circuit unit 121 and the control circuit unit 122, and the MOSFET 102 controlled by the control IC 107 are individually connected to the outside. However, in recent years, with the advancement of high voltage IC technology, the JFET 105, the control IC 107 and the MOSFET 102 are integrated on the same semiconductor chip 101, so that the number of parts can be reduced and the power supply system can be simplified. It was.
FIG. 7 is a block diagram of a main part of a conventional switching power supply control semiconductor device. The lead frame 112 includes a chip mounting portion 118 and a terminal portion 119, and the semiconductor chip 101 on which the MOSFET 102, the JFET 105, and the control IC 107 are formed is mounted on the chip mounting portion 118. Further, the drain pad 103 of the MOSFET 102 and the drain terminal 113 of the lead frame 112, and the drain pad 106 of the JFET 105 and the starting power input terminal 114 of the lead frame 112 are connected by bonding wires 109, respectively. Of course, the VCC pad 108a of the control IC 107 and the source pad 104 of the MOSFET 102 are also connected to the VCC terminal 116 and the source terminal 115 of the lead frame by bonding wires.

Note that the pad is an electrode formed on the semiconductor chip 101 to which the bonding wire 109 is fixed. The source pad 104 of the MOSFET 102 and the pads 108 of the control IC 107 are also connected to the terminals 115, 116, and 117 of the lead frame 112 by bonding wires 109. The semiconductor chip 101, the lead frame 112, and the bonding wire 109 are sealed with a mold resin package 111.
Next, the operation of this switching power supply will be described with reference to FIG. A current supplied from a power supply 131 of about AC 100 V to 240 V and rectified by the rectifier 133 flows to the power supply capacitor 134, smoothed by the power supply capacitor 134, and applied to one end of the primary winding 136 of the transformer 135. The other end of the primary winding 136 is connected to the drain terminal 113 of the MOSFET 102 constituting the switching power source control semiconductor element device 120, and the MOSFET 102 is switched at a frequency of about 100 kHz to switch the primary winding 136 of the transformer 135. Is supplied with high frequency power. The chopped high frequency power is rectified by the diode 138, smoothed by the output capacitor 139, and DC power is supplied to the output terminal 150.

Next, the operation of the switching power supply control semiconductor device 120 will be described. The current smoothed by the power supply capacitor 134 flows to the smoothing capacitor 142 via the drain terminal 114-JFET 105-VCC terminal 116, charges the smoothing capacitor 142, and when the voltage of the smoothing capacitor 142 rises, the JFET 105 is turned off. Become. Starting power is supplied from the smoothing capacitor 142 to the power supply circuit section 121 through the VCC terminal 116.
The control circuit unit 122 uses the starting power stored in the power circuit unit 121 as a power source, controls the switching of the MOSFET 102 based on an on / off command of command means (not shown), and performs a switching operation at a frequency of about 100 kHz. Power is supplied to the primary winding 136 of the transformer 135. Thereafter, switching is started, and when a voltage is generated in the secondary windings 137a and 137b of the transformer 135, the power generated in the secondary winding 137b is rectified by the diode 141, smoothed by the smoothing capacitor 142, and the VCC terminal The power is supplied to the power supply circuit unit 121 through 116. The control circuit unit 122 can operate with this electric power.

In the above operation, the starting power for starting the control circuit unit 122 of the MOSFET 102 used as the high voltage switching transistor is rectified by the power supply 131 and supplied from the starting power input terminal 114 to the control IC 107 via the JFET 105. Therefore, the voltage applied to the JFET 105 is lower than the applied voltage applied to the MOSFET 102 by superimposing the jumping voltage of the transformer on the power supply voltage. Therefore, when the power supply voltage is set to AC 100 to 240 V, the rated voltage of JFET 105 as a starting power supply element is required to be about 450 V, and the rated voltage of MOSFET 102 is required to be about 700 V. Next, the structure of the JFET will be described.
FIGS. 8 and 9 are configuration diagrams of the JFET. FIG. 8A is a plan view of a main part, FIG. 8B is a detailed view of a portion B in FIG. 8A, and FIG. 9 (a) is a cross-sectional view of the main part taken along line X1-X1 of FIG. 8 (b), and FIG. 9 (b) is a cross-sectional view of line X2-X2 of FIG. 8 (b). It is the principal part sectional drawing cut | disconnected.

The configuration of the JFET 105 will be described with reference to FIGS. A p region 201 (p well region) is selectively formed on the surface layer of the p substrate 220, and a part of the p region 201 is inserted into the p region 201 to form a first n region 202 as a drain drift layer. The second n region 203 serving as an n ⁺ source region is formed at a portion where the n ⁺ region enters, and the third n region 4 serving as an n ⁺ drain region is separately formed at a portion facing the second n region 203.
An n ⁺ source contact region 206 is formed in the surface layer of the second n region 203, and an n ⁺ drain contact region 207 is formed in the surface layer of the third n region 204. Due to the difference in impurity concentration between the second n region 203 and the first n region 202 surrounded by the p region 201, the depletion spreads from the pn junction formed by the first and second n regions 202 and 203 and the p region 201 to the first n region 202. Since the spreading method of the layers is different, the channel width W3 is controlled by changing the concentration difference. The p region 201 corresponding to the gate region of the JFET 105 is always grounded. Although not shown, the gate electrode is connected to the p region 201 and has a field plate structure extending on the first n region 202 via an insulating film.

When an input signal voltage is supplied to the drain contact region 207, a drain current flows and current is supplied from the source contact region 206 to the power supply circuit unit 121 in FIG. After that, when the starting circuit in the power supply circuit unit 121 rises to a certain voltage, the switching power supply semiconductor device 120 in FIG. 6 starts to operate. In this JFET 105, the source contact region 206 is biased to a positive potential and the channel is cut off. Then, the current supply is stopped. The drain-source region is designed to have a breakdown voltage of 500 V or more mainly at the junction of the p region 201 and the first n region 202.
In this JFET 105, the p region 202 serving as the gate region is always grounded, and when the second n region 203 serving as the source region is biased to a positive potential, the channel is narrowed due to the spread of the depletion layer, and the current is reduced. When a certain drain voltage is applied, the drain current continues to decrease as the potential of the second n region 203 as the source region increases. When the channel is cut off, the drain current hardly flows. Is necessary only at the time of start-up, and when the switching power supply control semiconductor device 120 is in an operating state, it becomes an extra power consumption component. Therefore, a power supply system that suppresses power consumption by pinching off (cutting off) the channel and reducing the drain current. realizable.

In addition to the above, a conventional JFET disclosed in Patent Document 2 will be described. Depends on drain voltage by forming multiple JFETs, connecting the drains and sources of these JFETs in series, and grounding the gates of the JFETs that are used as elements upstream of the startup circuit section of the power supply control IC A power supply with a low cut-off voltage is realized.
In addition to the above, a conventional JFET disclosed in Patent Document 3 will be described. A JFET formed on a thin film silicon-on-insulator (SOI) has a semiconductor substrate, an insulating buried layer on the substrate, and a JFET in a first conductive type semiconductor thin layer on the buried insulating layer. The JFET has a first conductivity type source region, a second conductivity type control region spaced laterally from the source region, and a first conductivity type lateral drift region adjacent to the control region. The drain region of the first conductivity type is provided so as to be separated by the lateral drift region. At least one field plate electrode is provided on at least a major portion of the lateral drift region and is insulated from the drift region by an insulating region. The control region includes control region segments spaced apart in a second lateral direction perpendicular to the first lateral direction by a portion of the semiconductor thin layer. Thus, a normally-on JFET having a high withstand voltage and a low on-resistance is completed.
JP-A-11-289044 Japanese Patent Laid-Open No. 2001-7121 Special Table 2002-532905 gazette

When the JFET 105 in FIGS. 8 and 9 is increased in breakdown voltage, the channel width W3 is narrowed because the impurity concentration of the first n region 202, which is the drain drift region, is low, and the drain current flows through the narrow channel width W3. Resistance increases. Further, since the temperature coefficient of the on-resistance is positive, for example, the on-resistance increases under a high temperature condition, and the amount of current supplied to the power supply capacitor 142 decreases.
When the amount of current supply decreases, the rise in the charging voltage of the power supply capacitor 142 becomes small and the power supply circuit unit cannot be started up, or the rise in the charging voltage of the power supply capacitor 142 becomes slow. Inconvenience such as increase.
Therefore, the JFET 105 positioned upstream of the power supply circuit unit 121 needs to have a low on-resistance in order to increase the current supply amount. However, there is a trade-off relationship between on-resistance and breakdown voltage. For example, in order to reduce the on-resistance, increasing the impurity concentration of the first n region 202 as the drain drift region or shortening the drift length L increases the breakdown voltage. It becomes difficult.

  An object of the present invention is to solve the above-described problems and provide a semiconductor device having a high breakdown voltage and a low on-resistance.

  In order to achieve the above object, the first region of the first conductivity type having a higher concentration than the semiconductor substrate formed on the surface layer of the semiconductor substrate of the first conductivity type is selectively in contact with the first region, A part of the contact portion enters the first region with a predetermined width, and is selected as the second region of the second conductivity type formed in the surface layer of the semiconductor substrate and the second region of the entering portion. The second region of the second conductivity type having a higher concentration than that of the second region formed in the second region and the third region selectively disposed in contact with the second region. The second conductivity type fourth region having a higher concentration than the two regions, the third region and the fourth region are disposed between and in contact with both regions, and are selectively formed on the surface layer of the second region. A fifth region of the second conductivity type having a higher concentration than the second region; a first electrode connected to the first region; and the third region. A second electrode for connection to a structure and a third electrode connected to the fourth region.

  Further, in a semiconductor device in which a control circuit and a start-up semiconductor element for supplying start-up power of the control circuit are integrated on the same semiconductor substrate, the semiconductor formed on the surface layer of the first conductivity type semiconductor substrate A first region of a first conductivity type having a higher concentration than the substrate; and a portion selectively contacting the first region and entering the first region with a predetermined width; and a surface layer of the semiconductor substrate A second region of the second conductivity type formed in the second region, a third region of the second conductivity type having a higher concentration than the second region formed in contact with the second region of the entering portion, and the third region A fourth region of the second conductivity type having a higher concentration than the second region, which is disposed at a position facing the region and selectively formed on a surface layer of the second region, and the third region and the fourth region Between the two regions and selectively formed on the surface layer of the second region. A fifth region of the second conductivity type having a higher concentration than the region, a first electrode connected to the first region, a second electrode connected to the third region, and a third electrode connected to the fourth region It is set as the structure which has.

The third region may be formed between the second region and the first region in a direction in which the second region enters.
The planar shape of the fifth region may be an elongated shape in which a partial width in contact with the third region and the fourth region is narrower than the predetermined width.
In addition, the sixth region of the first conductivity type having a concentration lower than that of the first region may be formed in the surface layer of the first region at the intrusion portion and in contact with the second region.

  According to the present invention, a semiconductor having a JFET having a high breakdown voltage and a low on-resistance by forming a high-concentration fourth n region connected to the second n region and the third n region on the surface layer of the first n region. An apparatus can be provided.

  The best mode of implementation is to form a high-concentration low on-resistance region that is connected to the source region and drain region in the surface layer of the drain drift region in an elongated shape, thereby achieving high breakdown voltage and low on-resistance. is there. Specific contents will be described in the following examples.

1 and 2 are configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of a main part, FIG. 1B is a detailed view of a part A of FIG. 2A is a cross-sectional view of main parts cut along line X1-X1 in FIG. 1B, and FIG. 2B is a cross-sectional view of main parts cut along line X2-X2 in FIG. In the following description, the JFET 10 is a normally-on lateral high breakdown voltage junction transistor, and is a starting semiconductor element that supplies starting power to the control IC 107 in FIG.
The configuration of the JFET 10 will be described with reference to FIGS. 1 and 2. A p region 1 (p well region) is selectively formed on the surface layer of the p substrate 20, and is inserted into a part of the p region 1 with a predetermined width a, so that a first n region 2 (first n) is formed as a drain drift region. Well region), a second n region 3 (second n well region) serving as an n ⁺ source region at a position where the first n region 2 enters, and an n ⁺ drain region serving as an n ⁺ drain region at a position facing the second n region 3. The 3n regions 4 (third n well regions) are separated from each other and simultaneously formed at a high concentration. As the channel resistance reduction region, the fourth n region 5 (fourth n well region) is formed in a narrow and narrow shape having a width smaller than the predetermined width a at a high concentration in contact with the second n region 3 and the third n region 4 that are separated from each other.

An n ⁺ source contact region 6 is formed in the surface layer of the second n region 3, and an n ⁺ drain contact region 7 is formed in the surface layer of the third n region 4. The spread of the depletion layer extending from the pn junction formed by the second n region 3, the first n region 2, and the p region 1 surrounded by the p region 1 is narrow on the high concentration second n region 3 side. Widely spread to the 1n region 2 side. Therefore, by changing the concentration of the first n region 2, the channel width W1 can be controlled by changing the spread of the depletion layer. Further, when the concentration of the fourth n region 5 is increased, the channel width W1 is increased, and when the width W2 of the fourth n region 5 is increased, the channel width W1 is also increased. Therefore, the concentration and width W2 of the fourth n region 5 are changed. Thus, the channel width W1 can be controlled. The p region 1 corresponding to the gate region of the JFET 10 is always grounded.
Further, the fourth n region 5 is increased in concentration from the third n region 4 which is the drain region to the second n region 3 which is the source region along the vicinity of the channel center line, thereby increasing the on-resistance. Reduction can be achieved.

Although not shown, the gate electrode is connected to the p region 1 and extends on the first n region 2 via an insulating film to form a field plate structure.
As described above, the structure for increasing the breakdown voltage is assigned to the junction between the p-well region 1 and the first n-well region 2, and the structure for large current is assigned to the fourth n-region 5 so that the high-voltage structure can be achieved. Both withstand voltage and low on-resistance can be achieved.
When an input signal voltage is supplied to the drain contact region 7, a drain current flows and current is supplied from the source contact region 6 to the power supply circuit unit 121 of FIG. 6. After that, when the starting circuit in the power supply circuit unit 121 rises to a certain voltage, the switching power supply semiconductor device 120 of FIG. 7 starts to operate. In this JFET 10, the source contact region 6 is biased to a positive potential and the channel is cut off. Then, the current supply is stopped. The drain-source is designed to have a breakdown voltage of 500 V or more mainly at the junction of the p region 1 and the first n region 2.

The fourth n region 5 of the channel resistance reduction region has a channel width that increases as the width W2 of the fourth n region 5 is made wider than the channel width W1 in which the depletion layer before cut-off has an unexpanded width (current path width). W1 is widened, which is effective for low on-resistance. However, if it is too wide, the voltage required for the cutoff becomes equal to or higher than a predetermined voltage. Therefore, it is necessary to optimize the width W2 and the concentration of the fourth n region 5.
FIG. 3 is a diagram showing the relationship between the drain current and the source-gate voltage. For comparison, the conventional product of FIG. 8 is also shown. By forming the fourth n region 5, the channel resistance is reduced and the drain current is increased.
FIG. 4 is a diagram showing the relationship between leakage current and drain-source voltage. For comparison, the conventional product of FIG. 8 is also shown. The curves of the leakage current and the drain-source voltage are almost the same, and the breakdown voltage does not decrease even if the fourth n region 5 is formed.

As shown in FIG. 3 and FIG. 4, high breakdown voltage can be increased by forming the high-concentration fourth n region 5 connected to the second n region 3 and the third n region 4 in the surface layer of the first n region 2 in an elongated shape. A JFET with low on-resistance can be obtained.
By using this semiconductor device, a sufficient amount of current can be supplied to the power supply capacitor, so that it can be sufficiently activated even with a low input signal voltage, and the range of use conditions is expanded. In addition, since the operating voltage can be charged in a short time, the capacity of the power supply capacitor can be reduced, which is advantageous for downsizing the power supply system.

FIG. 5 is a block diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 5 (a) is a plan view of the main part corresponding to FIG. 1 (b), and FIG. The principal part sectional drawing cut | disconnected by the X1-X1 line | wire of FIG. 1, the figure (c) is principal part sectional drawing cut | disconnected by the X2-X2 line | wire of the figure (a).
The difference from FIG. 1 and FIG. 2 is that a p region 11 having an impurity concentration lower than that of the p region 1 is formed between the p region 1 and the first n region 2. By doing so, the depletion layer formed in the p-well region 11 is easy to spread, and the voltage (referred to as the cut-off voltage) required for the cut-off (contact with the depletion layer) is higher than that of the JFET 10 shown in FIGS. In addition, the breakdown voltage of the element can be increased.
By increasing the cut-off voltage, the power supply capacitor 142 in FIG. 6 can be quickly charged to a sufficiently high voltage.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is the A section detail drawing of (a). BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is principal part sectional drawing cut | disconnected by the X1-X1 line | wire of FIG.1 (b), (b) is X2-X2 of FIG.1 (b). Cross-sectional view of the main part cut by wire Diagram showing the relationship between drain current and source-gate voltage Diagram showing the relationship between leakage current and drain-source voltage FIG. 4 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention, in which (a) is a plan view of relevant parts corresponding to FIG. Sectional drawing, (c) is a sectional view of the principal part taken along line X2-X2 of (a). Main circuit diagram of conventional switching power supply Main part configuration diagram of conventional semiconductor device for switching power supply control It is a block diagram of JFET, (a) is a principal part top view, (b) is the B section detailed drawing of (a). It is principal part sectional drawing of FIG.8 (b), (a) is principal part sectional drawing cut | disconnected by the X1-X1 line | wire of FIG.8 (b), (b) is X2-X2 line | wire of FIG.8 (b). Cutaway main part sectional view

Explanation of symbols

1, 10 p region 2 1 n region 3 2 n region 4 3 n region 5 4 n region 6 n ⁺ source contact region 10 JFET
11 p region 20 p substrate 101 semiconductor chip 102 MOSFET
103 Drain pad 104 Source pad 105 JFET
106 Drain pad 107 Control IC
108a VCC pad 108b pad 109 Bonding wire 111 Package 112 Lead frame 113 Drain terminal 114 Starting power input terminal 115 Source terminal 116 VCC terminal 117 terminal 118 Chip mounting portion 119 Terminal portion 120 Switching power supply control semiconductor device 121 Power supply circuit portion 122 Control Circuit part 131 Power supply 132 Fuse 133 Rectifier 134 Power supply capacitor 135 Transformer 136 Primary winding 137a Secondary winding 137b Secondary winding 138 Diode 139 Output capacitor 141 Diode 142 Smoothing capacitor 150 Output terminal 201, 210 p region 202 1n region 203 the 2n region 204 first 3n region 206 n ⁺ source contact region 220 p substrate W1, W3 channel width W2 the 4n region Width L drift length S source G gate

Claims (5)

A first conductivity type first region having a higher concentration than the semiconductor substrate formed on the surface layer of the first conductivity type semiconductor substrate, and selectively contacted with the first region, and a part of the contacted part is A second region of a second conductivity type that enters the first region with a predetermined width and is formed in the surface layer of the semiconductor substrate, and the second region that is selectively formed in the second region of the part of the entry. A third region having a higher concentration of the second conductivity type and a second conductivity having a concentration higher than that of the second region which is disposed at a position facing the third region and selectively formed in contact with the second region. The fourth region of the mold, and disposed between the third region and the fourth region, in contact with both regions, and having a higher concentration than the second region selectively formed on the surface layer of the second region A fifth region of a second conductivity type, a first electrode connected to the first region, a second electrode connected to the third region, and the fourth Wherein a and a third electrode connected to pass. In a semiconductor device in which a control circuit and a startup semiconductor element that supplies startup power of the control circuit are integrated on the same semiconductor substrate,
A first conductivity type first region having a higher concentration than the semiconductor substrate formed on the surface layer of the first conductivity type semiconductor substrate, and selectively contacted with the first region, and a part of the contacted part is From the second region of the second conductivity type formed in the surface layer of the semiconductor substrate and entering the first region with a predetermined width, and the second region formed in contact with the second region of the entering portion A third region having a high concentration of the second conductivity type and a second conductivity having a concentration higher than that of the second region which is disposed at a position facing the third region and selectively formed on a surface layer of the second region. The fourth region of the mold, and disposed between the third region and the fourth region, in contact with both regions, and having a higher concentration than the second region selectively formed on the surface layer of the second region A fifth region of a second conductivity type, a first electrode connected to the first region, a second electrode connected to the third region, and the fourth Wherein a and a third electrode connected to pass. The said 3rd area | region was formed between the said 2nd area | region and the said 1st area | region in the direction which the said 2nd area | region entered, The Claim 1 or 2 characterized by the above-mentioned. Semiconductor device. 4. The planar shape of the fifth region is an elongated shape in which a partial width in contact with the third region and the fourth region is narrower than the predetermined width. 5. The semiconductor device described. The sixth region of the first conductivity type having a concentration lower than that of the first region is formed in the surface layer of the first region at the intrusion portion and in contact with the second region. The semiconductor device according to any one of 5.

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