JP2004517462A - Microelectronic piezoelectric structure - Google Patents

Abstract

By first forming a barium strontium titanate layer on a silicon wafer with (104), to form a single crystal Pb covering the silicon wafer having a large diameter (Zr, Ti) high-quality epitaxial layer of O ₃ (110) It is possible. The barium strontium titanate layer (104) is a single crystal layer and is separated from the silicon wafer by an amorphous intermediate layer (116) of silicon oxide. The (La, Sr) CoO ₃ single crystal conductive layers (106, 108) are formed adjacent to the Pb (Zr, Tr) O ₃ layer.

Description

[0001]
(Field of the Invention)
The present invention relates generally to microelectronic structures and devices, and methods of making the same, and more particularly to structures and devices having piezoelectric thin films, and methods of making and using the structures and devices.
[0002]
(background)
Piezoelectric materials are useful in various applications. For example, piezoelectric materials are used to manufacture pressure gauges, transducers, tactile sensors, robotic manipulators, treble sound generators, frequency control circuits, and oscillators.
[0003]
Generally, the higher the crystallinity of a piezoelectric material, the greater the desired property of the material, the piezoelectric effect. For this reason, piezoelectric materials made of high quality crystals are often desired.
[0004]
Piezoelectric materials are relatively expensive in bulk form compared to other materials used in the manufacture of microelectronic devices such as microelectronic pressure sensors and oscillators. Since piezoelectric materials are expensive and difficult to obtain in bulk form, many years have been attempted to grow piezoelectric material thin films on substrates of different materials. However, in order to optimize the characteristics of the piezoelectric material, a single crystal film made of a high quality crystal is desirable. For example, attempts have been made to grow a layer of single crystal piezoelectric material on a substrate such as silicon. However, many of these attempts have usually failed. This is because the crystal lattice of the obtained crystal is different from that of the host crystal, so that the crystal quality of the piezoelectric material thin film deteriorates.
[0005]
If a large-area thin film made of high-quality single-crystal piezoelectric material can be formed at low cost, this film can be used to manufacture various devices at a lower cost than when semiconductor microelectronic devices are formed on a bulk wafer of piezoelectric material. It can be manufactured. Further, if a high-quality single-crystal piezoelectric material thin film can be formed on a bulk wafer such as a silicon wafer, an integrated device structure utilizing the best characteristics of both silicon and the piezoelectric material can be realized.
[0006]
Therefore, there is a need for microelectronic structures in which a high quality single crystal piezoelectric film is provided on another single crystal material, as well as a method of manufacturing such structures.
The present invention is described by way of example only and is not limited to the accompanying figures. This drawing is a schematic view of a cross section of a device structure according to the present invention.
[0007]
(Detailed description of drawings)
The drawing is a schematic illustration of a cross section of a portion of a microelectronic structure 100 according to one embodiment of the present invention. The structure 100 can be used to form piezoelectric actuators, piezoelectric transducers, ferroelectric memory cells, and the like, schematically shown in cross-section.
[0008]
The microelectronic structure 100 includes a single-crystal silicon substrate 102, a single-crystal (Ba, Sr) TiO ₃ layer 104, conductive single-crystal (La, Sr) CoO ₃ layers 106 and 108, and a single-crystal Pb (Zr, Ti). O _3, that is, the PZT layer 110, the first electrode 112, and the second electrode 114. As used herein, the term "single crystal" shall have the meaning commonly used in the semiconductor industry. This term refers to the transitions commonly found in substrates and epitaxial layers of single-crystal or near-single-crystal materials that are commonly used in the semiconductor industry, such as silicon or germanium, or a mixture of silicon and germanium. Refers to materials of this type having relatively few defects. According to the present invention, structure 100 also has an amorphous intermediate layer 116 between substrate 102 and corresponding buffer layer 104.
[0009]
According to one embodiment of the present invention, substrate 102 is preferably a high quality single crystal silicon wafer used in the semiconductor industry. The single crystal (Ba, Sr) TiO ₃ layer 104 is preferably a single crystal strontium titanate material epitaxially grown on an underlying substrate. In one embodiment according to the present invention, by oxidizing the substrate 102 during the growth of the layer 104, the amorphous intermediate layer 116 is formed at the interface between the substrate 102 and the growing (Ba, Sr) TiO layer. Grow on.
[0010]
The amorphous intermediate layer 116 is preferably an oxide formed on the surface of the substrate 102 by oxidation, and is more preferably made of silicon oxide. Typically, the thickness of layer 116 is in the range of about 0.5-5 nm.
[0011]
Generally, the (La, Sr) CoO ₃ layers 106, 108 are configured to enable the generation of an electric field across the PZT layer 110. Further, the single crystal layer 106 allows a single crystal of the layer 110 to be formed over the layer 106. According to a preferred embodiment of the present invention, the composition of the layers 106, 108 are _La 0.5 _Sr 0.5 CoO _3, beyond the 30nm film thickness is preferably in the layer, more preferably about 30 １００100 nm.
[0012]
The single crystal piezoelectric PZT layer 110 has a larger piezoelectric effect than a polycrystalline film of the same material or a similar material. For this reason, in the structure including this single crystal film, the electronic signal that can be generated per strain amount in the film increases. In other words, the strain per electric field applied to the film increases. In order to provide the desired piezoelectric effect, the layer 110 preferably has a thickness of about 30 to 500 _nm, the composition of Pb _{0.4 Zr} 0.6 TiO _3.
[0013]
The electrodes 112, 114 facilitate electrical coupling to the layers 108, 106, respectively, but are themselves relatively inert as electrodes. According to the present invention, the thickness of the electrodes 112, 114 is about 100-200 nm.
[0014]
The crystal structure of single crystal substrate 102 is characterized by a lattice constant and lattice orientation. Similarly, PZT layer 110 is also a single crystal material, and the lattice of this single crystal material is characterized by a lattice constant and lattice orientation. The lattice constant of the PZT layer and the single crystal silicon substrate are substantially the same, or when one crystal orientation is relatively rotated with respect to the other crystal orientation, the two lattice constants are substantially the same. Need to be. As used herein, the terms "substantially equal" and "substantially match" mean that the lattice constants of both are sufficiently close so that a high quality crystal layer can be grown on the underlayer.
[0015]
According to one embodiment of the present invention, substrate 102 is a single crystal silicon wafer having a (100) or (111) orientation, wherein the crystal orientation of the titanide material is 45 degrees relative to the crystal orientation of the silicon substrate wafer. When rotated, the lattice constant of the silicon substrate and the lattice constant of the titanium nitride layer 104 substantially match.
[0016]
Layers 106-110 are epitaxially grown single crystal materials, which are also characterized by their respective crystal lattice constants and crystal orientations. In order to improve the crystal quality of these epitaxially grown single crystal layers, the crystals of the corresponding buffer layer must be of high quality. Furthermore, in order to improve the crystal quality of the films 106 to 110 to be continuously deposited, the crystal lattice constant of the host crystal (in this example, (Ba, Sr) TiO ₃ single crystal) and the crystal lattice constant of the crystal to be grown substantially match. Is desirable.
[0017]
The following describes an example of a process according to the invention for producing a microelectronic structure, such as the structure shown in the figures. In the present process, first, a single crystal semiconductor substrate made of silicon is provided. According to a preferred embodiment of the present invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably on-axis oriented, but may be off-axis by up to about 0.5 °. The semiconductor substrate has a bare surface at least in part, but other parts of the substrate may include other structures, as described below. As used herein, the term "bare" refers to the cleaning of a portion of the surface of a substrate to remove oxides, contaminants, or other foreign matter. As is known, bare silicon is very reactive and native oxides are easily produced. The term "bear" is intended to include this type of native oxide. Although a silicon oxide thin film may be intentionally grown on a semiconductor substrate, such grown oxide is not essential to the process according to the present invention. In order to epitaxially grow a single-crystal (Ba, Sr) TiO ₃ layer covering the single-crystal silicon substrate, the natural oxide layer is first removed to expose the crystal structure of the underlying substrate. The following process is preferably performed by molecular beam epitaxy (MBE), but other epitaxial processes can be used according to the invention. The native oxide can be removed first by thermally depositing a thin layer of strontium, barium, or a mixture of strontium and barium in an MBE apparatus. If strontium is used, the substrate is heated to a temperature of about 750 ° C. to react the strontium with the native silicon oxide layer. The strontium reduces silicon oxide, so that a surface free of silicon oxide is obtained. The resulting surface has a regular 2 × 1 structure and contains strontium, oxygen, and silicon. This regular 2 × 1 structure serves as a template for the regular growth of the titanium nitride layer deposited on top. This template provides the chemical and physical properties necessary for nucleation of the crystal growth of the layer deposited on top.
[0018]
According to another embodiment of the present invention, the native silicon oxide is deposited on the substrate surface at a low temperature by depositing strontium oxide, strontium, barium oxide or barium oxide with MBE, and then heating the structure to about 750 ° C. By chemical change, the substrate surface can be treated so that a single crystal oxide layer can be grown. At this temperature, a solid phase reaction occurs between the strontium oxide and the native silicon oxide, the native silicon oxide is reduced, and strontium, oxygen and silicon remain on the substrate surface in a regular 2 × 1 structure. This structure also serves as a template for growing a regular single crystal titanate layer.
[0019]
According to one embodiment of the present invention, after removing the silicon oxide from the substrate surface, the substrate is cooled to a range of about 200-800 ° C., and a layer of strontium titanate is deposited on the template layer by molecular beam epitaxy (eg, about (To a thickness of 9 to 11 nm). In the MBE process, the shutter of the MBE apparatus is first opened and exposed to a strontium source, a titanium source and an oxygen source. The ratio of strontium to titanium is approximately 1: 1. The initial value of the oxygen partial pressure is set to the minimum value for growing stoichiometric strontium titanate at a growth rate of about 0.3 to 0.5 nm / min. Once the growth of strontium titanate has begun, the partial pressure of oxygen is raised above the initial minimum. When the oxygen partial pressure is high, an amorphous silicon oxide layer grows at the interface between the underlying substrate and the growing strontium titanate layer. Oxygen diffuses from the growing strontium titanate layer to the interface, and reacts with oxygen and silicon on the surface of the underlying substrate at the interface, whereby the silicon oxide layer grows. Strontium titanate grows as a regular single crystal having a crystal orientation rotated by 45 ° with respect to the regular 2 × 1 crystal structure of the underlying substrate.
[0020]
After growing the strontium titanate layer to the desired thickness, the single crystal strontium titanate may be capped by the template layer. This template layer leads to the growth of the subsequently formed epitaxial layer of the desired piezoelectric material. For example, strontium grown by MBE by interrupting the growth of one or two titanium monolayers, one or two titanium-oxygen monolayers, or one or two strontium-oxygen monolayers The titanate single crystal layer may be capped.
[0021]
After forming the mold (or after forming the titanate layer if no mold is formed), the (La, Sr) CoO ₃ material is deposited by sputter deposition. More specifically, the (La, Sr) CoO ₃ layer is deposited by RF magnetron sputtering (facing configuration) using a compressed (La, Sr) CoO ₃ target. Deposition is performed using oxygen as a sputtering gas and setting the substrate temperature at about 400 to 600 ° C.
[0022]
Next, a spin-on sol-gel coating technique is performed, followed by calcination and crystallization at 450 ° C. to 800 ° C. to form a single crystal layer, thereby forming a single crystal layer on the (La, Sr) CoO ₃ layer 106. A PZT layer 110 is formed. PZT layer 110 can also be formed using PVD or CVD techniques.
[0023]
Depositing an electrode material (such as platinum or iridium) using a sputter deposition technique, followed by patterning and etching the material to remove material from portions of layers 106, 108, thereby forming single crystal layer 106. , 108 are continuously formed with electrodes 112 and 114. For example, using RF magnetron sputtering, platinum is deposited on the (La, Sr) CoO ₃ layers 106 and 108 by sputtering a material from a platinum target on the (La, Sr) CoO ₃ layers under an inert environment. I can do it. After depositing the platinum, the platinum is photolithographically patterned and etched in a suitable dry or wet etch environment to form electrodes 112,114.
[0024]
In the above specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made in the present invention without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and drawings are considered to be illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present invention.
[0025]
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the envisaged or more obvious advantages, advantages, solutions and advantages to the problem, and any elements that can produce a solution to any advantage, advantage, or problem, are at least in part intended to be covered by the appended claims. It is not to be construed as an important, essential or essential feature or element. As used herein, the terms "consisting of,""including," or any of these variations, are intended to mean a non-exclusive inclusion. Thus, the process, method, article, or device that comprises the listed element may not only include those elements, but may also include other elements not specified or other elements that are unique to this type of process, method, article, or apparatus. May also be included.
[Brief description of the drawings]
FIG. 1 is a schematic view of a cross section of a device structure according to the present invention.

Claims (4)

A single-crystal silicon substrate,
A first layer of a single crystal oxide made of (Sr, Ba) TiO ₃ and covering the silicon substrate;
A second single crystal layer made of (La, Sr) CoO ₃ and covering the first layer;
A _third single crystal layer made of Pb (Zr, Ti) O ₃ and covering the second single crystal layer;
A perovskite heterostructure comprising (La, Sr) CoO ₃ and a fourth single crystal layer covering the third single crystal layer. A single-crystal silicon substrate,
A first single-crystal layer made of (Ba, Sr) TiO ₃ and covering the silicon substrate;
A silicon oxide layer formed below the first single crystal layer;
A second single crystal layer made of (La, Sr) CoO ₃ and covering the first layer;
A first electrode in electrical contact with the second single crystal layer;
A _third single crystal layer made of Pb (Zr, Ti) O ₃ and covering the second single crystal layer;
A fourth single crystal layer made of (La, Sr) CoO ₃ and covering the third single crystal layer;
A perovskite heterostructure comprising: a second electrode in electrical contact with the fourth single crystal layer. Providing a silicon substrate;
Epitaxially growing a first single-crystal oxide layer made of (Sr, Ba) TiO ₃ and covering the silicon substrate;
Forming an amorphous layer of silicon oxide below the first single-crystal oxide layer during the step of epitaxially growing the first single-crystal oxide layer;
Epitaxially growing a second single crystal layer made of (La, Sr) CoO ₃ and covering the first single crystal layer;
Epitaxially growing a third single crystal layer made of Pb (Zr, Ti) O ₃ and covering the second single crystal layer;
Epitaxially growing a fourth single crystal layer made of (La, Sr) CoO ₃ and covering the third single crystal layer. Providing a silicon substrate;
Epitaxially growing a first single crystal layer made of (Sr, Ba) TiO ₃ and covering the silicon substrate;
Epitaxially growing a second single crystal layer made of (La, Sr) CoO ₃ and covering the first layer;
Epitaxially growing a third single crystal layer made of Pb (Zr, Ti) O ₃ and covering the second single crystal layer;
Forming a conductive layer covering the third single crystal layer.