JP2004363842A - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit capable of selecting one of a plurality of voltage ranges and outputting a signal.
The semiconductor integrated circuit is capable of selecting any one of a plurality of voltage ranges and outputting a signal. The semiconductor integrated circuit is supplied with a first power supply voltage. An output driver circuit 10 that outputs a signal in a voltage range, and a signal output from the output driver circuit is converted to a signal in a second voltage range determined by a gate voltage via a source / drain and output to the outside. A transistor QN2, a first power supply voltage supplied thereto, a first gate voltage supply circuit 20 for supplying a first voltage to the gate of the transistor when the control signal is at a first level, and a first power supply voltage And a second gate voltage supply circuit 20 that supplies a second voltage to the gate of the transistor when the control signal is at a second level.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit capable of selecting any one of a plurality of voltage ranges and outputting a signal.
[0002]
[Prior art]
In recent years, in order to realize high-speed operation and low power consumption of various electronic devices, high integration and low voltage of semiconductor integrated circuits such as ICs and LSIs used in these electronic devices have been advanced. However, it is extremely difficult to uniformly reduce the operating voltages of all the semiconductor integrated circuits in consideration of the characteristics unique to the device. Therefore, a plurality of semiconductor integrated circuits operating at different power supply voltages may be connected to each other via an interface circuit built in the semiconductor integrated circuit.
[0003]
For example, it is conceivable that a certain semiconductor integrated circuit is connected to a circuit that operates with a 3.3 V power supply or a circuit that operates with a 1.8 V power supply via an interface circuit. In such a semiconductor integrated circuit, it is convenient if the output signal of the 3.3 V system and the output signal of the 1.8 V system can be switched and output from the same external input / output terminal (pad).
[0004]
Further, it is conceivable that a signal is applied to such a semiconductor integrated circuit from a circuit operating with a 5V power supply. Therefore, it is required that no leak current flows even when a voltage of 5 V is applied to the external input / output terminal (pad).
[0005]
As a related technique, Patent Literature 1 listed below discloses that in an interface circuit as a voltage tolerant circuit, current leakage which substantially poses a problem in any voltage transition state considered during signal input / output is prevented. , Has been disclosed. However, it does not disclose selecting any one of a plurality of voltage ranges to output a signal.
[0006]
[Patent Document 1]
JP-A-2000-77996 (page 1, FIG. 2)
[0007]
[Problems to be solved by the invention]
In view of the above, an object of the present invention is to provide a semiconductor integrated circuit capable of selecting any one of a plurality of voltage ranges and outputting a signal.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit capable of selecting any one of a plurality of voltage ranges and outputting a signal, and comprising a first power supply voltage And an output driver circuit for outputting a signal in a first voltage range, and converting a signal output from the output driver circuit into a signal in a second voltage range defined by a gate voltage via a source / drain A first gate voltage supply circuit that supplies a first voltage to a gate of the transistor when a control signal is at a first level; And a second gate voltage supply circuit that supplies a second voltage to the gate of the transistor when the control signal is at the second level.
[0009]
Here, the output driver circuit includes a second transistor formed in a first well provided in the semiconductor substrate and inverting a signal input to a gate and outputting the inverted signal from a drain, and a first gate voltage supply. A circuit is formed in a second well provided in the semiconductor substrate and includes a third transistor that supplies a first voltage to the gate of the transistor when the control signal is at a first level, the second gate The voltage supply circuit may include a fourth transistor formed in the second well and supplying a second voltage to the gate of the transistor when the control signal is at the second level.
[0010]
Further, the semiconductor integrated circuit according to the present invention may include an inverter that inverts a control signal supplied to the first gate voltage supply circuit and supplies the inverted signal to the second gate voltage supply circuit.
[0011]
According to the semiconductor integrated circuit of the present invention configured as described above, the first gate voltage supply circuit supplies the first gate voltage supply circuit to the gate of the transistor that converts the voltage range of the signal output from the output driver circuit. By selectively supplying one of the voltage and the second voltage supplied by the second gate voltage supply circuit, one of the plurality of voltage ranges is selected to output a signal. be able to. As a result, the number of input / output cells can be reduced, and the chip area can be reduced.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a circuit diagram showing a part of the configuration of a semiconductor integrated circuit according to one embodiment of the present invention. This semiconductor integrated circuit includes an external input / output terminal (pad) PD, and an input / output cell 100 connected to the pad PD and exchanging signals with an external circuit. Generally, a plurality of systems of pads and input / output cells are provided in the peripheral portion of the semiconductor substrate, but FIG. 1 shows only one system of pads and input / output cells.
[0013]
The power supply voltage HV _DD (3.3 V in the present embodiment) and the power supply voltage LV _DD (1.8 V in the present embodiment) are supplied to the input / output cell 100. For example, the power supply voltage LV _DD is supplied to the internal circuits other than the input / output cells.
[0014]
The input / output cell 100 includes an output driver 10 and an N-channel MOS for converting a signal output from the output driver circuit 10 to a signal in a voltage range determined by a gate voltage via a source / drain and outputting the signal to a pad PD. It has a transistor QN2, gate voltage supply circuits 20 and 30 for supplying a voltage to the gate of the transistor QN2, an inverter 40 for inverting the control signal CN and outputting an inverted control signal CN bar, and an input buffer 50. . Note that the input buffer 50 may be omitted, and the cell according to the present embodiment may be used as an output cell.
[0015]
Output driver 10 includes an inverter constituted by P-channel MOS transistor QP1 and N-channel MOS transistor QN1. Here, the transistor QP1 is formed in the floating N well 1 shown in FIG. 3, and the back gate of the transistor QP1 has a floating structure. As a result, a leak current can be prevented as will be described later in detail. On the other hand, the back gate of transistor QN1 is connected to the ground potential. The output driver 10 converts the voltage range of the output data D _OUT output from another internal circuit so as to be compatible with the power supply voltage HV _DD , and supplies the converted voltage to the transistor QN2.
[0016]
The drain of the transistor QN2 is electrically connected to the output terminal of the output driver 10 and the input terminal of the input buffer 50, and the source of the transistor QN2 is electrically connected to the pad PD. When a predetermined voltage is supplied to the gate (node N1) of transistor QN2, transistor QN2 is turned on, and transmits a signal between an internal circuit and an external circuit via pad PD. Ideally, the threshold voltage V _TN of the transistor QN2 is 0 V. For example, a transistor having a threshold voltage V _TN of about 0.2 V or less is used.
[0017]
Gate voltage supply circuit 20 includes a P-channel MOS transistor QP2. The power supply potential HV _DD (3.3 V) is supplied to the source of the transistor QP2, and the control signal CN is applied to the gate. The drain of transistor QP2 is electrically connected to the gate of transistor QN2. When the control signal CN goes low, the transistor QP2 is turned on, and supplies a voltage of about 3.3 V to the gate of the transistor QN2.
[0018]
At this time, the transistor QN2 supplies an output signal from the source to the pad PD based on a signal input from the output driver 10 to the drain. Since the maximum voltage of the signal input to the drain is about 3.3 V and the gate voltage is also about 3.3 V, the maximum voltage of the output signal of the transistor QN2 is about (3.3−V _TN ) V It becomes.
[0019]
Gate voltage supply circuit 30 includes a P-channel MOS transistor QP3. The power supply voltage LV _DD (1.8 V) is supplied to the source of the transistor QP3, and the inversion control signal CN is supplied to the gate. The drain of transistor QP3 is electrically connected to the gate of transistor QN2. When the control signal CN goes high and the inverted control signal CN goes low, the transistor QP3 is turned on and supplies a voltage of about 1.8 V to the gate of the transistor QN2.
[0020]
At this time, the transistor QN2 supplies an output signal from the source to the pad PD based on a signal input from the output driver 10 to the drain. Although the maximum voltage of the signal input to the drain is about 3.3 V, the maximum voltage of the output signal of the transistor QN2 is about (1.8−V _TN ) V because the gate voltage is about 1.8 V. Become.
[0021]
Here, the transistors QP2 and QP3 are formed in the floating N-well 2 shown in FIG. 2, and the back gates of these transistors are shared and floated. As a result, a leak current can be prevented as will be described later in detail.
[0022]
The input buffer 50 is configured by two-stage inverters 51 and 52 that operate by being supplied with the power supply voltage LV _DD (1.8 V). By the control signal CN to the high level, the transistors QN2, the voltage range of the signal supplied from the pad PD, can be converted to match the power supply voltage LV _DD inverter 51.
[0023]
Next, a measure for preventing a leak current will be described.
Normally, a power supply potential is applied to the back gate electrode of a P-channel MOS transistor. That is, the power supply potential HV _DD (3.3 V) is applied to the back gate electrode of the transistor QP 2, and the power supply potential LV _DD (1.8 V) is applied to the back gate electrode of the transistor QP 3.
[0024]
FIG. 2 is a diagram for explaining a problem when the transistors QP2 and QP3 shown in FIG. 1 have a normal structure. As shown in FIG. 2, N wells 210 and 220 are formed in a P type semiconductor substrate 200. On N well 210, gate electrode 218 of transistor QP2 is formed via a gate insulating film. On the N well 220, the gate electrode 228 of the transistor QP3 is formed via a gate insulating film.
[0025]
In N well 210, P-type impurity diffusion regions 212 and 214 serving as the source and drain of transistor QP2 and N-type impurity diffusion region 216 corresponding to the back gate electrode of transistor QP2 are formed. In the N well 220, impurity diffusion regions 222 and 224 serving as the source / drain of the transistor QP3 and an N-type impurity diffusion region 226 corresponding to the back gate electrode of the transistor QP3 are formed.
[0026]
P-type impurity diffusion regions 212 and 222 serving as drains of transistors QP2 and QP3 are electrically connected to the gate (node N1) of transistor QN2. The power supply voltage HV _DD (3.3 V) is supplied to the P-type impurity diffusion region 214 serving as the source of the transistor QP2 and the N-type impurity diffusion region 216 corresponding to the back gate electrode. On the other hand, the power supply voltage LV _DD (1.8 V) is supplied to the P-type impurity diffusion region 224 serving as the source of the transistor QP3 and the N-type impurity diffusion region 226 corresponding to the back gate electrode. The control signal CN is applied to the gate electrode 218 of the transistor QP2, and the inversion control signal CN is applied to the gate electrode 228 of the transistor QP3.
[0027]
Here, it is assumed that the control signal CN goes low, the transistor QP2 is turned on, and the transistor QP3 is turned off. At this time, although the transistor QP3 is off, the junction surface (PN junction) between the P-type impurity diffusion region 222 and the N well 220 is biased in the forward direction, so that the P-type impurity diffusion region 214 Part of the current flowing to the P-type impurity diffusion region 212 via the N-well 210 flows from the P-type impurity diffusion region 222 to the P-type impurity diffusion region 226 via the N-well 220, and a leakage current flows between different power supply potentials. Will flow. In order to prevent such a leak current, the present embodiment employs a structure as shown in FIG.
[0028]
FIG. 3 is a diagram showing the structure of the transistors QP1 to QP3 and QN1 to QN2 in the present embodiment. As shown in FIG. 3, in a P-type semiconductor substrate 300, floating N wells 1 and 2 not connected to any power supply potential, a P well 3 connected to ground potential, and any power supply A floating P well 4 not connected to the potential is formed.
[0029]
On floating N well 1, gate electrode 11 of transistor QP1 is formed via a gate insulating film. In the N well 1 on both sides of the gate electrode 11, P-type impurity diffusion regions 12 and 13 serving as the source and drain of the transistor QP1 are formed. Here, since N well 1 has a floating structure, even if a potential higher than power supply potential HV _DD is applied to P-type impurity diffusion region 13, there is no path through which a leak current flows.
[0030]
On P well 3, gate electrode 31 of transistor QN1 is formed via a gate insulating film. In the P well 3 on both sides of the gate electrode 31, N-type impurity diffusion regions 32 and 33 serving as the source and drain of the transistor QN1 are formed. In the P well 3, a P-type impurity diffusion region 34 corresponding to the back gate electrode of the transistor QN1 is formed.
[0031]
On floating P well 4, gate electrode 41 of transistor QN2 is formed via a gate insulating film. In the P well 4 on both sides of the gate electrode 41, N-type impurity diffusion regions 42 and 43 serving as the source and drain of the transistor QN2 are formed. Here, since the P well 4 has a floating structure, even if a high potential is applied to the pad PD, there is no path through which a leak current flows.
[0032]
On the floating N-well 2, gate electrodes 21 and 22 of the transistors QP2 and QP3 are formed via gate insulating films, respectively. In the N well 2 on both sides of the gate electrode 21, P-type impurity diffusion regions 23 and 24 serving as the source and drain of the transistor QP2 are formed. In the N well 2 on both sides of the gate electrode 22, the source of the transistor QP3 -P-type impurity diffusion regions 25 and 26 serving as drains are formed. Since the transistors QP2 and QP3 are formed in the same N well 2, the back gates of the transistors QP2 and QP3 are substantially shared.
[0033]
P-type impurity diffusion regions 24 and 26 serving as drains of transistors QP2 and QP3 are electrically connected to gate electrode 41 (node N1) of transistor QN2. The power supply voltage HV _DD (3.3 V) is supplied to the P-type impurity diffusion region 23 serving as the source of the transistor QP2, and the power supply voltage LV _DD (1. 8V) is supplied. The control signal CN is applied to the gate electrode 21 of the transistor QP2, and the inversion control signal CN is applied to the gate electrode 22 of the transistor QP3.
[0034]
When the control signal CN goes low, the transistor QP2 is turned on and the transistor QP3 is turned off, and a voltage of about 3.3 V is supplied to the gate electrode 41 (node N1) of the transistor QN2. . On the other hand, when the control signal CN becomes high level, the transistor QP3 is turned off, the transistor QP2 is turned on, and a voltage of about 1.8 V is supplied to the gate electrode 41 (node N1) of the transistor QN2. Is done. In any mode, since the N-well 2 has a floating structure, there is no path through which a leak current flows between the power supply potential HV _DD and the power supply potential LV _DD .
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a part of a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a problem in a case where a transistor has a normal structure.
FIG. 3 is a diagram showing a structure of transistors QP1 to QP3 and the like in the embodiment.
[Explanation of symbols]
Reference Signs List 10 output driver, 20, 30 gate voltage supply circuit, 40 inverter, 50 input buffer, 100 input / output cell, PD external input / output terminal (pad), QP1 to QP3 P channel MOS transistor, QN1 to QN2 N channel MOS transistor, 1 2, floating N well, 3P well, 4 floating P well, 11, 21, 22, 31, 41 gate electrode, 12, 13, 23 to 26, 34 P type impurity diffusion region, 32, 33, 42, 43 N type Impurity diffusion region, 300 semiconductor substrate

Claims (3)

A semiconductor integrated circuit capable of selecting one of a plurality of voltage ranges and outputting a signal,
An output driver circuit supplied with a first power supply voltage and outputting a signal in a first voltage range;
A transistor that converts a signal output from the output driver circuit to a signal in a second voltage range determined by a gate voltage via a source and a drain, and outputs the signal to the outside;
A first gate voltage supply circuit that supplies the first power supply voltage and supplies a first voltage to the gate of the transistor when a control signal is at a first level;
A second gate voltage supply circuit that supplies a second power supply voltage lower than the first power supply voltage and supplies a second voltage to the gate of the transistor when the control signal is at a second level; A semiconductor integrated circuit provided. The output driver circuit includes a second transistor formed in a first well provided in a semiconductor substrate and inverting a signal input to a gate and outputting the inverted signal from a drain,
The first gate voltage supply circuit is formed in a second well provided in the semiconductor substrate, and supplies a first voltage to a gate of the transistor when a control signal is at a first level. Including transistors,
The second gate voltage supply circuit includes a fourth transistor formed in the second well and supplying a second voltage to a gate of the transistor when a control signal is at a second level. 2. The semiconductor integrated circuit according to 1. 3. The semiconductor integrated circuit according to claim 1, further comprising an inverter that inverts a control signal supplied to the first gate voltage supply circuit and supplies the inverted signal to the second gate voltage supply circuit.

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