JP2004266161A - Semiconductor device and layout design method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of readjusting a timing without increasing an area, and correcting it only by a wiring layer. <P>SOLUTION: This semiconductor device is constituted of an input/output pin 10 and a chip main body 11 to and from which an external signal is inputted/outputted through the input/output pin 10. A timing adjusting logic circuit 14 for adjusting the input/output timing of the external signal is embedded at a position in the neighborhood of the input/output pin 10 at the outer peripheral part of the chip main body 11. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a timing constraint (AC-SPEC) for input / output of an external signal is adjusted.
[0002]
[Prior art]
The design process when manufacturing a semiconductor device includes, in order, a logic design, a circuit design, a layout design, and a test design. In the layout design, the layout of cells, blocks, and wiring paths are designed based on net data generated by logic / circuit design.
[0003]
In a conventional semiconductor layout design, a timing constraint (AC-SPEC) on input / output of an external signal has been adjusted by giving input / output delay, capacitance, and resistance information to an external pin. In particular, in the design, it is necessary to adjust the timing between the pin and the flip-flop so as to satisfy the given constraint. As shown in FIG. 10, by giving the delay value and the resistance / capacitance component outside the IO pins 100 as constraints to the chip body 101, the layout design tool arranges the cells including the existing cells 102 so as to satisfy the constraints. , Addition, deletion, etc., to match the timing with the design specifications. That is, the outer delay information is given to the IO pin 100 (1), and the target time (Target Speed (1)) from the IO pin 100 to the flip-flop circuit 103 in the chip body is allowed to remain inside the remaining time t (2). For example, a new cell is arranged or deleted between the IO pin 100 and the existing cell 102 so as to satisfy (3). The thus designed chip body 101 is actually measured, and if the characteristics do not match, the AC timing is adjusted again.
[0004]
However, this method has a problem in that when the timing needs to be readjusted, correction from the lowest layer is required. When a cell is newly added / deleted, a position is adjusted, a driving capability is changed, or the like for correction, it is necessary to re-create all masks including the lowermost layer, which leads to an increase in manufacturing cost. That is, as shown in FIG. 11, if the desired AC timing is not obtained in the actual wafer test after the wafer is out, this method has only to newly perform the arrangement adjustment, addition, deletion, rewiring, etc. of the cell 104. Absent. Of these, those that cannot be adjusted by wiring are corrected from the lower layer again (4), which leads to a significant increase in design time and cost.
[0005]
Therefore, burying a gate has been conventionally considered as a solution. In this method, a gate is buried in a vacant area where no cell is placed, and the route is changed in the wiring layer as necessary. In this case, as shown in FIG. 12, cells 105 that do not exist in the original logical net are buried in a vacant area (vacant bench) where the existing cells 102 and the like are not placed on the layout. The cell 105 is not a buried gate specialized for AC timing, but is also used for data path and clock adjustment.
[0006]
As a specific example of such a delay circuit adjusting method, there is a semiconductor integrated circuit disclosed in, for example, Japanese Patent Application Laid-Open No. 4-134922. This semiconductor integrated circuit is characterized by having a cell storing a plurality of buffer gates connected in series from input to output. A plurality of output pins are prepared in one cell, and the connection destination is changed according to a required delay value.
[0007]
As another delay circuit adjustment method, for example, a delay adjustment circuit is created as a library as disclosed in Japanese Patent Application Laid-Open No. 2000-243843, and the delay adjustment circuit is previously embedded as a macro in a region where delay variation is expected. There is a way to keep it.
[Patent Document 1]
Japanese Patent Laid-Open No. 4-134922 [Patent Document 1]
JP 2000-243843 A
[Problems to be solved by the invention]
However, the method shown in FIG. 12 has a problem in that the range of values that can be adjusted is limited depending on the positional relationship between the buried portion of the gate and the path to be adjusted. Further, the number of layers required for correction is greatly affected by the degree of congestion of the surrounding wiring. That is, since the delay varies depending on the location of the embedded cell 105, it is difficult to adjust the delay value.
[0009]
Further, the semiconductor integrated circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 4-134922 uses a cell newly developed particularly for delay adjustment. If there is no cell suitable for delay adjustment, a new cell must be developed and rebuilt.
[0010]
Further, the delay adjustment circuit disclosed in Japanese Patent Application Laid-Open No. 2000-243843 does not increase the area when the delay value is readjusted, but the initial area is larger than when a normal library is used. In addition, it is necessary to newly develop a library for each delay value, and it is not possible to determine whether or not the created new library has the same delay value as the original combination of the single library cells without making it.
[0011]
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device capable of re-adjusting the timing without increasing the area and capable of correcting only the wiring layer. It is another object of the present invention to provide a semiconductor device capable of shortening a turn-around-time (TAT) until a product is completely finished and capable of re-adjusting timing with low risk.
[0012]
It is another object of the present invention to provide a layout design method for a semiconductor device in which the timing can be readjusted without increasing the area and the correction can be made only with the wiring layer. It is another object of the present invention to provide a layout design method of a semiconductor device capable of shortening a turn-around-time (TAT) until a product is completely finished, and re-adjusting a timing with a low risk.
[0013]
[Means for Solving the Problems]
According to another aspect of the present invention, there is provided a semiconductor device in which an external signal is input / output via an input / output pin. And buried in a position near the input / output pin.
[0014]
The outer peripheral portion is a vacant area under a main power supply or an outermost peripheral portion of a chip, which has hardly been used as a logic portion of a semiconductor device until now. A logic circuit for timing adjustment is embedded therein. It can be modified without changing the chip size and only with the wiring layer.
[0015]
In order to solve the above-described problems, a layout design method for a semiconductor device according to the present invention is a layout design method for designing a layout of a cell and a circuit in a semiconductor device. A layout processing step of determining wiring, a cell obtained according to the layout determined in the layout processing step, a verification step of verifying a delay value between circuits, and a semiconductor device based on the verification result in the verification step. A timing correction step of correcting the timing of the cells and circuits by using a timing adjustment logic circuit which is embedded in the outer peripheral portion of the semiconductor device in advance and adjusts input / output timing of an external signal.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment is a semiconductor device comprising an input / output pin 10 and a chip body 11 to which an external signal is input / output via the input / output pin 10, as schematically shown in FIG. The timing adjustment logic circuit 14 for adjusting the input / output timing is embedded in the outer peripheral portion of the chip body 11 and at a position near the input / output pins 10. The chip body 11 is provided with a plurality of logics including existing cells 12 and flip-flops 13.
[0017]
The timing adjustment logic circuit 14 constituting a cell includes a plurality of gates having different delay characteristics. FIG. 1 describes each gate formed by connecting one buffer alone, two in series, three in series, and four in series with a buffer having a known delay value as a unit. . Each gate has a different number of buffers connected to each other, and thus has different delay characteristics. Since the delay time of each gate can be assumed, several variations in which the gates are connected in multiple stages are prepared, and a plurality of variations are embedded in the outer peripheral portion of the semiconductor chip body 11.
[0018]
In order to pass the verification of the layout tool, the input terminals 14i of the respective gates to be embedded are all grounded. The output terminal side 14o is left open. When correction is actually required, only the gate corresponding to the required delay value is disconnected from the ground and reconnected to a desired net.
[0019]
The plurality of gates in the timing adjustment logic circuit 14 constituting the cell are used for correcting the AC timing at the time of designing the layout of the semiconductor device. The AC timing is a timing for inputting / outputting an external signal, which is restricted as AC-SPEC. The correction of the AC timing is performed based on the net data generated by the logic / circuit design, such as the arrangement of the logic function cells (for example, the cells 12 and the flip-flops 13) and the wiring paths of the logic function cells (eg, the cells 12 and the flip-flops 13). This is performed after the layout is determined.
[0020]
FIG. 2 shows a processing procedure of a layout design process at the time of manufacturing a semiconductor device. First, based on the net data generated in the logic / circuit design process, layout of the logic function cells and wiring between the cells are performed using a layout processing tool such as a cell compiler or a data path compiler (step S1). .
[0021]
Next, a delay value is measured based on the layout result obtained by the layout processing tool and the layout processing (step S2). In step S3, timing verification is performed based on the measured delay value. The timing verification in step S3 is performed by comparing the delay value between the cells measured in step S2 with a set value whose timing is restricted. For example, if the delay value between the cells is equal to or less than the set value, the process proceeds to step S4, and the layout design process ends. If the delay value is larger than the set value, the layout result does not satisfy the timing constraint (AC-SPEC), and the process proceeds to the timing correction processing in step S5.
[0022]
This timing correction processing is performed by using a plurality of timing adjustment logic circuits 14 having different delay characteristics, which are preliminarily embedded in the outer peripheral portion of the chip body 11 and near the input / output pins 10. This is done by adjusting the timing.
[0023]
When the timing correction processing in step S5 ends, the process returns to the delay value measurement processing in step S2, and the processing up to the timing verification processing in step S3 is repeated.
[0024]
Hereinafter, a specific example of the timing correction processing in step S5 will be described with reference to FIG. It is assumed that the delay value between the I / O pin 10 and the cell 121 is determined to be larger than the set value in the timing verification in step S3 of FIG. That is, the delay value measured in step S2 between the I / O pin 10 and the cell 121 has failed to comply with the timing constraint, so that the timing correction process is performed.
[0025]
For example, it is assumed that the delay value between I / O pin 10 and cell 121 is larger by xnsec than the set value. The gates in the timing adjustment logic 14 that can modify this xnsec are known in advance. For example, if the delay value can be corrected by the two buffers constituting the gate NO2, the gate NO2 in the timing adjustment logic circuit 14 is inserted between the I / O pin 10 and the cell 121. Specifically, the input side 14i of the gate NO2 is disconnected from the ground and connected to the I / O pin 10, and the output side 14o is connected to the cell 121. In FIG. 3, the I / O pin 10 and the timing adjustment logic circuit 14 are separated from each other. However, in actuality, the timing adjustment logic circuit 14 is, as shown in FIG. 4, FIG. 5, and FIG. 11 is buried in the vicinity of the I / O pin 10 at the outer periphery of the I / O pin 10.
[0026]
Also, the size of the buffer constituting each gate in the vertical direction on the paper is very small as compared with the same size of one I / O pin. For example, the size of the buffer constituting each gate (gate NO1, gate NO2, gate NO3, gate NO4) of the timing adjustment logic circuit 14 is about 1/16 of the size of one I / O pin in the vertical direction of the drawing. It is. Therefore, as shown in FIG. 5, the timing adjustment logic circuit 14 including four gates (gate NO1, gate NO2, gate NO3, and gate NO4) has four (141, 142, 143, 144) per I / O pin. ) Can be embedded. FIG. 6 is an enlarged view of the specific example, in which the gate NO2 in the timing adjustment logic circuit 141 is inserted between the I / O pin 11 and the cell 121.
[0027]
Further, as shown in FIG. 4, the timing adjustment logic circuit 14 is conventionally buried under the area where the main power supply 15 is laid. This area is used as a main power supply area for drawing power to the chip central area 16 except for the AC timing adjustment circuit and the test circuit. As described above, since the timing adjustment logic circuit 14 is merely embedded in the region where no cell is originally provided, the area of the chip body does not increase.
[0028]
Further, when the semiconductor device is viewed in a hierarchical structure, the timing adjustment logic circuit 14 is embedded at the top of the base layer 21 and at the boundary with the wiring layer 22, so that only the mask of the wiring layer above it is changed. Is fine. That is, the adjustment of the delay value is easy, and the number of masks to be corrected can be small.
[0029]
FIG. 7 shows a hierarchical structure of the semiconductor device. This is a structure in which a wiring layer 22 is formed on a base layer 21. The underlayer 21 is Locos / PolySi-Gate / P + / N + /, and is used, for example, as a DRAM-dedicated layer. The wiring layer 22 is also called a metal layer, and is used for wiring for connection between cells. In the mask manufacturing process, the number of masks to be manufactured is about 30 for the underlayer 21 and, for example, for five metal layers for the wiring layer 22, M1C / M1 / M2C /. . . / M5.
[0030]
Conventionally, when a cell is added, as shown in FIG. 8, it is necessary to re-create a mask (approximately 30) of the entire underlayer in order to form a transistor in the underlayer 21. In addition, in the wiring layer 22, it is necessary to re-create the masks by the number of layers required for the reconnection. In total, it is necessary to recreate 30 or more masks.
[0031]
On the other hand, according to the present invention, as shown in FIG. 9, the timing adjustment logic circuit 14 is embedded at the top of the underlying layer 21 and at the boundary with the wiring layer 22, so that the No modification of about 30 masks of 21 is required. Even in the case of the wiring layer 22, it is sufficient to re-create the mask only for the number of layers required for the reconnection.
[0032]
Since the main power supply region (reference numeral 15 in FIG. 4) is formed in a layer above the wiring layer 22, it is hierarchically separated from the timing adjustment logic circuit 14.
[0033]
As described above, according to the layout design method of the present invention, the timing adjustment logic circuit 14 is embedded at the top of the underlayer 21 and at the boundary with the wiring layer 22 when the semiconductor device is viewed in a hierarchical structure. It is only necessary to re-create the mask for the number of layers required for the reconnection in the wiring layer 22 thereon, the delay value can be easily adjusted, and the number of masks to be corrected is small.
[0034]
In the above embodiment, a buffer is used as a cell to be embedded in advance, and the delay time is increased. However, an inverter may be used. Further, a delay may be used for delaying when the time is too early.
[0035]
【The invention's effect】
According to the semiconductor device of the present invention, it is an object of the present invention to provide a semiconductor device in which the timing can be readjusted without increasing the area, and which can be modified only by the wiring layer. Further, the time until the product is completely finished (turn-around-time: TAT) can be shortened, and the timing can be readjusted with low risk.
[0036]
Another object of the present invention is to provide a layout design method for a semiconductor device that can re-adjust the timing without increasing the area and that can correct only the wiring layer. In addition, the time required to complete the product can be reduced, and the timing can be readjusted with low risk.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a semiconductor device of the present invention.
FIG. 2 is a flowchart showing a processing procedure of a layout design step when manufacturing the semiconductor device.
FIG. 3 is a diagram for explaining a delay adjustment method for a semiconductor device according to the present invention.
FIG. 4 is a schematic diagram of a semiconductor device of the present invention.
FIG. 5 is an enlarged view of a timing adjustment logic circuit 14 of the semiconductor device of the present invention.
FIG. 6 is an enlarged view of a timing adjustment logic circuit 14 of the semiconductor device of the present invention.
FIG. 7 is a hierarchical structure diagram of a semiconductor device.
FIG. 8 is a hierarchical structure diagram for explaining cell addition in a conventional semiconductor device.
FIG. 9 is a hierarchical structure diagram of the semiconductor device of the present invention.
FIG. 10 is a diagram for explaining a conventional design method (1) of a semiconductor device.
FIG. 11 is a diagram for explaining a timing readjustment method in a conventional design method (1) for a semiconductor device.
FIG. 12 is a diagram for explaining a conventional design method (2) of a semiconductor device.
[Explanation of symbols]
1 IO pin, 11 chip body, 14 timing adjustment logic circuit, 15 mains power supply

Claims (8)

In a semiconductor device in which an external signal is input / output via an input / output pin,
A semiconductor device, wherein a timing adjustment logic circuit for adjusting the input / output timing of the external signal is embedded in a position near an input / output pin in an outer peripheral portion. 2. The semiconductor device according to claim 1, wherein a plurality of the timing adjustment logic circuits having different delay characteristics are embedded in a position near the input / output pin in the outer peripheral portion. 2. The semiconductor device according to claim 1, wherein the timing adjustment logic circuit is embedded under the outer peripheral portion, which is a region where a main power supply is laid. 2. The semiconductor device according to claim 1, wherein the logic circuit for adjusting timing is embedded in a base layer in advance, and is used for adjustment by changing a wiring in a wiring layer. In a semiconductor device layout design method for designing a layout of a cell and a circuit in a semiconductor device,
A layout processing step of arranging cells and circuits based on the net data and determining wiring,
A cell obtained according to the layout determined in the layout processing step, a verification step of verifying a delay value between circuits;
On the basis of the verification result in the verification step, the timing of the cells and the circuit of the semiconductor device is corrected using a timing adjustment logic circuit that is embedded in the outer peripheral portion of the semiconductor device in advance and adjusts the input / output timing of an external signal. A semiconductor device layout design method. The timing correction step adjusts the input / output timing of an external signal by using a plurality of the timing adjustment logic circuits having different delay characteristics preliminarily embedded in a position near an input / output pin in an outer peripheral portion of the semiconductor device. 6. The layout design method for a semiconductor device according to claim 5, wherein: 7. The layout design method for a semiconductor device according to claim 6, wherein the logic circuit for adjusting timing is embedded below the outer peripheral portion, which is a region where a main power supply is laid. 7. The layout design method for a semiconductor device according to claim 6, wherein the logic circuit for adjusting timing is embedded in a base layer in advance, and is used for adjustment by changing wiring in a wiring layer.

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