JP2004111990A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a multi-layered wiring for fineness and high integration without reducing the reliability and the production yield due to the cutting of the fuse portion, without reducing the opening above the fuse portion. Shorten the forming time to shorten the manufacturing time.
SOLUTION: A fuse portion 13 and a pad electrode 17 are formed of an uppermost metal wiring layer on an interlayer insulating film 12, an inorganic insulating protective film 14 is formed thereon, and an opening 18 above the pad electrode 17 is formed. To form A photosensitive organic insulating protective film 15 is applied to the entire surface and patterned to form an opening 16 above the fuse 13 and an opening 19 above the pad electrode 17. If necessary, the inorganic insulating protective film 14 is etched to reduce the thickness of the inorganic insulating protective film 14 above the fuse portion 13.
[Selection] Fig. 2

Description

The present invention relates to a semiconductor integrated circuit device having a fuse portion used for a redundancy repair circuit, a function adjusting circuit, and the like of a large-capacity memory, and a method of manufacturing the same.

2. Description of the Related Art In recent years, with the advance of fine processing technology, the capacity of a storage device of a semiconductor integrated circuit represented by a dynamic random access memory (DRAM), a static random access memory (SRAM), and the like has a G-bit class. Is being developed. Also, multilayer wiring technology has been used for wiring connecting circuit elements in order to achieve high integration. As the storage capacity of semiconductor integrated circuits has increased due to the development of microfabrication technology, even fine dust during the manufacturing process has caused defective bits that cause the function of the element to deteriorate or malfunction. In such a case, the semiconductor integrated circuit as a whole becomes defective as it is, and a reduction in manufacturing yield has become a problem. One of the solutions to this is a redundancy relief technique. This is because spare memory bits are manufactured in advance at the same time as the chip manufacturing process in excess of the memory capacity of the product, and even if a part of the chip has a defect and a defective memory bit occurs, the spare memory bit is switched to the spare memory bit. This is a defective bit remedy technique in which the entire memory capacity of a product is converted into good bits. One of the methods for switching between a defective memory bit and a spare memory bit is a redundancy repair technique by laser processing. This is a technique for irradiating a laser beam to blow and cut a fuse portion of a redundant relief switching circuit on a chip, thereby realizing the switching.

Conventionally, one of the fuse materials to be laser-processed is mainly made of polysilicon or silicide of the same material as the gate electrode or bit signal line of the MOS transistor and polycide obtained by stacking them in layers because of the simplicity of the manufacturing process. Fuse material has been used.

(4) The fuse portion used in the conventional redundancy repair switching circuit will be described below. FIG. 22 is a partial cross-sectional view of a conventional semiconductor integrated circuit device. In FIG. 22, 1 is a semiconductor substrate, 2 is an interlayer insulating film, 3 is a fuse portion made of, for example, a polycide layer, 4 is an inorganic insulating protective film, 5 is an organic insulating protective film, 6 is an opening, and 7 is a pad electrode. . The pad electrode 7 is an electrode for connection with a lead for assembling the package. The organic insulating protective film 5 and the inorganic insulating protective film 4 on the pad electrode 7 are removed and etched by a usual method. At the same time, the opening 6 is formed by removing the organic insulating protective film 5 and the inorganic insulating protective film 4 on the fuse portion 3 by selective etching so that the fuse portion 3 can be easily cut by laser light irradiation. The interlayer insulating film 8 on 3 is also thinned.

However, semiconductor integrated circuits are becoming multi-layered in order to cope with high integration and miniaturization, so that the conventional configuration has a new technical problem. In other words, since a multi-layer wiring is used, there are many wiring layers above the fuse section made of a polycide layer or the like, and as a result, the thickness of the interlayer insulating film above the fuse section has increased. . Therefore, when forming the opening of the interlayer insulating film for making electrical contact between the multilayer wiring layers above the fuse, at the same time, applying the step of removing the opening of the interlayer insulating film above the fuse part as necessary, as a result The process of thinning the interlayer insulating film on the fuse was adopted. Otherwise, the thickness of the protective film and interlayer insulating film above the fuse part will be increased, and the fuse material gasified by laser irradiation when the fuse part is melted will break the protective film and the insulating film above it and chip. This is because a large explosive force was required to fly outside. That is, by increasing the irradiation energy of the laser to the fuse portion, it is necessary to melt and gasify the fuse portion in a shorter time, and to increase the instantaneous explosion pressure at that time.

However, the pressure also applied simultaneously to the direction of the semiconductor substrate below the blown fuse portion at the time of the explosion and to the peripheral direction of the blown fuse portion. At the same time, the excessive thermal energy for cutting the fuse portion causes excessive heating of the semiconductor substrate portion below the fuse portion. For this reason, excessive laser energy irradiation may damage the semiconductor substrate under the fuse, such as cracking and melting. This damage may affect the reliability of the semiconductor integrated circuit even if the damage is small with respect to the initial change in the electrical characteristics of the semiconductor integrated circuit. In addition, if a large explosion occurs in the semiconductor substrate at the same time, the explosion will also cause the adjacent fuse section that does not need to be cut to be cut by the explosion, making it impossible to operate the desired redundant rescue circuit. It became impossible and led to a decrease in manufacturing yield.

Therefore, as a countermeasure, the insulating film and the interlayer film above the fuse part were removed by selective etching and the remaining film was made thinner. In recent years, some multilayer wirings for increasing the degree of integration of a semiconductor integrated circuit exceed three layers, and the thickness of an interlayer insulating film above a fuse portion is also increasing. Therefore, the thickness of the interlayer insulating film to be removed by etching has been increased from about 1 μm to several μm or more, and a long etching removal time is required. This causes a decrease in throughput of the etching apparatus, and has a technical problem that a long manufacturing time is required. In addition, it is difficult to suppress the in-plane variation and fluctuation of the etching rate during etching removal of a wafer having a diameter of 8 inches or more, and it is difficult to accurately determine the remaining amount of the interlayer insulating film above the fuse portion. There was also a technical problem that it was difficult to control uniformly in the plane.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device having a multilayer wiring in accordance with fineness and high integration, which can prevent a decrease in reliability and a decrease in manufacturing yield due to cutting of a fuse portion, and manufacturing thereof. Is to provide a way.

It is still another object of the present invention to provide a semiconductor integrated circuit device and a method of manufacturing the same, which can reduce the time required for forming an opening above a fuse portion to reduce the manufacturing time.

The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a fuse portion for laser cutting, wherein the fuse portion comprising an insulating film formed on a semiconductor substrate and a wiring layer formed on the insulating film is provided. The wiring layer of the fuse portion has at least a barrier metal layer formed on the insulating film and a main conductive metal layer formed on the barrier metal layer.

A semiconductor integrated circuit device according to a second aspect is the semiconductor integrated circuit device according to the first aspect, further comprising an inorganic insulating protective film formed on the wiring layer and the insulating film, wherein the inorganic insulating protective film on the fuse portion is Characterized in that the film is not thinned or left by etching.

The semiconductor integrated circuit device according to claim 3 is the semiconductor integrated circuit device according to claim 1 or 2, wherein the barrier metal layer is a single-layer film made of titanium nitride, titanium, or tungsten nitride, or a multi-layer film thereof. It is characterized by being.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first to third aspects, the barrier metal layer has a thickness of 150 nm or less.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first to fourth aspects, the main conductive metal layer is a metal mainly composed of aluminum. And

A semiconductor integrated circuit device according to a sixth aspect is the semiconductor integrated circuit device according to any one of the first to fifth aspects, wherein the wiring layer of the fuse portion is formed of a reflective layer formed on the main conductive metal layer. It is characterized by further having a prevention film.

A semiconductor integrated circuit device according to a seventh aspect of the present invention is the semiconductor integrated circuit device according to any one of the first to sixth aspects, wherein the fuse portion is one of a multilayer wiring layer formed on the insulating film. It is characterized by being formed by the uppermost wiring layer.

According to an eighth aspect of the present invention, there is provided the semiconductor integrated circuit device according to any one of the first to seventh aspects, wherein the wiring width of the region where the fuse section is to be cut is 0.1 μm or more. It is characterized by being not more than 0 μm.

10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein in the method for manufacturing a semiconductor integrated circuit device having a fuse for laser cutting, a step of forming an insulating film on a semiconductor substrate; Forming a fuse portion comprising: a wiring layer of the fuse portion includes at least a barrier metal layer formed on the insulating film and a main conductive metal layer formed on the barrier metal layer. And

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit device according to the ninth aspect, an inorganic insulating protective film is formed on the wiring layer and the insulating film after the step of forming the fuse portion. The method is characterized by including a step of forming and a step of etching the inorganic insulating protective film on the fuse portion to at least reduce the thickness.

The method for manufacturing a semiconductor integrated circuit device according to claim 11 is the method for manufacturing a semiconductor integrated circuit device according to claim 9 or 10, wherein the barrier metal layer is a single-layer film made of titanium nitride, titanium or tungsten nitride, or And a multilayer film of these.

A method of manufacturing a semiconductor integrated circuit device according to a twelfth aspect is the method of manufacturing a semiconductor integrated circuit device according to any one of the ninth to eleventh aspects, wherein the thickness of the barrier metal layer is 150 nm or less. It is characterized by the following.

The method for manufacturing a semiconductor integrated circuit device according to claim 13 is the method for manufacturing a semiconductor integrated circuit device according to any one of claims 9 to 12, wherein the main conductive metal layer is mainly made of aluminum. It is characterized by being a metal.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit device according to any one of the ninth to thirteenth aspects, the wiring layer of the fuse part includes a main conductive metal layer. It further comprises an antireflection film formed thereon.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit device according to any one of the ninth to fourteenth aspects, the wiring width of the region where the fuse portion is to be cut is zero. .1 .mu.m or more is 1.0 .mu.m or less.

As described above, according to the present invention, since the fuse portion is formed by the wiring layer having the barrier metal layer and the main conductive metal layer formed on the barrier metal layer, the fuse portion is formed by the uppermost wiring layer. can do. As a result, it is not necessary to etch the interlayer insulating film to form the opening above the fuse portion as in the related art, and the time for forming the opening can be reduced, and the overall manufacturing time can be reduced. Further, since only the inorganic insulating protective film is formed on the fuse portion, the fuse portion can be easily cut without increasing the irradiation energy of the laser beam. High reliability and high productivity can be realized without causing a decrease and a decrease in manufacturing yield.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a partial cross-sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a semiconductor substrate, 12 denotes an interlayer insulating film, 13 denotes a fuse portion, and 14 denotes an inorganic insulating protection. Reference numeral 15 denotes an organic insulating protective film, reference numerals 16 and 19 denote openings of the organic insulating protective film 15, reference numeral 17 denotes a pad electrode serving as an external lead electrode, and reference numeral 18 denotes an opening of the inorganic insulating protective film.

In the semiconductor integrated circuit device of the present embodiment, the fuse portion 13 and the pad electrode 17 are formed by the uppermost wiring layer formed on the interlayer insulating film 12, and an organic insulating protective film is formed on the fuse portion 13. Fifteen openings 16 are provided, and an upper portion of the pad electrode 17 is opened by an opening 18 of the inorganic insulating protective film 14 and an opening 19 of the organic insulating protective film 15. Further, in order to reduce the thickness of the inorganic insulating protective film 14 on the fuse portion 13, the inorganic insulating protective film 14 exposed to the openings 16 and 19 of the organic insulating protective film is etched and thinned. Further, the opening 19 of the organic insulating protective film 15 provided above the pad electrode 17 is formed in a wider range than the opening 18 of the inorganic insulating protective film 14, and is formed in the pad electrode 17 and a region in the vicinity thereof. I have.

In the present embodiment, in order to reduce the pad electrode 17 as an external lead electrode to the package assembly limit, mount a large number of pad electrodes 17 at high density, and suppress the chip size, the opening 19 is Although the case where the opening 19 is wider than the opening 18 is shown, the present invention is not limited to this, and the opening 19 and the opening 18 may have the same width or the opening 19 may be narrower than the opening 18. Needless to say. Although the case where the inorganic insulating protective film 14 is thinned is shown, the present invention is not limited to this. For example, when the inorganic insulating protective film 14 is thin from the beginning with respect to fuse cutting, it is not necessary to thin the inorganic insulating protective film 14. Needless to say.

Further, in the present embodiment, the case where two fuse portions 13 are formed under one opening 16 has been described as an example, but the present invention is not limited to this. Needless to say, the number of fuse portions 13 may be one, or three or more.

FIG. 2 is a process sectional view showing a method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention, and FIG. 3 is a process flow chart showing the same method. This will be described below with reference to FIGS.

(4) The elements formed on the semiconductor substrate 11 are wired in multiple wiring layers (not shown). A fuse portion 13 and a pad electrode 17 are formed of an uppermost metal wiring layer on an interlayer insulating film 12 of a multilayer wiring, and a plasma silicon nitride film [a silicon nitride film formed by a plasma CVD (Chemical Vapor Deposition) method] is formed thereon. ] Is formed about 1 μm (steps S11 and S12 in FIG. 2A and FIG. 3).

Thereafter, a photoresist (not shown) is applied, an opening is formed in the resist above the pad electrode 17, and the inorganic insulating protective film 14 above the pad electrode 17 is removed by a normal dry etching process by selective etching. Then, an opening 18 is formed. Thereafter, the photoresist (not shown) is removed (FIG. 2B, steps S13 to S16 in FIG. 3).

Next, a photosensitive organic insulating protective film 15 having a thickness of about 10 μm is applied to the entire surface, and is patterned by a lithography process, so that an opening 16 is formed above the fuse 13 and an opening 19 is formed above the pad electrode 17. It is formed (FIG. 2C, steps S17 and S18 in FIG. 3). Normally, a photosensitive polyimide film or the like is used as the organic insulating protective film 15, but the present invention is not limited to this. Further, the case where the thickness is about 10 μm has been described, but it goes without saying that the present invention is not limited to this.

Thereafter, if necessary, the inorganic insulating protective film 14 exposed in the openings 16 and 19 is etched, and the thickness of the inorganic insulating protective film 14 above the fuse portion 13 is 0.1 to 0.8 μm. (The configuration in FIG. 1, step S19 in FIG. 3). The amount of etching is not limited to this, and the smaller the thickness of the inorganic insulating protective film 14 above the fuse portion 13 is, the more likely the fuse can be cut. However, if the thickness of the inorganic insulating protective film 14 is small, the inorganic insulating protective film 14 is susceptible to the influence of the resin sealing filler at the time of assembling the package later, and the thickness of the inorganic insulating protective film 14 is large from the viewpoint of moisture resistance performance. Is better. When the interval between the adjacent fuse portions 13 is large, the inorganic insulating protective film 14 does not need to be thinned by etching. This is because, when the fuse section 13 is cut by laser light irradiation to be performed later, as the thickness of the inorganic insulating protective film 14 on the fuse section 13 increases, the cut opening diameter increases, and the interval between the fuse sections 13 decreases. In this case, the adjacent fuse portions 13 are affected, but when the interval between the fuse portions 13 is wide, the adjacent fuse portions 13 are not affected.

As described above, according to the present embodiment, the fuse portion 13 is formed by the uppermost wiring layer formed on the interlayer insulating film 12, and the organic insulating protective film 15 is formed as an opening 16 above the fuse portion 13. Since the opening may be formed, there is no need to etch the interlayer insulating film 2 to form the opening 6 above the fuse portion 3 as in the conventional example shown in FIG. The time for forming the portion 16 can be reduced, and the overall manufacturing time can be reduced. Further, the opening 16 above the fuse portion 13 can be formed at the same time as the opening 19 above the pad electrode 17, so that no time is required for forming the opening 16 above the fuse portion 13. Further, since only the inorganic insulating protective film 14 is formed on the fuse portion 13, the fuse portion 13 can be easily cut without increasing the laser irradiation energy. High reliability and high productivity can be realized without lowering the productivity and lowering the production yield. Further, since the fuse portion 13 is covered with the inorganic insulating protective film 14, the moisture resistance can be improved.

(2) Further, after the step of FIG. 2 (c), the inorganic insulating protective film 14 is etched and thinned to obtain the structure of FIG. 1, whereby the cutting of the fuse portion 13 by laser beam irradiation becomes easier.

Further, in the present embodiment, since the fuse portion 13 is formed by the uppermost wiring layer on the interlayer insulating film 12, conventionally, a wafer having a diameter of 8 inches or more can accurately be formed on the upper portion of the fuse portion. There is no problem that it is difficult to uniformly control the remaining amount of the insulating film in the wafer surface.

Further, in the present embodiment, the thickness of the inorganic insulating protective film 14 on the fuse portion 13 can be uniformly controlled in the wafer surface on a wafer having a diameter larger than 8 inches. In the case of the configuration shown in FIG. 2C, uniformity can be ensured in the wafer surface within about ± 10% (about ± 0.1 μm) of the formed film thickness (about 1 μm) of the inorganic insulating protective film 14. Further, in the case of the configuration of FIG. 1 in which the inorganic insulating protective film 14 is thinned to about 0.1 to 0.8 μm, the etching amount for thinning corresponds to about 0.9 to 0.2 μm. , Can be controlled to within about ± 10% (about ± 0.09 to 0.02 μm), and the sum of squares of formed film thickness variation (about ± 10%) and etching variation (about ± 10%). The uniformity within the wafer surface within about ± 0.15 μm of the square root can be controlled.

In the above embodiment, the case where the inorganic insulating protective film 14 is formed to about 1 μm has been described. However, when the interlayer insulating film 12 has good flatness, there may be no problem in the moisture resistance and characteristics of the product. Needless to say, the inorganic insulating protective film 14 may be thinner than about 1 μm. In the case of a wiring method (Damascene) in which an interlayer insulating film is flattened by a CMP technique in forming a multilayer wiring and a groove is formed and then buried, the wiring of the uppermost layer is relatively flat and has good coverage, and inorganic insulating. Even if the protective film 14 is made thinner than 1 μm, the wiring of the uppermost layer is relatively flat, the coverage of the inorganic insulating protective film 14 is improved, and there may be no problem in the moisture resistance and characteristics of the product. It is needless to say that it is not necessary to further reduce the film thickness by etching.

Conversely, when the flatness of the interlayer insulating film 12 is poor or when the moisture resistance performance is deteriorated in a product reliability test, the inorganic insulating protective film 14 is formed to have a thickness of about 1 μm or more, and is formed once or divided into a plurality of times. I do. Needless to say, the inorganic insulating protective film 14 may be composed of a single layer or a combination of multiple layers of a silicon nitride film or a silicon oxide film.

(4) The thickness of the inorganic insulating protective film 14 on the fuse portion 13 is reduced to about 0.1 to 0.8 μm, but is not limited to this. For example, the inorganic insulating protective film 14 on the fuse portion 13 may not be left (the film thickness may be 0), and even if the inorganic insulating protective film 14 does not remain, no problem may occur in the moisture resistance and characteristics of the product. Needless to say.

However, if the inorganic insulating protective film 14 does not exist on the fuse portion 13 at all, since the moisture-resistant protective film is lost, the reliability generally tends to deteriorate. When the etching amount is set large for the purpose of completely removing the inorganic insulating protective film 14 on the fuse portion 13, the etching of the upper portion of the fuse portion 13 proceeds at the same time, so that the film thickness of the fuse portion 13 is reduced. It becomes thinner, deviates from the design value, and eventually has a higher resistance, leading to disconnection. Further, when the inorganic insulating protective film 14 does not exist on the fuse portion 13, the cutting of the fuse portion 13 by the laser becomes unstable. This is because the wiring layer forming the fuse portion 13 is usually connected to a lower wiring layer through a contact hole, a thin barrier metal layer having a high melting point is formed on the wall surface of the contact hole, and an aluminum metal is formed thereon. And a main conductive metal layer made of an aluminum-copper alloy or the like, a thin barrier metal layer having a high melting point is laid under the fuse portion 13. Only aluminum and the main conductive metal layer of the aluminum-copper system are preliminarily heated and melted immediately after laser irradiation, gasified and scattered, but the barrier metal layer having a high melting point is located below. This is because the barrier metal layer is partially left uncut as a result, and a fuse disconnection failure may occur. If the inorganic insulating protective film 14 remains on the upper part and the side part of the fuse part 13 even a little, the thin barrier metal layer laid under the fuse part 13 also receives heat conduction from the heated aluminum until it melts. You can earn time. As a result, when the fuse portion 13 is melted and gasified to break the inorganic insulating protective film and the fuse portion 13 is scattered, the barrier metal layer is also scattered at the same time, so that the fuse can be reliably cut.

When the fuse portion 13 is formed of the uppermost wiring layer, after the inorganic insulating protective film 14 is formed, the corner portion of the fuse portion 13 is rounded on a semicircle so as to cover the fuse portion 13. Covered by. When the inorganic insulating protective film 14 is thinned by dry etching, the thickness of the inorganic insulating protective film 14 remaining on the side wall of the fuse portion 13 is larger than the thickness of the inorganic insulating protective film 14 remaining on the fuse portion 13. 19 (see the inorganic insulating protective film 39 in FIG. 19), so that the time from the laser irradiation of the fuse cutting to the scattering can be sufficiently obtained, and the inorganic insulating portion at the upper portion of the fuse portion 13 which can be easily scattered upward. The thickness of the protective film 14 can be reduced. On the other hand, when the inorganic insulating protective film is formed with a small thickness on the fuse portion 13, the thickness of the inorganic insulating protective film on the upper portion and the side portion of the fuse portion 13 may be reduced to be almost the same. Although it is possible, the cutting probability in this case is high but not sufficiently stable. This is because, since the thickness of the side portion is small, the fuse starts to fly quickly, so that the heating and melting of the barrier metal layer becomes insufficient, and a part of the barrier metal layer may remain.

[Second embodiment]
FIG. 4 is a main part sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention. In FIG. 4, 11 is a semiconductor substrate, 12 is an interlayer insulating film, 13 is a fuse portion, and 14 is inorganic insulating protection. Reference numeral 15 denotes an organic insulating protective film, reference numerals 16 and 19 denote openings of the organic insulating protective film 15, reference numeral 17 denotes a pad electrode serving as an external lead electrode, reference numeral 18 denotes an opening of the inorganic insulating protective film 14, and reference numeral 20 denotes a portion on the fuse portion 13. It is an inorganic insulating protective film.

In the semiconductor integrated circuit device of the present embodiment, the fuse portion 13 and the pad electrode 17 are formed by the uppermost wiring layer formed on the interlayer insulating film 12, and an organic insulating protective film is formed on the fuse portion 13. Fifteen openings 16 are provided, and an upper portion of the pad electrode 17 is opened by an opening 18 of the inorganic insulating protective film 14 and an opening 19 of the organic insulating protective film 15. Further, in order to reduce the thickness of the inorganic insulating protective film 20 on the fuse portion 13, the inorganic insulating protective film 14 exposed at the opening 16 of the organic insulating protective film is etched and thinned. Further, the opening 19 of the organic insulating protective film 15 provided above the pad electrode 17 is formed in a wider range than the opening 18 of the inorganic insulating protective film 14, and is formed in the pad electrode 17 and a region in the vicinity thereof. I have.

In the present embodiment, in order to reduce the pad electrode 17 as an external lead electrode to the package assembly limit, mount a large number of pad electrodes 17 at high density, and suppress the chip size, the opening 19 is Although the case where the opening 19 is wider than the opening 18 is shown, the present invention is not limited to this, and the opening 19 and the opening 18 may have the same width or the opening 19 may be narrower than the opening 18. Needless to say. Then, the case where the inorganic insulating protective film 14 is thinned to form the inorganic insulating protective film 20 on the fuse portion 13 has been described. However, the present invention is not limited to this, and it is easy to form the opening 18 of the pad electrode 17. Needless to say, the inorganic insulating protective film 14 in the opening 19 may be thinned.

Further, in the present embodiment, the case where two fuse portions 13 are formed under one opening 16 has been described as an example, but the present invention is not limited to this. Needless to say, the number of fuse portions 13 may be one, or three or more.

FIGS. 5 and 6 are sectional views showing the steps of a method for manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention, and FIG. 7 is a step flow chart showing the same method. This will be described below with reference to FIGS.

(4) The elements formed on the semiconductor substrate 11 are wired in multiple wiring layers (not shown). A fuse portion 13 and a pad electrode 17 are formed of an uppermost metal wiring layer on an interlayer insulating film 12 of a multilayer wiring, and a plasma silicon nitride film [a silicon nitride film formed by a plasma CVD (Chemical Vapor Deposition) method] is formed thereon. Is formed to a thickness of about 1 μm (FIG. 5A, steps S21 and S22 in FIG. 7).

(4) Thereafter, a photoresist 21 is applied, and an opening A is formed in the resist above the fuse portion 13 (FIG. 5B, steps S23 and S24 in FIG. 7). Subsequently, the inorganic insulating protective film 14 in the opening A above the fuse portion 13 is thinned by ordinary dry etching. The thickness of the inorganic insulating protective film 14 below the opening A is reduced until the thickness of the inorganic insulating protective film 20 above the fuse portion 13 becomes about 0.1 to 0.8 μm. Thereafter, the photoresist 21 is removed (FIG. 5C, steps S25 and S26 in FIG. 7).

Next, a photoresist 22 is applied to form an opening B in the resist above the pad electrode 17 (FIGS. 6 (a), steps S27 and S28 in FIG. 7). Subsequently, the opening 18 is formed by removing the inorganic insulating protective film 14 in the opening B above the pad electrode 17 by selective etching by a normal dry etching process. At this time, the inorganic insulating protective film 20 on the fuse portion 13 whose thickness has already been reduced is not removed by etching. Thereafter, the photoresist 22 is removed (FIG. 6B, steps S29 and S30 in FIG. 7).

Next, a photosensitive organic insulating protective film 15 having a thickness of about 10 μm is applied to the entire surface, and is patterned by a lithography process, so that an opening 16 is formed above the fuse 13 and an opening 19 is formed above the pad electrode 17. It is formed (steps S31 and S32 in FIGS. 4 and 7). Normally, a photosensitive polyimide film or the like is used as the organic insulating protective film 15, but the present invention is not limited to this. Further, the case where the thickness is about 10 μm has been described, but it goes without saying that the present invention is not limited to this.

Then, as a result of measuring the thickness of the inorganic insulating protective film 20 on the fuse portion 13 with a usual measuring instrument, if necessary, the inorganic insulating protective films 20 and 23 exposed in the openings 16 and 19 are formed. May be etched to adjust the film thickness of the inorganic insulating protective film 20 on the fuse portion 13. If it is not necessary to adjust the thickness of the inorganic insulating protective film 20, it is needless to say that there is no need to intentionally perform etching.

As described above, according to the present embodiment, after the organic insulating protective film 15 is patterned to form the openings 16 and 19, if the inorganic insulating protective film 23 in the opening 19 is not intentionally etched, the film thickness of the inorganic insulating protective film 23 is reduced. The thickness of the inorganic insulating protective film 14 under the organic insulating protective film 15 is the same as that of the inorganic insulating protective film 23. Since the thickness of the inorganic insulating protective film is not reduced because of the inorganic insulating protective film on the upper part of (i), it works advantageously on the moisture resistance of the semiconductor chip. Further, the fuse portion 13 may be formed by the uppermost wiring layer formed on the interlayer insulating film 12, and an opening may be formed in the organic insulating protective film 15 as the opening 16 above the fuse portion 13. Unlike the prior art shown in FIG. 22, the interlayer insulating film 2 does not need to be etched to form the opening 6 above the fuse portion 3, and the time required to form the opening 16 above the fuse portion 13 is shortened. Manufacturing time can be shortened.

Further, in the step of FIG. 5C (step S25 of FIG. 7), the etching time for adjusting the film thickness of the inorganic insulating protective film 20 on the fuse portion 13 depends on the opening area ratio of the pad electrode 17. It can be set independently without any problem. Further, the metal (aluminum or the like) of the pad electrode 17 is not exposed to the etching gas, the thickness of the pad electrode 17 itself does not decrease, and no metal-based deposit (adhesion) occurs during etching. Therefore, stable etching for adjusting the film thickness can be performed.

Further, in order to first perform the etching for adjusting the thickness of the inorganic insulating protective film 20, the organic insulating protective film 15 (usually used photosensitive polyimide) to be performed later is patterned in a lithography process, thermally cured, and cured. When the layers 16 and 19 are formed, even if the organic insulating protective film (polyimide film) is left slightly but thinly, the thickness of the inorganic insulating protective film 20 is not affected. As a result, since the inorganic insulating protective film 20 having a reduced thickness is formed on the upper portion of the fuse portion 13, the cutting of the fuse portion 13 can be easily performed without increasing the laser irradiation energy, High reliability and high productivity can be achieved without cutting the fuse portion 13 without lowering the reliability or the manufacturing yield. Further, since the fuse portion 13 is covered with the inorganic insulating protective film 20, the moisture resistance can be improved.

Further, in the present embodiment, since the fuse portion 13 is formed by the uppermost wiring layer on the interlayer insulating film 12, conventionally, a wafer having a diameter of 8 inches or more can accurately be formed on the upper portion of the fuse portion. There is no problem that it is difficult to uniformly control the remaining amount of the insulating film in the wafer surface.

Further, in the present embodiment, the thickness of the inorganic insulating protective film 20 on the fuse portion 13 can be uniformly controlled in the wafer surface on a wafer having a diameter larger than 8 inches. In the case of the configuration of FIG. 4, uniformity can be ensured within a wafer surface within about ± 10% (about ± 0.1 μm) of the formed film thickness (about 1 μm) of the inorganic insulating protective film 14. Further, the etching amount for thinning the inorganic insulating protective film 20 on the fuse portion 13 to about 0.1 to 0.8 μm is equivalent to about 0.9 to 0.2 μm, and within about ± 10% ( It can be controlled to an etching variation of about ± 0.09 to 0.02 μm), and is about ± 0.15 μm of a square root of a sum of squares of a formed film thickness variation (about ± 10%) and an etching variation (about ± 10%). Within the wafer surface within the range.

In the above embodiment, the case where the inorganic insulating protective film 14 is formed to about 1 μm has been described. However, when the interlayer insulating film 12 has good flatness, there may be no problem in the moisture resistance and characteristics of the product. Needless to say, the inorganic insulating protective film 14 may be thinner than about 1 μm. In the case of a wiring method (Damascene) in which an interlayer insulating film is flattened by a CMP technique in forming a multilayer wiring and a groove is formed and then buried, the wiring of the uppermost layer is relatively flat and has good coverage, and inorganic insulating. Even if the protective film 14 is made thinner than 1 μm, the wiring of the uppermost layer is relatively flat, the coverage of the inorganic insulating protective film 14 is improved, and there may be no problem in the moisture resistance and characteristics of the product. It is needless to say that it is not necessary to further reduce the film thickness by etching.

Conversely, when the flatness of the interlayer insulating film 12 is poor or when the moisture resistance performance is deteriorated in a product reliability test, the inorganic insulating protective film 14 is formed to have a thickness of about 1 μm or more, and is formed once or divided into a plurality of times. I do. Needless to say, the inorganic insulating protective film 14 may be composed of a single layer or a combination of multiple layers of a silicon nitride film or a silicon oxide film. Further, the thickness of the inorganic insulating protective film 20 above the fuse portion 13 is reduced to about 0.1 to 0.8 μm, but is not limited thereto. For example, the inorganic insulating protective film 20 on the fuse portion 13 may not be left (the film thickness may be 0), and even if the inorganic insulating protective film 20 does not remain, no problem may occur in the moisture resistance and characteristics of the product. Needless to say.

[Third Embodiment]
FIG. 8A is a plan view showing an arrangement of a main part of a semiconductor integrated circuit device according to a third embodiment of the present invention, and FIGS. 8B and 8C show x in FIG. _{1 -x 1 ', x 2 -x} 2' is a cross-sectional view taken along. FIG. 9 is a sectional view taken along the line yy 'of FIG. 8 and 9, 12 is an interlayer insulating film formed on a semiconductor substrate (not shown), 13 is a fuse portion, 13A is a main conductive metal layer constituting the fuse portion 13, 13a is an antireflection layer, 13b is a barrier metal layer, 14 is an inorganic insulating protective film, 15 is an organic insulating protective film, 16 is an opening of the organic insulating protective film 15, and 20 is an inorganic insulating protective film on the fuse portion 13.

In the semiconductor integrated circuit device of the present embodiment, the case where the fuse portion 13 and the pad electrode (not shown) are formed by the uppermost wiring layer formed on the interlayer insulating film 12 is illustrated. After a via hole (not shown) is formed in the interlayer insulating film 12, a barrier metal layer 13b is formed to improve adhesion to a lower wiring and prevent penetration of a plug electrode metal or the like. As the barrier metal layer 13b, a single-layer or multi-layer metal layer of a dense metal film such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) is formed with a thickness of about 100 nm. . After forming the barrier metal layer 13b, a plug electrode (not shown) of a metal such as tungsten is formed in the via hole, and the barrier metal layer 13b in the region of the opening C (see FIG. 11A) in FIG. Has been removed by selective etching. Above it, a fuse portion 13 is formed by the uppermost wiring layer. The main conductive metal layer 13A of the fuse portion 13 is mainly made of an aluminum metal or an aluminum-copper alloy, and the upper portion thereof is often used in a stepper for fine processing in order to facilitate fine processing in a lithography process. As an anti-reflection layer 13a for preventing reflection of light at the time of exposure such as a potassium fluoride (KrF: 248 nm) laser or an i-line (365 nm) as an exposure light source, a titanium nitride (TiN) film or the like which is usually used is used. It is formed with a film thickness of about 10 to 50 nm.

As shown in FIG. 8 (b), a barrier metal layer 13b is formed below the fuse portion 13 and an antireflection layer 13a is formed above the fuse portion 13. However, before the main conductive metal layer 13A is formed, The barrier metal layer 13b in the region of the opening C in FIG. 8A is selectively etched, and the barrier metal layer 13b is not formed below the fuse portion 13 as shown in FIG. 8C. In addition, even when the thickness of the barrier metal layer 13b is reduced in the region of the opening C, the cutability of the fuse is improved, but the cutability of the fuse is further improved by removing the fuse by etching.

An opening 16 of the organic insulating protective film 15 is provided above the fuse 13, and an opening (not shown) of the inorganic insulating protective film 14 and an opening of the organic insulating protective film 15 are provided above the pad electrode (not shown). It is opened by a part (not shown). Further, when the inorganic insulating protective film 20 on the fuse portion 13 is made thinner to ensure the fuse cutting, the inorganic insulating protective film 14 exposed in the opening 16 of the organic insulating protective film is selectively etched as necessary. It is thinned.

(9) As shown in FIG. 9, a laser beam (hν) pulse is condensed and irradiated on a portion where there is no barrier metal layer 13b to heat and explode the fuse portion 13 to blow it. At this time, the antireflection layer 13a also blows at the same time. The opening of the inorganic insulating protective film 20 also scatters simultaneously with the explosion of the fuse portion 13. Since there is no barrier metal layer 13b having a high melting point, fuse cutting becomes more reliable. Further, an opening (not shown) of the organic insulating protective film 15 provided above the pad electrode (not shown) is formed in a wider range than an opening (not shown) of the inorganic insulating protective film 14. , A pad electrode (not shown) and a region in the vicinity thereof. The pad electrode and its vicinity can be configured in the same manner as in FIGS.

Although the case where the fuse portion 13 is formed of the uppermost wiring layer has been illustrated, the present invention is not limited to this, and it is possible to use a wiring layer one layer or two layers below the uppermost layer. Needless to say. This is because, when the barrier metal layer 13b exists under the fuse portion 13, the fuse portion 13 is one layer lower than the uppermost layer than when the uppermost wiring layer is used for the fuse portion 13. When the wiring layer two layers below is used, the interlayer insulating film layer is flatter, so that the probability of remaining the barrier metal layer at the time of fuse cutting increases and the probability of disconnection failure increases. This is because, in the embodiment, since the barrier metal layer 13b does not exist, cutting can be performed more reliably.

In the present embodiment, the case where two fuse portions 13 are formed under one opening 16 has been exemplified, but the present invention is not limited to this. Needless to say, the number of the parts 13 may be one or three or more.

FIGS. 10 to 12 are process cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention, and FIG. 13 is a process flow chart showing the same manufacturing method. This will be described below with reference to FIGS.

In FIG. 10A, the elements formed on the semiconductor substrate 11 are wired with a multilayer wiring layer (25 or the like) formed on the interlayer insulating film 24 and a plug metal (not shown). A wiring groove is formed on the surface of the interlayer insulating film 24, a wiring layer 25 embedded in the groove is formed, and then the next interlayer insulating film 26 is formed on the entire surface (Step S41 in FIG. 13). Here, the case where the wiring layer 25 is buried in the groove has been exemplified, but the present invention is not limited to this. The wiring layer 25 is formed on the surface of the planarized interlayer insulating film 24, and then the next surface is formed. It goes without saying that the interlayer insulating film 26 may be formed and its surface may be flattened.

Next, a contact via hole 27 is formed in the interlayer insulating film 26 above the wiring layer 25 to be connected (FIG. 10B, step S42 in FIG. 13). Next, a barrier metal layer 28 for improving adhesion with the lower wiring layer 25 and preventing penetration of plug electrode metal or the like is formed on the entire surface of the semiconductor substrate by a conventional method such as a CVD method. As the barrier metal layer 28, a single-layer or multilayer metal layer of a dense metal film such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) is formed with a thickness of about 100 nm. Next, a plug electrode 29 of a metal such as tungsten is formed in the via hole 27 by a normal selective growth method (FIG. 10C, steps S43 and S44 in FIG. 13).

Next, a photoresist 30 is applied to the entire surface, and an opening C is formed in the resist in a region corresponding to the fuse portion by ordinary mask exposure and development. Thereafter, the barrier metal layer 28 in the opening C of the photoresist 30 and the metal layer of the plug electrode 29 which may be left in a small amount are removed by selective etching (FIG. 11A, steps S45 to S45 in FIG. 13). S47). Note that even when the thickness of the barrier metal layer 28 is reduced, the cutability of the fuse is improved, but the cutability of the fuse is further improved by removing the fuse by etching.

Next, as shown in FIG. 11B, the photoresist 30 is removed (Step S48 in FIG. 13), and thereafter, the uppermost main conductive metal layer 13A is formed here, and the anti-reflection layer is formed thereon. After the formation of 13a, the fuse portion 13 is formed simultaneously with a pad electrode (not shown) as an external lead electrode by a normal lithography etching method (step S49 in FIG. 13). At this time, the barrier metal layer 28 is also etched into the same shape as the antireflection layer 13a and the main conductive metal layer 13A, and becomes the barrier metal layer 13b. The main conductive metal layer 13A of the fuse portion 13 is mainly made of an aluminum metal or an aluminum-copper alloy, and the upper portion thereof is often used in a stepper for fine processing in order to facilitate fine processing in a lithography process. As an anti-reflection layer 13a for preventing reflection of light at the time of exposure such as a potassium fluoride (KrF: 248 nm) laser or an i-line (365 nm) as an exposure light source, a titanium nitride (TiN) film or the like which is usually used is used. A film is formed with a thickness of about 10 to 50 nm.

Next, a plasma silicon nitride film (P-SiN) having a thickness of about 1 μm is formed as the inorganic insulating protective film 14 (Step S50 in FIG. 13). Note that the inorganic insulating protective film 14 is not limited to a plasma silicon nitride film, but is a single layer film of a silicon oxide film (SiO ₂ film), a silicon oxynitride film (SiON film), or a plasma silicon nitride film, which is commonly used. Needless to say, it may be a multilayer film obtained by combining these.

Next, a photoresist (not shown) is applied on the inorganic insulating protective film 14, an opening is formed in the photoresist on the fuse portion 13, and the inorganic insulating protective film 20 in the opening A corresponding to the opening is etched by ordinary etching. The thickness is reduced to about 0.1 to 0.8 μm (FIG. 11C). By reducing the thickness of the inorganic insulating protective film 20, it is possible to stably and surely blow and cut the fuse portion 13 with a smaller laser energy than when the inorganic insulating protective film 20 is thick. Damage to the lower interlayer insulating film 26 and the like can be reduced. However, if there is no inorganic insulating protective film above the fuse section 13, the moisture-resistant protective film is lost, and the reliability tends to deteriorate.

Thereafter, an opening (not shown) is formed on the inorganic insulating protective film 14 on the pad electrode (not shown) which is an external lead electrode, and a photosensitive polyimide film is applied and baked as an organic insulating protective film 15 to a film thickness of about 10 μm. The film is formed to be thick. An opening 16 on the fuse portion 13 and an opening (not shown) on a pad electrode (not shown), which is an external lead electrode, are formed by exposure and development processing, and cured in a thermosetting furnace (FIG. 12).

It should be noted that the thinning adjustment of the inorganic insulating protective film 20 above the fuse portion 13 is not limited only to the previous etching step, but the thinning adjustment is further performed by etching after the opening and curing of the organic insulating protective film 15. Needless to say, this may be done.

Further, in the present embodiment, the case where the fuse portion 13 is formed by the uppermost wiring layer is exemplified. In this case, the steps after the formation of the inorganic insulating protective film 14 are the same as those of the first embodiment. The steps described in Embodiment Mode and Embodiment Mode 2 can be applied.

In the above description, the case where the fuse portion 13 is formed by the uppermost wiring layer is exemplified. However, when the fuse portion 13 is formed by using the wiring layer one layer lower than the uppermost layer, the process shown in FIG. After the anti-reflection layer 13a, the fuse portion 13 and the barrier metal layer 13b are formed into desired shapes, an interlayer insulating film is formed, and then a wiring layer (top layer) is formed, and an inorganic insulating protection layer is formed thereon. The film 14 is formed. In this case, the inorganic insulating protective film 14 on the fuse portion 13 is completely removed by selective etching, and the interlayer insulating film is subsequently etched to reduce the thickness of the interlayer insulating film on the fuse portion 13 to 0.1 to 0.8 μm. Thinning. In this case, the configuration of the upper portion of the fuse section 13 is the same as that of FIG. The same applies to the case where the fuse portion 13 is formed using a wiring layer two layers below the uppermost layer. In these cases, the etching time is longer than in the case where the uppermost wiring layer is formed, and the variation in the thickness of the interlayer insulating film on the fuse portion 13 after the etching is increased.

[Fourth Embodiment]
14 and 15 are process sectional views showing a method for manufacturing a semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 15 (b) is a main part sectional view of the semiconductor integrated circuit device according to the present embodiment. In FIG. 15 (b), 11 is a semiconductor substrate, 24 and 41 are interlayer insulating films, and 13 is a main conductive metal layer. A fuse portion 13A, 14 an inorganic insulating protective film, 15 an organic insulating protective film, 16 an opening in the organic insulating protective film 15, 20 an inorganic insulating protective film on the fuse portion 13, 40 a barrier metal layer, 42 Is a via hole, and 43 is a wiring groove.

In the semiconductor integrated circuit device of the present embodiment, as shown in FIG. 15B, the fuse portion 13 and the pad electrode (not shown) are formed by the uppermost wiring layer formed in the groove 43 of the interlayer insulating film 41. Is formed. Via holes 42 and grooves 43 are formed in the interlayer insulating film 41 to form a so-called Dual Damascene wiring structure. A barrier metal layer 40 is formed for improving adhesion to the lower wiring and preventing penetration. As the barrier metal layer 40, a single-layer or multi-layer metal layer of a dense metal film such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) is formed with a thickness of about 100 nm. . After the barrier metal layer 40 is formed, the barrier metal below the fuse portion 13 is removed by selective etching, and then copper or the like is formed in the via hole 42 and the groove 43 by a commonly used method such as plating. An inorganic insulating protective film 14 and an organic insulating protective film 15 are formed on the main conductive metal layer 13A and the interlayer insulating film 41. Above the fuse portion 13, the inorganic insulating protective film 20 is formed in the region of the opening A. Are thinned, and an opening 16 is formed in the organic insulating protective film 15.

This embodiment is different from the third embodiment in that the wiring layer forming the fuse portion 13 has the above-described dual damascene wiring structure and there is no anti-reflection layer on the main conductive metal layer 13A. As in the third embodiment, since there is no high melting point barrier metal layer 40 under the fuse portion 13, the fuse can be more reliably cut. In addition, although the case of the copper wiring fuse is illustrated, the present invention is not limited to this, and an embedded wiring of aluminum or another metal may be used. Needless to say, the fuse section 13 is not limited to the uppermost wiring layer.

FIG. 16 is a process flow chart showing a manufacturing method in the present embodiment. Hereinafter, a method of manufacturing a main part will be described with reference to FIGS.

In FIG. 14A, the elements formed on the semiconductor substrate 11 are wired with a multilayer wiring layer (25 or the like) formed on the interlayer insulating film 24 and a plug metal (not shown). A wiring groove is formed on the surface of the interlayer insulating film 24, the wiring layer 25 embedded in the groove is formed, and then the next interlayer insulating film 41 is formed on the entire surface (Step S61 in FIG. 16).

Next, a via hole 42 and a wiring groove 43 are formed in the interlayer insulating film 41, and a barrier metal layer 40 for improving adhesion to the lower wiring and preventing penetration is formed on the inner surface thereof (FIG. 14B). ), Steps S62 and S63 in FIG. Here, as the barrier metal layer 40, a single-layer or a multi-layer metal layer of a dense metal film such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) is formed with a thickness of about 100 nm. I do.

Next, a photoresist 30 is applied to the entire surface, and an opening C is formed in the resist in a region corresponding to the fuse portion by ordinary mask exposure and development. Then, the barrier metal layer 40 in the opening C of the photoresist 30 is removed by selective etching (FIG. 14C, steps S64 to S66 in FIG. 16). Here, even if the thickness of the barrier metal layer 40 is reduced by etching, the cutability of the fuse is improved, but it is removed as much as possible.

Next, after the photoresist 30 is removed, a main conductive metal layer 13A such as copper is formed in the via hole 42 and the groove 43 by a commonly used method such as plating. At this time, after the main conductive metal layer 13A is buried in the via hole 42 and the groove 43, it is planarized by using at least one of a chemical mechanical polishing technique and an etch back technique. Thereby, the fuse portion 13 and the pad electrode (not shown) are formed. An inorganic insulating protective film 14 such as a plasma silicon nitride film is formed thereon (steps S67 to S69 in FIG. 15A and FIG. 16).

Thereafter, as in the third embodiment, the inorganic insulating protective film 20 above the fuse portion 13 is thinned to a thickness of about 0.1 to 0.8 μm by etching in the region of the opening A. Thereafter, an organic insulating protective film 15 of polyimide or the like is formed, and an opening 16 of the organic insulating protective film 15 is formed above the fuse portion 13. The openings of the inorganic insulating protective film 20 and the organic insulating protective film 15 above the pad electrode (not shown) can be formed in the same manner as in the third embodiment.

In the third embodiment, the plug electrode 29 of a metal such as tungsten is formed in the via hole 27 (step S44), and the main conductive metal layer 13A for the fuse is formed thereon (step S49). On the other hand, in the fourth embodiment, the main conductive metal layer 13A for the fuse is formed in both the via hole 42 and the groove 43 (step S68).

[Fifth Embodiment]
The fifth embodiment is applicable to the above-described first to fourth embodiments, and only the main part will be described here. FIGS. 17A and 17B are plan views showing the arrangement of main parts of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. 17A and 17B, reference numerals 100 to 106 denote fuse wirings each formed with one electrically continuous fuse portion, and D and E denote thin regions of an inorganic insulating protective film and organic insulating films. This is the opening of the protective film. _{L 0, L 1, L '} 1, L 3, L' 3, L '' 3, L 5, L '5, L 6, L' 6, L '' 6 is a laser irradiation portion.

In FIG. 17 (a), conventionally, a fuse wire 100 fuse material to melt cut only by the laser irradiation unit L _0, was electrically disconnected between the ends 0 of the fuse wire 100 and 0 '. In contrast, in the present embodiment is obtained by electrically disconnecting between the fuse wire 101 'at both ends 1 of the fuse wires 101 and 1 in ₁ of 2 places' laser irradiation unit L _1, L. Also, it is obtained by electrically disconnected between the ends 3 of the fuse wire 103 fuse wire 103 in the laser irradiation unit L _3, L _'3, L'_'3 in three locations with the 3'. The fuse wires 102 and 104 show a state where they are not cut.

As in the present embodiment, by cutting one electrically continuous fuse portion at a plurality of positions, the cut resistance value of one fuse is increased because the cut resistance value at one position becomes in series. . In addition, even if there is a disconnection failure at one location, it is possible to disconnect the fuse at the other fuse disconnection portion, so that the disconnection can be ensured. That is, the cutting resistance value is a multiple of the cutting location, and the cutting accuracy (probability) is the product of the cutting probabilities at one location.

Further, by employing the configuration shown in FIG. 17B, the fuse can be cut at a high speed. In the FIG. 17 (b), the two fuse wires 105 and 106, the laser irradiation unit L _5, L _'5 and _{L 6, L' 6, L} '' 6, electrical opposite ends of the fuse wires 105 5 5 'and the electrical ends 6 and 6' of the fuse wiring 106 are cut off in terms of circuit operation.

That is, two fuse wirings 105 and 106 having fuse portions that can be cut at a plurality of locations are provided in one opening E, and their laser irradiation portions L ₅ , L ′ ₅ , L ₆ , L ′ ₆ , L '' All of ₆ are arranged on the straight line of the II ′ line. By arranging in this way, the laser feed of the laser processing device is usually realized by moving the wafer, but it is possible to irradiate the laser in a straight line, and the fuse can be moved at high speed while moving without stopping the semiconductor substrate. Can be cut. As a result, throughput can be improved, productivity can be improved, and TAT can be shortened.

In the above embodiment, the number of cut portions in each of the fuse wires 102 to 106 is two or three. However, the present invention is not limited to this, and any number may be used. FIG. 17B shows a case where two fuse wirings 105 and 106 are provided in one opening E, but it goes without saying that three or more fuse wirings may be provided. However, as the number of cut portions increases, the cutting accuracy increases, but the occupied area increases, and the number of chips to be obtained decreases due to the increase in area. That is, there is a trade-off relationship between the cutting accuracy and the number of chips to be obtained, and the cutting position is determined by the relationship between the two.

In the case where the above configuration is applied to the third and fourth embodiments, at least the barrier metal layer is removed so as not to be present below the portion to be cut (laser irradiated portion).

Note that it goes without saying that even when the configuration of the present embodiment is applied to the conventional configuration as shown in FIG. 22, the unique effects described in the present embodiment can be obtained.

[Sixth Embodiment]
The sixth embodiment is applicable to the above-described first to fifth embodiments (provided that the fuse portion is formed by the uppermost wiring layer). I will explain only. FIG. 18 is a main part plan view of a semiconductor integrated circuit device according to the sixth embodiment of the present invention. In FIG. 18, 31 is a fuse portion, 32, 33, and 34 are metal wiring layers, 35 is a guard band, F is a thinned region of an inorganic insulating protective film, G is an opening of an organic insulating protective film, and CH1 to CH3 are wirings. This is a contact hole between layers.

In FIG. 18, the fuse part 31 is formed of the uppermost wiring layer, and is electrically connected to the wiring layer 32 one layer below the uppermost layer by a plug metal at the contact hole part CH1. The other part of the fuse portion 31 is electrically connected to the wiring layer 34 one layer below the uppermost layer via the plug metal via the contact hole CH2, and then to the wiring layer 33 via the plug metal via the contact hole CH3. Connected. The wiring layer 33 may be an uppermost layer wiring or a wiring layer two or more layers below the uppermost layer. In addition to the configuration shown in FIG. 18, both ends of the fuse portion 31 may be an electrical wiring layer change using a single contact hole like the wiring layer 32, or two or more times like the wiring layer 33. It goes without saying that the electrical wiring layer may be changed using the contact holes. The magnitude relationship between the thinned region F of the inorganic insulating protective film and the opening G of the organic insulating protective film is not particularly limited.

The guard band 35 is formed of a conductive layer. As the conductive layer, a wiring layer from the uppermost layer to the lowermost layer, a plug metal layer for contact between wirings, a substrate portion, and the like are used. The wiring layers and the like constituting the guard band 35 are electrically connected to each other. The guard band 35 surrounds the contact holes CH1 to CH3 as shown in FIG. However, the wiring layers 32 and 33 for electrical extraction of the fuse part 31 are separated by a predetermined distance so as not to be electrically connected to the guard band 35. Therefore, if the portions of the guard band 35 that intersect with the lead-out wiring layers 32 and 33 are the same wiring layers, the portions that are not partially connected can be very small.

According to the present embodiment, the fuse wiring is reconnected by the contact holes CH1 to CH3 inside the guard band 35, so that moisture and ionic components can be removed from the cut portion (not shown) of the fuse portion 31 after the cut. The route of penetration through the remaining fuse wiring is extended, and the plug metal embedded in the contact holes CH1 to CH3 is a metal such as tungsten which is hard to corrode. It can be blocked by metal parts. Further, since the entire periphery of the contact holes CH1 to CH3 is surrounded by the guard band 35, it is possible to prevent moisture and ionic components from penetrating inside the card band 35, and to cover the outside (semiconductor element portion) of the guard band 35. No moisture or ionic components come and the reliability can be improved. The potential of the guard band 35 is also connected to the semiconductor substrate, and the potential can be freely determined within the well. In other words, it goes without saying that the potentials of positive, negative and zero can be freely set. Although the case of a single guard band 35 is illustrated, the area increases, but the guard band 35 having two or more layers is used to apply a positive / negative voltage and to set a zero potential, respectively. It may be used as a trap for ions and moisture.

In the present embodiment, both ends of the wiring of the fuse part 31 are connected to the lower wiring layer through the contact holes CH1 to CH3 having the plug metal parts. However, only one end of the wiring of the fuse part 31 is connected. Is connected to the lower wiring layer through a contact hole, it is possible to prevent a corrosion reaction and penetration of moisture and ionic components at one end.

Further, even when the contact holes CH1 and CH2 at the ends of the wiring of the fuse portion 31 are not buried with the plug metal as in the fourth embodiment (see FIG. 15B), the effect of preventing corrosion by the plug metal. However, the effect of providing the guard band 35 can be obtained.

Next, in the configurations of the first and second embodiments (see FIGS. 1 and 4), the fuse portion 13 is formed of at least the main conductive metal layer and the barrier metal layer formed thereunder. In this case, preferred dimensions of each part will be described with reference to FIGS. 19 and 20.

FIG. 19 is a main cross-sectional view for describing dimensions of each part of the semiconductor integrated circuit device according to the embodiment of the present invention. In FIG. 19, 12 is an interlayer insulating film, 36 is a fuse portion, 37 is a barrier metal layer, 38 is an antireflection layer, and 39 is an inorganic insulating protective film. FIG. 20 is a diagram showing the relationship between the dimensions of each part and the ease of cutting the fuse part by laser irradiation.

In FIG. 19, after forming a fuse portion 36 composed of the uppermost wiring layer on the interlayer insulating film 12 with an inorganic insulating protective film 39 such as a plasma silicon nitride film of about 1 μm, a region including the fuse portion 36 is opened. The inorganic insulating protective film 39 is thinned by ordinary dry etching using a resist as a mask. Assuming that the film thickness of the inorganic insulating protective film 39 on the upper part of the fuse part 36 is _tp1 , and the film thickness of the inorganic insulating protective film 39 on the side wall of the fuse part 36 is _tp2 ,
_tp1 < _tp2
It is shown by the relational expression.

This is a shape that is generated because the normal dry etching of the inorganic insulating protective film 39 is anisotropic etching, and the progress of the horizontal etching is slower than the progress of the vertical etching. This is the same as the principle of a method of forming a sidewall spacer in a gate electrode portion of a transistor having an LDD (Lightly Doped Drain) structure. On the other hand, since the wet etching is an isotropic etching, the thickness _tp2 of the inorganic insulating protective film 39 on the side wall of the fuse portion 36 is also substantially equal to the thickness _tp1 of the inorganic insulating protective film 39 on the fuse portion. .

It is desirable that the ease of cutting Y (au) of the fuse portion 36 be thinner at t _{p1, and it} is better to be about 800 nm or less when other conditions are fixed and evaluated as shown in FIG. If the width W _FT of the upper portion and the width W _FB (≧ W _FT ) of the lower portion of the fuse portion 36 are greater than about 1.0 μm, it becomes difficult to cut the fuse portion 36 easily (see FIG. 20B). Further, if the thickness t _F3 of the barrier metal layer 37 exceeds about 150 nm, the barrier metal and the like remain, and the cuttability of the fuse deteriorates (see FIG. 20C).

In other words, the ease Y of cutting the fuse 36 depends on whether the barrier metal layer 37 can be scattered or not, because the fuse 36 is confined with the inorganic insulating protective film 39 so that the explosion does not proceed until the fuse is heated to a sufficiently high temperature. ing. However, if the thickness _tp1 of the inorganic insulating protective film 39 is too _large, the energy at which the fuse section explodes is also applied as damage to the direction of the interlayer insulating film 12 and a crack is formed. The upper limit value of the energy (about 800 nm) can be set (FIG. 20A). The lower limit value is a set value including the variation in etching so that the film thickness of the fuse portion 36 itself does not change due to the overetching of the fuse portion 36.

Width W _FB of the fuse portion 36 is wider as for potentially barrier metal layer 37 remains during fuse cutting is increased, as narrow well, for example, the thickness t _F2 of main conducting metal layer 36A made of aluminum layer 500nm before and after In this case, the upper limit value of the width of the fuse portion 36 is about 1.0 μm, and the lower limit value is the limit of fine processing. This is also true in the case where the barrier metal layers 13b and 40 (see FIGS. 12 and 15 (b) and the like) under the fuse portion 13 are thinned without being completely removed in the third and fourth embodiments. The same is true.

The thinner the film thickness t _F3 of the barrier metal layer 37 is, the better, but the lower limit is determined by the barrier property at the contact portion, and cannot be set to 0 nm at the contact portion. Therefore, the thickness t _F3 of the barrier metal layer 37 is desirably about 50 to 150 nm. However, it goes without saying that the present invention is not limited to this as long as it has a barrier property.

In some cases, a silicon dioxide film or the like (not shown) is thinly formed on the fuse portion 36 and patterned to form a mask for etching the fuse wiring layer in order to finely process the fuse portion 36. In this case, the thickness of the silicon dioxide film or the like can be considered as the thickness of the inorganic insulating protective film 39 on the fuse portion 36.

The film thickness t _F1 of the anti-reflection layer 38 is a film thickness capable of obtaining an effect of preventing reflection of light with respect to an exposure light source, and the cutting characteristic is about 10 to 50 nm of a commonly used titanium nitride (TiN) film. No difference occurs.

Further, as a laser used for cutting the fuse portion in the semiconductor integrated circuit device of the above embodiment, for example, a laser beam from a YLF (yttrium-lithium-fluoride) crystal is an infrared ray having a wavelength of 1047 to 1053 nm and a pulse width of about 1047 to 1053 nm. A short pulse of 2 to 10 nsec is preferable. In addition, there is an infrared ray of YAG (yttrium-aluminum-garnet) short crystal having a wavelength of 1064 nm and a pulse width of about 40 nsec. A pulse width shorter than 10 nsec is advantageous for cutting a fuse portion of a metal wiring. Tends to be. This is because if the pulse width is too long, damage to the base of the fuse portion is likely to occur.

Further, as shown in FIG. 19, the fuse portion 36 includes, for example, an antireflection layer 38, a main conductive metal layer 36A, and a barrier metal layer 37. The main conductive metal layer 36A is made of an aluminum-based metal. When the fuse 38 and the barrier metal layer 37 are made of a titanium nitride film, a titanium film, or the like, when the fuse portion 36 is cut, the cutting is performed by using a laser light source having two or more wavelength components to increase the processing yield. It becomes possible. In this example, it is possible to increase the processing yield by using a laser processing apparatus using so-called SDWL (Simultaneous dual wavelength lasers) having two kinds of oscillation wavelengths of laser light of 1340 nm and 1050 nm.

This is because when a laser beam having a wavelength of 1340 nm is used for cutting the main conductive metal layer 36A made of a metal mainly composed of aluminum, heat absorption is high and an energy margin is large with respect to silicon of the underlying semiconductor substrate. It is possible to take. The antireflection layer 38 and the barrier metal layer 37 made of a titanium nitride film, a titanium film, or the like can be cut by heating with infrared rays of 1050 nm. That is, laser processing of multilayer films having different absorption characteristics becomes possible. Since the laser energy margin can be increased, the processing yield can be further increased by using this apparatus for cutting the fuse.

Next, a method for evaluating a semiconductor integrated circuit device according to an embodiment of the present invention will be described. Here, a method for evaluating the ease of cutting Y of the fuse section (see FIG. 20) will be described. FIGS. 21A and 21B are a conceptual diagram and a characteristic diagram for explaining this evaluation method.

As shown in FIG. 21A, there is a fuse group in which n, m, and h fuses 51 formed on a semiconductor substrate are connected in parallel (where n, m, and h are two or more different numbers). Make a sample. The fuse portions 51 of these samples are the same as those of the semiconductor integrated circuit device to be evaluated, and the fuse portions 51 of each sample are connected by a wiring layer 52 forming the same. Next, a resistance value between terminals (ab, ad, ac, bd, etc.) of the fuse group of each sample is measured as an initial characteristic. Next, each sample is irradiated with a laser beam to cut all the fuse portions, and then the resistance value between the terminals of the fuse group (ab, ad, ac, bd, etc.) is again measured. Measure as characteristics after cutting. For each sample, the ease of cutting (cutting yield) Y is calculated from the results of the initial characteristics and the characteristics after cutting, and plotted (FIG. 21B). In FIG. 21B, the number of cuts is plotted on the horizontal axis (log scale), and the easiness of cutting (cutting yield) Y is plotted on the vertical axis (linear scale).

As the initial characteristics and the characteristics after cutting, the resistance values between a-b, a-d, a-c, and b-d were measured. The conductivity of the other terminals b, c, and d is measured by the initial characteristics. After the disconnection, the disconnection is confirmed by the resistance value between a and b, the resistance between a and d, and the resistance value between b and c. Confirmation requires measurements between ac and bd.

Further, a method of calculating the ease of cutting (cutting yield) Y from the results of the initial characteristics (characteristics before cutting) and the characteristics after cutting, specifically, compares the resistance value before cutting with the resistance value after cutting. It is determined that the one having a change in the resistance value before and after the disconnection that is equal to or more than a certain value can be cut off, or that the resistance value after the disconnection can be cut off when the resistance value is equal to or more than a certain resistance value can be disconnected. The number is divided by the total number of cutting processes to calculate the ease of cutting (cutting yield) Y. In other words, the ease of cutting (cutting yield) Y means the ratio of the cut.

In each sample, since most of the fuse portions can be cut, it is impossible to calculate the cut probability of each fuse. However, as shown in FIG. The h cut easiness Y is on a straight line, and it is possible to accurately estimate and evaluate the cut easiness Y in the number applied (actually used) to an actual semiconductor integrated circuit device.

Here, three samples in the case where the number of fuses connected in parallel are n, m, and h are used as samples, but two or more samples can be used. As the number of samples increases, the accuracy of estimating the ease of cutting Y in the number of fuses actually used increases.

In the past, resistance values at both ends of each fuse section were measured after cutting, but there was a limit to the number of electrodes that could be arranged on a wafer. In addition, the conductivity between the probe and the electrode must be assured for measurement on the wafer. Even if the probe is displaced from the electrode, the resistance value will increase. There was a possibility to judge. Then, it was impossible to evaluate the cutting yield when the number of cuts in the cutting yield near 100% increased.

A semiconductor integrated circuit device and a method of manufacturing the same according to the present invention have an effect of preventing a reduction in reliability and a reduction in manufacturing yield due to cutting of a fuse portion, and provide a redundancy repair circuit and a function adjustment circuit for a large-capacity memory. The present invention is useful for a semiconductor integrated circuit device having a fuse section used for a semiconductor device.

FIG. 2 is a main part cross-sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the first embodiment of the present invention. FIG. 4 is a flowchart showing a method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 9 is a main part sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 11 is a process sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the second embodiment of the present invention. FIG. 11 is a process sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the second embodiment of the present invention. FIG. 9 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention. FIGS. 9A and 9B are a main part plan view and a sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention. FIGS. FIG. 13 is a main part sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the third embodiment of the present invention. FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the third embodiment of the present invention. FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the third embodiment of the present invention. FIG. 13 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the fourth embodiment of the present invention. FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor integrated circuit device in the fourth embodiment of the present invention. FIG. 14 is a flowchart showing a method of manufacturing a semiconductor integrated circuit device according to a fourth embodiment of the present invention. FIG. 15 is a plan view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. FIG. 15 is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention. FIG. 2 is a cross-sectional view for explaining preferred dimensions of each part of the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 3 is a diagram showing a relationship between dimensions of each part of the semiconductor integrated circuit device according to the embodiment of the present invention and easiness of cutting a fuse part. FIG. 4 is a diagram for explaining a method for evaluating a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 7 is a main partial cross-sectional view of a conventional semiconductor integrated circuit device.

Explanation of reference numerals

Reference Signs List 11 semiconductor substrate 12 interlayer insulating film 13 fuse section 14 inorganic insulating protective film 15 organic insulating protective film 16 opening 17 pad electrode 18 opening 19 opening 20 inorganic insulating protective film on fuse section

Claims (15)

In a semiconductor integrated circuit device having a fuse section for laser cutting,
An insulating film formed on a semiconductor substrate,
Comprising the fuse portion comprising a wiring layer formed on the insulating film,
The semiconductor integrated circuit device according to claim 1, wherein the wiring layer of the fuse section includes at least a barrier metal layer formed on the insulating film and a main conductive metal layer formed on the barrier metal layer. The semiconductor integrated circuit device according to claim 1,
Having an inorganic insulating protective film formed on the wiring layer and the insulating film,
The semiconductor integrated circuit device, wherein the inorganic insulating protective film on the fuse part is not thinned or left by etching. The semiconductor integrated circuit device according to claim 1, wherein
The semiconductor integrated circuit device according to claim 1, wherein the barrier metal layer is a single-layer film made of titanium nitride, titanium, or tungsten nitride, or a multi-layer film thereof. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein the thickness of the barrier metal layer is 150 nm or less. The semiconductor integrated circuit device according to any one of claims 1 to 4,
The semiconductor integrated circuit device according to claim 1, wherein the main conductive metal layer is a metal mainly composed of aluminum. The semiconductor integrated circuit device according to any one of claims 1 to 5,
The semiconductor integrated circuit device according to claim 1, wherein the wiring layer of the fuse portion further includes an antireflection film formed on the main conductive metal layer. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device according to claim 1, wherein the fuse portion is formed of an uppermost wiring layer among multilayer wiring layers formed on the insulating film. The semiconductor integrated circuit device according to any one of claims 1 to 7,
A semiconductor integrated circuit device, wherein a wiring width of a region of the fuse section to be cut is 0.1 μm or more and 1.0 μm or less. In a method of manufacturing a semiconductor integrated circuit device having a fuse portion for laser cutting,
Forming an insulating film on the semiconductor substrate;
Forming the fuse section made of a wiring layer on the insulating film,
The semiconductor integrated circuit device according to claim 1, wherein the wiring layer of the fuse portion has at least a barrier metal layer formed on the insulating film and a main conductive metal layer formed on the barrier metal layer. Method. The method for manufacturing a semiconductor integrated circuit device according to claim 9,
After the step of forming the fuse section, the method includes a step of forming an inorganic insulating protective film on the wiring layer and the insulating film, and a step of at least thinning the inorganic insulating protective film on the fuse section by etching. A method of manufacturing a semiconductor integrated circuit device. The method of manufacturing a semiconductor integrated circuit device according to claim 9,
The method for manufacturing a semiconductor integrated circuit device, wherein the barrier metal layer is a single-layer film made of titanium nitride, titanium or tungsten nitride, or a multi-layer film thereof. The method for manufacturing a semiconductor integrated circuit device according to any one of claims 9 to 11,
The method of manufacturing a semiconductor integrated circuit device, wherein the thickness of the barrier metal layer is 150 nm or less. The method of manufacturing a semiconductor integrated circuit device according to claim 9,
The method for manufacturing a semiconductor integrated circuit device, wherein the main conductive metal layer is a metal mainly composed of aluminum. The method of manufacturing a semiconductor integrated circuit device according to claim 9,
The method for manufacturing a semiconductor integrated circuit device, wherein the wiring layer of the fuse portion further includes an antireflection film formed on the main conductive metal layer. The method of manufacturing a semiconductor integrated circuit device according to claim 9,
A method of manufacturing a semiconductor integrated circuit device, wherein a wiring width of an area to be cut of the fuse portion is 0.1 μm or more and 1.0 μm or less.

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