JP2004146490A - Method for manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a highly reliable grooved wiring by improving the coverage at the time of film formation in a groove opening and forming a film without generating overhang, thereby reducing the occurrence of defective copper embedding.
A step of forming a wiring groove on an interlayer insulating film formed on a semiconductor substrate, and a step of forming a copper diffusion barrier property over the entire surface of the interlayer insulating film including an inner surface of the wiring groove. Forming a barrier layer 14 having a metal layer, forming a seed layer 15 for electrolytic plating over the entire surface of the interlayer insulating film 12 including the inner surface of the wiring groove 13, and forming the seed layer 15 by an electrochemical film forming method. A step of forming an impurity layer 16 thereon, a step of forming a conductive layer 17 so as to fill the wiring groove 13, a step of diffusing an element contained in the impurity layer 16 into the conductive layer 17 by heat treatment, Removing the excess conductive layer 17 from the insulating layer 12 to the barrier layer 14.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for forming a wiring having a buried wiring structure.
[0002]
[Prior art]
In the LSIs of the 0.18 μm generation or later, the miniaturization of wiring has progressed, and it has become impossible to ignore the RC delay (wiring delay due to the resistance R and the capacitance C) in order to increase the speed of the transistor. Accordingly, semiconductor devices adopting a low dielectric constant film as an interlayer insulating film or introducing a copper wiring having a higher conductivity than an aluminum wiring conventionally used as a wiring material are increasing. Because copper has a higher melting point than aluminum, copper is less likely to deform, and as a result, migration (atom transfer), which is prominent in aluminum wiring, is expected to be less likely to occur.
[0003]
However, it has become clear that stress migration and electromigration also occur in copper wiring used in semiconductor devices, and disconnection of wiring has begun to become a problem due to migration. As used in aluminum wiring, it has already been adopted to add impurities to the wiring material and harden the wiring material to make migration less likely to occur. In order to achieve the same effect, there has been reported a case in which impurities such as silver (Ag), niobium (Nb), and aluminum oxide (Al ₂ O ₃ ) are added to a copper wiring (for example, see Patent Document 1). .).
[0004]
[Patent Document 1]
Japanese Patent No. 3040745 (page 3, FIG. 8)
[0005]
[Problems to be solved by the invention]
However, since the method of adding impurities is mainly a method using a sputtering method, in the case of trench wiring, it becomes difficult to introduce impurities into the wiring as the wiring width becomes narrower. Further, when the seed layer used in the electrolytic plating is formed by the sputtering method, the coverage to the trench wiring side wall and the bottom becomes uniform, so that the impurity concentration in the wiring after annealing becomes non-uniform. Further, in the method of sputtering a metal that is lower than copper, there is a problem that an additive element is eluted during copper electrolytic plating.
[0006]
Further, when the sputtering method is used, there is a problem that the frontage portion 113 becomes narrow due to overhang of the impurity layer 116 or the like depending on the sputtering conditions, as shown in FIG. 4, and the barrier metal layer (barrier layer) 114 and the copper seed layer 115 When the entirety of the impurity layer 116 is formed by sputtering, overhanging at the opening is promoted, and as shown in FIG. There is also a problem that the void 131 is likely to generate, for example, due to the improper embedding.
[0007]
[Means for Solving the Problems]
The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems.
[0008]
According to a first method of manufacturing a semiconductor device of the present invention, a wiring recess is formed on an interlayer insulating film formed on a semiconductor substrate, and the wiring recess is formed over the entire surface of the interlayer insulating film including the inner surface of the wiring recess. A step of forming a barrier layer having a copper diffusion barrier property, a step of forming a seed layer of electrolytic plating over the entire surface of the interlayer insulating film including the inner surface of the wiring recess, and an electrochemical film forming method Forming an impurity layer on the seed layer, forming a conductive layer so as to fill the wiring recess, and diffusing an element contained in the impurity layer into the conductive layer by heat treatment. And a step of removing excess from the conductive layer to the barrier layer on the interlayer insulating film.
[0009]
In the first method for manufacturing a semiconductor device, since the impurity layer is formed by using an electrochemical film formation method having better step coverage than the sputtering method, an impurity layer having excellent step coverage with reduced overhang is formed. You. Therefore, it is possible to reduce the embedding defect of the conductive layer and to uniformly diffuse the element contained in the impurity layer into the conductive layer. In addition, by forming the impurity layer using a metal that is more noble than copper, when the conductive layer is formed by copper electrolytic plating, particularly when the conductive layer comes into contact with a copper electrolytic plating solution, the impurity layer becomes a protective film. The element of the seed layer does not elute into the copper electrolytic plating solution.
[0010]
According to a second method of manufacturing a semiconductor device of the present invention, a wiring recess is formed on an interlayer insulating film formed on a semiconductor substrate, and the wiring recess is formed over the entire surface of the interlayer insulating film including the inner surface of the wiring recess. A step of forming a barrier layer having a copper diffusion barrier property, a step of forming a seed layer of electrolytic plating over the entire surface of the interlayer insulating film including the inner surface of the wiring recess, and an electrochemical film forming method Forming a catalyst layer on the seed layer, forming an impurity layer using the catalyst layer, forming a conductive layer so as to fill the wiring recess, and heat treating the catalyst layer. And a step of diffusing an element contained in the impurity layer into the conductive layer, and a step of removing excess from the conductive layer to the barrier layer on the interlayer insulating film.
[0011]
In the second method for manufacturing a semiconductor device, since the catalyst layer and the impurity layer are formed by using an electrochemical film forming method having better step coverage than the sputtering method, the impurity having excellent step coverage with reduced overhang is provided. A layer is formed. For this reason, it is possible to reduce the embedding failure of the conductive layer and to uniformly diffuse the elements contained in the catalyst layer and the impurity layer into the conductive layer. Also, by using a metal which is nobler than copper for the impurity layer, when the conductive layer is formed by copper electrolytic plating, particularly when the conductive layer comes into contact with a copper electrolytic plating solution, the impurity layer becomes a protective film and becomes a copper electrolytic plating. The element of the seed layer does not elute into the liquid.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
A first embodiment according to a first method of manufacturing a semiconductor device of the present invention will be described with reference to a manufacturing process sectional view of FIG.
[0013]
As shown in FIG. 1A, after a predetermined element (not shown) is formed on a semiconductor substrate 11, an interlayer insulating film 12 is formed. Further, a groove 13 is formed in the insulating film 12 as a wiring recess. Subsequently, the barrier layer 14 is formed of, for example, tantalum (Ta) or tantalum nitride (TaN) having a diffusion barrier property of copper by a PVD method, and the seed layer 15 used at the time of electrolytic plating of copper is formed of copper.
[0014]
Next, as shown in FIG. 1B, the seed layer 15 is brought into contact with an aqueous solution containing palladium chloride ions, and palladium is deposited on the seed layer 15 by displacement plating to form an impurity layer 16. In this displacement plating, for example, an aqueous solution of palladium chloride (0.2 mol / L) is used, and the impurity layer 16 is formed by immersion in the solution at room temperature for 30 seconds. Since the palladium ion in the aqueous palladium chloride solution has a smaller ionization tendency than the copper ion, substitution of electrons in the copper and the palladium ion of the seed layer 15 occurs, and instead of the copper ion being dissolved, palladium is replaced on the copper seed layer 15. Is deposited. Thus, the palladium impurity layer 16 is formed by the electrochemical film forming method. At this time, the impurity layer 16 may not be a continuous film, for example, it is formed in a so-called island shape.
[0015]
Subsequently, as shown in FIG. 1C, the conductive film 17 is formed by electrolytic plating via the barrier layer 14, the seed layer 15 and the impurity layer 16 so as to fill the trench 13 on the interlayer insulating film 12. For example, it is formed of copper. Generally, copper plating is performed to a thickness of about 1 micron at a current density of ⁶ mA / cm ² to ²⁰ mA / cm ² using a copper sulfate-based plating solution (here, as an example, 6 mA / cm ² : 1 minute). Then, plating was performed at 20 mA / cm ² until the total power reached 13.0 A · min.).
[0016]
Subsequently, as shown in FIG. 1D, by heat treatment, the palladium in the impurity layer 16 (refer to FIG. 1C) is converted to a copper conductive film 17 (see FIG. 1C). Including the layer 15: hereinafter, the seed layer 15 and the conductive film 17 are also diffused. This heat treatment is performed, for example, at a temperature of 150 ° C. to 350 ° C. (here, as an example, furnace annealing at 200 ° C. is performed for 30 minutes). FIG. 1 (4) shows the state after palladium has been diffused.
[0017]
Thereafter, as shown in FIG. 1 (5), the conductive film 17 is left only in the trench 13 via the barrier layer 14 by chemical mechanical polishing (CMP) or electrolytic polishing or the like so that the conductive film 17 is left. Unnecessary conductive film 17 and barrier layer 14 are removed. In this way, the wiring 18 made of the conductive film 17 in which palladium is diffused via the barrier layer 14 in the groove 13 is formed.
[0018]
The displacement plating is not limited to the palladium displacement plating, and the same effect can be obtained by displacement plating silver (Ag) using an aqueous silver nitrate solution. Alternatively, a commercially available catalyzer (palladium chloride / stannic chloride / hydrochloric acid aqueous solution) is applied to the substrate, and then a commercially available accelerator (sulfuric acid / hydrochloric acid aqueous solution) is applied to release the tin and adhere the palladium to the surface. May be used.
[0019]
In the first method for manufacturing a semiconductor device, since the impurity layer 16 is formed using an electrochemical film forming method having better step coverage than the sputtering method, the impurity layer 16 having less overhang and having excellent step coverage can be formed. It is formed. For this reason, it is possible to reduce the embedding defect of the conductive layer 17 and to uniformly diffuse the element contained in the impurity layer 16 into the conductive layer 17. In addition, since the impurity layer 16 is formed of a metal that is more noble than copper, the impurity layer 16 does not elute when the conductive layer 17 is formed by copper electrolytic plating.
[0020]
Next, a second embodiment of the first method for manufacturing a semiconductor device according to the present invention will be described with reference to the cross-sectional views of the manufacturing process shown in FIG.
[0021]
As shown in FIG. 2A, after forming a predetermined element (not shown) on a semiconductor substrate 11, an interlayer insulating film 12 is formed. Further, a groove 13 serving as a wiring recess is formed in the interlayer insulating film 12. Subsequently, the barrier layer 14 is formed of, for example, tantalum (Ta) or tantalum nitride (TaN) having a copper diffusion barrier property by a PVD method, and the seed layer 15 used at the time of electrolytic plating is formed of copper.
[0022]
Next, as shown in FIG. 2 (2), electrolytic plating is performed using an aqueous solution of palladium sulfate (0.2 mol / L to 0.5 mol / L). At this time, the replacement plating is started at the same time when the copper seed layer 15 is brought into contact with the plating solution, and there is a possibility that the copper (seed layer 15) may be etched more than necessary. And let it wet. After that, palladium plating (corresponding to a film thickness of 1 nm) is performed at ² mA / cm ² at an electric quantity of 0.01 A · min to form an impurity layer 16 on the surface of the seed layer 15. Thus, the impurity layer 16 is formed by an electrochemical film forming method.
[0023]
Subsequently, as shown in FIG. 2C, the conductive film 17 is formed by electrolytic plating via the barrier layer 14, the seed layer 15 and the impurity layer 16 so as to fill the inside of the groove 13 on the interlayer insulating film 12. For example, it is formed of copper. At this time, the impurity layer 16 has an effect of acting as an etching prevention film for the seed layer 15 when forming the conductive film 17.
[0024]
Subsequently, as shown in FIG. 2D, the palladium in the impurity layer 16 (see FIG. 2C) is converted into a conductive film 17 (seed layer 15 shown in FIG. 2C) by heat treatment. (Hereinafter referred to as the conductive film 17 including the seed layer 15). This heat treatment is performed, for example, at a temperature of 150 ° C. to 350 ° C. (here, as an example, furnace annealing at 200 ° C. is performed for 30 minutes). FIG. 2 (4) shows a state after palladium has been diffused.
[0025]
Thereafter, as shown in (5) of FIG. 2, the insulating film 12 is formed on the insulating film 12 by chemical mechanical polishing (CMP) or electrolytic polishing so that the conductive film 17 is left only in the groove 13 via the barrier layer 14. Unnecessary conductive film 17 and barrier layer 14 are removed. In this way, the wiring 18 made of the conductive film 17 in which palladium is diffused via the barrier layer 14 in the groove 13 is formed.
[0026]
The formation of the impurity layer 16 by the electrolytic plating method is not limited to the electrolytic plating method of palladium, and silver (Ag) may be plated to the same thickness as palladium using an aqueous silver nitrate / potassium iodide solution. Similar effects can be obtained. Electroplating may be performed using a silver cyanide / potassium cyanide aqueous solution.
[0027]
In the second embodiment, since the impurity layer 16 is formed by using an electrochemical film forming method (electrolytic plating method) having better step coverage than the sputtering method, the impurity having excellent step coverage with less overhang is formed. Layer 16 is formed. For this reason, it is possible to reduce the embedding defect of the conductive layer 17 and to uniformly diffuse the element contained in the impurity layer 16 into the conductive layer 17. In addition, since the impurity layer 16 is formed of a metal that is more noble than copper, the impurity layer 16 does not elute when the conductive layer 17 is formed by copper electrolytic plating.
[0028]
Next, an embodiment of the second method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional views of FIGS.
[0029]
As shown in FIG. 3A, after a predetermined element (not shown) is formed on a semiconductor substrate 11, an interlayer insulating film 12 is formed. Further, a groove 13 serving as a wiring recess is formed in the insulating film 12. Subsequently, the barrier layer 14 is formed of, for example, tantalum (Ta) or tantalum nitride (TaN) having a copper diffusion barrier property by a PVD method, and the seed layer 15 used at the time of electrolytic plating is formed of copper.
[0030]
Next, as shown in FIG. 3 (2), catalysis generally used for electroless plating is performed. A commercially available catalyzer (palladium chloride / stannic chloride / hydrochloric acid aqueous solution) is applied to the surface of the seed layer 15, and then a commercially available accelerator (sulfuric acid / hydrochloric acid aqueous solution) is applied to release tin and deposit palladium on the surface of the seed layer 15. Then, the catalyst layer 21 is formed. At this time, the catalyst layer 21 does not have to be a continuous film, for example, is formed in a so-called island shape.
[0031]
Thereafter, as shown in (3) of FIG. 3, a silver nitrate / ammonia aqueous solution (silver solution) and a reducing agent solution (for example, formalin aqueous solution) are mixed on the surface of the substrate (seed layer 15) using, for example, a spray gun. Then, a silver (Ag) is deposited using the palladium catalyst layer 21 (see (2) in FIG. 3) to form a silver impurity layer 16 having a thickness of about 1 nm with palladium as a nucleus. . Thus, the catalyst layer 21 and the impurity layer 16 are formed by an electrochemical film forming method.
[0032]
Subsequently, as shown in FIG. 3D, a conductive film 17 is formed by electrolytic plating via the barrier layer 14, the seed layer 15 and the impurity layer 16 so as to fill the inside of the groove 13 on the interlayer insulating film 12. For example, it is formed of copper. At this time, the impurity layer 16 has an effect of acting as an etching prevention film for the seed layer 15 when forming the conductive film 17.
[0033]
Subsequently, as shown in FIG. 3 (5), the palladium in the impurity layer 16 (see FIG. 3 (4)) is converted into a conductive film 17 (see FIG. 3 (4)) by heat treatment. Including: the conductive layer 17 including the seed layer 15). This heat treatment is performed, for example, at a temperature of 150 ° C. to 350 ° C. (here, as an example, furnace annealing at 200 ° C. is performed for 30 minutes). FIG. 3 (5) shows a state after palladium and silver are diffused.
[0034]
Thereafter, as shown in FIG. 3 (6), the conductive film 17 is left only in the trench 13 via the barrier layer 14 by chemical mechanical polishing (CMP) or electrolytic polishing or the like so that the conductive film 17 is left on the interlayer insulating film 12. Unnecessary conductive film 17 and barrier layer 14 are removed. In this way, the wiring 18 made of the conductive film 17 in which palladium is diffused via the barrier layer 14 in the groove 13 is formed.
[0035]
In the characterization method as in the above embodiment, palladium is generally used for the catalyst layer 21, but silver (Ag), platinum (Pt), and gold (Au) can be used, for example. . In the case of an electroless plating solution using a reducing agent such as hypophosphorous acid or formalin, a nickel (Ni) catalyst layer and a cobalt (Co) catalyst layer can be used.
[0036]
For the electroless plating of Pd or Ag, a normal immersion method may be used.
[0037]
In the second method for manufacturing a semiconductor device, since the catalyst layer 21 and the impurity layer 16 are formed by using an electrochemical film forming method having better step coverage than the sputtering method, the step coverage with less overhang is excellent. Impurity layer 16 is formed. For this reason, it is possible to reduce the embedding defect of the conductive layer 17 and to uniformly diffuse the element contained in the impurity layer 16 into the conductive layer 17. Further, by using a metal which is nobler than copper for the impurity layer 16, the elements of the impurity layer 16 do not elute when the conductive layer 17 is formed by copper electrolytic plating.
[0038]
In each of the above embodiments, the so-called single damascene structure in which only the trench wiring is formed is described. However, a wiring groove and a connection hole reaching the lower layer wiring are formed at the bottom of the wiring groove. The present invention can be applied to a so-called dual damascene structure in which a trench wiring and a plug connected to a lower wiring are formed at the same time by embedding a conductive film in the substrate, and the same effect can be obtained.
[0039]
In each of the above embodiments, palladium is used as a metal nobler than the seed layer 15 made of copper used for the impurity layer 16. However, the impurity layer may be made of a metal nobler than copper, for example, silver (Ag). ), Platinum (Pt), gold (Au), or the like. In particular, it is preferable to use palladium and silver as the metal having migration resistance without increasing the specific resistance of copper.
[0040]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, since the impurity layer is formed by an electrochemical film forming method, the impurity layer is formed with good coverage and without overhang. An element (Pd, Ag, or the like) of an impurity layer can be uniformly added to a conductive film in which a wiring is formed, so that electromigration resistance, that is, reliability of the wiring can be improved. In addition, the use of a metal which is more noble than copper for the impurity layer also has the effect of reinforcing the seed layer, and prevents elution of the seed layer during electrolytic plating for forming a conductive film (at the moment of contact with the electrolytic plating solution). Therefore, the embedding property of the electrolytic plating can be improved. Therefore, it is possible to manufacture a semiconductor device having highly reliable wiring.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a manufacturing process of a first embodiment of a semiconductor device according to the present invention in FIG.
FIG. 2 is a cross-sectional view of the manufacturing process of the second embodiment of the semiconductor device according to the first embodiment of the present invention, which is shown in FIG. 2;
FIG. 3 is a cross-sectional view illustrating a manufacturing step of the embodiment of the second manufacturing method of the semiconductor device according to the present invention in FIG. 3;
FIG. 4 is a schematic cross-sectional view illustrating a defect due to an overhang of an impurity layer.
FIG. 5 is a schematic cross-sectional view illustrating a failure in embedding a copper film due to overhang.
[Explanation of symbols]
11 semiconductor substrate, 12 interlayer insulating film, 13 groove, 14 barrier layer, 15 seed layer, 16 impurity layer, 17 conductive layer

Claims (6)

Forming a wiring recess on the interlayer insulating film formed on the semiconductor substrate;
Forming a barrier layer having a copper diffusion barrier property over the entire surface of the interlayer insulating film including the inner surface of the wiring recess;
Forming a seed layer of electrolytic plating over the entire surface of the interlayer insulating film including the inner surface of the wiring recess;
Forming an impurity layer on the seed layer by an electrochemical film forming method;
Forming a conductive layer so as to fill the wiring recess,
Diffusing the element contained in the impurity layer into the conductive layer by heat treatment;
Removing the excess from the conductive layer to the barrier layer on the interlayer insulating film. 2. The method according to claim 1, wherein the impurity layer is formed by displacement plating a metal which is more noble than the seed layer. The method according to claim 1, wherein the impurity layer is formed by depositing palladium using a sensitizing-activating method using tin ions. 2. The method according to claim 1, wherein the impurity layer is formed by electroplating a metal that is nobler than the seed layer. Forming a wiring recess on the interlayer insulating film formed on the semiconductor substrate;
Forming a barrier layer having a copper diffusion barrier property over the entire surface of the interlayer insulating film including the inner surface of the wiring recess;
Forming a seed layer of electrolytic plating over the entire surface of the interlayer insulating film including the inner surface of the wiring recess;
Forming a catalyst layer on the seed layer by an electrochemical film forming method,
Forming an impurity layer using the catalyst layer;
Forming a conductive layer so as to fill the wiring recess,
Diffusing the elements contained in the catalyst layer and the impurity layer into the conductive layer by heat treatment;
Removing the excess from the conductive layer to the barrier layer on the interlayer insulating film. 6. The method according to claim 5, wherein the impurity layer is formed by electrolessly plating a metal that is more noble than the seed layer.

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