JP2004014874A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control the thickness of a film obtained after a mechanical/chemical polishing process at high accuracy and high throughput in a semiconductor device manufacturing method having the mechanical/chemical polishing process. <P>SOLUTION: In steps S21 to S24 of a system for controlling the film thickness after polishing a semiconductor device wafer, the polishing rate profile of a reference wafer is found out from the film thickness measured values obtained after and before polishing the reference wafer, a film thickness profile of a wafer product before polishing is predicted from the measured value of the film thickness before polishing the reference wafer or a film forming profile, a film thickness profile of the wafer product after polishing is predicted from the polishing rate profile of the reference wafer and the predicted value of the film thickness profile of the wafer product before polishing, and the film thickness of parts whose film thickness prediction value after polishing the inner surface of the wafer product is maximum and minimum is measured on the basis of the predicted value of the film thickness profile of the product wafer after polishing to control the film thickness of a semiconductor device wafer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique effective in applying the method to the control of the film thickness of a semiconductor device wafer after mechanical chemical polishing (hereinafter referred to as CMP).
[0002]
[Prior art]
2. Description of the Related Art Densification of integrated circuits in semiconductor devices is continuing to progress. Also, with the increase in density, the importance of multilayer wiring and the accompanying technology for forming metal electrodes such as formation of interlayer insulating films, plasma, and damascene has been increasing.
[0003]
In particular, as the wiring layers are continuously deposited and etched, the top surface of the substrate, ie, the exposed surface of the substrate, becomes increasingly uneven. This non-planar surface is usually formed by continuously depositing a conductive, semiconductive or insulating layer on a substrate, especially a silicon wafer.
[0004]
The uneven surface causes a problem in a photolithography process in an integrated circuit manufacturing process in the manufacture of a semiconductor device. Therefore, it is necessary to periodically flatten the substrate surface to provide a flat surface.
[0005]
As a method for performing this planarization over the entire wafer region, a CMP method has been developed, and has become influential as a method for planarizing a semiconductor device wafer.
[0006]
In addition, as a technique related to such a CMP, for example, a technique described in “Detailed Explanation Semiconductor CMP Technology” issued by the Industrial Research Institute, Inc. on January 10, 2001 can be cited.
[0007]
[Problems to be solved by the invention]
However, since the film thickness profile of the product device wafer after the CMP changes depending on the pattern in the product wafer and the chip, the use time of the polishing pad, and the like, it is required to constantly measure the film thickness of the interlayer layer and the metal layer. .
[0008]
Therefore, for example, a method of measuring the film thickness using a general film thickness measuring device is considered.
[0009]
That is, this general film thickness measuring device cannot measure the actual pattern in the chip, and therefore measures the film thickness profile in the chip by performing SEM measurement (destructive measurement) on the cross section of the wafer in advance. In addition, a method is conceivable in which the quality control pattern (two-dimensional distribution of film thickness, ie, a pattern having no pattern concept) is measured to correct and calculate the unevenness of the product pattern portion that one actually wants to know.
[0010]
In addition, as a technique relating to such a film thickness management method after the CMP, for example, a technique described in JP-A-2001-21317 is cited.
[0011]
By the way, as a result of the present inventor's investigation on the technique of the above-mentioned method of controlling the film thickness after the CMP, the following has become clear.
[0012]
For example, as means for measuring the film thickness after CMP, it is desired to control the film thickness with high accuracy and high throughput, but there is no method that satisfies them.
In particular, when the measurement range is wide, the measurement takes time and the throughput is low.
[0013]
Further, the polishing rate and the film formation profile in the wafer surface change with time. Along with this, the maximum and minimum points of the film thickness in the wafer surface also change, but it is difficult to make a prediction in consideration of the change with time.
[0014]
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device having a CMP process, which can control the film thickness after CMP with high accuracy and high throughput.
[0015]
As for such a technique, as described in Japanese Patent No. 30777656, there is a method of creating a new recipe by monitoring the polishing fluctuation amount and adding the fluctuation amount to the standard polishing amount recipe. The present invention is significantly different in that the film thickness before and after polishing is predicted, and the maximum and minimum points of the film thickness after polishing are measured, thereby controlling the film thickness with high accuracy and high throughput.
[0016]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0017]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0018]
That is, the method of manufacturing a semiconductor device according to the present invention manages the film thickness of a semiconductor device wafer after CMP with high accuracy and high throughput, and uses the measured film thickness before and after polishing of the reference wafer. Determining a polishing rate profile P _S (x, y) of the reference wafer; and a pre-polishing film thickness profile P of a product wafer on which a large number of product chips are formed from the pre-polishing film thickness measurement value or the film forming profile of the reference wafer. Estimating _P (x, y); the polishing rate profile P _S (x, y) of the reference wafer; the predicted value P _P (x, y) of the pre-polishing film thickness profile of the product wafer; polishing time T _S of the reference _wafer, wherein the product wafer polishing time T and product-specific factor alpha (x, y), the film thickness after polishing of the product wafer favorable profile Le P (x, y) into _{P (x, y) = P} P (x, y) -α (x, y) · T / T S · P S (x, y)
And the predicted value P (x, y) of the post-polishing film thickness profile of the product wafer is set to a maximum value and a minimum value after polishing. The film thickness of a semiconductor device wafer is controlled by measuring the film thickness of a portion.
[0019]
Further, in the prediction of the pre-polishing film thickness profile P _P (x, y) of the product wafer, when the pre-polishing film thickness of the product wafer is composed of a plurality of types of films, The film thickness profile P _P (x, y) before polishing of the product wafer is predicted from the film formation profile of the reference wafer.
[0020]
Further, by using an in-chip film thickness predicting means capable of predicting a post-polishing film thickness profile from the in-chip design information of the product wafer, the in-plane film predicted value of the post-polishing film thickness of the product wafer is used. The maximum / minimum film thickness in the product chip near the maximum / minimum is predicted, and the inside of the product chip is measured based on the information.
[0021]
Further, the product specific coefficient α (x, y) is determined based on design information in the product wafer.
[0022]
Further, the product specific coefficient α (x, y) is determined based on design information in the product wafer and in the chip.
[0023]
Further, the product specific coefficient α (x, y) is updated based on a measured film thickness after polishing of the product wafer.
[0024]
Further, the polishing rate profile P _S (x, y) and the film forming profile of the reference wafer are managed by an online system, updated periodically or in real time, and each time the product wafer is updated, the product wafer is updated. In this method, the post-polishing film thickness profile is predicted.
[0025]
Further, in the online system, each time a polishing rate profile for each apparatus / polishing head and a film forming profile for each apparatus / chamber are updated periodically or in real time, the maximum / minimum thickness of the product wafer after polishing is minimized. Is predicted.
[0026]
Further, by using a film thickness measurement device capable of measuring the film thickness of the actual pattern portion in the chip of the product wafer, the in-plane profile predicted value of the film thickness after polishing of the product wafer is maximum and minimum. It is characterized by measuring a product chip in the vicinity.
[0027]
Further, the film thickness measurement of the product wafer is performed by irradiating the surface of the product wafer with white light, performing a phase / frequency analysis of a spectral waveform of the reflected light, and obtaining a frequency corresponding to the uppermost layer film. The thickness of the uppermost film is calculated.
[0028]
Therefore, according to the method of manufacturing a semiconductor device, the product specific coefficient α (x, y) based on the unevenness information in the product chip in the semiconductor device wafer and the unevenness information other than the chip acquired as the product is used for each product chip. In this case, it is possible to predict different irregularity information and surface dripping phenomenon at the outer peripheral portion of the wafer.
[0029]
Further, in the present invention, the post-polishing film thickness profile of the product wafer is predicted each time based on information updated in real time or periodically in the online system. Can be predicted with high accuracy.
[0030]
Furthermore, by actually measuring the portion where the post-polishing film thickness predicted by the simulation becomes the maximum or minimum, the post-polishing film thickness of the product wafer can be managed with high reliability and high throughput.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0032]
FIG. 1 is a block diagram showing a configuration of a semiconductor device wafer post-polishing film thickness management system in a semiconductor device manufacturing method according to an embodiment of the present invention. FIG. FIG. 3 is a flow chart showing a method of estimating a post-polishing film thickness profile of a product wafer, FIG. 3 is a view showing a shot layout of a product wafer, FIG. 4 is a view showing a difference in polishing rate between a solid wafer and a product wafer, and FIG. FIG. 6 is a flowchart showing a method of predicting a post-polishing film thickness profile in a chip, FIG. 6 is a diagram showing a difference in a flattening process due to a difference in a projection area ratio in a product chip, and FIG. It is a flowchart which shows the online processing of a management system.
[0033]
First, an example of a configuration of a semiconductor device wafer post-polishing film thickness management system in a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIG.
[0034]
The semiconductor device wafer post-polishing film thickness management system 100 in the semiconductor device manufacturing method according to the present embodiment includes, for example, a data analysis workstation 110, a high-precision film thickness measuring device 13 in a factory, and the like. Via the I / O 8 in the station 110, it is connected online with the high-accuracy film thickness measuring device 13, the factory CIM system 1, the design information database 2, and the like.
[0035]
The data analysis workstation 110 includes an I / F 3, a CPU 4, a RAM 5, a ROM 6, an I / O 8, a polishing rate profile / film formation profile information storage unit 9 for a reference wafer, a wafer / chip film thickness prediction simulation program storage unit 10, and a design. An I / F 3, a CPU 4, a RAM 5, and a ROM 6 are connected to an I / O 8 via a bus line 7, and include a polishing rate profile of a reference wafer. A film formation profile information storage unit 9, a wafer / chip film thickness prediction simulation program storage unit 10, a design information storage unit 11, and a polished film thickness maximum / minimum point storage unit 12 are connected to the I / O 8.
[0036]
In the factory CIM system 1, the polishing rate profile P _S (x, y) of the reference wafer obtained from the film thickness measurement values before and after polishing of the reference wafer for each device and polishing head, which are periodically measured, Data management of the film formation profile for each type of film (GPSiO, O3TEOS, PTEOS, etc.), device, and chamber is performed.
[0037]
The design information database 2 manages layout data in a product wafer, layout data in a product chip, and configuration data of an insulating film (vertical structure such as PTEOS 1000 nm + GPSiO 500 nm).
[0038]
The polishing rate profile / film formation profile information storage unit 9 of the reference wafer in the data analysis workstation 110 stores the polishing rate profile P _S (x, y) and the film formation profile of the reference wafer managed in the factory CIM system 1. Each time the information is updated, the updated information is stored.
[0039]
A program for predicting a polished film thickness profile P (x, y) of a product wafer is stored in the wafer / chip film thickness prediction simulation program storage unit 10. The program is loaded into the RAM 5 and executed. Accordingly, the post-polishing film thickness profile P (x, y) of the product wafer is predicted according to the flow shown in FIG. Further, based on the film thickness profiles after polishing in the product wafer and in the product chips, detailed program maximum and minimum points on the entire surface of the wafer are predicted by this program. Further, each time the polishing rate profile P _S (x, y) and the film formation profile information of the reference wafer managed in the factory CIM system 1 are updated, the program is executed, and the post-polishing film thickness of the product wafer is executed. The profile P (x, y) is recalculated.
[0040]
The design information storage unit 11 stores information of the design information database 2 for each product.
[0041]
The post-polishing film thickness maximum / minimum point storage unit 12 stores post-polishing film thickness profile P (x, y) prediction data and film thickness maximum / minimum point prediction data for each product.
[0042]
As described in Japanese Patent Application Laid-Open No. 2000-310512, the high-precision film thickness measuring device 13 irradiates the surface of a semiconductor device wafer with white light, and analyzes the spectral waveform of the reflected light by frequency and phase analysis. The frequency corresponding to the uppermost layer film is obtained and the film thickness is calculated, and the actual pattern portion in the product chip can be measured.
[0043]
Next, a method of estimating a post-polishing film thickness profile of a product wafer will be described with reference to FIG.
[0044]
First, the polishing rate profile P _S (x, y) of the reference wafer in the factory CIM system 1, the information of the film formation profile and the design information in the design information storage unit 11 are read (step S 21), and the unpolished film of the product wafer is read. The thickness profile P _P (x, y) is predicted (step S22). The pre-polishing film thickness profile P _P (x, y) of the product wafer is obtained by combining the film profile data for each type of film (GPSiO, O3TEOS, PTEOS, etc.), device, and chamber managed by the factory CIM system 1. Predicted from the configuration data of the insulating film. As an example, an expression for obtaining a pre-polishing film thickness profile P _P (x, y) when the insulating film is formed of a PTEOS or GPSiO film is shown below. Incidentally, _{P P} is a function of (x, y), for convenience, it is omitted (x, y).
[0045]
P _P = P _SPTEOS · D _PTEOS / Ds _PTEOS + P _SGPSiO · D _GPSiO / Ds _GPSiO
P _SPTEOS: reference wafer PTEOS film thickness profile _{D PTEOS:} product wafer PTEOS thickness _{Ds PTEOS:} PTEOS thickness of the reference wafer _{P SGPSiO:} GPSiO thickness profile _{D GPSiO} reference wafer: the product wafer GPSiO thickness _{Ds GPSiO:} Next, the product specific coefficient α (x, y) determined based on the design information in the design information storage unit 11, the polishing rate profile P _S (x, y) of the reference wafer, and the GPSiO film thickness of the reference wafer before polishing film thickness profile _{P P} (x, y) and after polishing thickness of the product wafer from a polishing time T of products wafers profile P (x, y) to predict (step S23, step S24). An equation for obtaining the post-polishing film thickness profile P (x, y) of the product wafer is shown below.
[0046]
_{P (x, y) = P} P (x, y) -α (x, y) · T / T S · P S (x, y)
T _S : polishing time of reference wafer T: polishing time of product wafer P _S (x, y): polishing rate profile of reference wafer α (x, y): product specific coefficient As described above, product specific coefficient α (x , Y), it is possible to simulate the influence other than the product chips in the wafer peculiar to the product wafer by predicting the polished film thickness profile P (x, y) of the product wafer.
[0047]
For example, when the shot layout of the product wafer is as shown in FIG. 3, and as shown in FIG. 4, when the positive resist is used and the area outside the product is removed, polishing of the solid wafer and the product wafer is performed. Rates are different. Thus, the post-polishing film thickness profile P (x, y) of the product wafer is affected, but can be corrected by the product specific coefficient α (x, y).
[0048]
Next, a post-polishing film thickness profile in the product chip is predicted based on the in-chip unevenness information of the design data. FIG. 5 shows the flow.
[0049]
First, based on the unevenness information based on the design information, a film thickness profile before polishing in a product chip, which is the unevenness film thickness distribution after film formation of O3TEOS, PTEOS, HDP or the like, is predicted (step S51). As a prediction method, an in-chip profile prediction coefficient after film formation may be experimentally obtained.
[0050]
Subsequently, the film thickness profile before polishing in the product chip is divided into divided regions id (arbitrary) based on the film thickness profile after film formation in the product chip (step S52).
[0051]
Here, assuming that the area ratio of the protrusions in each divided region is ρ (x, y), the film thickness z after T time in the divided region in the initial stage of polishing is as follows.
[0052]
z = z ₀ −KT / ρ (x, y)
K: Polishing rate z _{0 of the} solid film wafer: Initial film thickness Then, the film thickness z after the convex portions are flattened is as follows.
[0053]
z = z ₀ −z ₁ −KT + ρ (x, y) z ₁
z ₁ : Initial unevenness step At this time, chip flattening as shown in FIG. 6 is performed on the convex pattern area density of each divided area, that is, the sparse / medium / dense area ratio (in FIG. 6, Tt is the total Polishing time).
[0054]
Therefore, a distribution of the difference in film thickness occurs between the divided regions after polishing. In other words, the difference in film thickness in each of the divided regions becomes the post-polishing film thickness profile in the chip.
[0055]
A post-polishing film thickness profile in the product chip is predicted based on the above idea (step S53).
[0056]
Then, based on the above-described wafer and chip film thickness profiles, a detailed film thickness maximum / minimum point on the entire wafer is predicted by the wafer / chip film thickness prediction simulation program.
[0057]
Next, the flow of online processing in the semiconductor device wafer polishing thickness control system 100 will be described with reference to FIG.
[0058]
First, each time the polishing rate profile P _S (x, y) and the film formation profile of the reference wafer are updated in the factory CIM system 1, the server in the semiconductor device wafer post-polishing film thickness management system 100 updates the I / O 8 Then, the information is stored in the polishing rate profile / film formation profile information storage unit 9 of the reference wafer (step S71).
[0059]
Also, each time a new product is registered in the design information database 2, the server in the semiconductor device wafer polished film thickness management system 100 stores the information in the design information storage unit 11 via the I / O 8 ( Step S75).
[0060]
Then, the update of the polishing rate profile P _S (x, y) and the film formation profile of the reference wafer in step S71 as a trigger causes the simulation program stored in the wafer / chip internal film thickness prediction simulation program storage unit 10 to be stored in the RAM 5. Of the products that are loaded and stored in the design information storage unit 11, for all the products related to the update information, detailed prediction of the maximum and minimum points of the thickness after polishing on the entire product wafer is performed again (steps S72 to S72). S74, steps S76 to S78).
[0061]
Next, the result calculated in step S78 is stored in the post-polishing film thickness maximum / minimum point storage unit 12 (step S79).
[0062]
Next, the calculated position information of the maximum and minimum points of the thickness after polishing is transmitted to the high-accuracy film thickness measuring device 13 in the factory (step S710), and the measurement position information for each product or the measurement recipe for each product is updated. I do.
[0063]
When a new product is registered and the design information in the design information storage unit 11 is updated in step S75, the process from step S72 to step S710 is executed in the same manner as described above, using the update as a trigger.
[0064]
Therefore, by performing the above processing online in the semiconductor device wafer post-polishing film thickness management system 110, it is possible to predict the maximum and minimum points of the polishing thickness of the product wafer with high accuracy, and to improve the reliability. High film thickness control can be performed.
[0065]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0066]
For example, the inherent parameters determined by the simulation may fluctuate due to dimensional tolerances and variations of products, but the inherent parameters of each product are adjusted based on the values measured by the high-precision film thickness measuring device 13. It is also possible.
[0067]
If a value that does not satisfy the film thickness standard is found by simulation, compare with the past data stored in the storage unit, send an error message from the cause of large fluctuation, and give feedback such as process condition change. Is also possible.
[0068]
In the above embodiment, the film thickness on the surface of the product wafer after the CMP has been described. However, the present invention is not limited to this. Is also applicable.
[0069]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
(1) By estimating the post-polishing film thickness profile in the product wafer and the post-polishing film thickness profile in the product chip, the maximum and minimum points of the post-polishing film thickness of the product wafer can be predicted with high accuracy.
(2) Since the post-polishing film thickness profile P _S (x, y) of the product wafer is predicted each time based on information that is updated online or in real time or periodically, the maximum polishing film thickness of the product wafer is obtained. -The minimum point can be predicted with higher accuracy.
(3) By actually measuring the maximum and minimum points of the thickness of the product wafer after polishing predicted by the simulation, the thickness of the product wafer after polishing can be managed with high reliability and high throughput.
(4) The film thickness can be controlled over the entire area of the wafer, and the yield is improved.
(5) Since the film formation and polishing rate profiles can be updated in real time or periodically, the residual film profiles can be predicted based on the information and abnormalities can be detected early, so that the yield is improved.
(6) Since the inside of the chip can be measured, it is not necessary to provide a quality control (QC) pattern on the scribe, so that the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor device wafer post-polishing film thickness management system in a semiconductor device manufacturing method according to an embodiment of the present invention.
FIG. 2 is a flowchart showing a method of estimating a polished film thickness profile of a product wafer in the method of manufacturing a semiconductor device according to the present embodiment.
FIG. 3 is a view showing a shot layout of a product wafer in the method of manufacturing a semiconductor device according to the present embodiment;
FIG. 4 is a diagram showing a difference in polishing rate between a solid wafer and a product wafer in the method of manufacturing a semiconductor device according to the present embodiment.
FIG. 5 is a flowchart showing a method of estimating a polished film thickness profile in a product chip in the method of manufacturing a semiconductor device according to the present embodiment.
FIG. 6 is a diagram illustrating a difference in a flattening process due to a difference in a projection area ratio in a product chip in the method of manufacturing a semiconductor device according to the present embodiment.
FIG. 7 is a flow chart showing online processing of a film thickness management system after polishing a semiconductor device wafer in the method of manufacturing a semiconductor device according to the present embodiment.
[Explanation of symbols]
1 Factory CIM system 2 Design information database 3 I / F
4 CPU
5 RAM
6 ROM
7 Bus line 8 I / O
9 Reference wafer polishing rate profile / film formation profile information storage unit 10 Wafer / in-chip film thickness prediction simulation program storage unit 11 Design information storage unit 12 Maximum / minimum point storage unit for polished film thickness 13 High-precision film thickness measurement device 100 Semiconductor device wafer polishing thickness control system 110 Data analysis workstation

Claims (5)

A method of manufacturing a semiconductor device having a mechanical and chemical polishing step of a semiconductor device wafer,
The mechanical chemical polishing step,
Obtaining a polishing rate profile P _S (x, y) of the reference wafer from the measured film thickness before and after polishing of the reference wafer;
Estimating a pre-polishing film thickness profile P _P (x, y) from the pre-polishing film thickness measurement value or film forming profile of the reference wafer;
The polishing rate profile P _S (x, y) of the reference wafer, the predicted value P _P (x, y) of the film thickness profile before polishing of the product wafer, the polishing time T _{S of} the reference wafer, and the polishing time T _{S of} the product wafer. From the polishing time T and the product specific coefficient α (x, y), the polished film thickness profile P (x, y) of the product wafer is calculated as P (x, y) = P _P (x, y) −α (x, y) ) · T / T _S · P _S (x, y)
And predicting
Based on the predicted value P (x, y) of the post-polishing film thickness profile of the product wafer, measuring the film thickness of the portion where the predicted value of the post-polishing film thickness in the product wafer surface is maximum and minimum. A method for manufacturing a semiconductor device, comprising: controlling a film thickness of a semiconductor device wafer. The method for manufacturing a semiconductor device according to claim 1, wherein
The method of manufacturing a semiconductor device, wherein the product specific coefficient α (x, y) is determined based on design information in the product wafer and in the chip. The method for manufacturing a semiconductor device according to claim 1, wherein:
The method of manufacturing a semiconductor device, wherein the product specific coefficient α (x, y) is updated based on a measured film thickness after polishing of the product wafer. The method for manufacturing a semiconductor device according to claim 1, wherein:
The polishing rate profile P _S (x, y) and the film forming profile of the reference wafer are managed by an online system, and are updated periodically or in real time. A method for manufacturing a semiconductor device, comprising: estimating a film thickness profile P (x, y). The method for manufacturing a semiconductor device according to claim 1, wherein:
The film thickness measurement of the product wafer is performed by irradiating the surface of the product wafer with white light, performing a phase / frequency analysis of a spectral waveform of the reflected light, and obtaining a frequency corresponding to the top layer film, thereby obtaining the top layer film. A method of manufacturing a semiconductor device, wherein a film thickness of the semiconductor device is calculated.

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