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JP2004088791A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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JP2004088791A
JP2004088791A JP2003323904A JP2003323904A JP2004088791A JP 2004088791 A JP2004088791 A JP 2004088791A JP 2003323904 A JP2003323904 A JP 2003323904A JP 2003323904 A JP2003323904 A JP 2003323904A JP 2004088791 A JP2004088791 A JP 2004088791A
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frequency band
pin
input
amplifier
noise amplifier
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JP2004088791A5 (en
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Kumiko Takigawa
滝川　久美子
Satoshi Tanaka
田中　聡
Takashi Hashimoto
橋本　孝
Yoshiyuki Okabe
岡部　義行
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Hitachi Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent the frequency characteristics of the low noise amplifier and a reception mixer of a semiconductor integrated circuit for dual band transmission from degrading. <P>SOLUTION: The low noise amplifier is arranged at a position where the distance from the tip of an external pin of the low noise amplifier to its padding is the shortest. Mutual ground pins and mutual high frequency signal pins are arranged so that they are not adjacent. The ground pin of the low noise amplifier and the ground of a bias circuit are isolated. Pin layout is chosen so that mutual high frequency signal lines do not intersect. <P>COPYRIGHT: (C)2004,JPO

Description

　本発明は、主として高周波数バンドと、低周波数バンドの２つの周波数帯域の無線システムに適用する、デュアルバンド無線通信移動体端末機器において、低雑音増幅器を集積化したデュアルバンド送受信用半導体集積回路に関する。 The present invention relates to a dual band transmission / reception semiconductor integrated circuit in which a low noise amplifier is integrated in a dual band radio communication mobile terminal device mainly applied to a radio system of two frequency bands of a high frequency band and a low frequency band. .

　図４は、従来のデュアルバンド送受信用半導体集積回路（以下、送受信ＩＣと称す。）を適用した端末機器の構成例である。これは、２つの異なった周波数帯の無線通信システムの携帯端末に適用される。送受信ＩＣ４０１はデュアルバンド無線システムに適用する高周波数バンド受信ミキサ４０３ａ、及び低周波数バンド受信ミキサ４０３ｂ、次段のミキサ４０４、可変利得増幅器４０５、復調器４０６、変調器４０８、オフセットＰＬＬ４０９、及びデバイダ４０７から構成されている。周波数変換に必要な局部発振信号はシンセサイザ４１０、内蔵のデバイダ４０７から供給される。送受信ＩＣに接続された帯域通過フィルタ４１１は、帯域外スプリアスを除去する。高周波数バンド低雑音増幅器４０２ａ、及び低周波数バンド低雑音増幅器４０２ｂはＩＣ外付けとなっている。これまで、低雑音増幅器は、トランジスタプロセスのｆT限界や、トランジスタ基板間容量により高周波帯域での利得や、雑音特性の不足でIC内蔵化が困難であった。しかし、近年の微細プロセス向上により上記の問題が克服され、低雑音増幅器の内蔵が可能になった。
デュアルバンド送受信ＩＣに適用する低雑音増幅器の一例がKeng Leong Fong「Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications」ISSCC 1999,pp.224-225,p.463に開示されている。これは、デュアルバンド送受信ＩＣ向けに2つの低雑音増幅器を１チップ化し、TSSOP20ピンパッケージに封印したもので、送受信系全体を内蔵した構成でない。なお、信号線や接地線等とパッドの対応は不明である。また、低雑音増幅器を内蔵した送受信ＩＣの一例が、Michiel Steyaert et al.「A single-Chip CMOS Transceiver for DCS1800 wireless Communications」ISSCC 1998, pp.48-49, p.411である。これは、送受信回路を１チップ化したものであるが、デュアルバンドに適用するものでない。信号線や接地線等とパッドの対応は不明である。また、使用しているパッケージも不明である。 FIG. 4 is a configuration example of a terminal device to which a conventional dual-band transmission / reception semiconductor integrated circuit (hereinafter referred to as a transmission / reception IC) is applied. This applies to portable terminals of wireless communication systems in two different frequency bands. The transmission / reception IC 401 includes a high frequency band reception mixer 403a and a low frequency band reception mixer 403b, a next stage mixer 404, a variable gain amplifier 405, a demodulator 406, a modulator 408, an offset PLL 409, and a divider 407, which are applied to a dual band wireless system. It is composed of A local oscillation signal necessary for frequency conversion is supplied from a synthesizer 410 and a built-in divider 407. The band pass filter 411 connected to the transmission / reception IC removes out-of-band spurious. The high frequency band low noise amplifier 402a and the low frequency band low noise amplifier 402b are externally attached to the IC. Until now, low-noise amplifiers have been difficult to incorporate in an IC due to the fT limit of the transistor process, the gain in the high frequency band due to the capacitance between the transistor substrates, and the lack of noise characteristics. However, the above-mentioned problems have been overcome by the recent improvement in fine process, and it has become possible to incorporate a low-noise amplifier.
An example of a low-noise amplifier applied to a dual-band transceiver IC is disclosed in Keng Leong Fong “Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications” ISSCC 1999, pp.224-225, p.463 Yes. This is a dual-band transmission / reception IC with two low-noise amplifiers integrated into a single chip and sealed in a TSSOP 20-pin package, and does not have a built-in transmission / reception system. Note that the correspondence between signal lines, ground lines, etc., and pads is unknown. An example of a transmission / reception IC incorporating a low-noise amplifier is Michiel Steyaert et al. “A single-Chip CMOS Transceiver for DCS1800 wireless Communications” ISSCC 1998, pp. 48-49, p.411. This is a single-chip transmission / reception circuit, but it is not applied to a dual band. The correspondence between signal lines, ground lines, etc. and pads is unknown. Also, the package used is unknown.

Keng Leong Fong「Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications」ISSCC 1999,pp.224-225,p.463Keng Leong Fong `` Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications '' ISSCC 1999, pp.224-225, p.463

Michiel Steyaert et al.「A single-Chip CMOS Transceiver for DCS1800 wireless Communications」ISSCC 1998, pp.48-49, p.411Michiel Steyaert et al. "A single-Chip CMOS Transceiver for DCS1800 wireless Communications" ISSCC 1998, pp.48-49, p.411

　本発明では、図４で示したデュアルバンド向けの送受信回路チップ401に低雑音増幅器４０２ａ、及び４０２ｂを新たに内蔵した。この場合に、パッケージにおけるピンレイアウト上の課題が発見された。なお、本発明では、パッケージは４面にピンが配置されているQuad Flat package（以下、QFPと称す）を用いた。
第一の課題は、低雑音増幅器をQFPのリードピンのうち長いリードピンに長いボンディングワイヤでボンディングするようなレイアウトとすると、寄生インダクタンスによる負帰還量が大きくなり、高周波利得と雑音特性が劣化する、というものである。 In the present invention, low-noise amplifiers 402a and 402b are newly incorporated in the dual-band transceiver circuit chip 401 shown in FIG. In this case, a problem on the pin layout in the package was discovered. In the present invention, a quad flat package (hereinafter referred to as QFP) in which pins are arranged on four sides is used as the package.
The first problem is that if a low noise amplifier is laid out on a long lead pin of a QFP with a long bonding wire, the negative feedback due to parasitic inductance will increase and the high frequency gain and noise characteristics will deteriorate. Is.

　第二の課題は、ＩＣのピン間のトランス結合や、ＩＣを実装する多層基板上の配線交差によるトランス結合で同様にＩＣの高周波特性が劣化する、というものである。 The second problem is that the high frequency characteristics of the IC similarly deteriorate due to the transformer coupling between the pins of the IC and the transformer coupling due to the wiring crossing on the multilayer substrate on which the IC is mounted.

　第三の課題は、低雑音増幅器における寄生容量と寄生インダクタンスにより発振が発生する場合がある、というものである。 The third problem is that oscillation may occur due to parasitic capacitance and parasitic inductance in a low noise amplifier.

　本発明の目的は、デュアル送受信向けＩＣ回路に内蔵する低雑音増幅器の高周波特性を劣化させないピンレイアウトを提供することにある。 An object of the present invention is to provide a pin layout that does not deteriorate the high-frequency characteristics of a low-noise amplifier built in an IC circuit for dual transmission / reception.

　本発明は、第一に、低雑音増幅器のパッケージ外ピン先端からパッドまでの距離が最短となる位置に低雑音増幅器の回路を設けることで利得及び雑音特性が向上された。第二に、２つの低雑音増幅器の接地ピン，高周波信号ピン配置を隣り合わない様にして、ピン間でのトランス結合が低減された。第三に、受信ミキサと低雑音増幅器の多層実装基板で信号配線が交差しないピンレイアウトで配線間のトランス接合が低減された。第四に、低雑音増幅器の電源と接地ピンと、バイアス回路の電源、接地ピンを分けて、発振が低減された。 In the present invention, firstly, the gain and noise characteristics are improved by providing the low noise amplifier circuit at the position where the distance from the tip of the package outer pin of the low noise amplifier to the pad is the shortest. Second, transformer coupling between pins was reduced by not arranging the ground pin and high frequency signal pin arrangement of the two low noise amplifiers next to each other. Thirdly, the transformer junction between the wirings is reduced by the pin layout in which the signal wirings do not cross on the multilayer mounting board of the receiving mixer and the low noise amplifier. Fourthly, oscillation was reduced by dividing the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit.

　以下、本発明の実施例を図１に示す。図中の１００は、本発明を適用するデュアルバンド送受信ＩＣのＱＦＰである。１２３は図４の高周波数バンド低雑音増幅器４０２ａに相当するものであり、１２１は図４の低周波数バンド４０２ｂに相当するものである。１１８は、図４で示す高周波数バンド受信ミキサ４０３ａに相当し、１１９は、図４の低周波数バンド受信ミキサ４０３ｂに相当する。
図１において、低周波数バンド低雑音増幅器１２１と高周波数バンド低雑音増幅器１２３は、それぞれ低周波数バンド低雑音増幅器用バイアス回路１２５と、高周波数バンド低雑音増幅器用バイアス回路１２６から安定なバイアス電流が供給される。低周波数バンド低雑音増幅器用バイアス抵抗１２２及び高周波数バンド低雑音増幅器用バイアス抵抗１２４によって、それぞれバイアス回路からのバイアス電流がバイアス電圧に変換されて低雑損増幅器に供給される。１０３は低周波数バンド低雑音増幅器の出力ピン、１０４は低周波数バンド低雑音増幅器の接地ピン、１０５は低周波数バンド低雑音増幅器の入力ピン、１０６及び１０８は高周波数バンド低雑音増幅器の接地ピン、１０７は高周波数バンド低雑音増幅器の出力ピン、１０９は高周波数バンド低雑音増幅器の入力ピン、１２９は送信回路ブロックの電源ピン、１３０は送信回路ブロックの接地ピンである。１２９及び１３０はバイアス回路１２５と１２６の電源、接地でもある。１２７はデュアルバンド受信ミキサ部であり、高周波数バンド受信ミキサ１１８、低周波数バンドミキサ１１９、及び両受信ミキサに局部発振信号を供給する局部発振信号用増幅器１２０からなる。１０１、１０２は高周波数バンド受信ミキサ入力ピン、１１０、１１１は低周波数バンド受信ミキサ入力ピン、１１２はミキサ回路接地ピン、１１３はミキサ回路電源ピン、１１４、１１５はミキサ回路出力ピン、１１６及び１１７は局部発振信号入力ピンである。１４２は電源で、ピン１１３及びピン１２９を介し受信ミキサ、送信回路に電源電圧を供給すると共に，低雑音増幅器に出力整合回路１３１を介して電源電圧を供給する。 An embodiment of the present invention is shown in FIG. Reference numeral 100 in the figure denotes a QFP of a dual band transmission / reception IC to which the present invention is applied. 123 corresponds to the high frequency band low noise amplifier 402a of FIG. 4, and 121 corresponds to the low frequency band 402b of FIG. 118 corresponds to the high frequency band reception mixer 403a shown in FIG. 4, and 119 corresponds to the low frequency band reception mixer 403b of FIG.
In FIG. 1, a low frequency band low noise amplifier 121 and a high frequency band low noise amplifier 123 have stable bias currents from a low frequency band low noise amplifier bias circuit 125 and a high frequency band low noise amplifier bias circuit 126, respectively. Supplied. The bias current from the bias circuit is converted into a bias voltage by the low frequency band low noise amplifier bias resistor 122 and the high frequency band low noise amplifier bias resistor 124, respectively, and is supplied to the low noise amplifier. 103 is an output pin of the low frequency band low noise amplifier, 104 is a ground pin of the low frequency band low noise amplifier, 105 is an input pin of the low frequency band low noise amplifier, 106 and 108 are ground pins of the high frequency band low noise amplifier, 107 is an output pin of the high frequency band low noise amplifier, 109 is an input pin of the high frequency band low noise amplifier, 129 is a power supply pin of the transmission circuit block, and 130 is a ground pin of the transmission circuit block. Reference numerals 129 and 130 denote power sources and grounds for the bias circuits 125 and 126, respectively. Reference numeral 127 denotes a dual-band reception mixer unit, which includes a high-frequency band reception mixer 118, a low-frequency band mixer 119, and a local oscillation signal amplifier 120 that supplies local oscillation signals to both reception mixers. 101 and 102 are high frequency band reception mixer input pins, 110 and 111 are low frequency band reception mixer input pins, 112 is a mixer circuit ground pin, 113 is a mixer circuit power supply pin, 114 and 115 are mixer circuit output pins, 116 and 117 Is a local oscillation signal input pin. A power supply 142 supplies a power supply voltage to the reception mixer and the transmission circuit via the pin 113 and the pin 129, and supplies a power supply voltage to the low noise amplifier via the output matching circuit 131.

　以下、本発明のピンレイアウトの特徴について説明する。 Hereinafter, the features of the pin layout of the present invention will be described.

　第一に、低雑音増幅器のパッケージ外ピン先端からパッドまでの距離が最短となる位置に低雑音増幅器の回路を設ける。このようにすることでリードピンとボンディングワイヤの寄生インダクタンスによる負帰還の効果が低減し、利得、雑音特性が劣化を防止する。本実施例では、１０３から１０９ピンに配置することが、パッケージ外ピン先端から、低雑音増幅器の距離が最短となるケースである
。
なお、これらのピンの中で上記距離が最短のものはピン１０６であり、低雑音増幅器を形成するバイポーラトランジスタのエミッタが接続されている。 First, the circuit of the low noise amplifier is provided at a position where the distance from the tip of the outer pin of the low noise amplifier to the pad is the shortest. By doing so, the negative feedback effect due to the parasitic inductance of the lead pin and the bonding wire is reduced, and the gain and noise characteristics are prevented from deteriorating. In this embodiment, the arrangement from 103 to 109 pins is the case where the distance of the low noise amplifier from the front end of the package external pin is the shortest.
Of these pins, the pin having the shortest distance is a pin 106, to which the emitter of a bipolar transistor forming a low noise amplifier is connected.

　第二に、複数の低雑音増幅器の接地ピン同士は互いに隣り合わないようにした。本実施例では、高周波数バンド低雑音増幅器１２３の接地ピンは２本であり、そのため、寄生インダクタンスによる負帰還の効果が半減し、高利得が得られる。図５に接地したボンディングワイヤとリードピンとの等価回路を示す。５０２は集積回路基板である。５０３はその上に作られる集積回路であり、ここでは低雑音増幅器である。パッケージ支持部材５０１の上にあるリードピン５０６は、ボンディングワイヤ５０５で低雑音増幅器の接地のパッド５０４と接続される。このときの等価回路は、５０７で示される逆符号のトランス結合となり、一方のリードピンに流れる電流は他方のリードピンの電流を減少させる作用をする。このため、隣接したリードピンを２本用いた場合、寄生インダクタンスは半分にはならず、トランスの結合度の影響で、およそ単一リードと比較して７０％程度になる。従って、寄生インダクタンスの低減には、入力ピンと出力ピンは隣接しないことが重要となる。また、入出力高周波信号も隣り合わないように、接地ピンを間に挿入する。これにより、前述と同様のトランス結合を避けられる。すなわち、一方の高周波信号に流れる電流が隣の高周波信号の電流を減少させて、利得の劣化をもたらしてしまうという問題が防止される。本実施例では、１０６から１０９に示すピンレイアウトが相当する。１０３から１０５、のピンレイアウトも高周波信号線が隣り合わない例である。 Second, the ground pins of a plurality of low noise amplifiers were not adjacent to each other. In the present embodiment, the high frequency band low noise amplifier 123 has two ground pins. Therefore, the negative feedback effect due to the parasitic inductance is halved and a high gain is obtained. FIG. 5 shows an equivalent circuit of the grounded bonding wire and the lead pin. Reference numeral 502 denotes an integrated circuit substrate. Reference numeral 503 denotes an integrated circuit formed thereon, which is a low-noise amplifier here. The lead pin 506 on the package support member 501 is connected to the ground pad 504 of the low noise amplifier by a bonding wire 505. The equivalent circuit at this time is a transformer coupling of the opposite sign indicated by 507, and the current flowing through one lead pin acts to reduce the current of the other lead pin. For this reason, when two adjacent lead pins are used, the parasitic inductance is not halved, and is about 70% compared to a single lead due to the influence of the coupling degree of the transformer. Therefore, in order to reduce the parasitic inductance, it is important that the input pin and the output pin are not adjacent to each other. Also, a ground pin is inserted between the input and output high frequency signals so as not to be adjacent to each other. This avoids the same transformer coupling as described above. In other words, the problem that the current flowing in one high-frequency signal decreases the current of the adjacent high-frequency signal and causes deterioration of the gain is prevented. In the present embodiment, the pin layouts indicated by 106 to 109 are equivalent. The pin layouts 103 to 105 are also examples in which the high-frequency signal lines are not adjacent to each other.

　第三に、低周波数バンド受信ミキサ１１９の入力ピンと低周波数バンド低雑音増幅器１２１の入出力ピンとの間に高周波数バンド受信ミキサ１１８の入力ピンが配置され、高周波数バンド受信ミキサ１１８の入力ピンと高周波数バンド低雑音増幅器１２３の入出力ピンとの間に低周波数バンド低雑音増幅器１２１の入出力ピンが配置され、低周波数バンド受信ミキサ１１９の入力ピンと低周波数バンド低雑音増幅器１２１の入力ピン１０５との間に低周波数バンド低雑音増幅器１２１の出力ピン１０３が配置され、高周波数バンド受信ミキサの入力ピンと高周波数バンド低雑音増幅器１２３の入力ピン１０９との間に高周波数バンド低雑音増幅器１２３の出力ピン１０７が配置されている。 Third, the input pin of the high frequency band reception mixer 118 is arranged between the input pin of the low frequency band reception mixer 119 and the input / output pin of the low frequency band low noise amplifier 121, and the input pin of the high frequency band reception mixer 118 is high. The input / output pin of the low frequency band low noise amplifier 121 is arranged between the input / output pin of the frequency band low noise amplifier 123, and the input pin of the low frequency band reception mixer 119 and the input pin 105 of the low frequency band low noise amplifier 121 are arranged. The output pin 103 of the low frequency band low noise amplifier 121 is disposed between the input pin 109 of the high frequency band reception mixer and the input pin 109 of the high frequency band low noise amplifier 123. 107 is arranged.

　低雑音増幅器の出力ピンが入力ピンよりも受信ミキサに近い位置に置かれることにより、入力線と出力線が交差しない。なお、１３５及び１３６はそれぞれ低雑音増幅器１２１及び１２３へ入力する高周波信号の入力点で、アンテナへ接続されている。各々に付けられた帯域通過フィルタ１３３で、帯域外スプリアス信号を除去し、入力整合回路１３２で５０Ωインピーダンス整合をとり、各々の低雑音増幅器１２１、１２３へ高周波信号が入力する。出力は、入力整合回路１３１でインピーダンス整合をとる。次に、帯域外スプリアス信号を帯域通過フィルタ１３４で除去した後、ミキサ入力整合回路用容量１３８、１４１とミキサ入力整合回路用インダクタ１３７で差動信号を生成し、受信ミキサ１１８、１１９に入力する。このような配線実装によると、点線で囲まれた１３９や１４０で配線の交差が生じる。しかし、この交差は、異なるバンドの信号線同士によるものであり、一方のバンドが使用されているときは、他方は使用されていないため、相互干渉が生じない。 ∙ By placing the output pin of the low noise amplifier closer to the receiving mixer than the input pin, the input line and output line do not intersect. Reference numerals 135 and 136 are high-frequency signal input points that are input to the low-noise amplifiers 121 and 123, respectively, and are connected to the antenna. The band pass filter 133 attached to each removes the out-of-band spurious signal, the input matching circuit 132 performs 50Ω impedance matching, and the high frequency signal is input to the low noise amplifiers 121 and 123. The output is impedance matched by the input matching circuit 131. Next, after removing the out-of-band spurious signal by the band-pass filter 134, a differential signal is generated by the mixer input matching circuit capacitors 138 and 141 and the mixer input matching circuit inductor 137 and input to the reception mixers 118 and 119. . According to such wiring mounting, wiring intersections occur at 139 and 140 surrounded by dotted lines. However, this crossing is caused by signal lines of different bands. When one band is used, the other is not used, and thus no mutual interference occurs.

　第四に、低雑音増幅器の接地ピンと低雑音増幅器のバイアス回路の接地ピンがそれぞれ設けられる。なお、バイアス回路の電源ピン及び接地ピンは送信ブロックの電源，接地ピンと共有される。図２に、パッケージの寄生素子を含み、バイアス回路が低雑音増幅器と共通の接地ノードを持った場合の回路例を示す。図２の上段がその回路である。２０１が低雑音増幅器用トランジスタで、２０２がボンディングワイヤとパッケージのリード、２０３が低雑音増幅器のバイアス回路である。２０５はトランジスタ２０１のコレクタバイアス電位、２０６はバイアス回路の電源電位、２０７は接地である。図２の下段は上段の回路の等価回路である。２０８がバイアス回路の等価回路としての容量Ｃ２、２０９がトランジスタベース、エミッタ間容量Ｃ１、２１０がベース、エミッタ間電位、２１２がトランジスタの相互コンダクタンスｇｍ、２１１がボンディングワイヤとパッケージリードピンの等価回路としてのインダクタＬで表される。トランジスタの入力点２０４からみたインピーダンスＺｉｎは、次の式（１）で表される。
Zin=gmL/(C1(1−ω2Ｃ２Ｌ))＋j(ω2Ｌ−1)/(ωＣ1(1−ω2Ｃ２Ｌ))
　このとき、１＜ω2Ｃ２Ｌとなると、（１）式の実数部は負となって、インピーダンスが負性抵抗となり発振する場合がある。このため電源、接地を分け、発振の原因であるバイアス回路の寄生容量を取り除く。 Fourth, a ground pin for the low noise amplifier and a ground pin for the bias circuit of the low noise amplifier are provided. The power supply pin and the ground pin of the bias circuit are shared with the power supply and ground pin of the transmission block. FIG. 2 shows a circuit example in the case where the parasitic element of the package is included and the bias circuit has a common ground node with the low noise amplifier. The upper part of FIG. 2 is the circuit. 201 is a low-noise amplifier transistor, 202 is a bonding wire and package lead, and 203 is a low-noise amplifier bias circuit. 205 is a collector bias potential of the transistor 201, 206 is a power supply potential of the bias circuit, and 207 is ground. The lower part of FIG. 2 is an equivalent circuit of the upper part. 208 is a capacitance C2 as an equivalent circuit of a bias circuit, 209 is a transistor base, emitter capacitances C1 and 210 are bases, an emitter-to-emitter potential, 212 is a transistor mutual conductance gm, 211 is an equivalent circuit of a bonding wire and a package lead pin. It is represented by an inductor L. The impedance Zin viewed from the input point 204 of the transistor is expressed by the following equation (1).
Zin = gmL / (C1 (1−ω 2 C2L)) + j (ω 2 L−1) / (ωC1 (1−ω 2 C2L))
At this time, if 1 <ω 2 C2L, the real part of equation (1) may be negative, and the impedance may become a negative resistance and oscillate. For this reason, the power supply and the ground are separated, and the parasitic capacitance of the bias circuit that causes oscillation is removed.

　本実施例では、デュアルバンドのシステムについて述べているが、複数バンドを有する場合でも同様の考察により、実現されうる。 In this embodiment, a dual-band system is described. However, even in the case of having a plurality of bands, it can be realized by the same consideration.

　図３に本発明のピンレイアウトで構成した送受信ＩＣを示す。３００が本発明を適用した送受信ＩＣのチップである。３０３が送受信ＩＣを封印するＱＦＰであり、図１の１００に対応する。３０４はパッケージのチップ接着面３０５の支持材である。３０１が高周波数バンドと低周波数版との低雑音増幅器のレイアウトで、３０２が同様に２つのバンドの受信ミキサのレイアウトである。
３０８は低周波数バンド低雑音増幅器の出力ピン、３０９は低周波数バンド低雑音増幅器の接地ピン、３１０は低周波数バンド低雑音増幅器の入力ピン、３１１、３１３は高周波数バンド低雑音増幅器の接地ピン、３１２は高周波数バンド低雑音増幅器の出力ピン、３１４は高周波数バンド低雑音増幅器の入力ピン、３２３は送信回路ブロック電源ピン、３２４は送信回路ブロック接地ピンであり、図１のピン１０１〜１０９、及び１２９、１３０と対応している。また３１５、３１６は低周波数バンド受信ミキサ入力ピン、３１７はミキサ回路接地ピン、３１８はミキサ回路電源ピン、３１９、３２０はミキサ回路出力ピン、３２１、３２２は局部発振信号入力ピンであり、図１のピン１１０〜１１７に対応している。３２５はチップ上の各パッドから上記に示したリードピンにつけたボンディングワイヤである。 FIG. 3 shows a transmission / reception IC configured with the pin layout of the present invention. Reference numeral 300 denotes a chip of a transmission / reception IC to which the present invention is applied. Reference numeral 303 denotes a QFP for sealing the transmission / reception IC, which corresponds to 100 in FIG. Reference numeral 304 denotes a support material for the chip bonding surface 305 of the package. Reference numeral 301 denotes a layout of a low noise amplifier of a high frequency band and a low frequency version, and 302 denotes a layout of a reception mixer of two bands.
308 is an output pin of the low frequency band low noise amplifier, 309 is a ground pin of the low frequency band low noise amplifier, 310 is an input pin of the low frequency band low noise amplifier, 311 and 313 are ground pins of the high frequency band low noise amplifier, 312 is an output pin of the high frequency band low noise amplifier, 314 is an input pin of the high frequency band low noise amplifier, 323 is a transmission circuit block power supply pin, 324 is a transmission circuit block ground pin, and pins 101 to 109 in FIG. And 129, 130. Reference numerals 315 and 316 denote low frequency band reception mixer input pins, 317 denotes a mixer circuit ground pin, 318 denotes a mixer circuit power supply pin, 319 and 320 denote mixer circuit output pins, and 321 and 322 denote local oscillation signal input pins. Corresponding to the pins 110 to 117. Reference numeral 325 denotes a bonding wire attached to the above-described lead pin from each pad on the chip.

　図１で示したピン配置を実現するには、図３に示すように、以下の点が肝要である。低雑音増幅器のパッケージ外ピン先端からパッドまでの距離が最短となる位置に低雑音増幅器の回路を設ける。また受信ミキサは、３０１と３０２の関係のように低雑音増幅器に隣接して配置する。さらに、第一の受信ミキサの入力ピン、その隣に第二の受信ミキサの入力ピン、その隣に第一の受信ミキサに接続する低雑音増幅器の入出力ピン、その隣に第二の受信ミキサに接続する低雑音増幅器の入出力ピンが並ぶようにすることである。 In order to realize the pin arrangement shown in FIG. 1, the following points are important as shown in FIG. A circuit of the low noise amplifier is provided at a position where the distance from the tip of the external pin of the low noise amplifier to the pad is the shortest. The receiving mixer is arranged adjacent to the low noise amplifier as shown in the relationship between 301 and 302. Furthermore, the input pin of the first receiving mixer, the input pin of the second receiving mixer next to it, the input / output pin of the low noise amplifier connected to the first receiving mixer next to it, and the second receiving mixer next to it. The input / output pins of the low-noise amplifier connected to are arranged.

本発明の実施例。Examples of the present invention. パッケージの寄生素子を含み、バイアス回路が低雑音増幅器の接地ノードを持った場合の回路例。Circuit example when the parasitic circuit of the package is included and the bias circuit has the ground node of the low-noise amplifier. レイアウト構成例。Layout configuration example. 従来の移動体通信向け、デュアルバンド対応送受信用半導体集積回路。A conventional dual band compatible semiconductor integrated circuit for mobile communications. 隣接したボンディングワイヤ、リードピンと等価回路。Adjacent bonding wire, lead pin and equivalent circuit.

符号の説明Explanation of symbols

１００…デュアルバンド送受信ＩＣのパッケージ
１０１、１０２…高周波数バンド受信ミキサ入力ピン
１０３…低周波数バンド低雑音増幅器、出力ピン
１０４…低周波数バンド低雑音増幅器、接地ピン
１０５…低周波数バンド低雑音増幅器、入力ピン
１０６…高周波数バンド低雑音増幅器、接地ピン
１０７…高周波数バンド低雑音増幅器、出力ピン
１０８…高周波数バンド低雑音増幅器、接地ピン
１０９…高周波数バンド低雑音増幅器、入力ピン
１１０、１１１…低周波数バンド受信ミキサ入力ピン
１１２…ミキサ回路接地ピン
１１３…ミキサ回路電源ピン
１１４、１１５…ミキサ回路出力ピン
１１６、１１７…局部発振信号入力ピン
１１８…高周波数バンド受信ミキサ
１１９…低周波数バンド受信ミキサ
１２０…局部発振信号用増幅器
１２１…低周波数バンド低雑音増幅器用トランジスタ
１２２…低周波数バンド低雑音増幅器用バイアス抵抗
１２３…高周波数バンド低雑音増幅器用トランジスタ
１２４…高周波数バンド低雑音増幅器用バイアス抵抗
１２５…低周波数バンド低雑音増幅器用バイアス回路
１２６…高周波数バンド低雑音増幅器用バイアス回路
１２７…デュアルバンド受信ミキサ回路部
１２８…送信回路ブロック
１２９…送信回路ブロック電源ピン
１３０…送信回路ブロック接地ピン
１３１…低雑音増幅器用出力整合回路
１３２…低雑音増幅器用入力整合回路
１３３…帯域通過フィルタ
１３４…帯域通過フィルタ
１３５…低周波数バンド入力端子
１３６…高周波数バンド入力端子
１３７…ミキサ入力整合回路用インダクタ
１３８、１４１…ミキサ入力整合回路用容量
１３９、１４０…信号線交叉点
２０１…低雑音増幅器用トランジスタ
２０２…寄生素子としてのボンディングワイヤとパッケージのリードピン
２０３…バイアス回路
２０４…低雑音増幅器入力点
２０５…コレクタバイアス電位
２０６…電源電位
２０７…接地
２０８…バイアス回路の等価回路としての容量、Ｃ２
２０９…トランジスタベース、エミッタ間容量、Ｃ１
２１０…ベース、エミッタ電位
２１１…ボンディングワイヤとパッケージリードの等価回路としてのインダクタ、Ｌ
２１２…相互コンダクタンス、ｇｍ
３００…送受信ＩＣチップ
３０１…高周波数バンド及び低周波数バンド低雑音増幅器のレイアウト
３０２…高周波数バンド及び低周波数バンド受信ミキサ回路のレイアウト
３０３…送受信ＩＣのＱＦＰ
３０４…チップ接着面の支持材
３０５…チップ接着面
３０６、３０７…高周波数バンド受信ミキサ入力ピン
３０８…低周波数バンド低雑音増幅器、出力ピン
３０９…低周波数バンド低雑音増幅器、接地ピン
３１０…低周波数バンド低雑音増幅器、入力ピン
３１１…高周波数バンド低雑音増幅器、接地ピン
３１２…高周波数バンド低雑音増幅器、出力ピン
３１３…高周波数バンド低雑音増幅器、接地ピン
３１４…高周波数バンド低雑音増幅器、入力ピン
３１５、３１６…低周波数バンド受信ミキサ入力ピン
３１７…ミキサ回路接地ピン
３１８…ミキサ回路電源ピン
３１９、３２０…ミキサ回路出力ピン
３２１、３２２…局部発振信号入力ピン
３２３…送信回路ブロック電源ピン
３２４…送信回路ブロック接地ピン
３２５…ボンディングワイヤ
４０１…高周波部と中間周波数帯を含むＩＣ回路
４０２ａ…高周波数バンド低雑音増幅器
４０２ｂ…低周波数バンド低雑音増幅器
４０３ａ…高周波数バンド受信ミキサ
４０３ｂ…低周波数バンド受信ミキサ
４０４…ミキサ，４０５…可変利得増幅器
４０６…復調器、４０７…デバイダ
４０８…変調器、４０９…オフセットＰＬＬ、
４１０…シンセサイザ、４１１…帯域通過フィルタ
５０１…パッケージ支持部材
５０２…集積回路基板、５０３…集積回路
５０４…接地用パッド、５０５…ボンディングワイヤ
５０６…リードピン
５０７…寄生トランス。
DESCRIPTION OF SYMBOLS 100 ... Dual band transmission / reception IC package 101, 102 ... High frequency band receiving mixer input pin 103 ... Low frequency band low noise amplifier, Output pin 104 ... Low frequency band low noise amplifier, Ground pin 105 ... Low frequency band low noise amplifier, Input pin 106 ... high frequency band low noise amplifier, ground pin 107 ... high frequency band low noise amplifier, output pin 108 ... high frequency band low noise amplifier, ground pin 109 ... high frequency band low noise amplifier, input pins 110, 111 ... Low frequency band reception mixer input pin 112 ... Mixer circuit ground pin 113 ... Mixer circuit power supply pins 114 and 115 ... Mixer circuit output pins 116 and 117 ... Local oscillation signal input pins 118 ... High frequency band reception mixer 119 ... Low frequency band reception mixer 120... Local oscillation signal amplifier 12 ... Low frequency band low noise amplifier transistor 122 ... Low frequency band low noise amplifier bias resistor 123 ... High frequency band low noise amplifier transistor 124 ... High frequency band low noise amplifier bias resistor 125 ... Low frequency band low noise amplifier Bias circuit 126... High frequency band low noise amplifier bias circuit 127... Dual band reception mixer circuit 128... Transmission circuit block 129... Transmission circuit block power supply pin 130. ... Low noise amplifier input matching circuit 133 ... Band pass filter 134 ... Band pass filter 135 ... Low frequency band input terminal 136 ... High frequency band input terminal 137 ... Inductors 138 and 141 for mixer input matching circuits ... Capacitors for mixer input matching circuits 1 9, 140: Signal line crossing point 201: Low noise amplifier transistor 202 ... Parasitic bonding wire and package lead pin 203 ... Bias circuit 204 ... Low noise amplifier input point 205 ... Collector bias potential 206 ... Power supply potential 207 ... Ground 208: capacitance as an equivalent circuit of the bias circuit, C2
209 ... transistor base, capacitance between emitters, C1
210... Base, emitter potential 211... Inductor as an equivalent circuit of bonding wire and package lead, L
212 ... Mutual conductance, gm
300 ... Transmission / reception IC chip 301 ... High frequency band and low frequency band low noise amplifier layout 302 ... High frequency band and low frequency band reception mixer circuit layout 303 ... Transmission / reception IC QFP
304 ... Chip bonding surface support material 305 ... Chip bonding surface 306, 307 ... High frequency band receiving mixer input pin 308 ... Low frequency band low noise amplifier, output pin 309 ... Low frequency band low noise amplifier, ground pin 310 ... Low frequency Band low noise amplifier, input pin 311 ... high frequency band low noise amplifier, ground pin 312 ... high frequency band low noise amplifier, output pin 313 ... high frequency band low noise amplifier, ground pin 314 ... high frequency band low noise amplifier, input Pins 315, 316 ... Low frequency band reception mixer input pin 317 ... Mixer circuit ground pin 318 ... Mixer circuit power supply pins 319, 320 ... Mixer circuit output pins 321, 322 ... Local oscillation signal input pins 323 ... Transmission circuit block power supply pins 324 ... Transmission circuit block ground pin 325... Bonding wire 4 DESCRIPTION OF SYMBOLS 1 ... IC circuit 402a including a high frequency part and an intermediate frequency band ... High frequency band low noise amplifier 402b ... Low frequency band low noise amplifier 403a ... High frequency band receiving mixer 403b ... Low frequency band receiving mixer 404 ... Mixer, 405 ... Variable gain Amplifier 406 ... Demodulator, 407 ... Divider 408 ... Modulator, 409 ... Offset PLL,
410: synthesizer, 411: band-pass filter 501, package support member 502 ... integrated circuit board, 503 ... integrated circuit 504 ... grounding pad, 505 ... bonding wire 506 ... lead pin 507 ... parasitic transformer.

Claims (10)

　受信信号が入力される第1周波数バンド増幅器と、該第1周波数バンド増幅器の出力が入力される第1周波数バンド受信ミキサとを１チップ上に有し、パッケー
ジ外に突出するピン先端から上記第1周波数バンド増幅器に接続されるパッドまでの距離が他のリードピンの先端とそれに対応するパッドまでの距離に比べて最短となる位置に上記第1周波数バンド増幅器が配置されたことを特徴とする半導体集積回路。 The first frequency band amplifier to which the reception signal is input and the first frequency band reception mixer to which the output of the first frequency band amplifier is input are provided on one chip, and the first frequency band amplifier from the tip of the pin protruding out of the package. A semiconductor characterized in that the first frequency band amplifier is arranged at a position where the distance to the pad connected to one frequency band amplifier is the shortest compared to the distance between the tip of another lead pin and the corresponding pad. Integrated circuit. 　請求項１において、上記第1周波数バンド増幅器はバイポーラトランジスタを
有し、該バイポーラトランジスタのエミッタが接続されるパッドと該パッドに対応するピンの先端までの距離が最短であることを特徴とする半導体集積回路。 2. The semiconductor according to claim 1, wherein the first frequency band amplifier has a bipolar transistor, and a distance between a pad to which the emitter of the bipolar transistor is connected and a tip of a pin corresponding to the pad is shortest. Integrated circuit. 　受信信号が入力される第1周波数バンド増幅器及び第2周波数バンド増幅器と、該第1周波数バンド増幅器及び第2周波数バンド増幅器の出力がそれぞれ入力される第1周波数バンド受信ミキサ及び第2周波数バンド受信ミキサとを１チップ上に有し、上記第1周波数バンド受信ミキサの入力ピンと上記第1周波数バンド増幅器の入出力ピンとの間に上記第2周波数バンド受信ミキサの入力ピンが配置され、
上記第２周波数バンド受信ミキサの入力ピンと上記第２周波数バンド増幅器の入出力ピンとの間に上記第1周波数バンド増幅器の入出力ピンが配置され、上記第1周波数バンド受信ミキサの入力ピンと上記第1周波数バンド増幅器の入力ピンとの間に上記第1周波数バンド増幅器の出力ピンが配置され、上記第２周波数バン
ド受信ミキサの入力ピンと上記第２周波数バンド増幅器の入力ピンとの間に上記第２周波数バンド増幅器の出力ピンが配置されたことを特徴とする半導体集積回路。 A first frequency band amplifier and a second frequency band amplifier to which a reception signal is input, and a first frequency band reception mixer and a second frequency band reception to which outputs of the first frequency band amplifier and the second frequency band amplifier are respectively input. A mixer on one chip, and the input pin of the second frequency band receiving mixer is arranged between the input pin of the first frequency band receiving mixer and the input / output pin of the first frequency band amplifier,
An input / output pin of the first frequency band amplifier is disposed between an input pin of the second frequency band receiving mixer and an input / output pin of the second frequency band amplifier, and the input pin of the first frequency band receiving mixer and the first pin An output pin of the first frequency band amplifier is disposed between the input pin of the frequency band amplifier, and the second frequency band amplifier is disposed between the input pin of the second frequency band receiving mixer and the input pin of the second frequency band amplifier. A semiconductor integrated circuit characterized in that an output pin is arranged. 　請求項３において、上記第1周波数バンド増幅器の入出力ピン及び上記第２周
波数バンド増幅器の入出力ピンは、パッケージを形成する四辺の一辺上に設けられたことを特徴とする半導体集積回路。 4. The semiconductor integrated circuit according to claim 3, wherein the input / output pins of the first frequency band amplifier and the input / output pins of the second frequency band amplifier are provided on one side of four sides forming a package. 　受信信号が入力される第1周波数バンド増幅器及び第2周波数バンド増幅器と、該第1周波数バンド増幅器及び第2周波数バンド増幅器の出力がそれぞれ入力される第1周波数バンド受信ミキサ及び第2周波数バンド受信ミキサとを１チップ上に有し、パッケージ外に突出するピン先端から上記第1周波数バンド増幅器又は上
記第2周波数バンド増幅器に接続されるパッドまでの距離が他のリードピンの先端とそれに対応するパッドまでの距離に比べて最短となる位置に上記第1周波数バンド増幅器又は上記第2周波数バンド増幅器の回路が設けられたことを特徴とする半導体集積回路。 A first frequency band amplifier and a second frequency band amplifier to which a reception signal is input, and a first frequency band reception mixer and a second frequency band reception to which outputs of the first frequency band amplifier and the second frequency band amplifier are respectively input. The distance from the tip of the pin protruding out of the package to the pad connected to the first frequency band amplifier or the second frequency band amplifier is the other lead pin tip and the corresponding pad. A circuit of the first frequency band amplifier or the second frequency band amplifier is provided at a position that is the shortest compared to the distance to the semiconductor integrated circuit. 　請求項５において、上記第1周波数バンド増幅器及び上記第２周波数バンド増
幅器はそれぞれバイポーラトランジスタを有し、いずれかのバイポーラトランジスタのエミッタが接続されるパッドと該パッドに対応するピンの先端までの距離が最短であることを特徴とする半導体集積回路。 6. The first frequency band amplifier and the second frequency band amplifier according to claim 5, each having a bipolar transistor, and a distance between a pad to which the emitter of any bipolar transistor is connected and a tip of a pin corresponding to the pad. A semiconductor integrated circuit characterized by the shortest. 　増幅器と、該増幅器に接続されるバイアス回路とを有し、上記増幅器の接地ピンと上記バイアス回路の接地ピンとが各々設けられたことを特徴とする送受信用半導体集積回路。 A transmission / reception semiconductor integrated circuit comprising an amplifier and a bias circuit connected to the amplifier, wherein a ground pin of the amplifier and a ground pin of the bias circuit are provided. 　複数の増幅器を有し、該複数の増幅器の接地ピンが互いに隣り合わない配置とされたことを特徴とする送受信用半導体集積回路。 A semiconductor integrated circuit for transmission / reception, comprising a plurality of amplifiers, wherein the ground pins of the plurality of amplifiers are arranged not adjacent to each other. 　入力ピンと出力ピンと接地ピンが接続された増幅器を有し、上記入力ピンと上記出力ピンとの間に上記接地ピンが配置されたことを特徴とする半導体集積回路
。 A semiconductor integrated circuit, comprising an amplifier having an input pin, an output pin, and a ground pin connected, wherein the ground pin is disposed between the input pin and the output pin. 　請求項７乃至９の何れかにおいて、上記増幅器はバイポーラトランジスタを有し、そのエミッタが接地ピンに接続され、そのベースが入力ピンに接続され、そのコレクタが出力ピンに接続されたことを特徴とする半導体集積回路。
10. The amplifier according to claim 7, wherein the amplifier has a bipolar transistor, an emitter thereof is connected to a ground pin, a base thereof is connected to an input pin, and a collector thereof is connected to an output pin. A semiconductor integrated circuit.
JP2003323904A 2003-09-17 2003-09-17 Semiconductor integrated circuit Pending JP2004088791A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007208373A (en) * 2006-01-31 2007-08-16 Sharp Corp Semiconductor integrated circuit device and tuner device using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007208373A (en) * 2006-01-31 2007-08-16 Sharp Corp Semiconductor integrated circuit device and tuner device using the same

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