JP2003224550A - Timing signal generation circuit, signal transmission system, and timing signal generation method - Google Patents

Abstract

(57) [Problem] In a conventional signal transmission system, when a clock frequency becomes high, a phase difference between circuits may cause a problem, and data may not be transmitted accurately. SOLUTION: A candidate timing signal generation circuit 553 for generating a plurality of candidate timing signals having different phases, and a reception for selecting and holding a reception timing signal used for receiving data from the plurality of candidate timing signals according to a predetermined condition. And a timing signal control circuit 552 for use.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing signal generation circuit, a signal transmission system, and a timing signal generation method, and more particularly to an LSI (Large Scale Integration).
Circuit) or between devices or the like, and relates to a timing signal generation circuit in a signal transmission system that transmits and receives signals at high speed.

In recent years, with the high speed operation of LSIs,
Large-capacity signal transmission is performed between devices or devices configured with a plurality of LSIs. However, in such a large-capacity signal transmission system, signal skew (Skew) and jitter become a problem as the transmission speed increases, and accurate data reception (capturing) is required to obtain accurate data. Signal transmission becomes difficult. Therefore, it is desired to provide a timing signal generation circuit that can generate a timing signal for surely receiving data.

[0003]

2. Description of the Related Art In recent years, DRAM (Dynamic Random Acces
memory (SDRAM), SDRAM (Synchronous DRAM), etc., and MPU (Micro Processing Unit),
Alternatively, the components of a computer and other information processing equipment have their performance greatly improved, and each L
It has become necessary to perform high-speed signal transmission / reception (transmission) between SIs (LSI chips) or between circuit boards or devices composed of a plurality of LSIs.

FIG. 1 is a block diagram schematically showing an example of a conventional signal transmission system. In FIG. 1, reference numeral 101 is a transmitting side driving circuit (transmitting side buffer) for the clock CLK, 102 is wiring for the clock (clock signal line), 103 is a receiving side driving circuit for the clock (receiving side buffer), 110 11n are transmission side data fetch circuits (transmission side latches) for the data D0 to Dn, 120 to 12
n is a transmission side drive circuit (transmission side buffer) for the data D0 to Dn, 130 to 13n are data lines (data signal lines), 140 to 14n are reception side drive circuits (reception side buffers) for data, and , 150 to 15n are reception side data fetch circuits (reception side latches).

As shown in FIG. 1, conventionally, a signal transmission system having a large amount of data transmits a signal using a plurality of signal lines 102 and 130 to 13n, for example. That is, the data (signals) D1 to Dn are transmitted to the transmission side latches 110 to 11n and the transmission side buffer 120, respectively.
.About.12n and data signal lines 130 to 13n, are transmitted to the reception side buffers 140 to 14n, and then supplied to the reception side latches 150 to 15n. Clock CLK
Is supplied to, for example, the clock terminals (capture timing control terminals) of the respective transmission side latches 110 to 11n, and the transmission side buffer 101 and the clock signal line 102.
Is transmitted to the receiving side buffer 103 and is supplied to the clock terminals of the receiving side latches 150 to 15n.

As described above, in the conventional signal transmission system using a plurality of signal lines, the same clock CLK is supplied to the transmission side latches 110 to 11n and the reception side latches 150 to 15n to control the fetch timing. is doing.

[0007]

FIG. 2 is a timing chart for explaining an example of the operation in the signal transmission system of FIG.

As shown in FIG. 2, for example, even if the data D0 to Dn are output at the same timing on the transmitting side, the signal lines 130 to 13 on the receiving side.
The amount of delay of the data transmitted via n is slightly different.
That is, in the above-described conventional signal transmission system shown in FIG. 1, the clock CLK and the plurality of data D0 to D0.
Dn is a clock signal line and a plurality of signal lines 13 respectively
0 to 13n and the buffers 101 and 120 to 12
n; 103, 140 to 14n, etc. are used, the amount of delay in the signal transmitted via each signal line is different, and each signal line (data signal line 130 to 13n) is transmitted via that signal line. The optimum timing for capturing the signal (data) to be read will differ. Specifically, as shown in FIG. 2, for example, the data D0 and D1 can be taken in by the receiving side latches 150 and 151, but the difference in delay amount (skew: Skew: Skew: Skew: ), For example, when the data fetch timing for fetching the data Dn comes within the transition period (boundary) of the data, it becomes difficult to accurately fetch the data Dn by the receiving side latch 15n.

The skew is, for example, the clock CLK.
Becomes higher and the problem becomes larger as the high speed operation (high speed transmission) progresses, and it is common to the transmission side latches 110 to 11n and the reception side latches 150 to 15n provided in the respective signal lines 130 to 13n. If the strobe signal (clock CLK) is supplied to take in the signal (data), the skew for each signal line cannot be dealt with.

That is, the receiving side latch 150 of each signal line
15n, if the difference between the optimum signal acquisition timings becomes extremely large, all signals are correctly acquired (received) at the common timing (clock CLK).
As a result, the transmission distance and transmission speed at which signals can be accurately transmitted are limited. Or, in order to increase the signal transmission distance and increase the transmission speed (increasing the bit rate), it is necessary to use an expensive cable with a specially adjusted skew, which not only increases the cost but also increases the cost. The improvement of the transmission distance and the transmission speed cannot be expected to be great, and it cannot be said to be a fundamental solution.

FIG. 3 is a block diagram schematically showing another example of the conventional signal transmission system.

The signal transmission system shown in FIG.
First circuit (block A) 410 using clock CLOCK-A, second circuit using clock CLOCK-B
Circuit (block B) 450 and a signal transmission line (bus) 430 having an n-bit width for transmitting signals (data) between the first circuit 410 and the second circuit 450. Here, for example, the first circuit 410 is an ASIC.
(Application Specific IC) core circuit,
The second circuit 450 is a high speed I / O circuit. In addition, the clock CLOCK-A and the clock CLOCK
-B is a clock with the same frequency but different phase.

That is, FIG. 3 shows synchronization circuits (circuit 41
0, 450) is another example of the signal transmission system including the clock transfer circuit, in which n-bit data is transmitted from the first circuit 410 by the clock CLOCK-A, and is transmitted via the signal transmission path 430. In the second circuit 450, the received n-bit data is clocked by the clock CLOC.
It is adapted to receive by using KB.

In the conventional signal transmission system shown in FIG. 3, the clock CLOCK-A and the clock CL are assumed.
Even if the frequencies of OCK-B are equal, a non-zero phase difference is included between them. This phase difference is not a problem if it is sufficiently small with respect to the period of the synchronous circuit,
Further, this phase difference basically does not depend on the period or frequency.

Therefore, in the conventional signal transmission system shown in FIG. 3, the ratio of the phase difference to the cycle increases as the cycle becomes shorter (the frequency becomes higher), and eventually it becomes impossible to ignore it and data cannot be accurately received. There is a fear.

In view of the problems of the above-described conventional signal transmission system, the present invention generates a clock that can reliably receive data in consideration of the phase difference and enables high-speed and error-free signal transmission. It is intended to provide a signal transmission system.

[0017]

According to a first aspect of the present invention, there is provided a timing signal generation circuit including a candidate timing signal generation circuit and a reception timing signal control circuit. The candidate timing signal generation circuit generates a plurality of candidate timing signals having different phases, and the reception timing signal control circuit determines a reception timing signal used for receiving data from the plurality of candidate timing signals according to a predetermined condition. Select and retain.

According to the second aspect of the present invention, a signal transmission system having a transmission circuit for transmitting data, a signal transmission line, and a reception circuit for receiving data supplied from the transmission circuit via the signal transmission line. Will be provided. The receiving circuit
A candidate timing signal generation circuit that generates a plurality of candidate timing signals having different phases, and a reception timing signal control circuit that selects and holds a reception timing signal used for receiving data from the plurality of candidate timing signals according to a predetermined condition. Equipped with.

According to the third aspect of the present invention, a plurality of candidate timing signals having different phases are prepared, and a reception timing signal used for receiving data is selected and held from the plurality of candidate timing signals according to a predetermined condition. A timing signal generating method is provided.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a timing signal generating circuit, a signal transmission system, and a timing signal generating method according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 4 is a diagram for explaining an example of the timing signal generating method according to the present invention, and FIG. 5 is a timing diagram for explaining the timing signal generating method shown in FIG. 4 and 5, reference numeral CLOCK
-A indicates a clock used in the first circuit (for example, a core circuit in an ASIC), and CLOCK-
B0 to CLOCK-B7 are second circuits (for example, ASI
High-speed I / O circuit in C: Shows a clock used in data acquisition and determination of a clock to be selected (fixed). Here, the clock CLOCK-B0-C
LOCK-B7 is an eight-phase clock whose phases are different from each other by 45 °.

As shown in FIG. 5, an example of the timing signal generating method according to the present invention is as follows.
, The clock CLOCK-B is selected from the plurality of candidates.
5 (arbitrary candidate clock) is selected and step ST12
To CLOCK-A with clock CLOCK-A
K-B0 and CLOCK-B1 are hit, that is, the levels of the clocks CLOCK-B0 and CLOCK-B1 are fetched at the rising timing of the clock CLOCK-A. Further, in step ST13, it is determined whether the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are both low level "L".

At step ST13, the clock CL
When it is determined that the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of OCK-A are both low level "L", the process proceeds to step ST14, and like step ST12,
The levels of the clocks CLOCK-B0 and CLOCK-B1 are fetched again at the rising timing of the clock CLOCK-A, and the process proceeds to step ST15. In step ST15, similarly to step ST13,
Clocks CLOCK-B0 and CLOCK-B captured at the rising timing of the clock CLOCK-A
It is determined whether both the 1 levels are low level "L".

Also in step ST15, the clocks CLOCK-B0 and CLOCK-B1 fetched at the rising timing of the clock CLOCK-A.
If it is determined that both of the levels are low level "L", the candidate clock CLOCK-B5 is fixed as the optimum clock. That is, in the second circuit, the clock CLOCK-B5 is generated and used as a data fetch clock.

On the other hand, in steps ST13 and ST15, the clocks CLOCK-B0 and CLO fetched at the rising timing of the clock CLOCK-A.
When it is determined that the levels of both CK-B1 are not the low level "L", the candidate clock CLOCK-B5 is discarded and another clock (for example, the clock CLOCK-B) is discarded.
6) is selected as a candidate clock (step ST11)
Then, the same processing is repeated.

In the above, in the timing signal generating method shown in FIGS. 4 and 5, for example, two determination clocks (determination timing signals) CLOCK-B are provided for a candidate clock (reception timing signal) CLOCK-B5.
0 and CLOCK-B1 are defined, these determination clocks CLOCK-B0 and CLOCK-B1 are determined twice in steps ST13 and ST15, and the clock CL is determined.
Whether or not to fix the clock is determined by OCK-B5. Similarly, two determination clocks CLOCK-B1 and CLOC are set for the candidate clock CLOCK-B6.
K-B2 is defined, and these determination clocks CLOCK-
B1 and CLOCK-B2 are determined twice in steps ST13 and ST15, and it is determined whether or not to fix the clock CLOCK-B6.

The combination of the candidate clock and the determination clock can be changed according to the frequency of the clock used and the like. That is, when the clock frequency is relatively low (for example, about a hundred and several tens of MHz or less), the data acquisition timing (rising timing) of the candidate clock with respect to the determination clock is approximately the center (data) shown in FIG. F-c) and when the clock frequency is high (for example, several hundred MHz: 625 MH)
As shown in FIG. 4, data (DAT or more)
Timing later than the center of A) (for example, F-b5)
Is preferred. This is because when the frequency of the clock for transmitting data increases, the margin of setup time must be taken into consideration rather than the hold time of data.

Further, a determination clock (determination timing signal: CLOCK-B0, CLO) for one candidate clock (reception timing signal: CLOCK-B5).
The number of CK-B1) is not limited to two, and the number of determination processes by the determination clock (step S
(T13, ST15) is not limited to twice.

FIG. 6 is a diagram for explaining another example of the timing signal generating method according to the present invention, and FIG. 7 is a timing diagram for explaining the timing signal generating method shown in FIG. Here, the timing signal generating method shown in FIGS. 6 and 7 is a continuation of the timing signal generating method (clock selection and fixing) described with reference to FIGS. 4 and 5 described above. , And the selection of a new clock.

As shown in FIG. 6, in this timing signal generating method, the judgment clocks (CLOCK-B0, C
LOCK-B1) determines the candidate clock (CL
The range in which OCK-B5) is fixed is made narrower than the range in which the fixed clock in the determination processing using the determination clock is not released (the range to be maintained).

As shown in FIG. 7, in another example of the timing signal generating method according to the present invention, first, in step ST2.
1, the clock CLOCK- is selected from the plurality of candidates.
From the state of being fixed at B5, the process proceeds to step ST22, where clock CLOCK-A is used for clock CLOCK-B.
0 and CLOCK-B1, that is, clock CL at the rising timing of clock CLOCK-A.
Take in the levels of OCK-B0 and CLOCK-B1. Further, in step ST23, the clock CL
It is determined whether the levels of the clocks CLOCK-B0 and CLOCK-B1 fetched at the rising timing of OCK-A are the high level “H” and the low level “L” in order.

At step ST23, the clock CL
When it is determined that the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of OCK-A are the high level “H” and the low level “L” in order, the process proceeds to step ST24 and the above step S24.
Similarly to T22, the clocks CLOCK-B0 and CLOCK-B0 and C are again generated at the rising timing of the clock CLOCK-A.
The level of LOCK-B1 is taken in, and step ST25
Proceed to. Here, as shown in FIG.
The phase of OCK-B0 (rising timing) is the phase of the clock CLOCK-B1 (rising timing).
It is a timing advanced by 45 °.

At step ST25, the clock CLOC
Clock C captured at the rising timing of KA
It is determined whether the levels of LOCK-B0 and CLOCK-B1 are both high level "H". Step ST
25, it is determined that the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are both high level “H”, that is, the fixed clock CLOCK-B5 When the phase shifts in the direction in which the phase largely advances (when the phase P2 deviates from the range P2 shown in FIG. 6), the clock CLOCK-B7 having a phase delayed from the clock CLOCK-B5 is selected as the next candidate. When it is determined in step ST25 that the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are not both the high level "H", the process returns to step ST22.

On the other hand, if it is determined in step ST23 that the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are not the high level "H" and the low level "L" in order, In step ST27, the clock CLOCK- is restarted as in step ST22.
Clock CLOCK-B0 at the rising timing of A
Then, the levels of CLOCK-B1 are fetched, and the process proceeds to step ST28. In step ST28, when it is determined that both the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are the high level “H”, that is, the fixed clock CLOCK-B5. Phase shifts in the direction of being significantly delayed (range P shown in FIG. 6).
2) the clock CL as the next candidate.
A clock CLOCK- whose phase leads that of OCK-B5
Select B3. In step ST28, the clocks CLOCK-B0 and CLOCK-B1 fetched at the rising timing of the clock CLOCK-A.
If it is determined that both levels are not high level "H", the process returns to step ST22.

As described above, the range for releasing the fixed clock in the determination processing using the determination clock (comparison condition for releasing) is gentler than the comparison condition for holding (maintaining) the fixed clock. As a result, the clock is prevented from being canceled by the jitter of the clock itself, and the clock selection (fixing or canceling) operation is stabilized.

In the above, the clock used for fetching and selecting (fixing) data in the second circuit is not limited to the eight-phase clock, and the determination clock and the candidate used for determination are It goes without saying that the combination with the clock can be variously changed.

FIG. 8 is a block diagram schematically showing a first embodiment of the timing signal generation circuit (signal transmission system) according to the present invention, showing a plurality of transmission circuits. In FIG. 8, reference numerals 160 to 16n are D-type flip-flops, 170 to 17n are transmission circuits, 181 is a clock transfer circuit, and 182 is a PLL (Phase Locked Loop).
A circuit, 183 is a clock generation circuit, and 184 is a demultiplexer (DEMUX).

Here, each of the flip-flops 160 to 16
n corresponds to the flip-flop 100 for clock rearrangement, and each of the transmission circuits 170 to 17n corresponds to, for example, the transmission data processing unit 10 in FIG. In addition, for example, as described with reference to FIG.
0 to 17n have a 16: 1 demultiplexer function of converting 16-bit parallel data having a data rate of 156 bps into serial data having a data rate of 2.5 Gbps.

As shown in FIG. 8, in the timing signal generating circuit of the first embodiment, each transmission data processing unit 1
16-bit parallel data DATA0 [1 supplied to 70 to 17n (flip-flops 160 to 16n)
All of 5: 0] to DATAn [15: 0] are input in synchronization with one data input clock PCLK (common clock). By the way, since the data input clock PCLK synchronized with the parallel data is normally transmitted through the logic circuit, the phase variation (jitter) is large due to the characteristics of the clock propagation logic circuit and the influence of noise. Become. Therefore, in the timing signal generation circuit of the first embodiment, the signal transmission clock CLK (for example, the frequency is 2.5 GHz) that is transmitted at high speed is separated from the data input clock PCLK by the reference clock REFCLK in which jitter is suppressed. Generate from.

That is, the signal transmission clock CLK used for signal transmission is generated by the PLL circuit 182 by multiplying the frequency of the reference clock REFCLK. At this time, although the frequencies of the data input clock PCLK and the reference clock REFCLK have a dependency relationship, these data input clock PCLK and the reference clock RE
It is out of phase with FCLK. Therefore, the clock transfer circuit 181 uses the data input clock PCLK to generate the signal line transmission circuit driving clocks pll-clk0 to pll-cl generated by the PLL circuit 182.
The transfer to the k3 (signal transmission clock CLK) is performed. In the fourth embodiment, the PLL circuit 182
Is, for example, 90 degrees out of phase with each other and has a frequency of 625
MHz four-phase clock (pll-clk0-pll-c
lk3) and outputs its four-phase clock pll-clk0
From the pll-clk3 to the demultiplexer 184, the signal transmission clock CLK having a frequency of 1.25 GHz is generated, for example.

FIG. 9 is a diagram for explaining the operation of the timing signal generating circuit of FIG.

As shown in FIG. 9, the clock transfer circuit 181 uses four-phase clocks pll-clk0 to pll-clk3 output from the PLL circuit 182 and having a phase difference of 90 ° and a frequency of 625 MHz. , A clock clka having a frequency of 156 MHz, and a clock clka having a phase advanced by 90 ° from the clock clka.
-90, and the phase is 135 than the clock clka.
The advanced clock clka-135 is generated. Then, the rising edges of the data input clock PCLK are clock clka-90 and clock clka-.
When both 135 are in the low level “L” position, DATA input in synchronization with the data input clock PCLK
n [15: 0] (each 16-bit parallel input data D
ATA0 [15: 0] to DATAn [15: 0]),
Clock transfer flip-flop 16n (160-
16n) captures at the rising edge of the clock clka. That is, the clock clka is selected as an optimum clock (clock with sufficient margin for both setup / hold) and each channel (each clock transfer flip-flop 16 is used as a common clock for the transmission circuit).
0 to 16n).

If the data input clock PCLK is not in the position satisfying the above condition, the clock cl
For clkb with a phase delay of 90 ° from ka,
Clock c whose phase is advanced by 90 ° from clock clkb
Phase is 13 more than lkb-90 and clock clkb
When the clock clkb-135 advanced by 5 ° is generated and the rising edge of the data input clock PCLK is at the low level “L” position for both the clock clkb-90 and the clock clkb-135, the rising edge of the data input clock PCLK becomes the data input clock PCLK. DATAn [15:
0] is taken in by the clock transfer flip-flop 16n at the rising edge of the clock clkb.

Further, when the data input clock PCLK is not at the optimum position for the clock clkb, similarly, the comparison processing is performed for the clocks clkc and clkd, and finally, the clocks clka to clka.
Any clock of kd will be selected. That is, the data input clock PCLK and the PLL circuit 1
82 output (clocks pll-clk0-pll-cl
four-phase clocks (clka, cl) having the same frequency as the data input clock PCLK created from
kb, clkc, clkd) are compared, and parallel data (DATAn) synchronized with the data input clock PCLK is compared.
The clock (clka) having the optimum phase relationship for latching [15: 0]) is selected, and this clock is supplied to the plurality of clock transfer flip-flops 160 to 16n and transmitted via the plurality of signal lines 130 to 13n. Data can be transmitted in synchronization with one clock.

Here, as shown in FIG. 9, the selected clocks are clocks that rise at the timing of the approximate center (F-c) of the data, but for example, the frequency of the clock is further increased. If high (eg 8
In the case of (00 MHz, etc.), as explained with reference to FIG. 4, since the setup time margin has to be taken into consideration rather than the data hold time, there is a delay from the data center (F-c) timing. The clock that rises at the selected timing will be selected.

FIG. 10 is a circuit diagram showing an example of a PCLK position detection circuit which can be applied to the clock transfer circuit in the timing signal generation circuit of FIG. The operation of the clock rearrangement circuit 181 described with reference to FIG.
It can be realized by applying a PCLK position detection circuit 190 as shown in FIG.

As shown in FIG. 10, the PCLK position detection circuit 190 has two D-type flip-flops 191,
It comprises 192 and an OR gate 193. The clock c is applied to the data terminal D of the flip-flop 191.
A clock clka-9 whose phase is advanced by 90 ° from lka
0 is supplied to the data terminal D of the flip-flop 192, and a clock clka-135 whose phase is advanced by 135 ° from the clock clka is supplied to the data terminal D of each flip-flop 191 and 192. The data input clock PCLK is input. This allows flip-flops 191 and 19
2 is clocked by clocks clka-90 and clka-13 due to the rising edge of the data input clock PCLK.
Take in 5. Further, the outputs of the flip-flops 191 and 192 are supplied to the OR gate 193, and when the output of the OR gate 193 is at the low level “L”, that is, the rising edge of the data input clock PCLK is the clocks clka-90 and clka-. When both 135 are at the low level “L” position, the low level “L” selection signal SELa is output and the clock clk is output.
A is selected. Here, it goes without saying that the PCLK position detection circuit or the clock transfer circuit can be modified in various ways.

FIG. 11 is a block diagram schematically showing a second embodiment of the timing signal generating circuit (signal transmission system) according to the present invention. In FIG. 11, reference numeral 510 is a first circuit (block A: transmission circuit), 550 is a second circuit (block B), and 530 is a first circuit 510 and a second circuit.
An n-bit wide data transmission path 531 for transmitting data to and from the circuit 550 is a clock transmission path for transmitting a clock (CLOCK-A) from the first circuit 510 to the second circuit 550, and 532 is a first transmission path. The error signal transmission path for transmitting the error signal ERR from the second circuit 550 to the first circuit 510, 551 is a receiving circuit, and 552 is a determining circuit.

As shown in FIG. 11, in the timing signal generating circuit according to the second embodiment, the judging circuit 552 has m clocks CLOCK-B (for example, four-phase clocks) having different phases and a synchronous reset signal. RESYNC,
Further, the lock signal LOCK is supplied, and further, the clock CLOCK-A used in the first circuit 510 is supplied via the clock transmission line 531. Further, the determination circuit 552 outputs the error signal ERR to the reception circuit 551 and also outputs the error signal ERR to the transmission circuit 510.
Is output.

That is, the decision circuit 552 uses the optimum clock from the supplied m clocks CLOCK-B having different phases as the reception clock (CLK).
When it is determined that the fixed clock should be released while outputting to 1, the error signal ERR indicating this clock release is transmitted to the transmission circuit 51 which is the data transmission source.
0 and data are output to a receiving circuit 551 that receives (reproduces). The operation of the determination circuit 552 is the same as that described with reference to FIGS. 4 to 7 or 8 to 10.

Further, the determination circuit 552 has a synchronization reset signal RESYNC and a lock signal LO directly from the outside.
CK is input, and the operation of the determination circuit 552 is forcibly re-executed by the synchronous reset signal RESYNC, and the operation of the determination circuit is invalidated (forcedly fixed) by the lock signal LOCK. Has been done.

FIG. 12 is a block diagram schematically showing a third embodiment of the timing signal generating circuit (signal transmission system) according to the present invention.

As is clear from the comparison between FIG. 12 and FIG. 11, in the timing signal generating circuit of the third embodiment, from the clock ACLK to the four-phase clocks ACLK [0], ACL.
A four-phase clock generation circuit 553 for generating K [1], ACLK [2], ACLK [3] is provided, and the output of the four-phase clock generation circuit 553 (four-phase clock ACLK
[0] to ACLK [3]) are supplied to the determination circuit 552. The clock P in FIG.
CLK and data PDATA correspond to clock CLOCK-A and data DATA in FIG.

The first circuit (transmission circuit) 510 outputs data PDATA synchronized with the clock PCLK and supplies it to the reception circuit 551 via the data transmission line 530. In the second circuit 550, the four-phase clock generation circuit 553 uses the clock ACLK whose frequency is twice that of the clock PCLK.
Four-phase clock A used to receive data based on
CLK [0] to ACLK [3] are generated, and the determination circuit 55 is generated.
2 is the clock PCLK supplied from the transmission circuit 510
The level of the determination clock is determined by and the corresponding candidate clock is supplied to the reception circuit 551 as the reception clock (CLK). The operation of the determination circuit 552 is as follows.
This is the same as described with reference to FIGS. 4 to 7 or 8 to 10.

Further, also in this embodiment, the decision circuit 5
52 is an error signal ER when the clock cannot be specified.
RX is output to the transmission circuit 510 and the reception circuit 551 (the data reception unit in the second circuit 550), and the lock signal LOCK for forcibly fixing the clock and the selection operation are externally applied. The synchronous reset signal RESYNC for forcibly re-executing is input. Here, the error signal ERRX is a signal of a row enable which is a signal of an inverted logic of the error signal ERR.

FIG. 13 is a circuit diagram showing an example of a four-phase clock generation circuit in the timing signal generation circuit of FIG. 12, and FIG. 14 is a circuit diagram showing an example of a determination circuit in the timing signal generation circuit of FIG. 15 is a diagram for explaining the operation of the timing signal generation circuit of FIG.

As shown in FIG. 13, the four-phase clock generation circuit 553 includes two flip-flops 5531 and 5532, and as shown in FIG. 15, a clock ACLK having a frequency twice that of the clock PCLK is generated. The phase clocks ACLK [0] to ACLK [3] are generated. Also, each flip-flop 553
A preset signal PRESET is supplied to 1 and 5532. Four-phase clocks ACLK [0] to ACLK [3] generated by the four-phase clock generation circuit 553.
Is supplied to the determination circuit 552, and a predetermined candidate clock corresponding to the determination result of the determination clock is selected and supplied to the reception circuit 551 as the clock CLK.

The determination circuit 552 includes a plurality of flip-flops 5211 to 5216 and a plurality of NAND gates 5221.
5226, an AND gate 523, a plurality of NOR gates 5241 to 5244, an inverter 52, and a clock selection circuit 526. It is needless to say that the four-phase clock generation circuit 553 and the determination circuit 552 shown in FIGS. 13 and 14 are merely one configuration example and can have various configurations.

In the example of FIG. 14, two determination clocks (for example, clock ACLK) are provided for one candidate clock.
[0], ACLK [1]) are set, these judgment clocks are fetched by the clock PCLK to make judgment, and a four-phase clock ACLK [0] corresponding to the judgment clock is set.
~ ACLK [3] candidate clock (eg AC
LK [3]) is selected by the selection signal SEL and is output as the clock CLK used in the receiving circuit 551.

As shown in FIG. 14, the judgment clock ACL by the flip-flops 5211 and 5213.
By the determination of K [0] and ACLK [1] and the determination of the outputs of the flip-flops 5211 and 5213 by the flip-flops 5212 and 5214, that is, the two determination clocks ACLK [0], at the rising timing of the clock PCLK. The selection signal SEL is output by determining ACLK [1] twice consecutively, and the clock CLK supplied to the receiving circuit 551 is controlled to be fixed or released. The determination circuit 552 of FIG.
The error signal ERRX is output from the AND gate 5224.
Is output, and the circuit can be reset and locked (forcibly fixed) from the outside by the synchronous reset signal RESYNC and the lock signal LOCK.

Here, as shown in FIG. 12, the error signal ERRX is transmitted to the transmitting circuit 510 and the receiving circuit 551.
To the predetermined processing, for example, the transmission circuit 5
At 10, the data output is stopped or retransmitted, and at the receiving circuit 551, the data reception is stopped, or the received data is discarded or reacquired. In the third embodiment, as shown in FIG. 15, the determination of fixing the clock by the determination using the two determination clocks is performed in the range of 90 °, for example. The determination to cancel is made, for example, in the range of 270 °.

FIG. 16 is a block diagram schematically showing a fourth embodiment of the timing signal generating circuit according to the present invention, and FIG. 17 is a circuit showing an example of the eight-phase clock generating circuit in the timing signal generating circuit of FIG. FIG. 18 is a diagram for explaining the operation of the timing signal generation circuit of FIG. 16.

As is clear from the comparison between FIG. 16 and FIG. 12, in the timing signal generation circuit of the fourth embodiment, instead of the four-phase clock generation circuit 553 in the timing signal generation circuit of the third embodiment described above. 45 ° in phase with each other
Different 8-phase clocks BCLKK [0] to BCLK [7]
An eight-phase clock generation circuit 554 that generates

As shown in FIG. 17, the eight-phase clock generation circuit 554 includes five flip-flops 5541-5.
545, as shown in FIG. 18, a clock PC
The eight-phase clocks BCLK [0] to BCLK [7] are generated from the clock BCLK having a frequency four times LK.
The preset signal PRESET is supplied to each of the flip-flops 5541 to 5545. Eight-phase clock BC generated by this eight-phase clock generation circuit 554
LK [0] to BCLK [7] are supplied to the determination circuit 552, a predetermined candidate clock corresponding to the determination result of the determination clock is selected, and the reception circuit 5 as the clock CLK.
51 is supplied.

The determination circuit 552 is similar to that shown in FIG. 14 described above, but the clock supplied to the clock selection circuit 526 is a four-phase clock ACLK [0] to ACLK.
Eight-phase clock BCLK [0] to BCLK instead of [3]
[7] and the determination clock is the four-phase clock A.
The two clocks BCLK [0] and BCLK among the eight-phase clocks BCLK [0] to BCLK [7] instead of the two clocks ACLK [0] and ACLK [1] among the CLK [0] to ACLK [3]. It is said to be [1].

That is, as shown in FIG. 14, the decision circuit 552 has flip-flops 5211 and 521.
Judgment clocks BCLK [0] and BCLK according to 3
[1] determination and flip-flops 5212 and 52
Flip-flops 5211 and 521 according to 14
3 output determination, that is, the clock PCLK
Two determination clocks BCL at the rising timing of
The selection signal SEL is output by continuously determining K [0] and BCLK [1] twice, and control for fixing and releasing the clock CLK supplied to the receiving circuit 551 is performed (see FIGS. 5 and 7). The control described above is performed. Note that FIG.
As described above, the decision circuit 552 of No. 4 outputs the error signal ERRX as the output of the NAND gate 5224,
Further, it is possible to reset and lock (forcibly fix) from the outside by the synchronous reset signal RESYNC and the lock signal LOCK.

In the fourth embodiment, as shown in FIG. 18, the determination of fixing the clocks by the two determination clocks is performed in the range of 135 °, for example. The determination to cancel is, for example, 2
It is designed to be performed in the range of 25 °.

FIG. 19 is a block diagram schematically showing a fifth embodiment of the timing signal generating circuit according to the present invention. In FIG. 19, reference numeral 520 is a first circuit, 560 is a second circuit, and 530 is a first circuit 520 and a second circuit 5.
Data (including a clock) is transmitted to and from n
A data transmission line having a bit width, and 532, an error signal transmission line for transmitting the error signal ERRX from the second circuit 560 to the first circuit 520. Further, reference numeral 561 is a receiving circuit, 562 is a determination circuit, 564 is an eight-phase clock generation circuit, and 565 is a clock recovery circuit.

As shown in FIG. 19, in the timing signal generating circuit of the fifth embodiment, the first circuit to the second circuit are
Clock transmission line (531) for transmitting clock to other circuits
Is not provided and is included in the data PDATA for transmission. That is, the second circuit 560 is provided with the clock recovery circuit 565, and the data PDATA transmitted via the data transmission path 530 is changed to the clock DCLK (the first circuit 510 in FIG. 12).
From the second circuit 550 via the clock transmission line 531
(Corresponding to the clock PCLK transmitted to the determination circuit 552) is reproduced and supplied to the determination circuit 562. In addition, as the data transmission including the clock information from the first circuit 520 to the second circuit 560,
For example, run length 5 8B / 10B (or 10
B / 8B) and run length 72 SONET etc.,
Usually, as the standard of the actual data PDATA, a value within the above two ranges is used.

20 and 21 are circuit diagrams showing an example of the clock regeneration circuit in the timing signal generation circuit of FIG. 19, and FIG. 22 is a diagram for explaining the operation of the clock regeneration circuit in the timing signal generation circuit of FIG. It is a figure.

As shown in FIGS. 20 and 21, the clock recovery circuit 565 includes a plurality of flip-flops 65.
0-657 (FIG. 20 (a)) and a plurality of exclusive NOR (EXNOR) gates 660-667 (FIG. 20).
(B)), a NOR gate 670, a plurality of NAND gates 671 to 674, inverters 675 and 676 (FIG. 21).
(A)) and selection circuits 681 and 682 (FIG. 21 (b))
It has and.

As shown in FIG. 20A, each of the flip-flops 650 to 657 has a data PDA.
TA and 8-phase clock BCLK [0] to BCLK
One of [7] is supplied and the data PDATA is fetched at each eight-phase clock BCLK [0] to BCLK [7]. Actually, the outputs (BD [0] to BD [7]) are obtained after the flip-flop has been input a plurality of times. Therefore, there is a boundary where the data captured by any of the eight flip-flops 650 to 657 changes between the high level “H” and the low level “L”.

As shown in FIG. 20B, EXNO
The R gates 660 to 667 are for detecting the above-mentioned boundary, and two adjacent flip-flops 650 to 650.
657 output (BD [0], BD [1]; BD [1],
BD [2]; ...; BD [7], BD [0]) are input and their outputs change between high level “H” and low level “L” (EXNOR gates 660 to 667).
Output EX01X to EX70X of low level "L") is detected.

In this way, all clocks (clock B
CLK [0] to BCLK [7]), EX [n, n
+1] X is generated and then latches (NAND gates 671 and 672 and inverter 6 as shown in FIG.
75, 676) to hold each state as a flag, and further NOR gate 6
The reset signal RST23X is generated by the logic circuit formed by 70 and the NAND gates 673 and 674. Note that FIG. 21A shows the case where a boundary exists between BCLK [2] and BCLK [3] of the eight-phase clock, and in fact, there are eight similar blocks. Existence exists, the flags EX01-F to EX70F are held by this, and the reset signals RST01X to RST70 are also held.
X is generated. Note that the flags EX01-F to EX70.
One of the Fs has a high level "H" and the other has a low level "L".

Further, as shown in FIG. 21 (b),
Flags EX01-F to EX70F held in each latch
Is supplied as a selection signal to the selection control terminals sel of the selection circuits 681 and 682. The selection circuit 681 receives the 8-phase clock BCLK [0] input by the selection signal input.
~ BCLK [7] is selected and output as a clock DCLK. In addition, the selection circuit 682 has reset signals RST01X to RST input by the selection signal input.
One of 70X is selected and output as a reset signal RESETX.

Specifically, as shown in FIG. 22, for example, when only the flag EX23 of the selection logic is at the high level "H", the clock BCLK is output as the output signal (DCLK).
[0] is selected and the reset signal (RESET
The reset signal RST23X is selected as X).
Then, the clock DCLK and the reset signal RESETX are supplied to the determination circuit 562.

FIG. 23 is a circuit diagram showing an example of a decision circuit in the timing signal generation circuit of FIG.

As is apparent from the comparison between FIG. 23 and FIG. 14, the decision circuit 562 in the fifth embodiment has the NOR gate 621 and the inverter 622 added to the decision circuit 552 of FIG. The reset signal RESETX is supplied as an input of the inverter 622, and the clock PCLK in the determination circuit 552 of FIG.
Is configured to use the clock DCLK obtained by the clock reproduction circuit 565.

FIG. 24 is a diagram for explaining the operation of the decision circuit in the timing signal generation circuit of FIG.

Specifically, as shown in FIG. 24, two determination clocks BCLK [0] and BCLK [1] are continuously determined twice at the rising timing of the clock DCLK, all of which are low level "L". In this case, for example, the clock BCLK [5] is selected (fixed) and defined as the clock (reception clock) CLK to be supplied to the reception circuit 561.
Depending on the frequency of the clock used, the receiving circuit 56
1 is the received clock CLK is the clock BCLK
As described above, the clock BCLK [4] or the clock BCLK [3] may be defined instead of [5]. Also, an eight-phase clock BCLK [0] to BCL
Four-phase clocks ACLK [0] to AC instead of K [7]
When using LK [3], for example, clock DCLK
Two determination clock ACLs at the rising timing of
When K [0] and ACLK [1] are continuously determined twice and all are at the low level “L”, for example, the clock ACLK
[3] is selected to be the reception clock CLK.

In each of the above embodiments, the decision circuit (55
2, 562), a clock generation circuit (553, 554), a clock recovery circuit (565), and the like, and various configurations can be used, and the output of the clock generation circuit is a four-phase clock or an eight-phase clock It is not limited to.

As described above, according to the respective embodiments of the present invention, when the phase difference between the clocks of the transmitting and receiving circuits operating at the same frequency is not guaranteed, or when the jitter included in the clocks is not guaranteed, etc. Also in this case, it is possible to stably send and receive data. Further, when a data error occurs, it is possible to improve the accuracy of narrowing down the cause.

(Supplementary Note 1) A candidate timing signal generation circuit for generating a plurality of candidate timing signals having different phases,
A timing signal generation circuit for reception, which selects and holds a reception timing signal used for receiving data from the plurality of candidate timing signals according to a predetermined condition, and a timing signal generation circuit.

(Supplementary Note 2) In the timing signal generating circuit according to Supplementary Note 1, the reception timing signal control circuit compares a predetermined determination timing signal for each of the candidate timing signals with a comparison timing signal. A timing signal comparing circuit for judging, and a receiving timing signal selecting and holding circuit for selecting and holding the receiving timing signal according to the output of the judging timing signal comparing circuit. Generator circuit.

(Supplementary Note 3) In the timing signal generating circuit according to Supplementary Note 2, a plurality of the determination timing signals are set for each of the candidate timing signals, and the determination timing signal comparison circuit includes the comparison timing signal. A timing signal generating circuit for comparing a signal with a plurality of timing signals for judgment.

(Supplementary Note 4) In the timing signal generating circuit according to Supplementary Note 3, the determination timing signal comparison circuit executes the comparison between the comparison timing signal and the plurality of determination timing signals a plurality of times, and A timing signal generation circuit, wherein the reception timing signal selection / holding circuit selects and holds the reception timing signal in accordance with outputs of a plurality of comparisons by the determination timing signal comparison circuit.

(Supplementary Note 5) In the timing signal generating circuit according to supplementary note 2, the timing signal for comparison is supplied in parallel with the received data.

(Supplementary Note 6) In the timing signal generating circuit according to Supplementary Note 2, the timing signal for comparison is supplied by being included in the stream of the received data.

(Supplementary Note 7) In the timing signal generating circuit according to Supplementary Note 2, the reception timing signal control circuit further includes the selected and held reception signal according to the output of the determination timing signal comparison circuit. A timing signal generation circuit comprising a reception timing signal cancellation circuit for canceling a timing signal.

(Supplementary Note 8) In the timing signal generating circuit according to Supplementary Note 7, the reception timing signal selection holding circuit is configured to determine the determination timing when the reception timing signal cancellation circuit cancels the reception timing signal. A timing signal generation circuit, which selects and holds a new reception timing signal according to the output of a signal comparison circuit.

(Supplementary Note 9) In the timing signal generating circuit according to Supplementary Note 7, the reception timing signal control circuit further cancels the reception timing signal selected and held by the reception timing signal cancellation circuit. At this time, the timing signal generating circuit is provided with a reception timing signal cancellation notifying circuit for notifying the outside of the timing signal generating circuit of cancellation of the reception timing signal.

(Supplementary Note 10) In the timing signal generating circuit according to Supplementary Note 7, a comparison condition in the judgment timing signal comparison circuit for canceling the reception timing signal selected and held by the reception timing signal cancellation circuit. The timing signal generating circuit is characterized in that the reception timing signal selection holding circuit is more lenient than the comparison condition in the judgment timing signal comparison circuit for selecting and holding the reception timing signal.

(Supplementary Note 11) Any one of Supplementary Notes 1 to 10
In the timing signal generation circuit according to the item 1, the reception timing signal control circuit further includes a reception timing signal control stop circuit for externally stopping selection and holding of the reception timing signal from the plurality of candidate timing signals. A timing signal generation circuit comprising.

(Supplementary Note 12) Any one of Supplementary Notes 1 to 10
In the timing signal generation circuit according to the item 1, the reception timing signal control circuit further re-executes reception timing signal control re-execution for externally re-selecting and holding reception timing signals from the plurality of candidate timing signals. A timing signal generating circuit comprising a circuit.

(Supplementary Note 13) A signal transmission system comprising a transmission circuit for transmitting data, a signal transmission path, and a reception circuit for receiving data supplied from the transmission circuit via the signal transmission path, A signal transmission system, wherein the receiving circuit includes the timing signal generating circuit according to any one of appendices 1 to 12.

(Supplementary Note 14) A plurality of candidate timing signals having different phases are prepared, and a reception timing signal used for data reception is selected and held from the plurality of candidate timing signals according to a predetermined condition. Timing signal generation method.

(Supplementary Note 15) In the timing signal generating method according to Supplementary Note 14, the selection and holding of the reception timing signal is performed by comparing a predetermined determination timing signal for each of the candidate timing signals with a comparison timing signal. And a timing signal generating method for selecting and holding the reception timing signal according to a comparison result of the determination timing signal for each of the candidate timing signals and the comparison timing signal.

(Supplementary Note 16) In the timing signal generating method according to Supplementary Note 15, a plurality of the determination timing signals are set for each of the candidate timing signals, and the comparison timing signal and the plurality of determination timing signals are set. A timing signal generating method characterized by comparing.

(Supplementary Note 17) In the timing signal generating method according to Supplementary Note 16, the comparison between the comparison timing signal and the plurality of determination timing signals is performed a plurality of times, and the comparison timing signal is determined a plurality of times. A timing signal generating method, characterized in that the reception timing signal is selected and held according to the result of comparison with the reception timing signal.

(Supplementary Note 18) In the timing signal generating method according to Supplementary Note 15, the timing signal for comparison is supplied in parallel with the received data.

(Supplementary Note 19) In the timing signal generating method according to Supplementary Note 15, the timing signal for comparison is supplied by being included in the stream of the received data.

(Supplementary Note 20) In the method for generating a timing signal according to Supplementary Note 15, the reception timing signal is selected and held based on a comparison result between the determination timing signal and the comparison timing signal for each of the candidate timing signals. Accordingly, the selected and held reception timing signal is released.

(Supplementary Note 21) In the timing signal generating method according to supplementary note 20, when the reception timing signal is released, a predetermined determination timing signal is applied to each of the candidate timing signals and the comparison timing signal is generated. A timing signal generating method, characterized in that a new reception timing signal is selected and held in comparison with the signal.

(Supplementary Note 22) In the timing signal generating method according to Supplementary Note 20, when the selected and held reception timing signal is released, the release of the reception timing signal is notified to the outside. A characteristic timing signal generation method.

(Supplementary Note 23) In the timing signal generating method according to Supplementary Note 20, the comparison condition for releasing the selected and held reception timing signal is a comparison for selecting and holding the reception timing signal. A method for generating a timing signal, characterized in that it is gentler than the condition.

(Supplementary Note 24) In the timing signal generating method according to any one of Supplementary Notes 14 to 23, selection and holding of the reception timing signal from the plurality of candidate timing signals are stopped from the outside. Timing signal generation method.

(Supplementary Note 25) In the timing signal generating method according to any one of Supplementary Notes 14 to 23, the selection and holding of the reception timing signal from the plurality of candidate timing signals is re-executed from the outside. And timing signal generation method.

[0108]

As described above in detail, according to the present invention, a clock that can reliably receive data is generated in consideration of the phase difference, and high-speed error-free signal transmission is enabled. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing an example of a conventional signal transmission system.

FIG. 2 is a timing chart for explaining an example of the operation in the signal transmission system of FIG.

FIG. 3 is a block diagram schematically showing another example of a conventional signal transmission system.

FIG. 4 is a diagram for explaining an example of a timing signal generating method according to the present invention.

FIG. 5 is a timing chart for explaining the timing signal generating method shown in FIG.

FIG. 6 is a diagram for explaining another example of the timing signal generating method according to the present invention.

FIG. 7 is a timing diagram for explaining the timing signal generating method shown in FIG.

FIG. 8 is a block diagram schematically showing a first embodiment of the timing signal generating circuit according to the present invention.

9 is a diagram for explaining the operation of the timing signal generating circuit in FIG.

10 is a circuit diagram showing an example of a PCLK position detection circuit that can be applied to a clock transfer circuit in the timing signal generation circuit of FIG.

FIG. 11 is a second timing signal generating circuit according to the present invention.
It is a block diagram which shows an Example schematically.

FIG. 12 is a third timing signal generating circuit according to the present invention.
It is a block diagram which shows an Example schematically.

13 is a circuit diagram showing an example of a four-phase clock generation circuit in the timing signal generation circuit of FIG.

14 is a circuit diagram showing an example of a determination circuit in the timing signal generation circuit of FIG.

FIG. 15 is a diagram for explaining the operation of the timing signal generating circuit in FIG.

FIG. 16 is a fourth timing signal generating circuit according to the present invention.
It is a block diagram which shows an Example schematically.

17 is a circuit diagram showing an example of an eight-phase clock generation circuit in the timing signal generation circuit of FIG.

FIG. 18 is a diagram for explaining the operation of the timing signal generating circuit in FIG.

FIG. 19 is a fifth timing signal generating circuit according to the present invention.
It is a block diagram which shows an Example schematically.

20 is a circuit diagram (1) showing an example of a clock recovery circuit in the timing signal generation circuit of FIG.

21 is a circuit diagram (No. 2) showing an example of a clock recovery circuit in the timing signal generation circuit of FIG.

22 is a diagram for explaining the operation of the clock recovery circuit in the timing signal generation circuit of FIG.

23 is a circuit diagram showing an example of a determination circuit in the timing signal generation circuit of FIG.

24 is a diagram for explaining the operation of the determination circuit in the timing signal generation circuit of FIG.

[Explanation of symbols]

110 to 11n ... Data transmission side data capture circuit (transmission side latch) 120 to 12n ... Data transmission side drive circuit (transmission side buffer) 130 to 13n ... Data wiring (data signal line) 140 to 14n ... Data receiving side driving circuit (receiving side buffer) 150 to 15n ... Receiving side data fetching circuit (receiving side latch) 160 to 16n ... Clock replacement flip-flops 170 to 17n ... Transmission data processing unit (transmission side latch) 181 ... Clock transfer circuit 182 ... PLL circuit 183 ... Clock generation circuit 184 ... Demultiplexer 190 ... PCLK position detection circuits 510 and 520 ... First circuit (block A: transmission circuit) 530 ... Data transmission path 531 ... Clock transmission path 532 ... Error signal transmission paths 550, 560 ... Second circuit (block B) 51,561 ... receiving circuit 552, 562 ... judgment circuit 563 ... four-phase clock generation circuit 564 ... Hasso clock generation circuit 565 ... clock recovery circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B079 CC08 CC14 CC16 DD13 DD17                 5K047 AA03 AA11 GG07 GG45 MM28                       MM46 MM53

Claims (10)

[Claims] 1. A candidate timing signal generation circuit for generating a plurality of candidate timing signals having different phases, and a reception for selecting and holding a reception timing signal used for receiving data from the plurality of candidate timing signals according to a predetermined condition. Timing signal control circuit, and a timing signal generation circuit. 2. The timing signal generation circuit according to claim 1, wherein the reception timing signal control circuit compares a determination timing signal predetermined for each of the candidate timing signals with a comparison timing signal. A timing signal generator comprising: a judgment timing signal comparison circuit; and a reception timing signal selection holding circuit for selecting and holding the reception timing signal according to the output of the judgment timing signal comparison circuit. circuit. 3. The timing signal generating circuit according to claim 2, wherein a plurality of the determination timing signals are set for each of the candidate timing signals, and the determination timing signal comparison circuit is configured to set the comparison timing signal. And a plurality of timing signals for determination are compared with each other. 4. The timing signal generation circuit according to claim 2, wherein the reception timing signal control circuit further receives the selected and held reception timing according to the output of the determination timing signal comparison circuit. A timing signal generation circuit comprising a reception timing signal cancellation circuit for canceling a signal. 5. The timing signal generation circuit according to claim 4, wherein the comparison condition in the determination timing signal comparison circuit for releasing the reception timing signal selected and held by the reception timing signal release circuit is A timing signal generation circuit, wherein the reception timing signal selection and holding circuit is more lenient than a comparison condition in the determination timing signal comparison circuit for selecting and holding the reception timing signal. 6. The timing signal generation circuit according to claim 1, wherein the reception timing signal control circuit further selects a reception timing signal from the plurality of candidate timing signals and A timing signal generation circuit comprising a reception timing signal control stop circuit for stopping holding from the outside. 7. The timing signal generation circuit according to claim 1, wherein the reception timing signal control circuit further selects a reception timing signal from the plurality of candidate timing signals and A timing signal generation circuit comprising a reception timing signal control re-execution circuit for re-holding from outside. 8. A signal transmission system having a transmission circuit for transmitting data, a signal transmission line, and a reception circuit for receiving data supplied from the transmission circuit via the signal transmission line, the reception circuit Is a signal transmission system comprising the timing signal generating circuit according to claim 1. 9. A timing signal comprising: preparing a plurality of candidate timing signals having different phases, and selecting and holding a reception timing signal used for receiving data from the plurality of candidate timing signals according to a predetermined condition. Method of occurrence. 10. The timing signal generation method according to claim 9, wherein the selection and holding of the reception timing signal is performed by using a predetermined determination timing signal for each candidate timing signal as a comparison timing signal. In comparison, depending on the comparison result of the determination timing signal and the comparison timing signal for each candidate timing signal,
A method for generating a timing signal, characterized in that the timing signal for reception is selected and held.